GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/drivers/clk/tegra/Kconfig

@@ -0,0 +1,13 @@
+config TEGRA_CAR_CLOCK
+	bool "Enable Tegra CAR-based clock driver"
+	depends on TEGRA_CAR
+	help
+	  Enable support for manipulating Tegra's on-SoC clocks via direct
+	  register access to the Tegra CAR (Clock And Reset controller).
+
+config TEGRA186_CLOCK
+	bool "Enable Tegra186 BPMP-based clock driver"
+	depends on TEGRA186_BPMP
+	help
+	  Enable support for manipulating Tegra's on-SoC clocks via IPC
+	  requests to the BPMP (Boot and Power Management Processor).

source/bootloader/u-boot-2020.01/drivers/clk/tegra/Makefile

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+
+obj-$(CONFIG_TEGRA_CAR_CLOCK) += tegra-car-clk.o
+obj-$(CONFIG_TEGRA186_CLOCK) += tegra186-clk.o

source/bootloader/u-boot-2020.01/drivers/clk/tegra/tegra-car-clk.c

@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/clock.h>
+#include <asm/arch-tegra/clk_rst.h>
+
+static int tegra_car_clk_request(struct clk *clk)
+{
+	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+	      clk->id);
+
+	/*
+	 * Note that the first PERIPH_ID_COUNT clock IDs (where the value
+	 * varies per SoC) are the peripheral clocks, which use a numbering
+	 * scheme that matches HW registers 1:1. There are other clock IDs
+	 * beyond this that are assigned arbitrarily by the Tegra CAR DT
+	 * binding. Due to the implementation of this driver, it currently
+	 * only supports the peripheral IDs.
+	 */
+	if (clk->id >= PERIPH_ID_COUNT)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int tegra_car_clk_free(struct clk *clk)
+{
+	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+	      clk->id);
+
+	return 0;
+}
+
+static ulong tegra_car_clk_get_rate(struct clk *clk)
+{
+	enum clock_id parent;
+
+	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+	      clk->id);
+
+	parent = clock_get_periph_parent(clk->id);
+	return clock_get_periph_rate(clk->id, parent);
+}
+
+static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
+{
+	enum clock_id parent;
+
+	debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
+	      clk->dev, clk->id);
+
+	parent = clock_get_periph_parent(clk->id);
+	return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL);
+}
+
+static int tegra_car_clk_enable(struct clk *clk)
+{
+	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+	      clk->id);
+
+	clock_enable(clk->id);
+
+	return 0;
+}
+
+static int tegra_car_clk_disable(struct clk *clk)
+{
+	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+	      clk->id);
+
+	clock_disable(clk->id);
+
+	return 0;
+}
+
+static struct clk_ops tegra_car_clk_ops = {
+	.request = tegra_car_clk_request,
+	.free = tegra_car_clk_free,
+	.get_rate = tegra_car_clk_get_rate,
+	.set_rate = tegra_car_clk_set_rate,
+	.enable = tegra_car_clk_enable,
+	.disable = tegra_car_clk_disable,
+};
+
+static int tegra_car_clk_probe(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(tegra_car_clk) = {
+	.name = "tegra_car_clk",
+	.id = UCLASS_CLK,
+	.probe = tegra_car_clk_probe,
+	.ops = &tegra_car_clk_ops,
+};

source/bootloader/u-boot-2020.01/drivers/clk/tegra/tegra186-clk.c

@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <misc.h>
+#include <asm/arch-tegra/bpmp_abi.h>
+
+static ulong tegra186_clk_get_rate(struct clk *clk)
+{
+	struct mrq_clk_request req;
+	struct mrq_clk_response resp;
+	int ret;
+
+	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+	      clk->id);
+
+	req.cmd_and_id = (CMD_CLK_GET_RATE << 24) | clk->id;
+
+	ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
+			sizeof(resp));
+	if (ret < 0)
+		return ret;
+
+	return resp.clk_get_rate.rate;
+}
+
+static ulong tegra186_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct mrq_clk_request req;
+	struct mrq_clk_response resp;
+	int ret;
+
+	debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
+	      clk->dev, clk->id);
+
+	req.cmd_and_id = (CMD_CLK_SET_RATE << 24) | clk->id;
+	req.clk_set_rate.rate = rate;
+
+	ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
+			sizeof(resp));
+	if (ret < 0)
+		return ret;
+
+	return resp.clk_set_rate.rate;
+}
+
+static int tegra186_clk_en_dis(struct clk *clk,
+			       enum mrq_reset_commands cmd)
+{
+	struct mrq_clk_request req;
+	struct mrq_clk_response resp;
+	int ret;
+
+	req.cmd_and_id = (cmd << 24) | clk->id;
+
+	ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
+			sizeof(resp));
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int tegra186_clk_enable(struct clk *clk)
+{
+	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+	      clk->id);
+
+	return tegra186_clk_en_dis(clk, CMD_CLK_ENABLE);
+}
+
+static int tegra186_clk_disable(struct clk *clk)
+{
+	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+	      clk->id);
+
+	return tegra186_clk_en_dis(clk, CMD_CLK_DISABLE);
+}
+
+static struct clk_ops tegra186_clk_ops = {
+	.get_rate = tegra186_clk_get_rate,
+	.set_rate = tegra186_clk_set_rate,
+	.enable = tegra186_clk_enable,
+	.disable = tegra186_clk_disable,
+};
+
+static int tegra186_clk_probe(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(tegra186_clk) = {
+	.name		= "tegra186_clk",
+	.id		= UCLASS_CLK,
+	.probe		= tegra186_clk_probe,
+	.ops = &tegra186_clk_ops,
+};