GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/drivers/clk/uniphier/Kconfig

@@ -0,0 +1,8 @@
+config CLK_UNIPHIER
+	def_bool y
+	depends on ARCH_UNIPHIER
+	select CLK
+	help
+	  Support for clock controllers on UniPhier SoCs.
+	  Say Y if you want to control clocks provided by System Control
+	  block, Media I/O block, Peripheral Block.

source/bootloader/u-boot-2020.01/drivers/clk/uniphier/Makefile

@@ -0,0 +1,3 @@
+obj-y	+= clk-uniphier-core.o
+obj-y	+= clk-uniphier-sys.o
+obj-y	+= clk-uniphier-mio.o

source/bootloader/u-boot-2020.01/drivers/clk/uniphier/clk-uniphier-core.c

@@ -0,0 +1,345 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016-2017 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#include "clk-uniphier.h"
+
+/**
+ * struct uniphier_clk_priv - private data for UniPhier clock driver
+ *
+ * @base: base address of the clock provider
+ * @data: SoC specific data
+ */
+struct uniphier_clk_priv {
+	struct udevice *dev;
+	void __iomem *base;
+	const struct uniphier_clk_data *data;
+};
+
+static void uniphier_clk_gate_enable(struct uniphier_clk_priv *priv,
+				     const struct uniphier_clk_gate_data *gate)
+{
+	u32 val;
+
+	val = readl(priv->base + gate->reg);
+	val |= BIT(gate->bit);
+	writel(val, priv->base + gate->reg);
+}
+
+static void uniphier_clk_mux_set_parent(struct uniphier_clk_priv *priv,
+					const struct uniphier_clk_mux_data *mux,
+					u8 id)
+{
+	u32 val;
+	int i;
+
+	for (i = 0; i < mux->num_parents; i++) {
+		if (mux->parent_ids[i] != id)
+			continue;
+
+		val = readl(priv->base + mux->reg);
+		val &= ~mux->masks[i];
+		val |= mux->vals[i];
+		writel(val, priv->base + mux->reg);
+		return;
+	}
+
+	WARN_ON(1);
+}
+
+static u8 uniphier_clk_mux_get_parent(struct uniphier_clk_priv *priv,
+				      const struct uniphier_clk_mux_data *mux)
+{
+	u32 val;
+	int i;
+
+	val = readl(priv->base + mux->reg);
+
+	for (i = 0; i < mux->num_parents; i++)
+		if ((mux->masks[i] & val) == mux->vals[i])
+			return mux->parent_ids[i];
+
+	dev_err(priv->dev, "invalid mux setting\n");
+
+	return UNIPHIER_CLK_ID_INVALID;
+}
+
+static const struct uniphier_clk_data *uniphier_clk_get_data(
+					struct uniphier_clk_priv *priv, u8 id)
+{
+	const struct uniphier_clk_data *data;
+
+	for (data = priv->data; data->type != UNIPHIER_CLK_TYPE_END; data++)
+		if (data->id == id)
+			return data;
+
+	dev_err(priv->dev, "id=%u not found\n", id);
+
+	return NULL;
+}
+
+static const struct uniphier_clk_data *uniphier_clk_get_parent_data(
+					struct uniphier_clk_priv *priv,
+					const struct uniphier_clk_data *data)
+{
+	const struct uniphier_clk_data *parent_data;
+	u8 parent_id = UNIPHIER_CLK_ID_INVALID;
+
+	switch (data->type) {
+	case UNIPHIER_CLK_TYPE_GATE:
+		parent_id = data->data.gate.parent_id;
+		break;
+	case UNIPHIER_CLK_TYPE_MUX:
+		parent_id = uniphier_clk_mux_get_parent(priv, &data->data.mux);
+		break;
+	default:
+		break;
+	}
+
+	if (parent_id == UNIPHIER_CLK_ID_INVALID)
+		return NULL;
+
+	parent_data = uniphier_clk_get_data(priv, parent_id);
+
+	WARN_ON(!parent_data);
+
+	return parent_data;
+}
+
+static void __uniphier_clk_enable(struct uniphier_clk_priv *priv,
+				  const struct uniphier_clk_data *data)
+{
+	const struct uniphier_clk_data *parent_data;
+
+	if (data->type == UNIPHIER_CLK_TYPE_GATE)
+		uniphier_clk_gate_enable(priv, &data->data.gate);
+
+	parent_data = uniphier_clk_get_parent_data(priv, data);
+	if (!parent_data)
+		return;
+
+	return __uniphier_clk_enable(priv, parent_data);
+}
+
+static int uniphier_clk_enable(struct clk *clk)
+{
+	struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct uniphier_clk_data *data;
+
+	data = uniphier_clk_get_data(priv, clk->id);
+	if (!data)
+		return -ENODEV;
+
+	__uniphier_clk_enable(priv, data);
+
+	return 0;
+}
+
+static unsigned long __uniphier_clk_get_rate(
+					struct uniphier_clk_priv *priv,
+					const struct uniphier_clk_data *data)
+{
+	const struct uniphier_clk_data *parent_data;
+
+	if (data->type == UNIPHIER_CLK_TYPE_FIXED_RATE)
+		return data->data.rate.fixed_rate;
+
+	parent_data = uniphier_clk_get_parent_data(priv, data);
+	if (!parent_data)
+		return 0;
+
+	return __uniphier_clk_get_rate(priv, parent_data);
+}
+
+static unsigned long uniphier_clk_get_rate(struct clk *clk)
+{
+	struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct uniphier_clk_data *data;
+
+	data = uniphier_clk_get_data(priv, clk->id);
+	if (!data)
+		return -ENODEV;
+
+	return __uniphier_clk_get_rate(priv, data);
+}
+
+static unsigned long __uniphier_clk_set_rate(
+					struct uniphier_clk_priv *priv,
+					const struct uniphier_clk_data *data,
+					unsigned long rate, bool set)
+{
+	const struct uniphier_clk_data *best_parent_data = NULL;
+	const struct uniphier_clk_data *parent_data;
+	unsigned long best_rate = 0;
+	unsigned long parent_rate;
+	u8 parent_id;
+	int i;
+
+	if (data->type == UNIPHIER_CLK_TYPE_FIXED_RATE)
+		return data->data.rate.fixed_rate;
+
+	if (data->type == UNIPHIER_CLK_TYPE_GATE) {
+		parent_data = uniphier_clk_get_parent_data(priv, data);
+		if (!parent_data)
+			return 0;
+
+		return __uniphier_clk_set_rate(priv, parent_data, rate, set);
+	}
+
+	if (WARN_ON(data->type != UNIPHIER_CLK_TYPE_MUX))
+		return -EINVAL;
+
+	for (i = 0; i < data->data.mux.num_parents; i++) {
+		parent_id = data->data.mux.parent_ids[i];
+		parent_data = uniphier_clk_get_data(priv, parent_id);
+		if (WARN_ON(!parent_data))
+			return -EINVAL;
+
+		parent_rate = __uniphier_clk_set_rate(priv, parent_data, rate,
+						      false);
+
+		if (parent_rate <= rate && best_rate < parent_rate) {
+			best_rate = parent_rate;
+			best_parent_data = parent_data;
+		}
+	}
+
+	dev_dbg(priv->dev, "id=%u, best_rate=%lu\n", data->id, best_rate);
+
+	if (!best_parent_data)
+		return -EINVAL;
+
+	if (!set)
+		return best_rate;
+
+	uniphier_clk_mux_set_parent(priv, &data->data.mux,
+				    best_parent_data->id);
+
+	return best_rate = __uniphier_clk_set_rate(priv, best_parent_data,
+						   rate, true);
+}
+
+static unsigned long uniphier_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct uniphier_clk_data *data;
+
+	data = uniphier_clk_get_data(priv, clk->id);
+	if (!data)
+		return -ENODEV;
+
+	return __uniphier_clk_set_rate(priv, data, rate, true);
+}
+
+static const struct clk_ops uniphier_clk_ops = {
+	.enable = uniphier_clk_enable,
+	.get_rate = uniphier_clk_get_rate,
+	.set_rate = uniphier_clk_set_rate,
+};
+
+static int uniphier_clk_probe(struct udevice *dev)
+{
+	struct uniphier_clk_priv *priv = dev_get_priv(dev);
+	fdt_addr_t addr;
+
+	addr = devfdt_get_addr(dev->parent);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->base = devm_ioremap(dev, addr, SZ_4K);
+	if (!priv->base)
+		return -ENOMEM;
+
+	priv->dev = dev;
+	priv->data = (void *)dev_get_driver_data(dev);
+
+	return 0;
+}
+
+static const struct udevice_id uniphier_clk_match[] = {
+	/* System clock */
+	{
+		.compatible = "socionext,uniphier-ld4-clock",
+		.data = (ulong)uniphier_pxs2_sys_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pro4-clock",
+		.data = (ulong)uniphier_pxs2_sys_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-sld8-clock",
+		.data = (ulong)uniphier_pxs2_sys_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pro5-clock",
+		.data = (ulong)uniphier_pxs2_sys_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pxs2-clock",
+		.data = (ulong)uniphier_pxs2_sys_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-ld11-clock",
+		.data = (ulong)uniphier_ld20_sys_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-ld20-clock",
+		.data = (ulong)uniphier_ld20_sys_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pxs3-clock",
+		.data = (ulong)uniphier_pxs3_sys_clk_data,
+	},
+	/* Media I/O clock */
+	{
+		.compatible = "socionext,uniphier-ld4-mio-clock",
+		.data = (ulong)uniphier_mio_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pro4-mio-clock",
+		.data = (ulong)uniphier_mio_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-sld8-mio-clock",
+		.data = (ulong)uniphier_mio_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pro5-sd-clock",
+		.data = (ulong)uniphier_mio_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pxs2-sd-clock",
+		.data = (ulong)uniphier_mio_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-ld11-mio-clock",
+		.data = (ulong)uniphier_mio_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-ld20-sd-clock",
+		.data = (ulong)uniphier_mio_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pxs3-sd-clock",
+		.data = (ulong)uniphier_mio_clk_data,
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_clk) = {
+	.name = "uniphier-clk",
+	.id = UCLASS_CLK,
+	.of_match = uniphier_clk_match,
+	.probe = uniphier_clk_probe,
+	.priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
+	.ops = &uniphier_clk_ops,
+};

source/bootloader/u-boot-2020.01/drivers/clk/uniphier/clk-uniphier-mio.c

@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include "clk-uniphier.h"
+
+#define UNIPHIER_MIO_CLK_SD_FIXED					\
+	UNIPHIER_CLK_RATE(128, 44444444),				\
+	UNIPHIER_CLK_RATE(129, 33333333),				\
+	UNIPHIER_CLK_RATE(130, 50000000),				\
+	UNIPHIER_CLK_RATE(131, 66666667),				\
+	UNIPHIER_CLK_RATE(132, 100000000),				\
+	UNIPHIER_CLK_RATE(133, 40000000),				\
+	UNIPHIER_CLK_RATE(134, 25000000),				\
+	UNIPHIER_CLK_RATE(135, 22222222)
+
+#define UNIPHIER_MIO_CLK_SD(_id, ch)					\
+	{								\
+		.type = UNIPHIER_CLK_TYPE_MUX,				\
+		.id = (_id) + 32,					\
+		.data.mux = {						\
+			.parent_ids = {					\
+				128,					\
+				129,					\
+				130,					\
+				131,					\
+				132,					\
+				133,					\
+				134,					\
+				135,					\
+			},						\
+			.num_parents = 8,				\
+			.reg = 0x30 + 0x200 * (ch),			\
+			.masks = {					\
+				0x00031000,				\
+				0x00031000,				\
+				0x00031000,				\
+				0x00031000,				\
+				0x00001300,				\
+				0x00001300,				\
+				0x00001300,				\
+				0x00001300,				\
+			},						\
+			.vals = {					\
+				0x00000000,				\
+				0x00010000,				\
+				0x00020000,				\
+				0x00030000,				\
+				0x00001000,				\
+				0x00001100,				\
+				0x00001200,				\
+				0x00001300,				\
+			},						\
+		},							\
+	},								\
+	UNIPHIER_CLK_GATE((_id), (_id) + 32, 0x20 + 0x200 * (ch), 8)
+
+#define UNIPHIER_MIO_CLK_USB2(id, ch)					\
+	UNIPHIER_CLK_GATE_SIMPLE((id), 0x20 + 0x200 * (ch), 28)
+
+#define UNIPHIER_MIO_CLK_USB2_PHY(id, ch)				\
+	UNIPHIER_CLK_GATE_SIMPLE((id), 0x20 + 0x200 * (ch), 29)
+
+#define UNIPHIER_MIO_CLK_DMAC(id)					\
+	UNIPHIER_CLK_GATE_SIMPLE((id), 0x20, 25)
+
+const struct uniphier_clk_data uniphier_mio_clk_data[] = {
+	UNIPHIER_MIO_CLK_SD_FIXED,
+	UNIPHIER_MIO_CLK_SD(0, 0),
+	UNIPHIER_MIO_CLK_SD(1, 1),
+	UNIPHIER_MIO_CLK_SD(2, 2),
+	UNIPHIER_MIO_CLK_DMAC(7),
+	UNIPHIER_MIO_CLK_USB2(8, 0),
+	UNIPHIER_MIO_CLK_USB2(9, 1),
+	UNIPHIER_MIO_CLK_USB2(10, 2),
+	UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
+	UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
+	UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
+	{ /* sentinel */ }
+};

source/bootloader/u-boot-2020.01/drivers/clk/uniphier/clk-uniphier-sys.c

@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016-2017 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include "clk-uniphier.h"
+
+#define UNIPHIER_LD4_SYS_CLK_NAND(_id)					\
+	UNIPHIER_CLK_RATE(128, 50000000),				\
+	UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2)
+
+#define UNIPHIER_LD11_SYS_CLK_NAND(_id)					\
+	UNIPHIER_CLK_RATE(128, 50000000),				\
+	UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0)
+
+const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
+#if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_SLD8) ||\
+    defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\
+    defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
+	UNIPHIER_LD4_SYS_CLK_NAND(2),			/* nand */
+	UNIPHIER_CLK_RATE(3, 200000000),		/* nand-4x */
+	UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12),	/* ether (Pro4, PXs2) */
+	UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5),		/* ether-gb (Pro4) */
+	UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10),	/* stdmac */
+	UNIPHIER_CLK_GATE_SIMPLE(10, 0x2260, 0),	/* ether-phy (Pro4) */
+	UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6),	/* gio (Pro4, Pro5) */
+	UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16),	/* usb30 (Pro4, Pro5, PXs2) */
+	UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17),	/* usb31 (Pro4, Pro5, PXs2) */
+	UNIPHIER_CLK_GATE_SIMPLE(16, 0x2104, 19),	/* usb30-phy (PXs2) */
+	UNIPHIER_CLK_GATE_SIMPLE(20, 0x2104, 20),	/* usb31-phy (PXs2) */
+	{ /* sentinel */ }
+#endif
+};
+
+const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
+#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
+	UNIPHIER_LD11_SYS_CLK_NAND(2),			/* nand */
+	UNIPHIER_CLK_RATE(3, 200000000),		/* nand-4x */
+	UNIPHIER_CLK_GATE_SIMPLE(4, 0x210c, 2),		/* emmc */
+	UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6),		/* ether */
+	UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8),		/* stdmac */
+	UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14),	/* usb30 (LD20) */
+	UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12),	/* usb30-phy0 (LD20) */
+	UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 13),	/* usb30-phy1 (LD20) */
+	{ /* sentinel */ }
+#endif
+};
+
+const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
+#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
+	UNIPHIER_LD11_SYS_CLK_NAND(2),			/* nand */
+	UNIPHIER_CLK_RATE(3, 200000000),		/* nand-4x */
+	UNIPHIER_CLK_GATE_SIMPLE(4, 0x210c, 2),		/* emmc */
+	UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9),		/* ether0 */
+	UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10),	/* ether1 */
+	UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4),	/* usb30 (gio0) */
+	UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5),	/* usb31-0 (gio1) */
+	UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6),	/* usb31-1 (gio1-1) */
+	UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 16),	/* usb30-phy0 */
+	UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 18),	/* usb30-phy1 */
+	UNIPHIER_CLK_GATE_SIMPLE(18, 0x210c, 20),	/* usb30-phy2 */
+	UNIPHIER_CLK_GATE_SIMPLE(20, 0x210c, 17),	/* usb31-phy0 */
+	UNIPHIER_CLK_GATE_SIMPLE(21, 0x210c, 19),	/* usb31-phy1 */
+	{ /* sentinel */ }
+#endif
+};

source/bootloader/u-boot-2020.01/drivers/clk/uniphier/clk-uniphier.h

@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#ifndef __CLK_UNIPHIER_H__
+#define __CLK_UNIPHIER_H__
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#define UNIPHIER_CLK_MUX_MAX_PARENTS		8
+
+#define UNIPHIER_CLK_TYPE_END			0
+#define UNIPHIER_CLK_TYPE_FIXED_RATE		2
+#define UNIPHIER_CLK_TYPE_GATE			3
+#define UNIPHIER_CLK_TYPE_MUX			4
+
+#define UNIPHIER_CLK_ID_INVALID			(U8_MAX)
+
+struct uniphier_clk_fixed_rate_data {
+	unsigned long fixed_rate;
+};
+
+struct uniphier_clk_gate_data {
+	u8 parent_id;
+	u16 reg;
+	u8 bit;
+};
+
+struct uniphier_clk_mux_data {
+	u8 parent_ids[UNIPHIER_CLK_MUX_MAX_PARENTS];
+	u8 num_parents;
+	u16 reg;
+	u32 masks[UNIPHIER_CLK_MUX_MAX_PARENTS];
+	u32 vals[UNIPHIER_CLK_MUX_MAX_PARENTS];
+};
+
+struct uniphier_clk_data {
+	u8 type;
+	u8 id;
+	union {
+		struct uniphier_clk_fixed_rate_data rate;
+		struct uniphier_clk_gate_data gate;
+		struct uniphier_clk_mux_data mux;
+	} data;
+};
+
+#define UNIPHIER_CLK_RATE(_id, _rate)				\
+	{							\
+		.type = UNIPHIER_CLK_TYPE_FIXED_RATE,		\
+		.id = (_id),					\
+		.data.rate = {					\
+			.fixed_rate = (_rate),			\
+		},						\
+	}
+
+#define UNIPHIER_CLK_GATE(_id, _parent, _reg, _bit)		\
+	{							\
+		.type = UNIPHIER_CLK_TYPE_GATE,			\
+		.id = (_id),					\
+		.data.gate = {					\
+			.parent_id = (_parent),			\
+			.reg = (_reg),				\
+			.bit = (_bit),				\
+		},						\
+	}
+
+#define UNIPHIER_CLK_GATE_SIMPLE(_id, _reg, _bit)		\
+	UNIPHIER_CLK_GATE(_id, UNIPHIER_CLK_ID_INVALID, _reg, _bit)
+
+extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
+extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
+extern const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[];
+extern const struct uniphier_clk_data uniphier_mio_clk_data[];
+
+#endif /* __CLK_UNIPHIER_H__ */