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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
21813 changed files with 4413081 additions and 0 deletions
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source/bootloader/u-boot-2020.01/drivers/ddr/imx/imx8m/Kconfig
+32
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menu "i.MX8M DDR controllers"
depends on ARCH_IMX8M
config IMX8M_DRAM
bool "imx8m dram"
config IMX8M_LPDDR4
bool "imx8m lpddr4"
select IMX8M_DRAM
help
Select the i.MX8M LPDDR4 driver support on i.MX8M SOC.
config IMX8M_DDR4
bool "imx8m ddr4"
select IMX8M_DRAM
help
Select the i.MX8M DDR4 driver support on i.MX8M SOC.
config IMX8M_DDR3L
bool "imx8m ddr3l"
select IMX8M_DRAM
help
Select the i.MX8M DDR3L driver support on i.MX8M SOC.
config SAVED_DRAM_TIMING_BASE
hex "Define the base address for saved dram timing"
help
after DRAM is trained, need to save the dram related timming
info into memory for low power use. OCRAM_S is used for this
purpose on i.MX8MM.
default 0x180000
endmenu
source/bootloader/u-boot-2020.01/drivers/ddr/imx/imx8m/Makefile
+9
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@@ -0,0 +1,9 @@
#
# Copyright 2018 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o ddr_init.o
endif
source/bootloader/u-boot-2020.01/drivers/ddr/imx/imx8m/ddr_init.c
+168
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2019 NXP
*/
#include <common.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
{
int i = 0;
for (i = 0; i < num; i++) {
reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
ddrc_cfg++;
}
}
void ddr_init(struct dram_timing_info *dram_timing)
{
unsigned int tmp, initial_drate, target_freq;
debug("DDRINFO: start DRAM init\n");
/* Step1: Follow the power up procedure */
if (is_imx8mq()) {
reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F);
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
} else {
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F);
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
}
debug("DDRINFO: cfg clk\n");
/* change the clock source of dram_apb_clk_root: source 4 800MHz /4 = 200MHz */
clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
/* disable iso */
reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
initial_drate = dram_timing->fsp_msg[0].drate;
/* default to the frequency point 0 clock */
ddrphy_init_set_dfi_clk(initial_drate);
/* D-aasert the presetn */
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
/* Step2: Program the dwc_ddr_umctl2 registers */
debug("DDRINFO: ddrc config start\n");
ddr_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
debug("DDRINFO: ddrc config done\n");
/* Step3: De-assert reset signal(core_ddrc_rstn & aresetn_n) */
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
/*
* Step4: Disable auto-refreshes, self-refresh, powerdown, and
* assertion of dfi_dram_clk_disable by setting RFSHCTL3.dis_auto_refresh = 1,
* PWRCTL.powerdown_en = 0, and PWRCTL.selfref_en = 0, PWRCTL.en_dfi_dram_clk_disable = 0
*/
reg32_write(DDRC_DBG1(0), 0x00000000);
reg32_write(DDRC_RFSHCTL3(0), 0x0000001);
reg32_write(DDRC_PWRCTL(0), 0xa0);
/* if ddr type is LPDDR4, do it */
tmp = reg32_read(DDRC_MSTR(0));
if (tmp & (0x1 << 5))
reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */
/* determine the initial boot frequency */
target_freq = reg32_read(DDRC_MSTR2(0)) & 0x3;
target_freq = (tmp & (0x1 << 29)) ? target_freq : 0x0;
/* Step5: Set SWCT.sw_done to 0 */
reg32_write(DDRC_SWCTL(0), 0x00000000);
/* Set the default boot frequency point */
clrsetbits_le32(DDRC_DFIMISC(0), (0x1f << 8), target_freq << 8);
/* Step6: Set DFIMISC.dfi_init_complete_en to 0 */
clrbits_le32(DDRC_DFIMISC(0), 0x1);
/* Step7: Set SWCTL.sw_done to 1; need to polling SWSTAT.sw_done_ack */
reg32_write(DDRC_SWCTL(0), 0x00000001);
do {
tmp = reg32_read(DDRC_SWSTAT(0));
} while ((tmp & 0x1) == 0x0);
/*
* Step8 ~ Step13: Start PHY initialization and training by
* accessing relevant PUB registers
*/
debug("DDRINFO:ddrphy config start\n");
ddr_cfg_phy(dram_timing);
debug("DDRINFO: ddrphy config done\n");
/*
* step14 CalBusy.0 =1, indicates the calibrator is actively
* calibrating. Wait Calibrating done.
*/
do {
tmp = reg32_read(DDRPHY_CalBusy(0));
} while ((tmp & 0x1));
debug("DDRINFO:ddrphy calibration done\n");
/* Step15: Set SWCTL.sw_done to 0 */
reg32_write(DDRC_SWCTL(0), 0x00000000);
/* Step16: Set DFIMISC.dfi_init_start to 1 */
setbits_le32(DDRC_DFIMISC(0), (0x1 << 5));
/* Step17: Set SWCTL.sw_done to 1; need to polling SWSTAT.sw_done_ack */
reg32_write(DDRC_SWCTL(0), 0x00000001);
do {
tmp = reg32_read(DDRC_SWSTAT(0));
} while ((tmp & 0x1) == 0x0);
/* Step18: Polling DFISTAT.dfi_init_complete = 1 */
do {
tmp = reg32_read(DDRC_DFISTAT(0));
} while ((tmp & 0x1) == 0x0);
/* Step19: Set SWCTL.sw_done to 0 */
reg32_write(DDRC_SWCTL(0), 0x00000000);
/* Step20: Set DFIMISC.dfi_init_start to 0 */
clrbits_le32(DDRC_DFIMISC(0), (0x1 << 5));
/* Step21: optional */
/* Step22: Set DFIMISC.dfi_init_complete_en to 1 */
setbits_le32(DDRC_DFIMISC(0), 0x1);
/* Step23: Set PWRCTL.selfref_sw to 0 */
clrbits_le32(DDRC_PWRCTL(0), (0x1 << 5));
/* Step24: Set SWCTL.sw_done to 1; need polling SWSTAT.sw_done_ack */
reg32_write(DDRC_SWCTL(0), 0x00000001);
do {
tmp = reg32_read(DDRC_SWSTAT(0));
} while ((tmp & 0x1) == 0x0);
/* Step25: Wait for dwc_ddr_umctl2 to move to normal operating mode by monitoring
* STAT.operating_mode signal */
do {
tmp = reg32_read(DDRC_STAT(0));
} while ((tmp & 0x3) != 0x1);
/* Step26: Set back register in Step4 to the original values if desired */
reg32_write(DDRC_RFSHCTL3(0), 0x0000000);
/* enable selfref_en by default */
setbits_le32(DDRC_PWRCTL(0), 0x1 << 3);
/* enable port 0 */
reg32_write(DDRC_PCTRL_0(0), 0x00000001);
debug("DDRINFO: ddrmix config done\n");
/* save the dram timing config into memory */
dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
}
source/bootloader/u-boot-2020.01/drivers/ddr/imx/imx8m/ddrphy_csr.c
+732
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <linux/kernel.h>
#include <asm/arch/ddr.h>
/* ddr phy trained csr */
struct dram_cfg_param ddrphy_trained_csr[] = {
{ 0x200b2, 0x0 },
{ 0x1200b2, 0x0 },
{ 0x2200b2, 0x0 },
{ 0x200cb, 0x0 },
{ 0x10043, 0x0 },
{ 0x110043, 0x0 },
{ 0x210043, 0x0 },
{ 0x10143, 0x0 },
{ 0x110143, 0x0 },
{ 0x210143, 0x0 },
{ 0x11043, 0x0 },
{ 0x111043, 0x0 },
{ 0x211043, 0x0 },
{ 0x11143, 0x0 },
{ 0x111143, 0x0 },
{ 0x211143, 0x0 },
{ 0x12043, 0x0 },
{ 0x112043, 0x0 },
{ 0x212043, 0x0 },
{ 0x12143, 0x0 },
{ 0x112143, 0x0 },
{ 0x212143, 0x0 },
{ 0x13043, 0x0 },
{ 0x113043, 0x0 },
{ 0x213043, 0x0 },
{ 0x13143, 0x0 },
{ 0x113143, 0x0 },
{ 0x213143, 0x0 },
{ 0x80, 0x0 },
{ 0x100080, 0x0 },
{ 0x200080, 0x0 },
{ 0x1080, 0x0 },
{ 0x101080, 0x0 },
{ 0x201080, 0x0 },
{ 0x2080, 0x0 },
{ 0x102080, 0x0 },
{ 0x202080, 0x0 },
{ 0x3080, 0x0 },
{ 0x103080, 0x0 },
{ 0x203080, 0x0 },
{ 0x4080, 0x0 },
{ 0x104080, 0x0 },
{ 0x204080, 0x0 },
{ 0x5080, 0x0 },
{ 0x105080, 0x0 },
{ 0x205080, 0x0 },
{ 0x6080, 0x0 },
{ 0x106080, 0x0 },
{ 0x206080, 0x0 },
{ 0x7080, 0x0 },
{ 0x107080, 0x0 },
{ 0x207080, 0x0 },
{ 0x8080, 0x0 },
{ 0x108080, 0x0 },
{ 0x208080, 0x0 },
{ 0x9080, 0x0 },
{ 0x109080, 0x0 },
{ 0x209080, 0x0 },
{ 0x10080, 0x0 },
{ 0x110080, 0x0 },
{ 0x210080, 0x0 },
{ 0x10180, 0x0 },
{ 0x110180, 0x0 },
{ 0x210180, 0x0 },
{ 0x11080, 0x0 },
{ 0x111080, 0x0 },
{ 0x211080, 0x0 },
{ 0x11180, 0x0 },
{ 0x111180, 0x0 },
{ 0x211180, 0x0 },
{ 0x12080, 0x0 },
{ 0x112080, 0x0 },
{ 0x212080, 0x0 },
{ 0x12180, 0x0 },
{ 0x112180, 0x0 },
{ 0x212180, 0x0 },
{ 0x13080, 0x0 },
{ 0x113080, 0x0 },
{ 0x213080, 0x0 },
{ 0x13180, 0x0 },
{ 0x113180, 0x0 },
{ 0x213180, 0x0 },
{ 0x10081, 0x0 },
{ 0x110081, 0x0 },
{ 0x210081, 0x0 },
{ 0x10181, 0x0 },
{ 0x110181, 0x0 },
{ 0x210181, 0x0 },
{ 0x11081, 0x0 },
{ 0x111081, 0x0 },
{ 0x211081, 0x0 },
{ 0x11181, 0x0 },
{ 0x111181, 0x0 },
{ 0x211181, 0x0 },
{ 0x12081, 0x0 },
{ 0x112081, 0x0 },
{ 0x212081, 0x0 },
{ 0x12181, 0x0 },
{ 0x112181, 0x0 },
{ 0x212181, 0x0 },
{ 0x13081, 0x0 },
{ 0x113081, 0x0 },
{ 0x213081, 0x0 },
{ 0x13181, 0x0 },
{ 0x113181, 0x0 },
{ 0x213181, 0x0 },
{ 0x100d0, 0x0 },
{ 0x1100d0, 0x0 },
{ 0x2100d0, 0x0 },
{ 0x101d0, 0x0 },
{ 0x1101d0, 0x0 },
{ 0x2101d0, 0x0 },
{ 0x110d0, 0x0 },
{ 0x1110d0, 0x0 },
{ 0x2110d0, 0x0 },
{ 0x111d0, 0x0 },
{ 0x1111d0, 0x0 },
{ 0x2111d0, 0x0 },
{ 0x120d0, 0x0 },
{ 0x1120d0, 0x0 },
{ 0x2120d0, 0x0 },
{ 0x121d0, 0x0 },
{ 0x1121d0, 0x0 },
{ 0x2121d0, 0x0 },
{ 0x130d0, 0x0 },
{ 0x1130d0, 0x0 },
{ 0x2130d0, 0x0 },
{ 0x131d0, 0x0 },
{ 0x1131d0, 0x0 },
{ 0x2131d0, 0x0 },
{ 0x100d1, 0x0 },
{ 0x1100d1, 0x0 },
{ 0x2100d1, 0x0 },
{ 0x101d1, 0x0 },
{ 0x1101d1, 0x0 },
{ 0x2101d1, 0x0 },
{ 0x110d1, 0x0 },
{ 0x1110d1, 0x0 },
{ 0x2110d1, 0x0 },
{ 0x111d1, 0x0 },
{ 0x1111d1, 0x0 },
{ 0x2111d1, 0x0 },
{ 0x120d1, 0x0 },
{ 0x1120d1, 0x0 },
{ 0x2120d1, 0x0 },
{ 0x121d1, 0x0 },
{ 0x1121d1, 0x0 },
{ 0x2121d1, 0x0 },
{ 0x130d1, 0x0 },
{ 0x1130d1, 0x0 },
{ 0x2130d1, 0x0 },
{ 0x131d1, 0x0 },
{ 0x1131d1, 0x0 },
{ 0x2131d1, 0x0 },
{ 0x10068, 0x0 },
{ 0x10168, 0x0 },
{ 0x10268, 0x0 },
{ 0x10368, 0x0 },
{ 0x10468, 0x0 },
{ 0x10568, 0x0 },
{ 0x10668, 0x0 },
{ 0x10768, 0x0 },
{ 0x10868, 0x0 },
{ 0x11068, 0x0 },
{ 0x11168, 0x0 },
{ 0x11268, 0x0 },
{ 0x11368, 0x0 },
{ 0x11468, 0x0 },
{ 0x11568, 0x0 },
{ 0x11668, 0x0 },
{ 0x11768, 0x0 },
{ 0x11868, 0x0 },
{ 0x12068, 0x0 },
{ 0x12168, 0x0 },
{ 0x12268, 0x0 },
{ 0x12368, 0x0 },
{ 0x12468, 0x0 },
{ 0x12568, 0x0 },
{ 0x12668, 0x0 },
{ 0x12768, 0x0 },
{ 0x12868, 0x0 },
{ 0x13068, 0x0 },
{ 0x13168, 0x0 },
{ 0x13268, 0x0 },
{ 0x13368, 0x0 },
{ 0x13468, 0x0 },
{ 0x13568, 0x0 },
{ 0x13668, 0x0 },
{ 0x13768, 0x0 },
{ 0x13868, 0x0 },
{ 0x10069, 0x0 },
{ 0x10169, 0x0 },
{ 0x10269, 0x0 },
{ 0x10369, 0x0 },
{ 0x10469, 0x0 },
{ 0x10569, 0x0 },
{ 0x10669, 0x0 },
{ 0x10769, 0x0 },
{ 0x10869, 0x0 },
{ 0x11069, 0x0 },
{ 0x11169, 0x0 },
{ 0x11269, 0x0 },
{ 0x11369, 0x0 },
{ 0x11469, 0x0 },
{ 0x11569, 0x0 },
{ 0x11669, 0x0 },
{ 0x11769, 0x0 },
{ 0x11869, 0x0 },
{ 0x12069, 0x0 },
{ 0x12169, 0x0 },
{ 0x12269, 0x0 },
{ 0x12369, 0x0 },
{ 0x12469, 0x0 },
{ 0x12569, 0x0 },
{ 0x12669, 0x0 },
{ 0x12769, 0x0 },
{ 0x12869, 0x0 },
{ 0x13069, 0x0 },
{ 0x13169, 0x0 },
{ 0x13269, 0x0 },
{ 0x13369, 0x0 },
{ 0x13469, 0x0 },
{ 0x13569, 0x0 },
{ 0x13669, 0x0 },
{ 0x13769, 0x0 },
{ 0x13869, 0x0 },
{ 0x1008c, 0x0 },
{ 0x11008c, 0x0 },
{ 0x21008c, 0x0 },
{ 0x1018c, 0x0 },
{ 0x11018c, 0x0 },
{ 0x21018c, 0x0 },
{ 0x1108c, 0x0 },
{ 0x11108c, 0x0 },
{ 0x21108c, 0x0 },
{ 0x1118c, 0x0 },
{ 0x11118c, 0x0 },
{ 0x21118c, 0x0 },
{ 0x1208c, 0x0 },
{ 0x11208c, 0x0 },
{ 0x21208c, 0x0 },
{ 0x1218c, 0x0 },
{ 0x11218c, 0x0 },
{ 0x21218c, 0x0 },
{ 0x1308c, 0x0 },
{ 0x11308c, 0x0 },
{ 0x21308c, 0x0 },
{ 0x1318c, 0x0 },
{ 0x11318c, 0x0 },
{ 0x21318c, 0x0 },
{ 0x1008d, 0x0 },
{ 0x11008d, 0x0 },
{ 0x21008d, 0x0 },
{ 0x1018d, 0x0 },
{ 0x11018d, 0x0 },
{ 0x21018d, 0x0 },
{ 0x1108d, 0x0 },
{ 0x11108d, 0x0 },
{ 0x21108d, 0x0 },
{ 0x1118d, 0x0 },
{ 0x11118d, 0x0 },
{ 0x21118d, 0x0 },
{ 0x1208d, 0x0 },
{ 0x11208d, 0x0 },
{ 0x21208d, 0x0 },
{ 0x1218d, 0x0 },
{ 0x11218d, 0x0 },
{ 0x21218d, 0x0 },
{ 0x1308d, 0x0 },
{ 0x11308d, 0x0 },
{ 0x21308d, 0x0 },
{ 0x1318d, 0x0 },
{ 0x11318d, 0x0 },
{ 0x21318d, 0x0 },
{ 0x100c0, 0x0 },
{ 0x1100c0, 0x0 },
{ 0x2100c0, 0x0 },
{ 0x101c0, 0x0 },
{ 0x1101c0, 0x0 },
{ 0x2101c0, 0x0 },
{ 0x102c0, 0x0 },
{ 0x1102c0, 0x0 },
{ 0x2102c0, 0x0 },
{ 0x103c0, 0x0 },
{ 0x1103c0, 0x0 },
{ 0x2103c0, 0x0 },
{ 0x104c0, 0x0 },
{ 0x1104c0, 0x0 },
{ 0x2104c0, 0x0 },
{ 0x105c0, 0x0 },
{ 0x1105c0, 0x0 },
{ 0x2105c0, 0x0 },
{ 0x106c0, 0x0 },
{ 0x1106c0, 0x0 },
{ 0x2106c0, 0x0 },
{ 0x107c0, 0x0 },
{ 0x1107c0, 0x0 },
{ 0x2107c0, 0x0 },
{ 0x108c0, 0x0 },
{ 0x1108c0, 0x0 },
{ 0x2108c0, 0x0 },
{ 0x110c0, 0x0 },
{ 0x1110c0, 0x0 },
{ 0x2110c0, 0x0 },
{ 0x111c0, 0x0 },
{ 0x1111c0, 0x0 },
{ 0x2111c0, 0x0 },
{ 0x112c0, 0x0 },
{ 0x1112c0, 0x0 },
{ 0x2112c0, 0x0 },
{ 0x113c0, 0x0 },
{ 0x1113c0, 0x0 },
{ 0x2113c0, 0x0 },
{ 0x114c0, 0x0 },
{ 0x1114c0, 0x0 },
{ 0x2114c0, 0x0 },
{ 0x115c0, 0x0 },
{ 0x1115c0, 0x0 },
{ 0x2115c0, 0x0 },
{ 0x116c0, 0x0 },
{ 0x1116c0, 0x0 },
{ 0x2116c0, 0x0 },
{ 0x117c0, 0x0 },
{ 0x1117c0, 0x0 },
{ 0x2117c0, 0x0 },
{ 0x118c0, 0x0 },
{ 0x1118c0, 0x0 },
{ 0x2118c0, 0x0 },
{ 0x120c0, 0x0 },
{ 0x1120c0, 0x0 },
{ 0x2120c0, 0x0 },
{ 0x121c0, 0x0 },
{ 0x1121c0, 0x0 },
{ 0x2121c0, 0x0 },
{ 0x122c0, 0x0 },
{ 0x1122c0, 0x0 },
{ 0x2122c0, 0x0 },
{ 0x123c0, 0x0 },
{ 0x1123c0, 0x0 },
{ 0x2123c0, 0x0 },
{ 0x124c0, 0x0 },
{ 0x1124c0, 0x0 },
{ 0x2124c0, 0x0 },
{ 0x125c0, 0x0 },
{ 0x1125c0, 0x0 },
{ 0x2125c0, 0x0 },
{ 0x126c0, 0x0 },
{ 0x1126c0, 0x0 },
{ 0x2126c0, 0x0 },
{ 0x127c0, 0x0 },
{ 0x1127c0, 0x0 },
{ 0x2127c0, 0x0 },
{ 0x128c0, 0x0 },
{ 0x1128c0, 0x0 },
{ 0x2128c0, 0x0 },
{ 0x130c0, 0x0 },
{ 0x1130c0, 0x0 },
{ 0x2130c0, 0x0 },
{ 0x131c0, 0x0 },
{ 0x1131c0, 0x0 },
{ 0x2131c0, 0x0 },
{ 0x132c0, 0x0 },
{ 0x1132c0, 0x0 },
{ 0x2132c0, 0x0 },
{ 0x133c0, 0x0 },
{ 0x1133c0, 0x0 },
{ 0x2133c0, 0x0 },
{ 0x134c0, 0x0 },
{ 0x1134c0, 0x0 },
{ 0x2134c0, 0x0 },
{ 0x135c0, 0x0 },
{ 0x1135c0, 0x0 },
{ 0x2135c0, 0x0 },
{ 0x136c0, 0x0 },
{ 0x1136c0, 0x0 },
{ 0x2136c0, 0x0 },
{ 0x137c0, 0x0 },
{ 0x1137c0, 0x0 },
{ 0x2137c0, 0x0 },
{ 0x138c0, 0x0 },
{ 0x1138c0, 0x0 },
{ 0x2138c0, 0x0 },
{ 0x100c1, 0x0 },
{ 0x1100c1, 0x0 },
{ 0x2100c1, 0x0 },
{ 0x101c1, 0x0 },
{ 0x1101c1, 0x0 },
{ 0x2101c1, 0x0 },
{ 0x102c1, 0x0 },
{ 0x1102c1, 0x0 },
{ 0x2102c1, 0x0 },
{ 0x103c1, 0x0 },
{ 0x1103c1, 0x0 },
{ 0x2103c1, 0x0 },
{ 0x104c1, 0x0 },
{ 0x1104c1, 0x0 },
{ 0x2104c1, 0x0 },
{ 0x105c1, 0x0 },
{ 0x1105c1, 0x0 },
{ 0x2105c1, 0x0 },
{ 0x106c1, 0x0 },
{ 0x1106c1, 0x0 },
{ 0x2106c1, 0x0 },
{ 0x107c1, 0x0 },
{ 0x1107c1, 0x0 },
{ 0x2107c1, 0x0 },
{ 0x108c1, 0x0 },
{ 0x1108c1, 0x0 },
{ 0x2108c1, 0x0 },
{ 0x110c1, 0x0 },
{ 0x1110c1, 0x0 },
{ 0x2110c1, 0x0 },
{ 0x111c1, 0x0 },
{ 0x1111c1, 0x0 },
{ 0x2111c1, 0x0 },
{ 0x112c1, 0x0 },
{ 0x1112c1, 0x0 },
{ 0x2112c1, 0x0 },
{ 0x113c1, 0x0 },
{ 0x1113c1, 0x0 },
{ 0x2113c1, 0x0 },
{ 0x114c1, 0x0 },
{ 0x1114c1, 0x0 },
{ 0x2114c1, 0x0 },
{ 0x115c1, 0x0 },
{ 0x1115c1, 0x0 },
{ 0x2115c1, 0x0 },
{ 0x116c1, 0x0 },
{ 0x1116c1, 0x0 },
{ 0x2116c1, 0x0 },
{ 0x117c1, 0x0 },
{ 0x1117c1, 0x0 },
{ 0x2117c1, 0x0 },
{ 0x118c1, 0x0 },
{ 0x1118c1, 0x0 },
{ 0x2118c1, 0x0 },
{ 0x120c1, 0x0 },
{ 0x1120c1, 0x0 },
{ 0x2120c1, 0x0 },
{ 0x121c1, 0x0 },
{ 0x1121c1, 0x0 },
{ 0x2121c1, 0x0 },
{ 0x122c1, 0x0 },
{ 0x1122c1, 0x0 },
{ 0x2122c1, 0x0 },
{ 0x123c1, 0x0 },
{ 0x1123c1, 0x0 },
{ 0x2123c1, 0x0 },
{ 0x124c1, 0x0 },
{ 0x1124c1, 0x0 },
{ 0x2124c1, 0x0 },
{ 0x125c1, 0x0 },
{ 0x1125c1, 0x0 },
{ 0x2125c1, 0x0 },
{ 0x126c1, 0x0 },
{ 0x1126c1, 0x0 },
{ 0x2126c1, 0x0 },
{ 0x127c1, 0x0 },
{ 0x1127c1, 0x0 },
{ 0x2127c1, 0x0 },
{ 0x128c1, 0x0 },
{ 0x1128c1, 0x0 },
{ 0x2128c1, 0x0 },
{ 0x130c1, 0x0 },
{ 0x1130c1, 0x0 },
{ 0x2130c1, 0x0 },
{ 0x131c1, 0x0 },
{ 0x1131c1, 0x0 },
{ 0x2131c1, 0x0 },
{ 0x132c1, 0x0 },
{ 0x1132c1, 0x0 },
{ 0x2132c1, 0x0 },
{ 0x133c1, 0x0 },
{ 0x1133c1, 0x0 },
{ 0x2133c1, 0x0 },
{ 0x134c1, 0x0 },
{ 0x1134c1, 0x0 },
{ 0x2134c1, 0x0 },
{ 0x135c1, 0x0 },
{ 0x1135c1, 0x0 },
{ 0x2135c1, 0x0 },
{ 0x136c1, 0x0 },
{ 0x1136c1, 0x0 },
{ 0x2136c1, 0x0 },
{ 0x137c1, 0x0 },
{ 0x1137c1, 0x0 },
{ 0x2137c1, 0x0 },
{ 0x138c1, 0x0 },
{ 0x1138c1, 0x0 },
{ 0x2138c1, 0x0 },
{ 0x10020, 0x0 },
{ 0x110020, 0x0 },
{ 0x210020, 0x0 },
{ 0x11020, 0x0 },
{ 0x111020, 0x0 },
{ 0x211020, 0x0 },
{ 0x12020, 0x0 },
{ 0x112020, 0x0 },
{ 0x212020, 0x0 },
{ 0x13020, 0x0 },
{ 0x113020, 0x0 },
{ 0x213020, 0x0 },
{ 0x20072, 0x0 },
{ 0x20073, 0x0 },
{ 0x20074, 0x0 },
{ 0x100aa, 0x0 },
{ 0x110aa, 0x0 },
{ 0x120aa, 0x0 },
{ 0x130aa, 0x0 },
{ 0x20010, 0x0 },
{ 0x120010, 0x0 },
{ 0x220010, 0x0 },
{ 0x20011, 0x0 },
{ 0x120011, 0x0 },
{ 0x220011, 0x0 },
{ 0x100ae, 0x0 },
{ 0x1100ae, 0x0 },
{ 0x2100ae, 0x0 },
{ 0x100af, 0x0 },
{ 0x1100af, 0x0 },
{ 0x2100af, 0x0 },
{ 0x110ae, 0x0 },
{ 0x1110ae, 0x0 },
{ 0x2110ae, 0x0 },
{ 0x110af, 0x0 },
{ 0x1110af, 0x0 },
{ 0x2110af, 0x0 },
{ 0x120ae, 0x0 },
{ 0x1120ae, 0x0 },
{ 0x2120ae, 0x0 },
{ 0x120af, 0x0 },
{ 0x1120af, 0x0 },
{ 0x2120af, 0x0 },
{ 0x130ae, 0x0 },
{ 0x1130ae, 0x0 },
{ 0x2130ae, 0x0 },
{ 0x130af, 0x0 },
{ 0x1130af, 0x0 },
{ 0x2130af, 0x0 },
{ 0x20020, 0x0 },
{ 0x120020, 0x0 },
{ 0x220020, 0x0 },
{ 0x100a0, 0x0 },
{ 0x100a1, 0x0 },
{ 0x100a2, 0x0 },
{ 0x100a3, 0x0 },
{ 0x100a4, 0x0 },
{ 0x100a5, 0x0 },
{ 0x100a6, 0x0 },
{ 0x100a7, 0x0 },
{ 0x110a0, 0x0 },
{ 0x110a1, 0x0 },
{ 0x110a2, 0x0 },
{ 0x110a3, 0x0 },
{ 0x110a4, 0x0 },
{ 0x110a5, 0x0 },
{ 0x110a6, 0x0 },
{ 0x110a7, 0x0 },
{ 0x120a0, 0x0 },
{ 0x120a1, 0x0 },
{ 0x120a2, 0x0 },
{ 0x120a3, 0x0 },
{ 0x120a4, 0x0 },
{ 0x120a5, 0x0 },
{ 0x120a6, 0x0 },
{ 0x120a7, 0x0 },
{ 0x130a0, 0x0 },
{ 0x130a1, 0x0 },
{ 0x130a2, 0x0 },
{ 0x130a3, 0x0 },
{ 0x130a4, 0x0 },
{ 0x130a5, 0x0 },
{ 0x130a6, 0x0 },
{ 0x130a7, 0x0 },
{ 0x2007c, 0x0 },
{ 0x12007c, 0x0 },
{ 0x22007c, 0x0 },
{ 0x2007d, 0x0 },
{ 0x12007d, 0x0 },
{ 0x22007d, 0x0 },
{ 0x400fd, 0x0 },
{ 0x400c0, 0x0 },
{ 0x90201, 0x0 },
{ 0x190201, 0x0 },
{ 0x290201, 0x0 },
{ 0x90202, 0x0 },
{ 0x190202, 0x0 },
{ 0x290202, 0x0 },
{ 0x90203, 0x0 },
{ 0x190203, 0x0 },
{ 0x290203, 0x0 },
{ 0x90204, 0x0 },
{ 0x190204, 0x0 },
{ 0x290204, 0x0 },
{ 0x90205, 0x0 },
{ 0x190205, 0x0 },
{ 0x290205, 0x0 },
{ 0x90206, 0x0 },
{ 0x190206, 0x0 },
{ 0x290206, 0x0 },
{ 0x90207, 0x0 },
{ 0x190207, 0x0 },
{ 0x290207, 0x0 },
{ 0x90208, 0x0 },
{ 0x190208, 0x0 },
{ 0x290208, 0x0 },
{ 0x10062, 0x0 },
{ 0x10162, 0x0 },
{ 0x10262, 0x0 },
{ 0x10362, 0x0 },
{ 0x10462, 0x0 },
{ 0x10562, 0x0 },
{ 0x10662, 0x0 },
{ 0x10762, 0x0 },
{ 0x10862, 0x0 },
{ 0x11062, 0x0 },
{ 0x11162, 0x0 },
{ 0x11262, 0x0 },
{ 0x11362, 0x0 },
{ 0x11462, 0x0 },
{ 0x11562, 0x0 },
{ 0x11662, 0x0 },
{ 0x11762, 0x0 },
{ 0x11862, 0x0 },
{ 0x12062, 0x0 },
{ 0x12162, 0x0 },
{ 0x12262, 0x0 },
{ 0x12362, 0x0 },
{ 0x12462, 0x0 },
{ 0x12562, 0x0 },
{ 0x12662, 0x0 },
{ 0x12762, 0x0 },
{ 0x12862, 0x0 },
{ 0x13062, 0x0 },
{ 0x13162, 0x0 },
{ 0x13262, 0x0 },
{ 0x13362, 0x0 },
{ 0x13462, 0x0 },
{ 0x13562, 0x0 },
{ 0x13662, 0x0 },
{ 0x13762, 0x0 },
{ 0x13862, 0x0 },
{ 0x20077, 0x0 },
{ 0x10001, 0x0 },
{ 0x11001, 0x0 },
{ 0x12001, 0x0 },
{ 0x13001, 0x0 },
{ 0x10040, 0x0 },
{ 0x10140, 0x0 },
{ 0x10240, 0x0 },
{ 0x10340, 0x0 },
{ 0x10440, 0x0 },
{ 0x10540, 0x0 },
{ 0x10640, 0x0 },
{ 0x10740, 0x0 },
{ 0x10840, 0x0 },
{ 0x10030, 0x0 },
{ 0x10130, 0x0 },
{ 0x10230, 0x0 },
{ 0x10330, 0x0 },
{ 0x10430, 0x0 },
{ 0x10530, 0x0 },
{ 0x10630, 0x0 },
{ 0x10730, 0x0 },
{ 0x10830, 0x0 },
{ 0x11040, 0x0 },
{ 0x11140, 0x0 },
{ 0x11240, 0x0 },
{ 0x11340, 0x0 },
{ 0x11440, 0x0 },
{ 0x11540, 0x0 },
{ 0x11640, 0x0 },
{ 0x11740, 0x0 },
{ 0x11840, 0x0 },
{ 0x11030, 0x0 },
{ 0x11130, 0x0 },
{ 0x11230, 0x0 },
{ 0x11330, 0x0 },
{ 0x11430, 0x0 },
{ 0x11530, 0x0 },
{ 0x11630, 0x0 },
{ 0x11730, 0x0 },
{ 0x11830, 0x0 },
{ 0x12040, 0x0 },
{ 0x12140, 0x0 },
{ 0x12240, 0x0 },
{ 0x12340, 0x0 },
{ 0x12440, 0x0 },
{ 0x12540, 0x0 },
{ 0x12640, 0x0 },
{ 0x12740, 0x0 },
{ 0x12840, 0x0 },
{ 0x12030, 0x0 },
{ 0x12130, 0x0 },
{ 0x12230, 0x0 },
{ 0x12330, 0x0 },
{ 0x12430, 0x0 },
{ 0x12530, 0x0 },
{ 0x12630, 0x0 },
{ 0x12730, 0x0 },
{ 0x12830, 0x0 },
{ 0x13040, 0x0 },
{ 0x13140, 0x0 },
{ 0x13240, 0x0 },
{ 0x13340, 0x0 },
{ 0x13440, 0x0 },
{ 0x13540, 0x0 },
{ 0x13640, 0x0 },
{ 0x13740, 0x0 },
{ 0x13840, 0x0 },
{ 0x13030, 0x0 },
{ 0x13130, 0x0 },
{ 0x13230, 0x0 },
{ 0x13330, 0x0 },
{ 0x13430, 0x0 },
{ 0x13530, 0x0 },
{ 0x13630, 0x0 },
{ 0x13730, 0x0 },
{ 0x13830, 0x0 },
};
uint32_t ddrphy_trained_csr_num = ARRAY_SIZE(ddrphy_trained_csr);
source/bootloader/u-boot-2020.01/drivers/ddr/imx/imx8m/ddrphy_train.c
+86
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@@ -0,0 +1,86 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <common.h>
#include <linux/kernel.h>
#include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
void ddr_cfg_phy(struct dram_timing_info *dram_timing)
{
struct dram_cfg_param *dram_cfg;
struct dram_fsp_msg *fsp_msg;
unsigned int num;
int i = 0;
int j = 0;
/* initialize PHY configuration */
dram_cfg = dram_timing->ddrphy_cfg;
num = dram_timing->ddrphy_cfg_num;
for (i = 0; i < num; i++) {
/* config phy reg */
dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
dram_cfg++;
}
/* load the frequency setpoint message block config */
fsp_msg = dram_timing->fsp_msg;
for (i = 0; i < dram_timing->fsp_msg_num; i++) {
debug("DRAM PHY training for %dMTS\n", fsp_msg->drate);
/* set dram PHY input clocks to desired frequency */
ddrphy_init_set_dfi_clk(fsp_msg->drate);
/* load the dram training firmware image */
dwc_ddrphy_apb_wr(0xd0000, 0x0);
ddr_load_train_firmware(fsp_msg->fw_type);
/* load the frequency set point message block parameter */
dram_cfg = fsp_msg->fsp_cfg;
num = fsp_msg->fsp_cfg_num;
for (j = 0; j < num; j++) {
dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
dram_cfg++;
}
/*
* -------------------- excute the firmware --------------------
* Running the firmware is a simply process to taking the
* PMU out of reset and stall, then the firwmare will be run
* 1. reset the PMU;
* 2. begin the excution;
* 3. wait for the training done;
* 4. read the message block result.
* -------------------------------------------------------------
*/
dwc_ddrphy_apb_wr(0xd0000, 0x1);
dwc_ddrphy_apb_wr(0xd0099, 0x9);
dwc_ddrphy_apb_wr(0xd0099, 0x1);
dwc_ddrphy_apb_wr(0xd0099, 0x0);
/* Wait for the training firmware to complete */
wait_ddrphy_training_complete();
/* Halt the microcontroller. */
dwc_ddrphy_apb_wr(0xd0099, 0x1);
/* Read the Message Block results */
dwc_ddrphy_apb_wr(0xd0000, 0x0);
ddrphy_init_read_msg_block(fsp_msg->fw_type);
dwc_ddrphy_apb_wr(0xd0000, 0x1);
fsp_msg++;
}
/* Load PHY Init Engine Image */
dram_cfg = dram_timing->ddrphy_pie;
num = dram_timing->ddrphy_pie_num;
for (i = 0; i < num; i++) {
dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
dram_cfg++;
}
/* save the ddr PHY trained CSR in memory for low power use */
ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num);
}
source/bootloader/u-boot-2020.01/drivers/ddr/imx/imx8m/ddrphy_utils.c
+190
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@@ -0,0 +1,190 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <common.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <asm/arch/clock.h>
#include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
static inline void poll_pmu_message_ready(void)
{
unsigned int reg;
do {
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
} while (reg & 0x1);
}
static inline void ack_pmu_message_receive(void)
{
unsigned int reg;
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0);
do {
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
} while (!(reg & 0x1));
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1);
}
static inline unsigned int get_mail(void)
{
unsigned int reg;
poll_pmu_message_ready();
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
ack_pmu_message_receive();
return reg;
}
static inline unsigned int get_stream_message(void)
{
unsigned int reg, reg2;
poll_pmu_message_ready();
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034);
reg2 = (reg2 << 16) | reg;
ack_pmu_message_receive();
return reg2;
}
static inline void decode_major_message(unsigned int mail)
{
debug("[PMU Major message = 0x%08x]\n", mail);
}
static inline void decode_streaming_message(void)
{
unsigned int string_index, arg __maybe_unused;
int i = 0;
string_index = get_stream_message();
debug("PMU String index = 0x%08x\n", string_index);
while (i < (string_index & 0xffff)) {
arg = get_stream_message();
debug("arg[%d] = 0x%08x\n", i, arg);
i++;
}
debug("\n");
}
void wait_ddrphy_training_complete(void)
{
unsigned int mail;
while (1) {
mail = get_mail();
decode_major_message(mail);
if (mail == 0x08) {
decode_streaming_message();
} else if (mail == 0x07) {
debug("Training PASS\n");
break;
} else if (mail == 0xff) {
printf("Training FAILED\n");
break;
}
}
}
void ddrphy_init_set_dfi_clk(unsigned int drate)
{
switch (drate) {
case 3200:
dram_pll_init(MHZ(800));
dram_disable_bypass();
break;
case 3000:
dram_pll_init(MHZ(750));
dram_disable_bypass();
break;
case 2400:
dram_pll_init(MHZ(600));
dram_disable_bypass();
break;
case 1600:
dram_pll_init(MHZ(400));
dram_disable_bypass();
break;
case 1066:
dram_pll_init(MHZ(266));
dram_disable_bypass();
break;
case 667:
dram_pll_init(MHZ(167));
dram_disable_bypass();
break;
case 400:
dram_enable_bypass(MHZ(400));
break;
case 100:
dram_enable_bypass(MHZ(100));
break;
default:
return;
}
}
void ddrphy_init_read_msg_block(enum fw_type type)
{
}
void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr,
unsigned int mr_data)
{
unsigned int tmp;
/*
* 1. Poll MRSTAT.mr_wr_busy until it is 0.
* This checks that there is no outstanding MR transaction.
* No writes should be performed to MRCTRL0 and MRCTRL1 if
* MRSTAT.mr_wr_busy = 1.
*/
do {
tmp = reg32_read(DDRC_MRSTAT(0));
} while (tmp & 0x1);
/*
* 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and
* (for MRWs) MRCTRL1.mr_data to define the MR transaction.
*/
reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4));
reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data);
reg32setbit(DDRC_MRCTRL0(0), 31);
}
unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
{
unsigned int tmp;
reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1);
do {
tmp = reg32_read(DDRC_MRSTAT(0));
} while (tmp & 0x1);
reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8));
reg32setbit(DDRC_MRCTRL0(0), 31);
do {
tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
} while ((tmp & 0x8) == 0);
tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
tmp = tmp & 0xff;
reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
return tmp;
}
source/bootloader/u-boot-2020.01/drivers/ddr/imx/imx8m/helper.c
+180
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@@ -0,0 +1,180 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <common.h>
#include <spl.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
#define IMEM_LEN 32768 /* byte */
#define DMEM_LEN 16384 /* byte */
#define IMEM_2D_OFFSET 49152
#define IMEM_OFFSET_ADDR 0x00050000
#define DMEM_OFFSET_ADDR 0x00054000
#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
/* We need PHY iMEM PHY is 32KB padded */
void ddr_load_train_firmware(enum fw_type type)
{
u32 tmp32, i;
u32 error = 0;
unsigned long pr_to32, pr_from32;
unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
unsigned long imem_start = (unsigned long)&_end + fw_offset;
unsigned long dmem_start;
#ifdef CONFIG_SPL_OF_CONTROL
if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) {
imem_start = roundup((unsigned long)&_end +
fdt_totalsize(gd->fdt_blob), 4) +
fw_offset;
}
#endif
dmem_start = imem_start + IMEM_LEN;
pr_from32 = imem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
for (i = 0x0; i < IMEM_LEN; ) {
tmp32 = readl(pr_from32);
writew(tmp32 & 0x0000ffff, pr_to32);
pr_to32 += 4;
writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
pr_to32 += 4;
pr_from32 += 4;
i += 4;
}
pr_from32 = dmem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
for (i = 0x0; i < DMEM_LEN; ) {
tmp32 = readl(pr_from32);
writew(tmp32 & 0x0000ffff, pr_to32);
pr_to32 += 4;
writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
pr_to32 += 4;
pr_from32 += 4;
i += 4;
}
debug("check ddr_pmu_train_imem code\n");
pr_from32 = imem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
for (i = 0x0; i < IMEM_LEN; ) {
tmp32 = (readw(pr_to32) & 0x0000ffff);
pr_to32 += 4;
tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
if (tmp32 != readl(pr_from32)) {
debug("%lx %lx\n", pr_from32, pr_to32);
error++;
}
pr_from32 += 4;
pr_to32 += 4;
i += 4;
}
if (error)
printf("check ddr_pmu_train_imem code fail=%d\n", error);
else
debug("check ddr_pmu_train_imem code pass\n");
debug("check ddr4_pmu_train_dmem code\n");
pr_from32 = dmem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
for (i = 0x0; i < DMEM_LEN;) {
tmp32 = (readw(pr_to32) & 0x0000ffff);
pr_to32 += 4;
tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
if (tmp32 != readl(pr_from32)) {
debug("%lx %lx\n", pr_from32, pr_to32);
error++;
}
pr_from32 += 4;
pr_to32 += 4;
i += 4;
}
if (error)
printf("check ddr_pmu_train_dmem code fail=%d", error);
else
debug("check ddr_pmu_train_dmem code pass\n");
}
void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr,
unsigned int num)
{
int i = 0;
/* enable the ddrphy apb */
dwc_ddrphy_apb_wr(0xd0000, 0x0);
dwc_ddrphy_apb_wr(0xc0080, 0x3);
for (i = 0; i < num; i++) {
ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg);
ddrphy_csr++;
}
/* disable the ddrphy apb */
dwc_ddrphy_apb_wr(0xc0080, 0x2);
dwc_ddrphy_apb_wr(0xd0000, 0x1);
}
void dram_config_save(struct dram_timing_info *timing_info,
unsigned long saved_timing_base)
{
int i = 0;
struct dram_timing_info *saved_timing = (struct dram_timing_info *)saved_timing_base;
struct dram_cfg_param *cfg;
saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num;
saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num;
saved_timing->ddrphy_trained_csr_num = ddrphy_trained_csr_num;
saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num;
/* save the fsp table */
for (i = 0; i < 4; i++)
saved_timing->fsp_table[i] = timing_info->fsp_table[i];
cfg = (struct dram_cfg_param *)(saved_timing_base +
sizeof(*timing_info));
/* save ddrc config */
saved_timing->ddrc_cfg = cfg;
for (i = 0; i < timing_info->ddrc_cfg_num; i++) {
cfg->reg = timing_info->ddrc_cfg[i].reg;
cfg->val = timing_info->ddrc_cfg[i].val;
cfg++;
}
/* save ddrphy config */
saved_timing->ddrphy_cfg = cfg;
for (i = 0; i < timing_info->ddrphy_cfg_num; i++) {
cfg->reg = timing_info->ddrphy_cfg[i].reg;
cfg->val = timing_info->ddrphy_cfg[i].val;
cfg++;
}
/* save the ddrphy csr */
saved_timing->ddrphy_trained_csr = cfg;
for (i = 0; i < ddrphy_trained_csr_num; i++) {
cfg->reg = ddrphy_trained_csr[i].reg;
cfg->val = ddrphy_trained_csr[i].val;
cfg++;
}
/* save the ddrphy pie */
saved_timing->ddrphy_pie = cfg;
for (i = 0; i < timing_info->ddrphy_pie_num; i++) {
cfg->reg = timing_info->ddrphy_pie[i].reg;
cfg->val = timing_info->ddrphy_pie[i].val;
cfg++;
}
}