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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
21813 changed files with 4413081 additions and 0 deletions
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source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/Makefile
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# SPDX-License-Identifier: GPL-2.0+
obj-$(CONFIG_SPL_BUILD) += mv_ddr_plat.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr_sys_env_lib.o
obj-$(CONFIG_SPL_BUILD) += ddr3_debug.o
obj-$(CONFIG_SPL_BUILD) += ddr3_init.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_bist.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_centralization.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_db.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_hw_algo.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_ip_engine.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_leveling.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_pbs.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr_build_message.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr_common.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr_spd.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr_topology.o
obj-$(CONFIG_SPL_BUILD) += xor.o
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_debug.c
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source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_init.c
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#include "ddr3_init.h"
#include "mv_ddr_common.h"
static char *ddr_type = "DDR3";
/*
* generic_init_controller controls D-unit configuration:
* '1' - dynamic D-unit configuration,
*/
u8 generic_init_controller = 1;
static int mv_ddr_training_params_set(u8 dev_num);
/*
* Name: ddr3_init - Main DDR3 Init function
* Desc: This routine initialize the DDR3 MC and runs HW training.
* Args: None.
* Notes:
* Returns: None.
*/
int ddr3_init(void)
{
int status;
int is_manual_cal_done;
/* Print mv_ddr version */
mv_ddr_ver_print();
mv_ddr_pre_training_fixup();
/* SoC/Board special initializations */
mv_ddr_pre_training_soc_config(ddr_type);
/* Set log level for training library */
mv_ddr_user_log_level_set(DEBUG_BLOCK_ALL);
mv_ddr_early_init();
if (mv_ddr_topology_map_update()) {
printf("mv_ddr: failed to update topology\n");
return MV_FAIL;
}
if (mv_ddr_early_init2() != MV_OK)
return MV_FAIL;
/* Set training algorithm's parameters */
status = mv_ddr_training_params_set(0);
if (MV_OK != status)
return status;
mv_ddr_mc_config();
is_manual_cal_done = mv_ddr_manual_cal_do();
mv_ddr_mc_init();
if (!is_manual_cal_done) {
}
status = ddr3_silicon_post_init();
if (MV_OK != status) {
printf("DDR3 Post Init - FAILED 0x%x\n", status);
return status;
}
/* PHY initialization (Training) */
status = hws_ddr3_tip_run_alg(0, ALGO_TYPE_DYNAMIC);
if (MV_OK != status) {
printf("%s Training Sequence - FAILED\n", ddr_type);
return status;
}
#if defined(CONFIG_PHY_STATIC_PRINT)
mv_ddr_phy_static_print();
#endif
/* Post MC/PHY initializations */
mv_ddr_post_training_soc_config(ddr_type);
mv_ddr_post_training_fixup();
if (mv_ddr_is_ecc_ena())
mv_ddr_mem_scrubbing();
printf("mv_ddr: completed successfully\n");
return MV_OK;
}
/*
* Name: mv_ddr_training_params_set
* Desc:
* Args:
* Notes: sets internal training params
* Returns:
*/
static int mv_ddr_training_params_set(u8 dev_num)
{
struct tune_train_params params;
int status;
u32 cs_num;
cs_num = mv_ddr_cs_num_get();
/* NOTE: do not remove any field initilization */
params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY;
params.phy_reg3_val = TUNE_TRAINING_PARAMS_PHYREG3VAL;
params.g_zpri_data = TUNE_TRAINING_PARAMS_PRI_DATA;
params.g_znri_data = TUNE_TRAINING_PARAMS_NRI_DATA;
params.g_zpri_ctrl = TUNE_TRAINING_PARAMS_PRI_CTRL;
params.g_znri_ctrl = TUNE_TRAINING_PARAMS_NRI_CTRL;
params.g_znodt_data = TUNE_TRAINING_PARAMS_N_ODT_DATA;
params.g_zpodt_ctrl = TUNE_TRAINING_PARAMS_P_ODT_CTRL;
params.g_znodt_ctrl = TUNE_TRAINING_PARAMS_N_ODT_CTRL;
params.g_zpodt_data = TUNE_TRAINING_PARAMS_P_ODT_DATA;
params.g_dic = TUNE_TRAINING_PARAMS_DIC;
params.g_rtt_nom = TUNE_TRAINING_PARAMS_RTT_NOM;
if (cs_num == 1) {
params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_1CS;
params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS;
} else {
params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_2CS;
params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS;
}
status = ddr3_tip_tune_training_params(dev_num, &params);
if (MV_OK != status) {
printf("%s Training Sequence - FAILED\n", ddr_type);
return status;
}
return MV_OK;
}
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_init.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR3_INIT_H
#define _DDR3_INIT_H
#include "ddr_ml_wrapper.h"
#include "mv_ddr_plat.h"
#include "seq_exec.h"
#include "ddr3_logging_def.h"
#include "ddr3_training_hw_algo.h"
#include "ddr3_training_ip.h"
#include "ddr3_training_ip_centralization.h"
#include "ddr3_training_ip_engine.h"
#include "ddr3_training_ip_flow.h"
#include "ddr3_training_ip_pbs.h"
#include "ddr3_training_ip_prv_if.h"
#include "ddr3_training_leveling.h"
#include "xor.h"
/* For checking function return values */
#define CHECK_STATUS(orig_func) \
{ \
int status; \
status = orig_func; \
if (MV_OK != status) \
return status; \
}
#define SUB_VERSION 0
enum log_level {
MV_LOG_LEVEL_0,
MV_LOG_LEVEL_1,
MV_LOG_LEVEL_2,
MV_LOG_LEVEL_3
};
/* TODO: consider to move to misl phy driver */
#define MISL_PHY_DRV_P_OFFS 0x7
#define MISL_PHY_DRV_N_OFFS 0x0
#define MISL_PHY_ODT_P_OFFS 0x6
#define MISL_PHY_ODT_N_OFFS 0x0
/* Globals */
extern u8 debug_training, debug_calibration, debug_ddr4_centralization,
debug_tap_tuning, debug_dm_tuning;
extern u8 is_reg_dump;
extern u8 generic_init_controller;
/* list of allowed frequency listed in order of enum mv_ddr_freq */
extern u32 is_pll_old;
extern struct pattern_info pattern_table[];
extern u8 debug_centralization, debug_training_ip, debug_training_bist,
debug_pbs, debug_training_static, debug_leveling;
extern struct hws_tip_config_func_db config_func_info[];
extern u8 twr_mask_table[];
extern u8 cl_mask_table[];
extern u8 cwl_mask_table[];
extern u32 speed_bin_table_t_rc[];
extern u32 speed_bin_table_t_rcd_t_rp[];
extern u32 vref_init_val;
extern u32 g_zpri_data;
extern u32 g_znri_data;
extern u32 g_zpri_ctrl;
extern u32 g_znri_ctrl;
extern u32 g_zpodt_data;
extern u32 g_znodt_data;
extern u32 g_zpodt_ctrl;
extern u32 g_znodt_ctrl;
extern u32 g_dic;
extern u32 g_odt_config;
extern u32 g_rtt_nom;
extern u32 g_rtt_wr;
extern u32 g_rtt_park;
extern u8 debug_training_access;
extern u32 first_active_if;
extern u32 delay_enable, ck_delay, ca_delay;
extern u32 mask_tune_func;
extern u32 rl_version;
extern int rl_mid_freq_wa;
extern u8 calibration_update_control; /* 2 external only, 1 is internal only */
extern enum mv_ddr_freq medium_freq;
extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
extern enum mv_ddr_freq low_freq;
extern enum auto_tune_stage training_stage;
extern u32 is_pll_before_init;
extern u32 is_adll_calib_before_init;
extern u32 is_dfs_in_init;
extern int wl_debug_delay;
extern u32 silicon_delay[MAX_DEVICE_NUM];
extern u32 start_pattern, end_pattern;
extern u32 phy_reg0_val;
extern u32 phy_reg1_val;
extern u32 phy_reg2_val;
extern u32 phy_reg3_val;
extern enum hws_pattern sweep_pattern;
extern enum hws_pattern pbs_pattern;
extern u32 g_znri_data;
extern u32 g_zpri_data;
extern u32 g_znri_ctrl;
extern u32 g_zpri_ctrl;
extern u32 finger_test, p_finger_start, p_finger_end, n_finger_start,
n_finger_end, p_finger_step, n_finger_step;
extern u32 mode_2t;
extern u32 xsb_validate_type;
extern u32 xsb_validation_base_address;
extern u32 odt_additional;
extern u32 debug_mode;
extern u32 debug_dunit;
extern u32 clamp_tbl[];
extern u32 freq_mask[MAX_DEVICE_NUM][MV_DDR_FREQ_LAST];
extern u32 maxt_poll_tries;
extern u32 is_bist_reset_bit;
extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
extern u32 effective_cs;
extern int ddr3_tip_centr_skip_min_win_check;
extern u32 *dq_map_table;
extern u8 debug_training_hw_alg;
extern u32 start_xsb_offset;
extern u32 odt_config;
extern u16 mask_results_dq_reg_map[];
extern u32 target_freq;
extern u32 dfs_low_freq;
extern u32 nominal_avs;
extern u32 extension_avs;
/* Prototypes */
int ddr3_init(void);
int ddr3_tip_enable_init_sequence(u32 dev_num);
int ddr3_hws_hw_training(enum hws_algo_type algo_mode);
int mv_ddr_early_init(void);
int mv_ddr_early_init2(void);
int ddr3_silicon_post_init(void);
int ddr3_post_run_alg(void);
void ddr3_new_tip_ecc_scrub(void);
int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data);
int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
int ddr3_silicon_get_ddr_target_freq(u32 *ddr_freq);
int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
int print_ph(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
int read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
int reg_addr, u32 mask);
int write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
u32 pup_ph_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], int reg_addr);
int ddr3_tip_restore_dunit_regs(u32 dev_num);
void print_topology(struct mv_ddr_topology_map *tm);
u32 mv_board_id_get(void);
int ddr3_load_topology_map(void);
void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level);
void mv_ddr_user_log_level_set(enum ddr_lib_debug_block block);
int ddr3_tip_tune_training_params(u32 dev_num,
struct tune_train_params *params);
void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
void ddr3_fast_path_static_cs_size_config(u32 cs_ena);
u32 mv_board_id_index_get(u32 board_id);
void ddr3_set_log_level(u32 n_log_level);
int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr);
int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode);
int ddr3_tip_clean_pbs_result(u32 dev_num, enum pbs_dir pbs_mode);
void mv_ddr_mc_config(void);
int mv_ddr_mc_init(void);
void mv_ddr_set_calib_controller(void);
/* TODO: consider to move to misl phy driver */
unsigned int mv_ddr_misl_phy_drv_data_p_get(void);
unsigned int mv_ddr_misl_phy_drv_data_n_get(void);
unsigned int mv_ddr_misl_phy_drv_ctrl_p_get(void);
unsigned int mv_ddr_misl_phy_drv_ctrl_n_get(void);
unsigned int mv_ddr_misl_phy_odt_p_get(void);
unsigned int mv_ddr_misl_phy_odt_n_get(void);
#endif /* _DDR3_INIT_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_logging_def.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR3_LOGGING_CONFIG_H
#define _DDR3_LOGGING_CONFIG_H
#ifdef SILENT_LIB
#define DEBUG_TRAINING_BIST_ENGINE(level, s)
#define DEBUG_TRAINING_IP(level, s)
#define DEBUG_CENTRALIZATION_ENGINE(level, s)
#define DEBUG_TRAINING_HW_ALG(level, s)
#define DEBUG_TRAINING_IP_ENGINE(level, s)
#define DEBUG_LEVELING(level, s)
#define DEBUG_PBS_ENGINE(level, s)
#define DEBUG_TRAINING_STATIC_IP(level, s)
#define DEBUG_TRAINING_ACCESS(level, s)
#else
#ifdef LIB_FUNCTIONAL_DEBUG_ONLY
#define DEBUG_TRAINING_BIST_ENGINE(level, s)
#define DEBUG_TRAINING_IP_ENGINE(level, s)
#define DEBUG_TRAINING_IP(level, s) \
if (level >= debug_training) \
printf s
#define DEBUG_CENTRALIZATION_ENGINE(level, s) \
if (level >= debug_centralization) \
printf s
#define DEBUG_TRAINING_HW_ALG(level, s) \
if (level >= debug_training_hw_alg) \
printf s
#define DEBUG_LEVELING(level, s) \
if (level >= debug_leveling) \
printf s
#define DEBUG_PBS_ENGINE(level, s) \
if (level >= debug_pbs) \
printf s
#define DEBUG_TRAINING_STATIC_IP(level, s) \
if (level >= debug_training_static) \
printf s
#define DEBUG_TRAINING_ACCESS(level, s) \
if (level >= debug_training_access) \
printf s
#else
#define DEBUG_TRAINING_BIST_ENGINE(level, s) \
if (level >= debug_training_bist) \
printf s
#define DEBUG_TRAINING_IP_ENGINE(level, s) \
if (level >= debug_training_ip) \
printf s
#define DEBUG_TRAINING_IP(level, s) \
if (level >= debug_training) \
printf s
#define DEBUG_CENTRALIZATION_ENGINE(level, s) \
if (level >= debug_centralization) \
printf s
#define DEBUG_TRAINING_HW_ALG(level, s) \
if (level >= debug_training_hw_alg) \
printf s
#define DEBUG_LEVELING(level, s) \
if (level >= debug_leveling) \
printf s
#define DEBUG_PBS_ENGINE(level, s) \
if (level >= debug_pbs) \
printf s
#define DEBUG_TRAINING_STATIC_IP(level, s) \
if (level >= debug_training_static) \
printf s
#define DEBUG_TRAINING_ACCESS(level, s) \
if (level >= debug_training_access) \
printf s
#endif
#endif
/* Logging defines */
enum mv_ddr_debug_level {
DEBUG_LEVEL_TRACE = 1,
DEBUG_LEVEL_INFO = 2,
DEBUG_LEVEL_ERROR = 3,
DEBUG_LEVEL_LAST
};
enum ddr_lib_debug_block {
DEBUG_BLOCK_STATIC,
DEBUG_BLOCK_TRAINING_MAIN,
DEBUG_BLOCK_LEVELING,
DEBUG_BLOCK_CENTRALIZATION,
DEBUG_BLOCK_PBS,
DEBUG_BLOCK_IP,
DEBUG_BLOCK_BIST,
DEBUG_BLOCK_ALG,
DEBUG_BLOCK_DEVICE,
DEBUG_BLOCK_ACCESS,
DEBUG_STAGES_REG_DUMP,
/* All excluding IP and REG_DUMP, should be enabled separatelly */
DEBUG_BLOCK_ALL
};
int ddr3_tip_print_log(u32 dev_num, u32 mem_addr);
int ddr3_tip_print_stability_log(u32 dev_num);
#endif /* _DDR3_LOGGING_CONFIG_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_patterns_64bit.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef __DDR3_PATTERNS_64_H
#define __DDR3_PATTERNS_64_H
#define FAB_OPT 21
/*
* Patterns Declerations
*/
u32 wl_sup_pattern[LEN_WL_SUP_PATTERN] __aligned(32) = {
0x04030201, 0x08070605, 0x0c0b0a09, 0x100f0e0d,
0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d,
0x24232221, 0x28272625, 0x2c2b2a29, 0x302f2e2d,
0x34333231, 0x38373635, 0x3c3b3a39, 0x403f3e3d,
0x44434241, 0x48474645, 0x4c4b4a49, 0x504f4e4d,
0x54535251, 0x58575655, 0x5c5b5a59, 0x605f5e5d,
0x64636261, 0x68676665, 0x6c6b6a69, 0x706f6e6d,
0x74737271, 0x78777675, 0x7c7b7a79, 0x807f7e7d
};
u32 pbs_pattern_32b[2][LEN_PBS_PATTERN] __aligned(32) = {
{
0xaaaaaaaa, 0x55555555, 0xaaaaaaaa, 0x55555555,
0xaaaaaaaa, 0x55555555, 0xaaaaaaaa, 0x55555555,
0xaaaaaaaa, 0x55555555, 0xaaaaaaaa, 0x55555555,
0xaaaaaaaa, 0x55555555, 0xaaaaaaaa, 0x55555555
},
{
0x55555555, 0xaaaaaaaa, 0x55555555, 0xaaaaaaaa,
0x55555555, 0xaaaaaaaa, 0x55555555, 0xaaaaaaaa,
0x55555555, 0xaaaaaaaa, 0x55555555, 0xaaaaaaaa,
0x55555555, 0xaaaaaaaa, 0x55555555, 0xaaaaaaaa
}
};
u32 pbs_pattern_64b[2][LEN_PBS_PATTERN] __aligned(32) = {
{
0xaaaaaaaa, 0xaaaaaaaa, 0x55555555, 0x55555555,
0xaaaaaaaa, 0xaaaaaaaa, 0x55555555, 0x55555555,
0xaaaaaaaa, 0xaaaaaaaa, 0x55555555, 0x55555555,
0xaaaaaaaa, 0xaaaaaaaa, 0x55555555, 0x55555555
},
{
0x55555555, 0x55555555, 0xaaaaaaaa, 0xaaaaaaaa,
0x55555555, 0x55555555, 0xaaaaaaaa, 0xaaaaaaaa,
0x55555555, 0x55555555, 0xaaaaaaaa, 0xaaaaaaaa,
0x55555555, 0x55555555, 0xaaaaaaaa, 0xaaaaaaaa
}
};
u32 rl_pattern[LEN_STD_PATTERN] __aligned(32) = {
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x01010101, 0x01010101, 0x01010101, 0x01010101
};
u32 killer_pattern_32b[DQ_NUM][LEN_KILLER_PATTERN] __aligned(32) = {
{
0x01010101, 0x00000000, 0x01010101, 0xffffffff,
0x01010101, 0x00000000, 0x01010101, 0xffffffff,
0xfefefefe, 0xfefefefe, 0x01010101, 0xfefefefe,
0xfefefefe, 0xfefefefe, 0x01010101, 0xfefefefe,
0x01010101, 0xfefefefe, 0x01010101, 0x01010101,
0x01010101, 0xfefefefe, 0x01010101, 0x01010101,
0xfefefefe, 0x01010101, 0xfefefefe, 0x00000000,
0xfefefefe, 0x01010101, 0xfefefefe, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x01010101,
0xffffffff, 0x00000000, 0xffffffff, 0x01010101,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0xfefefefe,
0x00000000, 0x00000000, 0x00000000, 0xfefefefe,
0xfefefefe, 0xffffffff, 0x00000000, 0x00000000,
0xfefefefe, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0xfefefefe, 0x00000000, 0xfefefefe, 0x00000000,
0xfefefefe, 0x00000000, 0xfefefefe, 0x00000000,
0x00000000, 0xffffffff, 0xffffffff, 0x01010101,
0x00000000, 0xffffffff, 0xffffffff, 0x01010101,
0xffffffff, 0xffffffff, 0x01010101, 0x00000000,
0xffffffff, 0xffffffff, 0x01010101, 0x00000000,
0x01010101, 0xffffffff, 0xfefefefe, 0xfefefefe,
0x01010101, 0xffffffff, 0xfefefefe, 0xfefefefe
},
{
0x02020202, 0x00000000, 0x02020202, 0xffffffff,
0x02020202, 0x00000000, 0x02020202, 0xffffffff,
0xfdfdfdfd, 0xfdfdfdfd, 0x02020202, 0xfdfdfdfd,
0xfdfdfdfd, 0xfdfdfdfd, 0x02020202, 0xfdfdfdfd,
0x02020202, 0xfdfdfdfd, 0x02020202, 0x02020202,
0x02020202, 0xfdfdfdfd, 0x02020202, 0x02020202,
0xfdfdfdfd, 0x02020202, 0xfdfdfdfd, 0x00000000,
0xfdfdfdfd, 0x02020202, 0xfdfdfdfd, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x02020202,
0xffffffff, 0x00000000, 0xffffffff, 0x02020202,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0xfdfdfdfd,
0x00000000, 0x00000000, 0x00000000, 0xfdfdfdfd,
0xfdfdfdfd, 0xffffffff, 0x00000000, 0x00000000,
0xfdfdfdfd, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0xfdfdfdfd, 0x00000000, 0xfdfdfdfd, 0x00000000,
0xfdfdfdfd, 0x00000000, 0xfdfdfdfd, 0x00000000,
0x00000000, 0xffffffff, 0xffffffff, 0x02020202,
0x00000000, 0xffffffff, 0xffffffff, 0x02020202,
0xffffffff, 0xffffffff, 0x02020202, 0x00000000,
0xffffffff, 0xffffffff, 0x02020202, 0x00000000,
0x02020202, 0xffffffff, 0xfdfdfdfd, 0xfdfdfdfd,
0x02020202, 0xffffffff, 0xfdfdfdfd, 0xfdfdfdfd
},
{
0x04040404, 0x00000000, 0x04040404, 0xffffffff,
0x04040404, 0x00000000, 0x04040404, 0xffffffff,
0xfbfbfbfb, 0xfbfbfbfb, 0x04040404, 0xfbfbfbfb,
0xfbfbfbfb, 0xfbfbfbfb, 0x04040404, 0xfbfbfbfb,
0x04040404, 0xfbfbfbfb, 0x04040404, 0x04040404,
0x04040404, 0xfbfbfbfb, 0x04040404, 0x04040404,
0xfbfbfbfb, 0x04040404, 0xfbfbfbfb, 0x00000000,
0xfbfbfbfb, 0x04040404, 0xfbfbfbfb, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x04040404,
0xffffffff, 0x00000000, 0xffffffff, 0x04040404,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0xfbfbfbfb,
0x00000000, 0x00000000, 0x00000000, 0xfbfbfbfb,
0xfbfbfbfb, 0xffffffff, 0x00000000, 0x00000000,
0xfbfbfbfb, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0xfbfbfbfb, 0x00000000, 0xfbfbfbfb, 0x00000000,
0xfbfbfbfb, 0x00000000, 0xfbfbfbfb, 0x00000000,
0x00000000, 0xffffffff, 0xffffffff, 0x04040404,
0x00000000, 0xffffffff, 0xffffffff, 0x04040404,
0xffffffff, 0xffffffff, 0x04040404, 0x00000000,
0xffffffff, 0xffffffff, 0x04040404, 0x00000000,
0x04040404, 0xffffffff, 0xfbfbfbfb, 0xfbfbfbfb,
0x04040404, 0xffffffff, 0xfbfbfbfb, 0xfbfbfbfb
},
{
0x08080808, 0x00000000, 0x08080808, 0xffffffff,
0x08080808, 0x00000000, 0x08080808, 0xffffffff,
0xf7f7f7f7, 0xf7f7f7f7, 0x08080808, 0xf7f7f7f7,
0xf7f7f7f7, 0xf7f7f7f7, 0x08080808, 0xf7f7f7f7,
0x08080808, 0xf7f7f7f7, 0x08080808, 0x08080808,
0x08080808, 0xf7f7f7f7, 0x08080808, 0x08080808,
0xf7f7f7f7, 0x08080808, 0xf7f7f7f7, 0x00000000,
0xf7f7f7f7, 0x08080808, 0xf7f7f7f7, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x08080808,
0xffffffff, 0x00000000, 0xffffffff, 0x08080808,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0xf7f7f7f7,
0x00000000, 0x00000000, 0x00000000, 0xf7f7f7f7,
0xf7f7f7f7, 0xffffffff, 0x00000000, 0x00000000,
0xf7f7f7f7, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0xf7f7f7f7, 0x00000000, 0xf7f7f7f7, 0x00000000,
0xf7f7f7f7, 0x00000000, 0xf7f7f7f7, 0x00000000,
0x00000000, 0xffffffff, 0xffffffff, 0x08080808,
0x00000000, 0xffffffff, 0xffffffff, 0x08080808,
0xffffffff, 0xffffffff, 0x08080808, 0x00000000,
0xffffffff, 0xffffffff, 0x08080808, 0x00000000,
0x08080808, 0xffffffff, 0xf7f7f7f7, 0xf7f7f7f7,
0x08080808, 0xffffffff, 0xf7f7f7f7, 0xf7f7f7f7
},
{
0x10101010, 0x00000000, 0x10101010, 0xffffffff,
0x10101010, 0x00000000, 0x10101010, 0xffffffff,
0xefefefef, 0xefefefef, 0x10101010, 0xefefefef,
0xefefefef, 0xefefefef, 0x10101010, 0xefefefef,
0x10101010, 0xefefefef, 0x10101010, 0x10101010,
0x10101010, 0xefefefef, 0x10101010, 0x10101010,
0xefefefef, 0x10101010, 0xefefefef, 0x00000000,
0xefefefef, 0x10101010, 0xefefefef, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x10101010,
0xffffffff, 0x00000000, 0xffffffff, 0x10101010,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0xefefefef,
0x00000000, 0x00000000, 0x00000000, 0xefefefef,
0xefefefef, 0xffffffff, 0x00000000, 0x00000000,
0xefefefef, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0xefefefef, 0x00000000, 0xefefefef, 0x00000000,
0xefefefef, 0x00000000, 0xefefefef, 0x00000000,
0x00000000, 0xffffffff, 0xffffffff, 0x10101010,
0x00000000, 0xffffffff, 0xffffffff, 0x10101010,
0xffffffff, 0xffffffff, 0x10101010, 0x00000000,
0xffffffff, 0xffffffff, 0x10101010, 0x00000000,
0x10101010, 0xffffffff, 0xefefefef, 0xefefefef,
0x10101010, 0xffffffff, 0xefefefef, 0xefefefef
},
{
0x20202020, 0x00000000, 0x20202020, 0xffffffff,
0x20202020, 0x00000000, 0x20202020, 0xffffffff,
0xdfdfdfdf, 0xdfdfdfdf, 0x20202020, 0xdfdfdfdf,
0xdfdfdfdf, 0xdfdfdfdf, 0x20202020, 0xdfdfdfdf,
0x20202020, 0xdfdfdfdf, 0x20202020, 0x20202020,
0x20202020, 0xdfdfdfdf, 0x20202020, 0x20202020,
0xdfdfdfdf, 0x20202020, 0xdfdfdfdf, 0x00000000,
0xdfdfdfdf, 0x20202020, 0xdfdfdfdf, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x20202020,
0xffffffff, 0x00000000, 0xffffffff, 0x20202020,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0xdfdfdfdf,
0x00000000, 0x00000000, 0x00000000, 0xdfdfdfdf,
0xdfdfdfdf, 0xffffffff, 0x00000000, 0x00000000,
0xdfdfdfdf, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0xdfdfdfdf, 0x00000000, 0xdfdfdfdf, 0x00000000,
0xdfdfdfdf, 0x00000000, 0xdfdfdfdf, 0x00000000,
0x00000000, 0xffffffff, 0xffffffff, 0x20202020,
0x00000000, 0xffffffff, 0xffffffff, 0x20202020,
0xffffffff, 0xffffffff, 0x20202020, 0x00000000,
0xffffffff, 0xffffffff, 0x20202020, 0x00000000,
0x20202020, 0xffffffff, 0xdfdfdfdf, 0xdfdfdfdf,
0x20202020, 0xffffffff, 0xdfdfdfdf, 0xdfdfdfdf
},
{
0x40404040, 0x00000000, 0x40404040, 0xffffffff,
0x40404040, 0x00000000, 0x40404040, 0xffffffff,
0xbfbfbfbf, 0xbfbfbfbf, 0x40404040, 0xbfbfbfbf,
0xbfbfbfbf, 0xbfbfbfbf, 0x40404040, 0xbfbfbfbf,
0x40404040, 0xbfbfbfbf, 0x40404040, 0x40404040,
0x40404040, 0xbfbfbfbf, 0x40404040, 0x40404040,
0xbfbfbfbf, 0x40404040, 0xbfbfbfbf, 0x00000000,
0xbfbfbfbf, 0x40404040, 0xbfbfbfbf, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x40404040,
0xffffffff, 0x00000000, 0xffffffff, 0x40404040,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0xbfbfbfbf,
0x00000000, 0x00000000, 0x00000000, 0xbfbfbfbf,
0xbfbfbfbf, 0xffffffff, 0x00000000, 0x00000000,
0xbfbfbfbf, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0xbfbfbfbf, 0x00000000, 0xbfbfbfbf, 0x00000000,
0xbfbfbfbf, 0x00000000, 0xbfbfbfbf, 0x00000000,
0x00000000, 0xffffffff, 0xffffffff, 0x40404040,
0x00000000, 0xffffffff, 0xffffffff, 0x40404040,
0xffffffff, 0xffffffff, 0x40404040, 0x00000000,
0xffffffff, 0xffffffff, 0x40404040, 0x00000000,
0x40404040, 0xffffffff, 0xbfbfbfbf, 0xbfbfbfbf,
0x40404040, 0xffffffff, 0xbfbfbfbf, 0xbfbfbfbf
},
{
0x80808080, 0x00000000, 0x80808080, 0xffffffff,
0x80808080, 0x00000000, 0x80808080, 0xffffffff,
0x7f7f7f7f, 0x7f7f7f7f, 0x80808080, 0x7f7f7f7f,
0x7f7f7f7f, 0x7f7f7f7f, 0x80808080, 0x7f7f7f7f,
0x80808080, 0x7f7f7f7f, 0x80808080, 0x80808080,
0x80808080, 0x7f7f7f7f, 0x80808080, 0x80808080,
0x7f7f7f7f, 0x80808080, 0x7f7f7f7f, 0x00000000,
0x7f7f7f7f, 0x80808080, 0x7f7f7f7f, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x80808080,
0xffffffff, 0x00000000, 0xffffffff, 0x80808080,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x7f7f7f7f,
0x00000000, 0x00000000, 0x00000000, 0x7f7f7f7f,
0x7f7f7f7f, 0xffffffff, 0x00000000, 0x00000000,
0x7f7f7f7f, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
0x7f7f7f7f, 0x00000000, 0x7f7f7f7f, 0x00000000,
0x7f7f7f7f, 0x00000000, 0x7f7f7f7f, 0x00000000,
0x00000000, 0xffffffff, 0xffffffff, 0x80808080,
0x00000000, 0xffffffff, 0xffffffff, 0x80808080,
0xffffffff, 0xffffffff, 0x80808080, 0x00000000,
0xffffffff, 0xffffffff, 0x80808080, 0x00000000,
0x80808080, 0xffffffff, 0x7f7f7f7f, 0x7f7f7f7f,
0x80808080, 0xffffffff, 0x7f7f7f7f, 0x7f7f7f7f
}
};
u32 killer_pattern_64b[DQ_NUM][LEN_KILLER_PATTERN] __aligned(32) = {
{
0x01010101, 0x01010101, 0x00000000, 0x00000000,
0x01010101, 0x01010101, 0xffffffff, 0xffffffff,
0xfefefefe, 0xfefefefe, 0xfefefefe, 0xfefefefe,
0x01010101, 0x01010101, 0xfefefefe, 0xfefefefe,
0x01010101, 0x01010101, 0xfefefefe, 0xfefefefe,
0x01010101, 0x01010101, 0x01010101, 0x01010101,
0xfefefefe, 0xfefefefe, 0x01010101, 0x01010101,
0xfefefefe, 0xfefefefe, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x01010101, 0x01010101,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xfefefefe, 0xfefefefe,
0xfefefefe, 0xfefefefe, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xfefefefe, 0xfefefefe, 0x00000000, 0x00000000,
0xfefefefe, 0xfefefefe, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x01010101, 0x01010101,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x01010101, 0x01010101, 0x00000000, 0x00000000,
0x01010101, 0x01010101, 0xffffffff, 0xffffffff,
0xfefefefe, 0xfefefefe, 0xfefefefe, 0xfefefefe
},
{
0x02020202, 0x02020202, 0x00000000, 0x00000000,
0x02020202, 0x02020202, 0xffffffff, 0xffffffff,
0xfdfdfdfd, 0xfdfdfdfd, 0xfdfdfdfd, 0xfdfdfdfd,
0x02020202, 0x02020202, 0xfdfdfdfd, 0xfdfdfdfd,
0x02020202, 0x02020202, 0xfdfdfdfd, 0xfdfdfdfd,
0x02020202, 0x02020202, 0x02020202, 0x02020202,
0xfdfdfdfd, 0xfdfdfdfd, 0x02020202, 0x02020202,
0xfdfdfdfd, 0xfdfdfdfd, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x02020202, 0x02020202,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xfdfdfdfd, 0xfdfdfdfd,
0xfdfdfdfd, 0xfdfdfdfd, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xfdfdfdfd, 0xfdfdfdfd, 0x00000000, 0x00000000,
0xfdfdfdfd, 0xfdfdfdfd, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x02020202, 0x02020202,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x02020202, 0x02020202, 0x00000000, 0x00000000,
0x02020202, 0x02020202, 0xffffffff, 0xffffffff,
0xfdfdfdfd, 0xfdfdfdfd, 0xfdfdfdfd, 0xfdfdfdfd
},
{
0x04040404, 0x04040404, 0x00000000, 0x00000000,
0x04040404, 0x04040404, 0xffffffff, 0xffffffff,
0xfbfbfbfb, 0xfbfbfbfb, 0xfbfbfbfb, 0xfbfbfbfb,
0x04040404, 0x04040404, 0xfbfbfbfb, 0xfbfbfbfb,
0x04040404, 0x04040404, 0xfbfbfbfb, 0xfbfbfbfb,
0x04040404, 0x04040404, 0x04040404, 0x04040404,
0xfbfbfbfb, 0xfbfbfbfb, 0x04040404, 0x04040404,
0xfbfbfbfb, 0xfbfbfbfb, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x04040404, 0x04040404,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xfbfbfbfb, 0xfbfbfbfb,
0xfbfbfbfb, 0xfbfbfbfb, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xfbfbfbfb, 0xfbfbfbfb, 0x00000000, 0x00000000,
0xfbfbfbfb, 0xfbfbfbfb, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x04040404, 0x04040404,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x04040404, 0x04040404, 0x00000000, 0x00000000,
0x04040404, 0x04040404, 0xffffffff, 0xffffffff,
0xfbfbfbfb, 0xfbfbfbfb, 0xfbfbfbfb, 0xfbfbfbfb
},
{
0x08080808, 0x08080808, 0x00000000, 0x00000000,
0x08080808, 0x08080808, 0xffffffff, 0xffffffff,
0xf7f7f7f7, 0xf7f7f7f7, 0xf7f7f7f7, 0xf7f7f7f7,
0x08080808, 0x08080808, 0xf7f7f7f7, 0xf7f7f7f7,
0x08080808, 0x08080808, 0xf7f7f7f7, 0xf7f7f7f7,
0x08080808, 0x08080808, 0x08080808, 0x08080808,
0xf7f7f7f7, 0xf7f7f7f7, 0x08080808, 0x08080808,
0xf7f7f7f7, 0xf7f7f7f7, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x08080808, 0x08080808,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xf7f7f7f7, 0xf7f7f7f7,
0xf7f7f7f7, 0xf7f7f7f7, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xf7f7f7f7, 0xf7f7f7f7, 0x00000000, 0x00000000,
0xf7f7f7f7, 0xf7f7f7f7, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x08080808, 0x08080808,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x08080808, 0x08080808, 0x00000000, 0x00000000,
0x08080808, 0x08080808, 0xffffffff, 0xffffffff,
0xf7f7f7f7, 0xf7f7f7f7, 0xf7f7f7f7, 0xf7f7f7f7
},
{
0x10101010, 0x10101010, 0x00000000, 0x00000000,
0x10101010, 0x10101010, 0xffffffff, 0xffffffff,
0xefefefef, 0xefefefef, 0xefefefef, 0xefefefef,
0x10101010, 0x10101010, 0xefefefef, 0xefefefef,
0x10101010, 0x10101010, 0xefefefef, 0xefefefef,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0xefefefef, 0xefefefef, 0x10101010, 0x10101010,
0xefefefef, 0xefefefef, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x10101010, 0x10101010,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xefefefef, 0xefefefef,
0xefefefef, 0xefefefef, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xefefefef, 0xefefefef, 0x00000000, 0x00000000,
0xefefefef, 0xefefefef, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x10101010, 0x10101010,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x10101010, 0x10101010, 0x00000000, 0x00000000,
0x10101010, 0x10101010, 0xffffffff, 0xffffffff,
0xefefefef, 0xefefefef, 0xefefefef, 0xefefefef
},
{
0x20202020, 0x20202020, 0x00000000, 0x00000000,
0x20202020, 0x20202020, 0xffffffff, 0xffffffff,
0xdfdfdfdf, 0xdfdfdfdf, 0xdfdfdfdf, 0xdfdfdfdf,
0x20202020, 0x20202020, 0xdfdfdfdf, 0xdfdfdfdf,
0x20202020, 0x20202020, 0xdfdfdfdf, 0xdfdfdfdf,
0x20202020, 0x20202020, 0x20202020, 0x20202020,
0xdfdfdfdf, 0xdfdfdfdf, 0x20202020, 0x20202020,
0xdfdfdfdf, 0xdfdfdfdf, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x20202020, 0x20202020,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xdfdfdfdf, 0xdfdfdfdf,
0xdfdfdfdf, 0xdfdfdfdf, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xdfdfdfdf, 0xdfdfdfdf, 0x00000000, 0x00000000,
0xdfdfdfdf, 0xdfdfdfdf, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x20202020, 0x20202020,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x20202020, 0x20202020, 0x00000000, 0x00000000,
0x20202020, 0x20202020, 0xffffffff, 0xffffffff,
0xdfdfdfdf, 0xdfdfdfdf, 0xdfdfdfdf, 0xdfdfdfdf
},
{
0x40404040, 0x40404040, 0x00000000, 0x00000000,
0x40404040, 0x40404040, 0xffffffff, 0xffffffff,
0xbfbfbfbf, 0xbfbfbfbf, 0xbfbfbfbf, 0xbfbfbfbf,
0x40404040, 0x40404040, 0xbfbfbfbf, 0xbfbfbfbf,
0x40404040, 0x40404040, 0xbfbfbfbf, 0xbfbfbfbf,
0x40404040, 0x40404040, 0x40404040, 0x40404040,
0xbfbfbfbf, 0xbfbfbfbf, 0x40404040, 0x40404040,
0xbfbfbfbf, 0xbfbfbfbf, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x40404040, 0x40404040,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xbfbfbfbf, 0xbfbfbfbf,
0xbfbfbfbf, 0xbfbfbfbf, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xbfbfbfbf, 0xbfbfbfbf, 0x00000000, 0x00000000,
0xbfbfbfbf, 0xbfbfbfbf, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x40404040, 0x40404040,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x40404040, 0x40404040, 0x00000000, 0x00000000,
0x40404040, 0x40404040, 0xffffffff, 0xffffffff,
0xbfbfbfbf, 0xbfbfbfbf, 0xbfbfbfbf, 0xbfbfbfbf
},
{
0x80808080, 0x80808080, 0x00000000, 0x00000000,
0x80808080, 0x80808080, 0xffffffff, 0xffffffff,
0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f,
0x80808080, 0x80808080, 0x7f7f7f7f, 0x7f7f7f7f,
0x80808080, 0x80808080, 0x7f7f7f7f, 0x7f7f7f7f,
0x80808080, 0x80808080, 0x80808080, 0x80808080,
0x7f7f7f7f, 0x7f7f7f7f, 0x80808080, 0x80808080,
0x7f7f7f7f, 0x7f7f7f7f, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x80808080, 0x80808080,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x7f7f7f7f, 0x7f7f7f7f,
0x7f7f7f7f, 0x7f7f7f7f, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x7f7f7f7f, 0x7f7f7f7f, 0x00000000, 0x00000000,
0x7f7f7f7f, 0x7f7f7f7f, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x80808080, 0x80808080,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x80808080, 0x80808080, 0x00000000, 0x00000000,
0x80808080, 0x80808080, 0xffffffff, 0xffffffff,
0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f
}
};
u32 special_pattern[DQ_NUM][LEN_SPECIAL_PATTERN] __aligned(32) = {
{
0x00000000, 0x00000000, 0x01010101, 0x01010101,
0xffffffff, 0xffffffff, 0xfefefefe, 0xfefefefe,
0xfefefefe, 0xfefefefe, 0x01010101, 0x01010101,
0xfefefefe, 0xfefefefe, 0x01010101, 0x01010101,
0xfefefefe, 0xfefefefe, 0x01010101, 0x01010101,
0x01010101, 0x01010101, 0xfefefefe, 0xfefefefe,
0x01010101, 0x01010101, 0xfefefefe, 0xfefefefe,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x01010101, 0x01010101, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xfefefefe, 0xfefefefe, 0xfefefefe, 0xfefefefe,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xfefefefe, 0xfefefefe,
0x00000000, 0x00000000, 0xfefefefe, 0xfefefefe,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x01010101, 0x01010101, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x01010101, 0x01010101,
0x00000000, 0x00000000, 0x01010101, 0x01010101,
0xffffffff, 0xffffffff, 0xfefefefe, 0xfefefefe,
0xfefefefe, 0xfefefefe, 0x00000000, 0x00000000
},
{
0x00000000, 0x00000000, 0x02020202, 0x02020202,
0xffffffff, 0xffffffff, 0xfdfdfdfd, 0xfdfdfdfd,
0xfdfdfdfd, 0xfdfdfdfd, 0x02020202, 0x02020202,
0xfdfdfdfd, 0xfdfdfdfd, 0x02020202, 0x02020202,
0xfdfdfdfd, 0xfdfdfdfd, 0x02020202, 0x02020202,
0x02020202, 0x02020202, 0xfdfdfdfd, 0xfdfdfdfd,
0x02020202, 0x02020202, 0xfdfdfdfd, 0xfdfdfdfd,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x02020202, 0x02020202, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xfdfdfdfd, 0xfdfdfdfd, 0xfdfdfdfd, 0xfdfdfdfd,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xfdfdfdfd, 0xfdfdfdfd,
0x00000000, 0x00000000, 0xfdfdfdfd, 0xfdfdfdfd,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x02020202, 0x02020202, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x02020202, 0x02020202,
0x00000000, 0x00000000, 0x02020202, 0x02020202,
0xffffffff, 0xffffffff, 0xfdfdfdfd, 0xfdfdfdfd,
0xfdfdfdfd, 0xfdfdfdfd, 0x00000000, 0x00000000
},
{
0x00000000, 0x00000000, 0x04040404, 0x04040404,
0xffffffff, 0xffffffff, 0xfbfbfbfb, 0xfbfbfbfb,
0xfbfbfbfb, 0xfbfbfbfb, 0x04040404, 0x04040404,
0xfbfbfbfb, 0xfbfbfbfb, 0x04040404, 0x04040404,
0xfbfbfbfb, 0xfbfbfbfb, 0x04040404, 0x04040404,
0x04040404, 0x04040404, 0xfbfbfbfb, 0xfbfbfbfb,
0x04040404, 0x04040404, 0xfbfbfbfb, 0xfbfbfbfb,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x04040404, 0x04040404, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xfbfbfbfb, 0xfbfbfbfb, 0xfbfbfbfb, 0xfbfbfbfb,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xfbfbfbfb, 0xfbfbfbfb,
0x00000000, 0x00000000, 0xfbfbfbfb, 0xfbfbfbfb,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x04040404, 0x04040404, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x04040404, 0x04040404,
0x00000000, 0x00000000, 0x04040404, 0x04040404,
0xffffffff, 0xffffffff, 0xfbfbfbfb, 0xfbfbfbfb,
0xfbfbfbfb, 0xfbfbfbfb, 0x00000000, 0x00000000
},
{
0x00000000, 0x00000000, 0x08080808, 0x08080808,
0xffffffff, 0xffffffff, 0xf7f7f7f7, 0xf7f7f7f7,
0xf7f7f7f7, 0xf7f7f7f7, 0x08080808, 0x08080808,
0xf7f7f7f7, 0xf7f7f7f7, 0x08080808, 0x08080808,
0xf7f7f7f7, 0xf7f7f7f7, 0x08080808, 0x08080808,
0x08080808, 0x08080808, 0xf7f7f7f7, 0xf7f7f7f7,
0x08080808, 0x08080808, 0xf7f7f7f7, 0xf7f7f7f7,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x08080808, 0x08080808, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xf7f7f7f7, 0xf7f7f7f7, 0xf7f7f7f7, 0xf7f7f7f7,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xf7f7f7f7, 0xf7f7f7f7,
0x00000000, 0x00000000, 0xf7f7f7f7, 0xf7f7f7f7,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x08080808, 0x08080808, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x08080808, 0x08080808,
0x00000000, 0x00000000, 0x08080808, 0x08080808,
0xffffffff, 0xffffffff, 0xf7f7f7f7, 0xf7f7f7f7,
0xf7f7f7f7, 0xf7f7f7f7, 0x00000000, 0x00000000
},
{
0x00000000, 0x00000000, 0x10101010, 0x10101010,
0xffffffff, 0xffffffff, 0xefefefef, 0xefefefef,
0xefefefef, 0xefefefef, 0x10101010, 0x10101010,
0xefefefef, 0xefefefef, 0x10101010, 0x10101010,
0xefefefef, 0xefefefef, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0xefefefef, 0xefefefef,
0x10101010, 0x10101010, 0xefefefef, 0xefefefef,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x10101010, 0x10101010, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xefefefef, 0xefefefef, 0xefefefef, 0xefefefef,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xefefefef, 0xefefefef,
0x00000000, 0x00000000, 0xefefefef, 0xefefefef,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x10101010, 0x10101010, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x10101010, 0x10101010,
0x00000000, 0x00000000, 0x10101010, 0x10101010,
0xffffffff, 0xffffffff, 0xefefefef, 0xefefefef,
0xefefefef, 0xefefefef, 0x00000000, 0x00000000
},
{
0x00000000, 0x00000000, 0x20202020, 0x20202020,
0xffffffff, 0xffffffff, 0xdfdfdfdf, 0xdfdfdfdf,
0xdfdfdfdf, 0xdfdfdfdf, 0x20202020, 0x20202020,
0xdfdfdfdf, 0xdfdfdfdf, 0x20202020, 0x20202020,
0xdfdfdfdf, 0xdfdfdfdf, 0x20202020, 0x20202020,
0x20202020, 0x20202020, 0xdfdfdfdf, 0xdfdfdfdf,
0x20202020, 0x20202020, 0xdfdfdfdf, 0xdfdfdfdf,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x20202020, 0x20202020, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xdfdfdfdf, 0xdfdfdfdf, 0xdfdfdfdf, 0xdfdfdfdf,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xdfdfdfdf, 0xdfdfdfdf,
0x00000000, 0x00000000, 0xdfdfdfdf, 0xdfdfdfdf,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x20202020, 0x20202020, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x20202020, 0x20202020,
0x00000000, 0x00000000, 0x20202020, 0x20202020,
0xffffffff, 0xffffffff, 0xdfdfdfdf, 0xdfdfdfdf,
0xdfdfdfdf, 0xdfdfdfdf, 0x00000000, 0x00000000
},
{
0x00000000, 0x00000000, 0x40404040, 0x40404040,
0xffffffff, 0xffffffff, 0xbfbfbfbf, 0xbfbfbfbf,
0xbfbfbfbf, 0xbfbfbfbf, 0x40404040, 0x40404040,
0xbfbfbfbf, 0xbfbfbfbf, 0x40404040, 0x40404040,
0xbfbfbfbf, 0xbfbfbfbf, 0x40404040, 0x40404040,
0x40404040, 0x40404040, 0xbfbfbfbf, 0xbfbfbfbf,
0x40404040, 0x40404040, 0xbfbfbfbf, 0xbfbfbfbf,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x40404040, 0x40404040, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xbfbfbfbf, 0xbfbfbfbf, 0xbfbfbfbf, 0xbfbfbfbf,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xbfbfbfbf, 0xbfbfbfbf,
0x00000000, 0x00000000, 0xbfbfbfbf, 0xbfbfbfbf,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x40404040, 0x40404040, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x40404040, 0x40404040,
0x00000000, 0x00000000, 0x40404040, 0x40404040,
0xffffffff, 0xffffffff, 0xbfbfbfbf, 0xbfbfbfbf,
0xbfbfbfbf, 0xbfbfbfbf, 0x00000000, 0x00000000
},
{
0x00000000, 0x00000000, 0x80808080, 0x80808080,
0xffffffff, 0xffffffff, 0x7f7f7f7f, 0x7f7f7f7f,
0x7f7f7f7f, 0x7f7f7f7f, 0x80808080, 0x80808080,
0x7f7f7f7f, 0x7f7f7f7f, 0x80808080, 0x80808080,
0x7f7f7f7f, 0x7f7f7f7f, 0x80808080, 0x80808080,
0x80808080, 0x80808080, 0x7f7f7f7f, 0x7f7f7f7f,
0x80808080, 0x80808080, 0x7f7f7f7f, 0x7f7f7f7f,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x80808080, 0x80808080, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0x7f7f7f7f, 0x7f7f7f7f,
0x00000000, 0x00000000, 0x7f7f7f7f, 0x7f7f7f7f,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x80808080, 0x80808080, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0x80808080, 0x80808080,
0x00000000, 0x00000000, 0x80808080, 0x80808080,
0xffffffff, 0xffffffff, 0x7f7f7f7f, 0x7f7f7f7f,
0x7f7f7f7f, 0x7f7f7f7f, 0x00000000, 0x00000000
}
};
/* Fabric ratios table */
u32 fabric_ratio[FAB_OPT] = {
0x04010204,
0x04020202,
0x08020306,
0x08020303,
0x04020303,
0x04020204,
0x04010202,
0x08030606,
0x08030505,
0x04020306,
0x0804050a,
0x04030606,
0x04020404,
0x04030306,
0x04020505,
0x08020505,
0x04010303,
0x08050a0a,
0x04030408,
0x04010102,
0x08030306
};
u32 pbs_dq_mapping[PUP_NUM_64BIT + 1][DQ_NUM] = {
{3, 2, 5, 7, 1, 0, 6, 4},
{2, 3, 6, 7, 1, 0, 4, 5},
{1, 3, 5, 6, 0, 2, 4, 7},
{0, 2, 4, 7, 1, 3, 5, 6},
{3, 0, 4, 6, 1, 2, 5, 7},
{0, 3, 5, 7, 1, 2, 4, 6},
{2, 3, 5, 7, 1, 0, 4, 6},
{0, 2, 5, 4, 1, 3, 6, 7},
{2, 3, 4, 7, 0, 1, 5, 6}
};
#endif /* __DDR3_PATTERNS_64_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training.c
+2896
View File
File diff suppressed because it is too large Load Diff
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training_bist.c
+603
View File
@@ -0,0 +1,603 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#include "ddr3_init.h"
#include "mv_ddr_regs.h"
static u32 bist_offset = 32;
enum hws_pattern sweep_pattern = PATTERN_KILLER_DQ0;
static int ddr3_tip_bist_operation(u32 dev_num,
enum hws_access_type access_type,
u32 if_id,
enum hws_bist_operation oper_type);
/*
* BIST activate
*/
int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern,
enum hws_access_type access_type, u32 if_num,
enum hws_dir dir,
enum hws_stress_jump addr_stress_jump,
enum hws_pattern_duration duration,
enum hws_bist_operation oper_type,
u32 offset, u32 cs_num, u32 pattern_addr_length)
{
u32 tx_burst_size;
u32 delay_between_burst;
u32 rd_mode;
struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
/* odpg bist write enable */
ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG,
(ODPG_WRBUF_WR_CTRL_ENA << ODPG_WRBUF_WR_CTRL_OFFS),
(ODPG_WRBUF_WR_CTRL_MASK << ODPG_WRBUF_WR_CTRL_OFFS));
/* odpg bist read enable/disable */
ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG,
(dir == OPER_READ) ? (ODPG_WRBUF_RD_CTRL_ENA << ODPG_WRBUF_RD_CTRL_OFFS) :
(ODPG_WRBUF_RD_CTRL_DIS << ODPG_WRBUF_RD_CTRL_OFFS),
(ODPG_WRBUF_RD_CTRL_MASK << ODPG_WRBUF_RD_CTRL_OFFS));
ddr3_tip_load_pattern_to_odpg(0, access_type, 0, pattern, offset);
ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_BUFFER_SIZE_REG, pattern_addr_length, MASK_ALL_BITS);
tx_burst_size = (dir == OPER_WRITE) ?
pattern_table[pattern].tx_burst_size : 0;
delay_between_burst = (dir == OPER_WRITE) ? 2 : 0;
rd_mode = (dir == OPER_WRITE) ? 1 : 0;
ddr3_tip_configure_odpg(0, access_type, 0, dir,
pattern_table[pattern].num_of_phases_tx, tx_burst_size,
pattern_table[pattern].num_of_phases_rx,
delay_between_burst,
rd_mode, cs_num, addr_stress_jump, duration);
ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_BUFFER_OFFS_REG, offset, MASK_ALL_BITS);
if (oper_type == BIST_STOP) {
ddr3_tip_bist_operation(0, access_type, 0, BIST_STOP);
} else {
ddr3_tip_bist_operation(0, access_type, 0, BIST_START);
if (mv_ddr_is_odpg_done(MAX_POLLING_ITERATIONS) != MV_OK)
return MV_FAIL;
ddr3_tip_bist_operation(0, access_type, 0, BIST_STOP);
}
ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS);
return MV_OK;
}
/*
* BIST read result
*/
int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id,
struct bist_result *pst_bist_result)
{
int ret;
u32 read_data[MAX_INTERFACE_NUM];
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
if (IS_IF_ACTIVE(tm->if_act_mask, if_id) == 0)
return MV_NOT_SUPPORTED;
DEBUG_TRAINING_BIST_ENGINE(DEBUG_LEVEL_TRACE,
("ddr3_tip_bist_read_result if_id %d\n",
if_id));
ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id,
ODPG_DATA_RX_WORD_ERR_DATA_HIGH_REG, read_data,
MASK_ALL_BITS);
if (ret != MV_OK)
return ret;
pst_bist_result->bist_fail_high = read_data[if_id];
ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id,
ODPG_DATA_RX_WORD_ERR_DATA_LOW_REG, read_data,
MASK_ALL_BITS);
if (ret != MV_OK)
return ret;
pst_bist_result->bist_fail_low = read_data[if_id];
ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id,
ODPG_DATA_RX_WORD_ERR_ADDR_REG, read_data,
MASK_ALL_BITS);
if (ret != MV_OK)
return ret;
pst_bist_result->bist_last_fail_addr = read_data[if_id];
ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id,
ODPG_DATA_RX_WORD_ERR_CNTR_REG, read_data,
MASK_ALL_BITS);
if (ret != MV_OK)
return ret;
pst_bist_result->bist_error_cnt = read_data[if_id];
return MV_OK;
}
/*
* BIST flow - Activate & read result
*/
int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result,
u32 cs_num)
{
int ret;
u32 i = 0;
u32 win_base;
struct bist_result st_bist_result;
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
for (i = 0; i < MAX_INTERFACE_NUM; i++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, i);
hws_ddr3_cs_base_adr_calc(i, cs_num, &win_base);
ret = ddr3_tip_bist_activate(dev_num, pattern,
ACCESS_TYPE_UNICAST,
i, OPER_WRITE, STRESS_NONE,
DURATION_SINGLE, BIST_START,
bist_offset + win_base,
cs_num, 15);
if (ret != MV_OK) {
printf("ddr3_tip_bist_activate failed (0x%x)\n", ret);
return ret;
}
ret = ddr3_tip_bist_activate(dev_num, pattern,
ACCESS_TYPE_UNICAST,
i, OPER_READ, STRESS_NONE,
DURATION_SINGLE, BIST_START,
bist_offset + win_base,
cs_num, 15);
if (ret != MV_OK) {
printf("ddr3_tip_bist_activate failed (0x%x)\n", ret);
return ret;
}
ret = ddr3_tip_bist_read_result(dev_num, i, &st_bist_result);
if (ret != MV_OK) {
printf("ddr3_tip_bist_read_result failed\n");
return ret;
}
result[i] = st_bist_result.bist_error_cnt;
}
return MV_OK;
}
/*
* Set BIST Operation
*/
static int ddr3_tip_bist_operation(u32 dev_num,
enum hws_access_type access_type,
u32 if_id, enum hws_bist_operation oper_type)
{
if (oper_type == BIST_STOP)
mv_ddr_odpg_disable();
else
mv_ddr_odpg_enable();
return MV_OK;
}
/*
* Print BIST result
*/
void ddr3_tip_print_bist_res(void)
{
u32 dev_num = 0;
u32 i;
struct bist_result st_bist_result[MAX_INTERFACE_NUM];
int res;
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
for (i = 0; i < MAX_INTERFACE_NUM; i++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, i);
res = ddr3_tip_bist_read_result(dev_num, i, &st_bist_result[i]);
if (res != MV_OK) {
DEBUG_TRAINING_BIST_ENGINE(
DEBUG_LEVEL_ERROR,
("ddr3_tip_bist_read_result failed\n"));
return;
}
}
DEBUG_TRAINING_BIST_ENGINE(
DEBUG_LEVEL_INFO,
("interface | error_cnt | fail_low | fail_high | fail_addr\n"));
for (i = 0; i < MAX_INTERFACE_NUM; i++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, i);
DEBUG_TRAINING_BIST_ENGINE(
DEBUG_LEVEL_INFO,
("%d | 0x%08x | 0x%08x | 0x%08x | 0x%08x\n",
i, st_bist_result[i].bist_error_cnt,
st_bist_result[i].bist_fail_low,
st_bist_result[i].bist_fail_high,
st_bist_result[i].bist_last_fail_addr));
}
}
enum {
PASS,
FAIL
};
#define TIP_ITERATION_NUM 31
static int mv_ddr_tip_bist(enum hws_dir dir, u32 val, enum hws_pattern pattern, u32 cs, u32 *result)
{
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
enum hws_training_ip_stat training_result;
u16 *reg_map = ddr3_tip_get_mask_results_pup_reg_map();
u32 max_subphy = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
u32 subphy, read_data;
ddr3_tip_ip_training(0, ACCESS_TYPE_MULTICAST, 0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
RESULT_PER_BYTE, HWS_CONTROL_ELEMENT_ADLL, HWS_LOW2HIGH, dir, tm->if_act_mask, val,
TIP_ITERATION_NUM, pattern, EDGE_FP, CS_SINGLE, cs, &training_result);
for (subphy = 0; subphy < max_subphy; subphy++) {
ddr3_tip_if_read(0, ACCESS_TYPE_UNICAST, 0, reg_map[subphy], &read_data, MASK_ALL_BITS);
if (((read_data >> BLOCK_STATUS_OFFS) & BLOCK_STATUS_MASK) == BLOCK_STATUS_NOT_LOCKED)
*result |= (FAIL << subphy);
}
return MV_OK;
}
struct interval {
u8 *vector;
u8 lendpnt; /* interval's left endpoint */
u8 rendpnt; /* interval's right endpoint */
u8 size; /* interval's size */
u8 lmarker; /* left marker */
u8 rmarker; /* right marker */
u8 pass_lendpnt; /* left endpoint of internal pass interval */
u8 pass_rendpnt; /* right endpoint of internal pass interval */
};
static int interval_init(u8 *vector, u8 lendpnt, u8 rendpnt,
u8 lmarker, u8 rmarker, struct interval *intrvl)
{
if (intrvl == NULL) {
printf("%s: NULL intrvl pointer found\n", __func__);
return MV_FAIL;
}
if (vector == NULL) {
printf("%s: NULL vector pointer found\n", __func__);
return MV_FAIL;
}
intrvl->vector = vector;
if (lendpnt >= rendpnt) {
printf("%s: incorrect lendpnt and/or rendpnt parameters found\n", __func__);
return MV_FAIL;
}
intrvl->lendpnt = lendpnt;
intrvl->rendpnt = rendpnt;
intrvl->size = rendpnt - lendpnt + 1;
if ((lmarker < lendpnt) || (lmarker > rendpnt)) {
printf("%s: incorrect lmarker parameter found\n", __func__);
return MV_FAIL;
}
intrvl->lmarker = lmarker;
if ((rmarker < lmarker) || (rmarker > (intrvl->rendpnt + intrvl->size))) {
printf("%s: incorrect rmarker parameter found\n", __func__);
return MV_FAIL;
}
intrvl->rmarker = rmarker;
return MV_OK;
}
static int interval_set(u8 pass_lendpnt, u8 pass_rendpnt, struct interval *intrvl)
{
if (intrvl == NULL) {
printf("%s: NULL intrvl pointer found\n", __func__);
return MV_FAIL;
}
intrvl->pass_lendpnt = pass_lendpnt;
intrvl->pass_rendpnt = pass_rendpnt;
return MV_OK;
}
static int interval_proc(struct interval *intrvl)
{
int curr;
int pass_lendpnt, pass_rendpnt;
int lmt;
int fcnt = 0, pcnt = 0;
if (intrvl == NULL) {
printf("%s: NULL intrvl pointer found\n", __func__);
return MV_FAIL;
}
/* count fails and passes */
curr = intrvl->lendpnt;
while (curr <= intrvl->rendpnt) {
if (intrvl->vector[curr] == PASS)
pcnt++;
else
fcnt++;
curr++;
}
/* check for all fail */
if (fcnt == intrvl->size) {
printf("%s: no pass found\n", __func__);
return MV_FAIL;
}
/* check for all pass */
if (pcnt == intrvl->size) {
if (interval_set(intrvl->lendpnt, intrvl->rendpnt, intrvl) != MV_OK)
return MV_FAIL;
return MV_OK;
}
/* proceed with rmarker */
curr = intrvl->rmarker;
if (intrvl->vector[curr % intrvl->size] == PASS) { /* pass at rmarker */
/* search for fail on right */
if (intrvl->rmarker > intrvl->rendpnt)
lmt = intrvl->rendpnt + intrvl->size;
else
lmt = intrvl->rmarker + intrvl->size - 1;
while ((curr <= lmt) &&
(intrvl->vector[curr % intrvl->size] == PASS))
curr++;
if (curr > lmt) { /* fail not found */
printf("%s: rmarker: fail following pass not found\n", __func__);
return MV_FAIL;
}
/* fail found */
pass_rendpnt = curr - 1;
} else { /* fail at rmarker */
/* search for pass on left */
if (intrvl->rmarker > intrvl->rendpnt)
lmt = intrvl->rmarker - intrvl->size + 1;
else
lmt = intrvl->lendpnt;
while ((curr >= lmt) &&
(intrvl->vector[curr % intrvl->size] == FAIL))
curr--;
if (curr < lmt) { /* pass not found */
printf("%s: rmarker: pass preceding fail not found\n", __func__);
return MV_FAIL;
}
/* pass found */
pass_rendpnt = curr;
}
/* search for fail on left */
curr = pass_rendpnt;
if (pass_rendpnt > intrvl->rendpnt)
lmt = pass_rendpnt - intrvl->size + 1;
else
lmt = intrvl->lendpnt;
while ((curr >= lmt) &&
(intrvl->vector[curr % intrvl->size] == PASS))
curr--;
if (curr < lmt) { /* fail not found */
printf("%s: rmarker: fail preceding pass not found\n", __func__);
return MV_FAIL;
}
/* fail found */
pass_lendpnt = curr + 1;
if (interval_set(pass_lendpnt, pass_rendpnt, intrvl) != MV_OK)
return MV_FAIL;
return MV_OK;
}
#define ADLL_TAPS_PER_PERIOD 64
int mv_ddr_dm_to_dq_diff_get(u8 vw_sphy_hi_lmt, u8 vw_sphy_lo_lmt, u8 *vw_vector,
int *vw_sphy_hi_diff, int *vw_sphy_lo_diff)
{
struct interval intrvl;
/* init interval structure */
if (interval_init(vw_vector, 0, ADLL_TAPS_PER_PERIOD - 1,
vw_sphy_lo_lmt, vw_sphy_hi_lmt, &intrvl) != MV_OK)
return MV_FAIL;
/* find pass sub-interval */
if (interval_proc(&intrvl) != MV_OK)
return MV_FAIL;
/* check for all pass */
if ((intrvl.pass_rendpnt == intrvl.rendpnt) &&
(intrvl.pass_lendpnt == intrvl.lendpnt)) {
printf("%s: no fail found\n", __func__);
return MV_FAIL;
}
*vw_sphy_hi_diff = intrvl.pass_rendpnt - vw_sphy_hi_lmt;
*vw_sphy_lo_diff = vw_sphy_lo_lmt - intrvl.pass_lendpnt;
return MV_OK;
}
static int mv_ddr_bist_tx(enum hws_access_type access_type)
{
mv_ddr_odpg_done_clr();
ddr3_tip_bist_operation(0, access_type, 0, BIST_START);
if (mv_ddr_is_odpg_done(MAX_POLLING_ITERATIONS) != MV_OK)
return MV_FAIL;
ddr3_tip_bist_operation(0, access_type, 0, BIST_STOP);
ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS);
return MV_OK;
}
/* prepare odpg for bist operation */
#define WR_OP_ODPG_DATA_CMD_BURST_DLY 2
static int mv_ddr_odpg_bist_prepare(enum hws_pattern pattern, enum hws_access_type access_type,
enum hws_dir dir, enum hws_stress_jump stress_jump_addr,
enum hws_pattern_duration duration, u32 offset, u32 cs,
u32 pattern_addr_len, enum dm_direction dm_dir)
{
struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
u32 tx_burst_size;
u32 burst_delay;
u32 rd_mode;
/* odpg bist write enable */
ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG,
(ODPG_WRBUF_WR_CTRL_ENA << ODPG_WRBUF_WR_CTRL_OFFS),
(ODPG_WRBUF_WR_CTRL_MASK << ODPG_WRBUF_WR_CTRL_OFFS));
/* odpg bist read enable/disable */
ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG,
(dir == OPER_READ) ? (ODPG_WRBUF_RD_CTRL_ENA << ODPG_WRBUF_RD_CTRL_OFFS) :
(ODPG_WRBUF_RD_CTRL_DIS << ODPG_WRBUF_RD_CTRL_OFFS),
(ODPG_WRBUF_RD_CTRL_MASK << ODPG_WRBUF_RD_CTRL_OFFS));
if (pattern == PATTERN_00 || pattern == PATTERN_FF)
ddr3_tip_load_pattern_to_odpg(0, access_type, 0, pattern, offset);
else
mv_ddr_load_dm_pattern_to_odpg(access_type, pattern, dm_dir);
ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_BUFFER_SIZE_REG, pattern_addr_len, MASK_ALL_BITS);
if (dir == OPER_WRITE) {
tx_burst_size = pattern_table[pattern].tx_burst_size;
burst_delay = WR_OP_ODPG_DATA_CMD_BURST_DLY;
rd_mode = ODPG_MODE_TX;
} else {
tx_burst_size = 0;
burst_delay = 0;
rd_mode = ODPG_MODE_RX;
}
ddr3_tip_configure_odpg(0, access_type, 0, dir, pattern_table[pattern].num_of_phases_tx,
tx_burst_size, pattern_table[pattern].num_of_phases_rx, burst_delay,
rd_mode, cs, stress_jump_addr, duration);
return MV_OK;
}
#define BYTES_PER_BURST_64BIT 0x20
#define BYTES_PER_BURST_32BIT 0x10
int mv_ddr_dm_vw_get(enum hws_pattern pattern, u32 cs, u8 *vw_vector)
{
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
u32 adll_tap;
u32 wr_ctrl_adll[MAX_BUS_NUM] = {0};
u32 rd_ctrl_adll[MAX_BUS_NUM] = {0};
u32 subphy;
u32 subphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
u32 odpg_addr = 0x0;
u32 result;
u32 idx;
/* burst length in bytes */
u32 burst_len = (MV_DDR_IS_64BIT_DRAM_MODE(tm->bus_act_mask) ?
BYTES_PER_BURST_64BIT : BYTES_PER_BURST_32BIT);
/* save dqs values to restore after algorithm's run */
ddr3_tip_read_adll_value(0, wr_ctrl_adll, CTX_PHY_REG(cs), MASK_ALL_BITS);
ddr3_tip_read_adll_value(0, rd_ctrl_adll, CRX_PHY_REG(cs), MASK_ALL_BITS);
/* fill memory with base pattern */
ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS);
mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE,
bist_offset, cs, pattern_table[pattern].num_of_phases_tx,
(pattern == PATTERN_00) ? DM_DIR_DIRECT : DM_DIR_INVERSE);
for (adll_tap = 0; adll_tap < ADLL_TAPS_PER_PERIOD; adll_tap++) {
/* change target odpg address */
odpg_addr = adll_tap * burst_len;
ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_BUFFER_OFFS_REG,
odpg_addr, MASK_ALL_BITS);
ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE,
pattern_table[pattern].num_of_phases_tx,
pattern_table[pattern].tx_burst_size,
pattern_table[pattern].num_of_phases_rx,
WR_OP_ODPG_DATA_CMD_BURST_DLY,
ODPG_MODE_TX, cs, STRESS_NONE, DURATION_SINGLE);
/* odpg bist write enable */
ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG,
(ODPG_WRBUF_WR_CTRL_ENA << ODPG_WRBUF_WR_CTRL_OFFS),
(ODPG_WRBUF_WR_CTRL_MASK << ODPG_WRBUF_WR_CTRL_OFFS));
/* odpg bist read disable */
ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG,
(ODPG_WRBUF_RD_CTRL_DIS << ODPG_WRBUF_RD_CTRL_OFFS),
(ODPG_WRBUF_RD_CTRL_MASK << ODPG_WRBUF_RD_CTRL_OFFS));
/* trigger odpg */
mv_ddr_bist_tx(ACCESS_TYPE_MULTICAST);
}
/* fill memory with vref pattern to increment addr using odpg bist */
mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE,
bist_offset, cs, pattern_table[pattern].num_of_phases_tx,
(pattern == PATTERN_00) ? DM_DIR_DIRECT : DM_DIR_INVERSE);
for (adll_tap = 0; adll_tap < ADLL_TAPS_PER_PERIOD; adll_tap++) {
ddr3_tip_bus_write(0, ACCESS_TYPE_UNICAST, 0, ACCESS_TYPE_MULTICAST, 0,
DDR_PHY_DATA, CTX_PHY_REG(cs), adll_tap);
/* change target odpg address */
odpg_addr = adll_tap * burst_len;
ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_BUFFER_OFFS_REG,
odpg_addr, MASK_ALL_BITS);
ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE,
pattern_table[pattern].num_of_phases_tx,
pattern_table[pattern].tx_burst_size,
pattern_table[pattern].num_of_phases_rx,
WR_OP_ODPG_DATA_CMD_BURST_DLY,
ODPG_MODE_TX, cs, STRESS_NONE, DURATION_SINGLE);
/* odpg bist write enable */
ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG,
(ODPG_WRBUF_WR_CTRL_ENA << ODPG_WRBUF_WR_CTRL_OFFS),
(ODPG_WRBUF_WR_CTRL_MASK << ODPG_WRBUF_WR_CTRL_OFFS));
/* odpg bist read disable */
ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG,
(ODPG_WRBUF_RD_CTRL_DIS << ODPG_WRBUF_RD_CTRL_OFFS),
(ODPG_WRBUF_RD_CTRL_MASK << ODPG_WRBUF_RD_CTRL_OFFS));
/* trigger odpg */
mv_ddr_bist_tx(ACCESS_TYPE_MULTICAST);
}
/* restore subphy's tx adll_tap to its position */
for (subphy = 0; subphy < subphy_max; subphy++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy);
ddr3_tip_bus_write(0, ACCESS_TYPE_UNICAST, 0, ACCESS_TYPE_UNICAST,
subphy, DDR_PHY_DATA, CTX_PHY_REG(cs),
wr_ctrl_adll[subphy]);
}
/* read and validate bist (comparing with the base pattern) */
for (adll_tap = 0; adll_tap < ADLL_TAPS_PER_PERIOD; adll_tap++) {
result = 0;
odpg_addr = adll_tap * burst_len;
/* change addr to fit write */
mv_ddr_pattern_start_addr_set(pattern_table, pattern, odpg_addr);
mv_ddr_tip_bist(OPER_READ, 0, pattern, 0, &result);
for (subphy = 0; subphy < subphy_max; subphy++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy);
idx = ADLL_TAPS_PER_PERIOD * subphy + adll_tap;
vw_vector[idx] |= ((result >> subphy) & 0x1);
}
}
/* restore subphy's rx adll_tap to its position */
for (subphy = 0; subphy < subphy_max; subphy++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy);
ddr3_tip_bus_write(0, ACCESS_TYPE_UNICAST, 0, ACCESS_TYPE_UNICAST,
subphy, DDR_PHY_DATA, CRX_PHY_REG(cs),
rd_ctrl_adll[subphy]);
}
return MV_OK;
}
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
+716
View File
@@ -0,0 +1,716 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#include "ddr3_init.h"
#include "mv_ddr_regs.h"
#define VALIDATE_WIN_LENGTH(e1, e2, maxsize) \
(((e2) + 1 > (e1) + (u8)MIN_WINDOW_SIZE) && \
((e2) + 1 < (e1) + (u8)maxsize))
#define IS_WINDOW_OUT_BOUNDARY(e1, e2, maxsize) \
(((e1) == 0 && (e2) != 0) || \
((e1) != (maxsize - 1) && (e2) == (maxsize - 1)))
#define CENTRAL_TX 0
#define CENTRAL_RX 1
#define NUM_OF_CENTRAL_TYPES 2
u32 start_pattern = PATTERN_KILLER_DQ0, end_pattern = PATTERN_KILLER_DQ7;
u32 start_if = 0, end_if = (MAX_INTERFACE_NUM - 1);
u8 bus_end_window[NUM_OF_CENTRAL_TYPES][MAX_INTERFACE_NUM][MAX_BUS_NUM];
u8 bus_start_window[NUM_OF_CENTRAL_TYPES][MAX_INTERFACE_NUM][MAX_BUS_NUM];
u8 centralization_state[MAX_INTERFACE_NUM][MAX_BUS_NUM];
static u8 ddr3_tip_special_rx_run_once_flag;
static int ddr3_tip_centralization(u32 dev_num, u32 mode);
/*
* Centralization RX Flow
*/
int ddr3_tip_centralization_rx(u32 dev_num)
{
CHECK_STATUS(ddr3_tip_special_rx(dev_num));
CHECK_STATUS(ddr3_tip_centralization(dev_num, CENTRAL_RX));
return MV_OK;
}
/*
* Centralization TX Flow
*/
int ddr3_tip_centralization_tx(u32 dev_num)
{
CHECK_STATUS(ddr3_tip_centralization(dev_num, CENTRAL_TX));
return MV_OK;
}
/*
* Centralization Flow
*/
static int ddr3_tip_centralization(u32 dev_num, u32 mode)
{
enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM];
u32 if_id, pattern_id, bit_id;
u8 bus_id;
u8 cur_start_win[BUS_WIDTH_IN_BITS];
u8 centralization_result[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS];
u8 cur_end_win[BUS_WIDTH_IN_BITS];
u8 current_window[BUS_WIDTH_IN_BITS];
u8 opt_window, waste_window, start_window_skew, end_window_skew;
u8 final_pup_window[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS];
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
enum hws_training_result result_type = RESULT_PER_BIT;
enum hws_dir direction;
u32 *result[HWS_SEARCH_DIR_LIMIT];
u32 reg_phy_off, reg;
u8 max_win_size;
int lock_success = 1;
u8 cur_end_win_min, cur_start_win_max;
u32 cs_enable_reg_val[MAX_INTERFACE_NUM];
int is_if_fail = 0;
enum hws_result *flow_result = ddr3_tip_get_result_ptr(training_stage);
u32 pup_win_length = 0;
enum hws_search_dir search_dir_id;
u8 cons_tap = (mode == CENTRAL_TX) ? (64) : (0);
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
/* save current cs enable reg val */
CHECK_STATUS(ddr3_tip_if_read
(dev_num, ACCESS_TYPE_UNICAST, if_id,
DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS));
/* enable single cs */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id,
DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3)));
}
if (mode == CENTRAL_TX) {
max_win_size = MAX_WINDOW_SIZE_TX;
reg_phy_off = CTX_PHY_REG(effective_cs);
direction = OPER_WRITE;
} else {
max_win_size = MAX_WINDOW_SIZE_RX;
reg_phy_off = CRX_PHY_REG(effective_cs);
direction = OPER_READ;
}
/* DB initialization */
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (bus_id = 0;
bus_id < octets_per_if_num; bus_id++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
centralization_state[if_id][bus_id] = 0;
bus_end_window[mode][if_id][bus_id] =
(max_win_size - 1) + cons_tap;
bus_start_window[mode][if_id][bus_id] = 0;
centralization_result[if_id][bus_id] = 0;
}
}
/* start flow */
for (pattern_id = start_pattern; pattern_id <= end_pattern;
pattern_id++) {
ddr3_tip_ip_training_wrapper(dev_num, ACCESS_TYPE_MULTICAST,
PARAM_NOT_CARE,
ACCESS_TYPE_MULTICAST,
PARAM_NOT_CARE, result_type,
HWS_CONTROL_ELEMENT_ADLL,
PARAM_NOT_CARE, direction,
tm->
if_act_mask, 0x0,
max_win_size - 1,
max_win_size - 1,
pattern_id, EDGE_FPF, CS_SINGLE,
PARAM_NOT_CARE, training_result);
for (if_id = start_if; if_id <= end_if; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (bus_id = 0;
bus_id <= octets_per_if_num - 1;
bus_id++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
for (search_dir_id = HWS_LOW2HIGH;
search_dir_id <= HWS_HIGH2LOW;
search_dir_id++) {
CHECK_STATUS
(ddr3_tip_read_training_result
(dev_num, if_id,
ACCESS_TYPE_UNICAST, bus_id,
ALL_BITS_PER_PUP,
search_dir_id,
direction, result_type,
TRAINING_LOAD_OPERATION_UNLOAD,
CS_SINGLE,
&result[search_dir_id],
1, 0, 0));
DEBUG_CENTRALIZATION_ENGINE
(DEBUG_LEVEL_INFO,
("%s pat %d IF %d pup %d Regs: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
((mode ==
CENTRAL_TX) ? "TX" : "RX"),
pattern_id, if_id, bus_id,
result[search_dir_id][0],
result[search_dir_id][1],
result[search_dir_id][2],
result[search_dir_id][3],
result[search_dir_id][4],
result[search_dir_id][5],
result[search_dir_id][6],
result[search_dir_id][7]));
}
for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS;
bit_id++) {
/* check if this code is valid for 2 edge, probably not :( */
cur_start_win[bit_id] =
GET_TAP_RESULT(result
[HWS_LOW2HIGH]
[bit_id],
EDGE_1);
cur_end_win[bit_id] =
GET_TAP_RESULT(result
[HWS_HIGH2LOW]
[bit_id],
EDGE_1);
/* window length */
current_window[bit_id] =
cur_end_win[bit_id] -
cur_start_win[bit_id] + 1;
DEBUG_CENTRALIZATION_ENGINE
(DEBUG_LEVEL_TRACE,
("cs %x patern %d IF %d pup %d cur_start_win %d cur_end_win %d current_window %d\n",
effective_cs, pattern_id,
if_id, bus_id,
cur_start_win[bit_id],
cur_end_win[bit_id],
current_window[bit_id]));
}
if ((ddr3_tip_is_pup_lock
(result[HWS_LOW2HIGH], result_type)) &&
(ddr3_tip_is_pup_lock
(result[HWS_HIGH2LOW], result_type))) {
/* read result success */
DEBUG_CENTRALIZATION_ENGINE
(DEBUG_LEVEL_INFO,
("Pup locked, pat %d IF %d pup %d\n",
pattern_id, if_id, bus_id));
} else {
/* read result failure */
DEBUG_CENTRALIZATION_ENGINE
(DEBUG_LEVEL_INFO,
("fail Lock, pat %d IF %d pup %d\n",
pattern_id, if_id, bus_id));
if (centralization_state[if_id][bus_id]
== 1) {
/* continue with next pup */
DEBUG_CENTRALIZATION_ENGINE
(DEBUG_LEVEL_TRACE,
("continue to next pup %d %d\n",
if_id, bus_id));
continue;
}
for (bit_id = 0;
bit_id < BUS_WIDTH_IN_BITS;
bit_id++) {
/*
* the next check is relevant
* only when using search
* machine 2 edges
*/
if (cur_start_win[bit_id] > 0 &&
cur_end_win[bit_id] == 0) {
cur_end_win
[bit_id] =
max_win_size - 1;
DEBUG_CENTRALIZATION_ENGINE
(DEBUG_LEVEL_TRACE,
("fail, IF %d pup %d bit %d fail #1\n",
if_id, bus_id,
bit_id));
/* the next bit */
continue;
} else {
centralization_state
[if_id][bus_id] = 1;
DEBUG_CENTRALIZATION_ENGINE
(DEBUG_LEVEL_TRACE,
("fail, IF %d pup %d bit %d fail #2\n",
if_id, bus_id,
bit_id));
}
}
if (centralization_state[if_id][bus_id]
== 1) {
/* going to next pup */
continue;
}
} /*bit */
opt_window =
ddr3_tip_get_buf_min(current_window);
/* final pup window length */
final_pup_window[if_id][bus_id] =
ddr3_tip_get_buf_min(cur_end_win) -
ddr3_tip_get_buf_max(cur_start_win) +
1;
waste_window =
opt_window -
final_pup_window[if_id][bus_id];
start_window_skew =
ddr3_tip_get_buf_max(cur_start_win) -
ddr3_tip_get_buf_min(
cur_start_win);
end_window_skew =
ddr3_tip_get_buf_max(
cur_end_win) -
ddr3_tip_get_buf_min(
cur_end_win);
/* min/max updated with pattern change */
cur_end_win_min =
ddr3_tip_get_buf_min(
cur_end_win);
cur_start_win_max =
ddr3_tip_get_buf_max(
cur_start_win);
bus_end_window[mode][if_id][bus_id] =
GET_MIN(bus_end_window[mode][if_id]
[bus_id],
cur_end_win_min);
bus_start_window[mode][if_id][bus_id] =
GET_MAX(bus_start_window[mode][if_id]
[bus_id],
cur_start_win_max);
DEBUG_CENTRALIZATION_ENGINE(
DEBUG_LEVEL_INFO,
("pat %d IF %d pup %d opt_win %d final_win %d waste_win %d st_win_skew %d end_win_skew %d cur_st_win_max %d cur_end_win_min %d bus_st_win %d bus_end_win %d\n",
pattern_id, if_id, bus_id, opt_window,
final_pup_window[if_id][bus_id],
waste_window, start_window_skew,
end_window_skew,
cur_start_win_max,
cur_end_win_min,
bus_start_window[mode][if_id][bus_id],
bus_end_window[mode][if_id][bus_id]));
/* check if window is valid */
if (ddr3_tip_centr_skip_min_win_check == 0) {
if ((VALIDATE_WIN_LENGTH
(bus_start_window[mode][if_id]
[bus_id],
bus_end_window[mode][if_id]
[bus_id],
max_win_size) == 1) ||
(IS_WINDOW_OUT_BOUNDARY
(bus_start_window[mode][if_id]
[bus_id],
bus_end_window[mode][if_id]
[bus_id],
max_win_size) == 1)) {
DEBUG_CENTRALIZATION_ENGINE
(DEBUG_LEVEL_INFO,
("win valid, pat %d IF %d pup %d\n",
pattern_id, if_id,
bus_id));
/* window is valid */
} else {
DEBUG_CENTRALIZATION_ENGINE
(DEBUG_LEVEL_INFO,
("fail win, pat %d IF %d pup %d bus_st_win %d bus_end_win %d\n",
pattern_id, if_id, bus_id,
bus_start_window[mode]
[if_id][bus_id],
bus_end_window[mode]
[if_id][bus_id]));
centralization_state[if_id]
[bus_id] = 1;
if (debug_mode == 0) {
flow_result[if_id] = TEST_FAILED;
return MV_FAIL;
}
}
} /* ddr3_tip_centr_skip_min_win_check */
} /* pup */
} /* interface */
} /* pattern */
for (if_id = start_if; if_id <= end_if; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
is_if_fail = 0;
flow_result[if_id] = TEST_SUCCESS;
for (bus_id = 0;
bus_id <= (octets_per_if_num - 1); bus_id++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
/* continue only if lock */
if (centralization_state[if_id][bus_id] != 1) {
if (ddr3_tip_centr_skip_min_win_check == 0) {
if ((bus_end_window
[mode][if_id][bus_id] ==
(max_win_size - 1)) &&
((bus_end_window
[mode][if_id][bus_id] -
bus_start_window[mode][if_id]
[bus_id]) < MIN_WINDOW_SIZE) &&
((bus_end_window[mode][if_id]
[bus_id] - bus_start_window
[mode][if_id][bus_id]) > 2)) {
/* prevent false lock */
/* TBD change to enum */
centralization_state
[if_id][bus_id] = 2;
}
if ((bus_end_window[mode][if_id][bus_id]
== 0) &&
((bus_end_window[mode][if_id]
[bus_id] -
bus_start_window[mode][if_id]
[bus_id]) < MIN_WINDOW_SIZE) &&
((bus_end_window[mode][if_id]
[bus_id] -
bus_start_window[mode][if_id]
[bus_id]) > 2))
/*prevent false lock */
centralization_state[if_id]
[bus_id] = 3;
}
if ((bus_end_window[mode][if_id][bus_id] >
(max_win_size - 1)) && direction ==
OPER_WRITE) {
DEBUG_CENTRALIZATION_ENGINE
(DEBUG_LEVEL_INFO,
("Tx special pattern\n"));
cons_tap = 64;
}
}
/* check states */
if (centralization_state[if_id][bus_id] == 3) {
DEBUG_CENTRALIZATION_ENGINE(
DEBUG_LEVEL_INFO,
("SSW - TBD IF %d pup %d\n",
if_id, bus_id));
lock_success = 1;
} else if (centralization_state[if_id][bus_id] == 2) {
DEBUG_CENTRALIZATION_ENGINE(
DEBUG_LEVEL_INFO,
("SEW - TBD IF %d pup %d\n",
if_id, bus_id));
lock_success = 1;
} else if (centralization_state[if_id][bus_id] == 0) {
lock_success = 1;
} else {
DEBUG_CENTRALIZATION_ENGINE(
DEBUG_LEVEL_ERROR,
("fail, IF %d pup %d\n",
if_id, bus_id));
lock_success = 0;
}
if (lock_success == 1) {
centralization_result[if_id][bus_id] =
(bus_end_window[mode][if_id][bus_id] +
bus_start_window[mode][if_id][bus_id])
/ 2 - cons_tap;
DEBUG_CENTRALIZATION_ENGINE(
DEBUG_LEVEL_TRACE,
(" bus_id %d Res= %d\n", bus_id,
centralization_result[if_id][bus_id]));
/* copy results to registers */
pup_win_length =
bus_end_window[mode][if_id][bus_id] -
bus_start_window[mode][if_id][bus_id] +
1;
ddr3_tip_bus_read(dev_num, if_id,
ACCESS_TYPE_UNICAST, bus_id,
DDR_PHY_DATA,
RESULT_PHY_REG +
effective_cs, &reg);
reg = (reg & (~0x1f <<
((mode == CENTRAL_TX) ?
(RESULT_PHY_TX_OFFS) :
(RESULT_PHY_RX_OFFS))))
| pup_win_length <<
((mode == CENTRAL_TX) ?
(RESULT_PHY_TX_OFFS) :
(RESULT_PHY_RX_OFFS));
CHECK_STATUS(ddr3_tip_bus_write
(dev_num, ACCESS_TYPE_UNICAST,
if_id, ACCESS_TYPE_UNICAST,
bus_id, DDR_PHY_DATA,
RESULT_PHY_REG +
effective_cs, reg));
/* offset per CS is calculated earlier */
CHECK_STATUS(
ddr3_tip_bus_write(dev_num,
ACCESS_TYPE_UNICAST,
if_id,
ACCESS_TYPE_UNICAST,
bus_id,
DDR_PHY_DATA,
reg_phy_off,
centralization_result
[if_id]
[bus_id]));
} else {
is_if_fail = 1;
}
}
if (is_if_fail == 1)
flow_result[if_id] = TEST_FAILED;
}
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
/* restore cs enable value */
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST,
if_id, DUAL_DUNIT_CFG_REG,
cs_enable_reg_val[if_id],
MASK_ALL_BITS));
}
return is_if_fail;
}
/*
* Centralization Flow
*/
int ddr3_tip_special_rx(u32 dev_num)
{
enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM];
u32 if_id, pup_id, pattern_id, bit_id;
u8 cur_start_win[BUS_WIDTH_IN_BITS];
u8 cur_end_win[BUS_WIDTH_IN_BITS];
enum hws_training_result result_type = RESULT_PER_BIT;
enum hws_dir direction;
enum hws_search_dir search_dir_id;
u32 *result[HWS_SEARCH_DIR_LIMIT];
u32 max_win_size;
u8 cur_end_win_min, cur_start_win_max;
u32 cs_enable_reg_val[MAX_INTERFACE_NUM];
u32 temp = 0;
int pad_num = 0;
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
if ((ddr3_tip_special_rx_run_once_flag & (1 << effective_cs)) == (1 << effective_cs))
return MV_OK;
ddr3_tip_special_rx_run_once_flag |= (1 << effective_cs);
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
/* save current cs enable reg val */
CHECK_STATUS(ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST,
if_id, DUAL_DUNIT_CFG_REG,
cs_enable_reg_val,
MASK_ALL_BITS));
/* enable single cs */
CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST,
if_id, DUAL_DUNIT_CFG_REG,
(1 << 3), (1 << 3)));
}
max_win_size = MAX_WINDOW_SIZE_RX;
direction = OPER_READ;
pattern_id = PATTERN_FULL_SSO1;
/* start flow */
ddr3_tip_ip_training_wrapper(dev_num, ACCESS_TYPE_MULTICAST,
PARAM_NOT_CARE, ACCESS_TYPE_MULTICAST,
PARAM_NOT_CARE, result_type,
HWS_CONTROL_ELEMENT_ADLL,
PARAM_NOT_CARE, direction,
tm->if_act_mask, 0x0,
max_win_size - 1, max_win_size - 1,
pattern_id, EDGE_FPF, CS_SINGLE,
PARAM_NOT_CARE, training_result);
for (if_id = start_if; if_id <= end_if; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (pup_id = 0;
pup_id <= octets_per_if_num; pup_id++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup_id);
for (search_dir_id = HWS_LOW2HIGH;
search_dir_id <= HWS_HIGH2LOW;
search_dir_id++) {
CHECK_STATUS(ddr3_tip_read_training_result
(dev_num, if_id,
ACCESS_TYPE_UNICAST, pup_id,
ALL_BITS_PER_PUP, search_dir_id,
direction, result_type,
TRAINING_LOAD_OPERATION_UNLOAD,
CS_SINGLE, &result[search_dir_id],
1, 0, 0));
DEBUG_CENTRALIZATION_ENGINE(DEBUG_LEVEL_INFO,
("Special: pat %d IF %d pup %d Regs: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
pattern_id, if_id,
pup_id,
result
[search_dir_id][0],
result
[search_dir_id][1],
result
[search_dir_id][2],
result
[search_dir_id][3],
result
[search_dir_id][4],
result
[search_dir_id][5],
result
[search_dir_id][6],
result
[search_dir_id]
[7]));
}
for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS; bit_id++) {
/*
* check if this code is valid for 2 edge,
* probably not :(
*/
cur_start_win[bit_id] =
GET_TAP_RESULT(result[HWS_LOW2HIGH]
[bit_id], EDGE_1);
cur_end_win[bit_id] =
GET_TAP_RESULT(result[HWS_HIGH2LOW]
[bit_id], EDGE_1);
}
if (!((ddr3_tip_is_pup_lock
(result[HWS_LOW2HIGH], result_type)) &&
(ddr3_tip_is_pup_lock
(result[HWS_HIGH2LOW], result_type)))) {
DEBUG_CENTRALIZATION_ENGINE(
DEBUG_LEVEL_ERROR,
("Special: Pup lock fail, pat %d IF %d pup %d\n",
pattern_id, if_id, pup_id));
return MV_FAIL;
}
cur_end_win_min =
ddr3_tip_get_buf_min(cur_end_win);
cur_start_win_max =
ddr3_tip_get_buf_max(cur_start_win);
if (cur_start_win_max <= 1) { /* Align left */
for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS;
bit_id++) {
pad_num =
dq_map_table[bit_id +
pup_id *
BUS_WIDTH_IN_BITS +
if_id *
BUS_WIDTH_IN_BITS *
MAX_BUS_NUM];
CHECK_STATUS(ddr3_tip_bus_read
(dev_num, if_id,
ACCESS_TYPE_UNICAST,
pup_id, DDR_PHY_DATA,
PBS_RX_PHY_REG(effective_cs, pad_num),
&temp));
temp = (temp + 0xa > 31) ?
(31) : (temp + 0xa);
CHECK_STATUS(ddr3_tip_bus_write
(dev_num,
ACCESS_TYPE_UNICAST,
if_id,
ACCESS_TYPE_UNICAST,
pup_id, DDR_PHY_DATA,
PBS_RX_PHY_REG(effective_cs, pad_num),
temp));
}
DEBUG_CENTRALIZATION_ENGINE(
DEBUG_LEVEL_INFO,
("Special: PBS:: I/F# %d , Bus# %d fix align to the Left\n",
if_id, pup_id));
}
if (cur_end_win_min > 30) { /* Align right */
CHECK_STATUS(ddr3_tip_bus_read
(dev_num, if_id,
ACCESS_TYPE_UNICAST, pup_id,
DDR_PHY_DATA,
PBS_RX_PHY_REG(effective_cs, 4),
&temp));
temp += 0xa;
CHECK_STATUS(ddr3_tip_bus_write
(dev_num, ACCESS_TYPE_UNICAST,
if_id, ACCESS_TYPE_UNICAST,
pup_id, DDR_PHY_DATA,
PBS_RX_PHY_REG(effective_cs, 4),
temp));
CHECK_STATUS(ddr3_tip_bus_read
(dev_num, if_id,
ACCESS_TYPE_UNICAST, pup_id,
DDR_PHY_DATA,
PBS_RX_PHY_REG(effective_cs, 5),
&temp));
temp += 0xa;
CHECK_STATUS(ddr3_tip_bus_write
(dev_num, ACCESS_TYPE_UNICAST,
if_id, ACCESS_TYPE_UNICAST,
pup_id, DDR_PHY_DATA,
PBS_RX_PHY_REG(effective_cs, 5),
temp));
DEBUG_CENTRALIZATION_ENGINE(
DEBUG_LEVEL_INFO,
("Special: PBS:: I/F# %d , Bus# %d fix align to the right\n",
if_id, pup_id));
}
vref_window_size[if_id][pup_id] =
cur_end_win_min -
cur_start_win_max + 1;
DEBUG_CENTRALIZATION_ENGINE(
DEBUG_LEVEL_INFO,
("Special: Winsize I/F# %d , Bus# %d is %d\n",
if_id, pup_id, vref_window_size
[if_id][pup_id]));
} /* pup */
} /* end of interface */
return MV_OK;
}
/*
* Print Centralization Result
*/
int ddr3_tip_print_centralization_result(u32 dev_num)
{
u32 if_id = 0, bus_id = 0;
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
dev_num = dev_num;
printf("Centralization Results\n");
printf("I/F0 Result[0 - success 1-fail 2 - state_2 3 - state_3] ...\n");
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (bus_id = 0; bus_id < octets_per_if_num;
bus_id++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
printf("%d ,\n", centralization_state[if_id][bus_id]);
}
}
return MV_OK;
}
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training_db.c
+871
View File
@@ -0,0 +1,871 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#include "ddr_ml_wrapper.h"
#include "ddr3_training_ip_flow.h"
#include "mv_ddr_topology.h"
#include "mv_ddr_training_db.h"
#include "ddr3_training_ip_db.h"
/* Device attributes structures */
enum mv_ddr_dev_attribute ddr_dev_attributes[MV_ATTR_LAST];
int ddr_dev_attr_init_done = 0;
static inline u32 pattern_table_get_killer_word16(u8 dqs, u8 index);
static inline u32 pattern_table_get_sso_word(u8 sso, u8 index);
static inline u32 pattern_table_get_vref_word(u8 index);
static inline u32 pattern_table_get_vref_word16(u8 index);
static inline u32 pattern_table_get_sso_full_xtalk_word(u8 bit, u8 index);
static inline u32 pattern_table_get_sso_full_xtalk_word16(u8 bit, u8 index);
static inline u32 pattern_table_get_sso_xtalk_free_word(u8 bit, u8 index);
static inline u32 pattern_table_get_sso_xtalk_free_word16(u8 bit, u8 index);
static inline u32 pattern_table_get_isi_word(u8 index);
static inline u32 pattern_table_get_isi_word16(u8 index);
/* List of allowed frequency listed in order of enum mv_ddr_freq */
static unsigned int freq_val[MV_DDR_FREQ_LAST] = {
0, /*MV_DDR_FREQ_LOW_FREQ */
400, /*MV_DDR_FREQ_400, */
533, /*MV_DDR_FREQ_533, */
666, /*MV_DDR_FREQ_667, */
800, /*MV_DDR_FREQ_800, */
933, /*MV_DDR_FREQ_933, */
1066, /*MV_DDR_FREQ_1066, */
311, /*MV_DDR_FREQ_311, */
333, /*MV_DDR_FREQ_333, */
467, /*MV_DDR_FREQ_467, */
850, /*MV_DDR_FREQ_850, */
600, /*MV_DDR_FREQ_600 */
300, /*MV_DDR_FREQ_300 */
900, /*MV_DDR_FREQ_900 */
360, /*MV_DDR_FREQ_360 */
1000 /*MV_DDR_FREQ_1000 */
};
unsigned int *mv_ddr_freq_tbl_get(void)
{
return &freq_val[0];
}
u32 mv_ddr_freq_get(enum mv_ddr_freq freq)
{
return freq_val[freq];
}
/* cas latency values per frequency for each speed bin index */
static struct mv_ddr_cl_val_per_freq cl_table[] = {
/*
* 400M 667M 933M 311M 467M 600M 360
* 100M 533M 800M 1066M 333M 850M 900
* 1000 (the order is 100, 400, 533 etc.)
*/
/* DDR3-800D */
{ {6, 5, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0, 5, 0, 5, 0} },
/* DDR3-800E */
{ {6, 6, 0, 0, 0, 0, 0, 6, 6, 0, 0, 0, 6, 0, 6, 0} },
/* DDR3-1066E */
{ {6, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 0, 5, 0, 5, 0} },
/* DDR3-1066F */
{ {6, 6, 7, 0, 0, 0, 0, 6, 6, 7, 0, 0, 6, 0, 6, 0} },
/* DDR3-1066G */
{ {6, 6, 8, 0, 0, 0, 0, 6, 6, 8, 0, 0, 6, 0, 6, 0} },
/* DDR3-1333F* */
{ {6, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
/* DDR3-1333G */
{ {6, 5, 7, 8, 0, 0, 0, 5, 5, 7, 0, 8, 5, 0, 5, 0} },
/* DDR3-1333H */
{ {6, 6, 8, 9, 0, 0, 0, 6, 6, 8, 0, 9, 6, 0, 6, 0} },
/* DDR3-1333J* */
{ {6, 6, 8, 10, 0, 0, 0, 6, 6, 8, 0, 10, 6, 0, 6, 0}
/* DDR3-1600G* */},
{ {6, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
/* DDR3-1600H */
{ {6, 5, 6, 8, 9, 0, 0, 5, 5, 6, 0, 8, 5, 0, 5, 0} },
/* DDR3-1600J */
{ {6, 5, 7, 9, 10, 0, 0, 5, 5, 7, 0, 9, 5, 0, 5, 0} },
/* DDR3-1600K */
{ {6, 6, 8, 10, 11, 0, 0, 6, 6, 8, 0, 10, 6, 0, 6, 0 } },
/* DDR3-1866J* */
{ {6, 5, 6, 8, 9, 11, 0, 5, 5, 6, 11, 8, 5, 0, 5, 0} },
/* DDR3-1866K */
{ {6, 5, 7, 8, 10, 11, 0, 5, 5, 7, 11, 8, 5, 11, 5, 11} },
/* DDR3-1866L */
{ {6, 6, 7, 9, 11, 12, 0, 6, 6, 7, 12, 9, 6, 12, 6, 12} },
/* DDR3-1866M* */
{ {6, 6, 8, 10, 11, 13, 0, 6, 6, 8, 13, 10, 6, 13, 6, 13} },
/* DDR3-2133K* */
{ {6, 5, 6, 7, 9, 10, 11, 5, 5, 6, 10, 7, 5, 11, 5, 11} },
/* DDR3-2133L */
{ {6, 5, 6, 8, 9, 11, 12, 5, 5, 6, 11, 8, 5, 12, 5, 12} },
/* DDR3-2133M */
{ {6, 5, 7, 9, 10, 12, 13, 5, 5, 7, 12, 9, 5, 13, 5, 13} },
/* DDR3-2133N* */
{ {6, 6, 7, 9, 11, 13, 14, 6, 6, 7, 13, 9, 6, 14, 6, 14} },
/* DDR3-1333H-ext */
{ {6, 6, 7, 9, 0, 0, 0, 6, 6, 7, 0, 9, 6, 0, 6, 0} },
/* DDR3-1600K-ext */
{ {6, 6, 7, 9, 11, 0, 0, 6, 6, 7, 0, 9, 6, 0, 6, 0} },
/* DDR3-1866M-ext */
{ {6, 6, 7, 9, 11, 13, 0, 6, 6, 7, 13, 9, 6, 13, 6, 13} },
};
u32 mv_ddr_cl_val_get(u32 index, u32 freq)
{
return cl_table[index].cl_val[freq];
}
/* cas write latency values per frequency for each speed bin index */
static struct mv_ddr_cl_val_per_freq cwl_table[] = {
/*
* 400M 667M 933M 311M 467M 600M 360
* 100M 533M 800M 1066M 333M 850M 900
* (the order is 100, 400, 533 etc.)
*/
/* DDR3-800D */
{ {5, 5, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0, 5, 0, 5, 0} },
/* DDR3-800E */
{ {5, 5, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0, 5, 0, 5, 0} },
/* DDR3-1066E */
{ {5, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
/* DDR3-1066F */
{ {5, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
/* DDR3-1066G */
{ {5, 5, 6, 0, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
/* DDR3-1333F* */
{ {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
/* DDR3-1333G */
{ {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
/* DDR3-1333H */
{ {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
/* DDR3-1333J* */
{ {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
/* DDR3-1600G* */
{ {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
/* DDR3-1600H */
{ {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
/* DDR3-1600J */
{ {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
/* DDR3-1600K */
{ {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
/* DDR3-1866J* */
{ {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 0, 5, 0} },
/* DDR3-1866K */
{ {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 0, 5, 0} },
/* DDR3-1866L */
{ {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 9, 5, 9} },
/* DDR3-1866M* */
{ {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 9, 5, 9} },
/* DDR3-2133K* */
{ {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} },
/* DDR3-2133L */
{ {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} },
/* DDR3-2133M */
{ {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} },
/* DDR3-2133N* */
{ {5, 5, 6, 7, 8, 9, 10, 5, 5, 6, 9, 7, 5, 9, 5, 10} },
/* DDR3-1333H-ext */
{ {5, 5, 6, 7, 0, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
/* DDR3-1600K-ext */
{ {5, 5, 6, 7, 8, 0, 0, 5, 5, 6, 0, 7, 5, 0, 5, 0} },
/* DDR3-1866M-ext */
{ {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 9, 5, 9} },
};
u32 mv_ddr_cwl_val_get(u32 index, u32 freq)
{
return cwl_table[index].cl_val[freq];
}
u8 twr_mask_table[] = {
10,
10,
10,
10,
10,
1, /* 5 */
2, /* 6 */
3, /* 7 */
4, /* 8 */
10,
5, /* 10 */
10,
6, /* 12 */
10,
7, /* 14 */
10,
0 /* 16 */
};
u8 cl_mask_table[] = {
0,
0,
0,
0,
0,
0x2,
0x4,
0x6,
0x8,
0xa,
0xc,
0xe,
0x1,
0x3,
0x5,
0x5
};
u8 cwl_mask_table[] = {
0,
0,
0,
0,
0,
0,
0x1,
0x2,
0x3,
0x4,
0x5,
0x6,
0x7,
0x8,
0x9,
0x9
};
/* RFC values (in ns) */
static unsigned int rfc_table[] = {
90, /* 512M */
110, /* 1G */
160, /* 2G */
260, /* 4G */
350, /* 8G */
0, /* TODO: placeholder for 16-Mbit dev width */
0, /* TODO: placeholder for 32-Mbit dev width */
0, /* TODO: placeholder for 12-Mbit dev width */
0 /* TODO: placeholder for 24-Mbit dev width */
};
u32 mv_ddr_rfc_get(u32 mem)
{
return rfc_table[mem];
}
u32 speed_bin_table_t_rc[] = {
50000,
52500,
48750,
50625,
52500,
46500,
48000,
49500,
51000,
45000,
46250,
47500,
48750,
44700,
45770,
46840,
47910,
43285,
44220,
45155,
46090
};
u32 speed_bin_table_t_rcd_t_rp[] = {
12500,
15000,
11250,
13125,
15000,
10500,
12000,
13500,
15000,
10000,
11250,
12500,
13750,
10700,
11770,
12840,
13910,
10285,
11220,
12155,
13090,
};
enum {
PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_AGGRESSOR = 0,
PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM
};
static u8 pattern_killer_pattern_table_map[KILLER_PATTERN_LENGTH * 2][2] = {
/*Aggressor / Victim */
{1, 0},
{0, 0},
{1, 0},
{1, 1},
{0, 1},
{0, 1},
{1, 0},
{0, 1},
{1, 0},
{0, 1},
{1, 0},
{1, 0},
{0, 1},
{1, 0},
{0, 1},
{0, 0},
{1, 1},
{0, 0},
{1, 1},
{0, 0},
{1, 1},
{0, 0},
{1, 1},
{1, 0},
{0, 0},
{1, 1},
{0, 0},
{1, 1},
{0, 0},
{0, 0},
{0, 0},
{0, 1},
{0, 1},
{1, 1},
{0, 0},
{0, 0},
{1, 1},
{1, 1},
{0, 0},
{1, 1},
{0, 0},
{1, 1},
{1, 1},
{0, 0},
{0, 0},
{1, 1},
{0, 0},
{1, 1},
{0, 1},
{0, 0},
{0, 1},
{0, 1},
{0, 0},
{1, 1},
{1, 1},
{1, 0},
{1, 0},
{1, 1},
{1, 1},
{1, 1},
{1, 1},
{1, 1},
{1, 1},
{1, 1}
};
static u8 pattern_vref_pattern_table_map[] = {
/* 1 means 0xffffffff, 0 is 0x0 */
0xb8,
0x52,
0x55,
0x8a,
0x33,
0xa6,
0x6d,
0xfe
};
static struct mv_ddr_page_element page_tbl[] = {
/* 8-bit, 16-bit page size */
{MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 512M */
{MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 1G */
{MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 2G */
{MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 4G */
{MV_DDR_PAGE_SIZE_2K, MV_DDR_PAGE_SIZE_2K}, /* 8G */
{0, 0}, /* TODO: placeholder for 16-Mbit die capacity */
{0, 0}, /* TODO: placeholder for 32-Mbit die capacity */
{0, 0}, /* TODO: placeholder for 12-Mbit die capacity */
{0, 0} /* TODO: placeholder for 24-Mbit die capacity */
};
u32 mv_ddr_page_size_get(enum mv_ddr_dev_width bus_width, enum mv_ddr_die_capacity mem_size)
{
if (bus_width == MV_DDR_DEV_WIDTH_8BIT)
return page_tbl[mem_size].page_size_8bit;
else
return page_tbl[mem_size].page_size_16bit;
}
/* Return speed Bin value for selected index and t* element */
unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_ddr_speed_bin_timing element)
{
u32 result = 0;
switch (element) {
case SPEED_BIN_TRCD:
case SPEED_BIN_TRP:
result = speed_bin_table_t_rcd_t_rp[index];
break;
case SPEED_BIN_TRAS:
if (index <= SPEED_BIN_DDR_1066G)
result = 37500;
else if (index <= SPEED_BIN_DDR_1333J)
result = 36000;
else if (index <= SPEED_BIN_DDR_1600K)
result = 35000;
else if (index <= SPEED_BIN_DDR_1866M)
result = 34000;
else
result = 33000;
break;
case SPEED_BIN_TRC:
result = speed_bin_table_t_rc[index];
break;
case SPEED_BIN_TRRD1K:
if (index <= SPEED_BIN_DDR_800E)
result = 10000;
else if (index <= SPEED_BIN_DDR_1066G)
result = 7500;
else if (index <= SPEED_BIN_DDR_1600K)
result = 6000;
else
result = 5000;
break;
case SPEED_BIN_TRRD2K:
if (index <= SPEED_BIN_DDR_1066G)
result = 10000;
else if (index <= SPEED_BIN_DDR_1600K)
result = 7500;
else
result = 6000;
break;
case SPEED_BIN_TPD:
if (index < SPEED_BIN_DDR_800E)
result = 7500;
else if (index < SPEED_BIN_DDR_1333J)
result = 5625;
else
result = 5000;
break;
case SPEED_BIN_TFAW1K:
if (index <= SPEED_BIN_DDR_800E)
result = 40000;
else if (index <= SPEED_BIN_DDR_1066G)
result = 37500;
else if (index <= SPEED_BIN_DDR_1600K)
result = 30000;
else if (index <= SPEED_BIN_DDR_1866M)
result = 27000;
else
result = 25000;
break;
case SPEED_BIN_TFAW2K:
if (index <= SPEED_BIN_DDR_1066G)
result = 50000;
else if (index <= SPEED_BIN_DDR_1333J)
result = 45000;
else if (index <= SPEED_BIN_DDR_1600K)
result = 40000;
else
result = 35000;
break;
case SPEED_BIN_TWTR:
result = 7500;
break;
case SPEED_BIN_TRTP:
result = 7500;
break;
case SPEED_BIN_TWR:
result = 15000;
break;
case SPEED_BIN_TMOD:
result = 15000;
break;
case SPEED_BIN_TXPDLL:
result = 24000;
break;
case SPEED_BIN_TXSDLL:
result = 512;
break;
default:
break;
}
return result;
}
static inline u32 pattern_table_get_killer_word(u8 dqs, u8 index)
{
u8 i, byte = 0;
u8 role;
for (i = 0; i < 8; i++) {
role = (i == dqs) ?
(PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_AGGRESSOR) :
(PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM);
byte |= pattern_killer_pattern_table_map[index][role] << i;
}
return byte | (byte << 8) | (byte << 16) | (byte << 24);
}
static inline u32 pattern_table_get_killer_word16(u8 dqs, u8 index)
{
u8 i, byte0 = 0, byte1 = 0;
u8 role;
for (i = 0; i < 8; i++) {
role = (i == dqs) ?
(PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_AGGRESSOR) :
(PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM);
byte0 |= pattern_killer_pattern_table_map[index * 2][role] << i;
byte1 |= pattern_killer_pattern_table_map[index * 2 + 1][role] << i;
}
return byte0 | (byte0 << 8) | (byte1 << 16) | (byte1 << 24);
}
static inline u32 pattern_table_get_sso_word(u8 sso, u8 index)
{
u8 step = sso + 1;
if (0 == ((index / step) & 1))
return 0x0;
else
return 0xffffffff;
}
static inline u32 pattern_table_get_sso_full_xtalk_word(u8 bit, u8 index)
{
u8 byte = (1 << bit);
if ((index & 1) == 1)
byte = ~byte;
return byte | (byte << 8) | (byte << 16) | (byte << 24);
}
static inline u32 pattern_table_get_sso_xtalk_free_word(u8 bit, u8 index)
{
u8 byte = (1 << bit);
if ((index & 1) == 1)
byte = 0;
return byte | (byte << 8) | (byte << 16) | (byte << 24);
}
static inline u32 pattern_table_get_isi_word(u8 index)
{
u8 i0 = index % 32;
u8 i1 = index % 8;
u32 word;
if (i0 > 15)
word = ((i1 == 5) | (i1 == 7)) ? 0xffffffff : 0x0;
else
word = (i1 == 6) ? 0xffffffff : 0x0;
word = ((i0 % 16) > 7) ? ~word : word;
return word;
}
static inline u32 pattern_table_get_sso_full_xtalk_word16(u8 bit, u8 index)
{
u8 byte = (1 << bit);
if ((index & 1) == 1)
byte = ~byte;
return byte | (byte << 8) | ((~byte) << 16) | ((~byte) << 24);
}
static inline u32 pattern_table_get_sso_xtalk_free_word16(u8 bit, u8 index)
{
u8 byte = (1 << bit);
if ((index & 1) == 0)
return (byte << 16) | (byte << 24);
else
return byte | (byte << 8);
}
static inline u32 pattern_table_get_isi_word16(u8 index)
{
u8 i0 = index % 16;
u8 i1 = index % 4;
u32 word;
if (i0 > 7)
word = (i1 > 1) ? 0x0000ffff : 0x0;
else
word = (i1 == 3) ? 0xffff0000 : 0x0;
word = ((i0 % 8) > 3) ? ~word : word;
return word;
}
static inline u32 pattern_table_get_vref_word(u8 index)
{
if (0 == ((pattern_vref_pattern_table_map[index / 8] >>
(index % 8)) & 1))
return 0x0;
else
return 0xffffffff;
}
static inline u32 pattern_table_get_vref_word16(u8 index)
{
if (0 == pattern_killer_pattern_table_map
[PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2] &&
0 == pattern_killer_pattern_table_map
[PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2 + 1])
return 0x00000000;
else if (1 == pattern_killer_pattern_table_map
[PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2] &&
0 == pattern_killer_pattern_table_map
[PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2 + 1])
return 0xffff0000;
else if (0 == pattern_killer_pattern_table_map
[PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2] &&
1 == pattern_killer_pattern_table_map
[PATTERN_KILLER_PATTERN_TABLE_MAP_ROLE_VICTIM][index * 2 + 1])
return 0x0000ffff;
else
return 0xffffffff;
}
static inline u32 pattern_table_get_static_pbs_word(u8 index)
{
u16 temp;
temp = ((0x00ff << (index / 3)) & 0xff00) >> 8;
return temp | (temp << 8) | (temp << 16) | (temp << 24);
}
u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index)
{
u32 pattern = 0;
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) == 0) {
/* 32/64-bit patterns */
switch (type) {
case PATTERN_PBS1:
case PATTERN_PBS2:
if (index == 0 || index == 2 || index == 5 ||
index == 7)
pattern = PATTERN_55;
else
pattern = PATTERN_AA;
break;
case PATTERN_PBS3:
if (0 == (index & 1))
pattern = PATTERN_55;
else
pattern = PATTERN_AA;
break;
case PATTERN_RL:
if (index < 6)
pattern = PATTERN_00;
else
pattern = PATTERN_80;
break;
case PATTERN_STATIC_PBS:
pattern = pattern_table_get_static_pbs_word(index);
break;
case PATTERN_KILLER_DQ0:
case PATTERN_KILLER_DQ1:
case PATTERN_KILLER_DQ2:
case PATTERN_KILLER_DQ3:
case PATTERN_KILLER_DQ4:
case PATTERN_KILLER_DQ5:
case PATTERN_KILLER_DQ6:
case PATTERN_KILLER_DQ7:
pattern = pattern_table_get_killer_word(
(u8)(type - PATTERN_KILLER_DQ0), index);
break;
case PATTERN_RL2:
if (index < 6)
pattern = PATTERN_00;
else
pattern = PATTERN_01;
break;
case PATTERN_TEST:
if (index > 1 && index < 6)
pattern = PATTERN_00;
else
pattern = PATTERN_FF;
break;
case PATTERN_FULL_SSO0:
case PATTERN_FULL_SSO1:
case PATTERN_FULL_SSO2:
case PATTERN_FULL_SSO3:
pattern = pattern_table_get_sso_word(
(u8)(type - PATTERN_FULL_SSO0), index);
break;
case PATTERN_VREF:
pattern = pattern_table_get_vref_word(index);
break;
case PATTERN_SSO_FULL_XTALK_DQ0:
case PATTERN_SSO_FULL_XTALK_DQ1:
case PATTERN_SSO_FULL_XTALK_DQ2:
case PATTERN_SSO_FULL_XTALK_DQ3:
case PATTERN_SSO_FULL_XTALK_DQ4:
case PATTERN_SSO_FULL_XTALK_DQ5:
case PATTERN_SSO_FULL_XTALK_DQ6:
case PATTERN_SSO_FULL_XTALK_DQ7:
pattern = pattern_table_get_sso_full_xtalk_word(
(u8)(type - PATTERN_SSO_FULL_XTALK_DQ0), index);
break;
case PATTERN_SSO_XTALK_FREE_DQ0:
case PATTERN_SSO_XTALK_FREE_DQ1:
case PATTERN_SSO_XTALK_FREE_DQ2:
case PATTERN_SSO_XTALK_FREE_DQ3:
case PATTERN_SSO_XTALK_FREE_DQ4:
case PATTERN_SSO_XTALK_FREE_DQ5:
case PATTERN_SSO_XTALK_FREE_DQ6:
case PATTERN_SSO_XTALK_FREE_DQ7:
pattern = pattern_table_get_sso_xtalk_free_word(
(u8)(type - PATTERN_SSO_XTALK_FREE_DQ0), index);
break;
case PATTERN_ISI_XTALK_FREE:
pattern = pattern_table_get_isi_word(index);
break;
default:
printf("error: %s: unsupported pattern type [%d] found\n",
__func__, (int)type);
pattern = 0;
break;
}
} else {
/* 16bit patterns */
switch (type) {
case PATTERN_PBS1:
case PATTERN_PBS2:
case PATTERN_PBS3:
pattern = PATTERN_55AA;
break;
case PATTERN_RL:
if (index < 3)
pattern = PATTERN_00;
else
pattern = PATTERN_80;
break;
case PATTERN_STATIC_PBS:
pattern = PATTERN_00FF;
break;
case PATTERN_KILLER_DQ0:
case PATTERN_KILLER_DQ1:
case PATTERN_KILLER_DQ2:
case PATTERN_KILLER_DQ3:
case PATTERN_KILLER_DQ4:
case PATTERN_KILLER_DQ5:
case PATTERN_KILLER_DQ6:
case PATTERN_KILLER_DQ7:
pattern = pattern_table_get_killer_word16(
(u8)(type - PATTERN_KILLER_DQ0), index);
break;
case PATTERN_RL2:
if (index < 3)
pattern = PATTERN_00;
else
pattern = PATTERN_01;
break;
case PATTERN_TEST:
if ((index == 0) || (index == 3))
pattern = 0x00000000;
else
pattern = 0xFFFFFFFF;
break;
case PATTERN_FULL_SSO0:
pattern = 0x0000ffff;
break;
case PATTERN_FULL_SSO1:
case PATTERN_FULL_SSO2:
case PATTERN_FULL_SSO3:
pattern = pattern_table_get_sso_word(
(u8)(type - PATTERN_FULL_SSO1), index);
break;
case PATTERN_VREF:
pattern = pattern_table_get_vref_word16(index);
break;
case PATTERN_SSO_FULL_XTALK_DQ0:
case PATTERN_SSO_FULL_XTALK_DQ1:
case PATTERN_SSO_FULL_XTALK_DQ2:
case PATTERN_SSO_FULL_XTALK_DQ3:
case PATTERN_SSO_FULL_XTALK_DQ4:
case PATTERN_SSO_FULL_XTALK_DQ5:
case PATTERN_SSO_FULL_XTALK_DQ6:
case PATTERN_SSO_FULL_XTALK_DQ7:
pattern = pattern_table_get_sso_full_xtalk_word16(
(u8)(type - PATTERN_SSO_FULL_XTALK_DQ0), index);
break;
case PATTERN_SSO_XTALK_FREE_DQ0:
case PATTERN_SSO_XTALK_FREE_DQ1:
case PATTERN_SSO_XTALK_FREE_DQ2:
case PATTERN_SSO_XTALK_FREE_DQ3:
case PATTERN_SSO_XTALK_FREE_DQ4:
case PATTERN_SSO_XTALK_FREE_DQ5:
case PATTERN_SSO_XTALK_FREE_DQ6:
case PATTERN_SSO_XTALK_FREE_DQ7:
pattern = pattern_table_get_sso_xtalk_free_word16(
(u8)(type - PATTERN_SSO_XTALK_FREE_DQ0), index);
break;
case PATTERN_ISI_XTALK_FREE:
pattern = pattern_table_get_isi_word16(index);
break;
default:
printf("error: %s: unsupported pattern type [%d] found\n",
__func__, (int)type);
pattern = 0;
break;
}
}
return pattern;
}
/* Device attribute functions */
void ddr3_tip_dev_attr_init(u32 dev_num)
{
u32 attr_id;
for (attr_id = 0; attr_id < MV_ATTR_LAST; attr_id++)
ddr_dev_attributes[attr_id] = 0xFF;
ddr_dev_attr_init_done = 1;
}
u32 ddr3_tip_dev_attr_get(u32 dev_num, enum mv_ddr_dev_attribute attr_id)
{
if (ddr_dev_attr_init_done == 0)
ddr3_tip_dev_attr_init(dev_num);
return ddr_dev_attributes[attr_id];
}
void ddr3_tip_dev_attr_set(u32 dev_num, enum mv_ddr_dev_attribute attr_id, u32 value)
{
if (ddr_dev_attr_init_done == 0)
ddr3_tip_dev_attr_init(dev_num);
ddr_dev_attributes[attr_id] = value;
}
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
+677
View File
@@ -0,0 +1,677 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#include "ddr3_init.h"
#include "mv_ddr_regs.h"
#define VREF_INITIAL_STEP 3
#define VREF_SECOND_STEP 1
#define VREF_MAX_INDEX 7
#define MAX_VALUE (1024 - 1)
#define MIN_VALUE (-MAX_VALUE)
#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0xf)
u32 ca_delay;
int ddr3_tip_centr_skip_min_win_check = 0;
u8 current_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];
u8 last_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];
u16 current_valid_window[MAX_BUS_NUM][MAX_INTERFACE_NUM];
u16 last_valid_window[MAX_BUS_NUM][MAX_INTERFACE_NUM];
u8 lim_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];
u8 interface_state[MAX_INTERFACE_NUM];
u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
u8 vref_window_size_th = 12;
static u8 pup_st[MAX_BUS_NUM][MAX_INTERFACE_NUM];
static u32 rd_sample_mask[] = {
0,
8,
16,
24
};
#define VREF_STEP_1 0
#define VREF_STEP_2 1
#define VREF_CONVERGE 2
/*
* ODT additional timing
*/
int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id)
{
u32 cs_num = 0, max_read_sample = 0, min_read_sample = 0x1f;
u32 data_read[MAX_INTERFACE_NUM] = { 0 };
u32 read_sample[MAX_CS_NUM];
u32 val;
u32 pup_index;
int max_phase = MIN_VALUE, current_phase;
enum hws_access_type access_type = ACCESS_TYPE_UNICAST;
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
unsigned int max_cs = mv_ddr_cs_num_get();
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
DUNIT_ODT_CTRL_REG,
0 << 8, 0x3 << 8));
CHECK_STATUS(ddr3_tip_if_read(dev_num, access_type, if_id,
RD_DATA_SMPL_DLYS_REG,
data_read, MASK_ALL_BITS));
val = data_read[if_id];
for (cs_num = 0; cs_num < max_cs; cs_num++) {
read_sample[cs_num] = GET_RD_SAMPLE_DELAY(val, cs_num);
/* find maximum of read_samples */
if (read_sample[cs_num] >= max_read_sample) {
if (read_sample[cs_num] == max_read_sample)
max_phase = MIN_VALUE;
else
max_read_sample = read_sample[cs_num];
for (pup_index = 0;
pup_index < octets_per_if_num;
pup_index++) {
CHECK_STATUS(ddr3_tip_bus_read
(dev_num, if_id,
ACCESS_TYPE_UNICAST, pup_index,
DDR_PHY_DATA,
RL_PHY_REG(cs_num),
&val));
current_phase = ((int)val & 0xe0) >> 6;
if (current_phase >= max_phase)
max_phase = current_phase;
}
}
/* find minimum */
if (read_sample[cs_num] < min_read_sample)
min_read_sample = read_sample[cs_num];
}
min_read_sample = min_read_sample - 1;
max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1;
if (min_read_sample >= 0xf)
min_read_sample = 0xf;
if (max_read_sample >= 0x1f)
max_read_sample = 0x1f;
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
DDR_ODT_TIMING_LOW_REG,
((min_read_sample - 1) << 12),
0xf << 12));
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
DDR_ODT_TIMING_LOW_REG,
(max_read_sample << 16),
0x1f << 16));
return MV_OK;
}
int get_valid_win_rx(u32 dev_num, u32 if_id, u8 res[4])
{
u32 reg_pup = RESULT_PHY_REG;
u32 reg_data;
u32 cs_num;
int i;
cs_num = 0;
/* TBD */
reg_pup += cs_num;
for (i = 0; i < 4; i++) {
CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id,
ACCESS_TYPE_UNICAST, i,
DDR_PHY_DATA, reg_pup,
&reg_data));
res[i] = (reg_data >> RESULT_PHY_RX_OFFS) & 0x1f;
}
return 0;
}
/*
* This algorithm deals with the vertical optimum from Voltage point of view
* of the sample signal.
* Voltage sample point can improve the Eye / window size of the bit and the
* pup.
* The problem is that it is tune for all DQ the same so there isn't any
* PBS like code.
* It is more like centralization.
* But because we don't have The training SM support we do it a bit more
* smart search to save time.
*/
int ddr3_tip_vref(u32 dev_num)
{
/*
* The Vref register have non linear order. Need to check what will be
* in future projects.
*/
u32 vref_map[8] = {
1, 2, 3, 4, 5, 6, 7, 0
};
/* State and parameter definitions */
u32 initial_step = VREF_INITIAL_STEP;
/* need to be assign with minus ????? */
u32 second_step = VREF_SECOND_STEP;
u32 algo_run_flag = 0, currrent_vref = 0;
u32 while_count = 0;
u32 pup = 0, if_id = 0, num_pup = 0, rep = 0;
u32 val = 0;
u32 reg_addr = 0xa8;
u32 copy_start_pattern, copy_end_pattern;
enum hws_result *flow_result = ddr3_tip_get_result_ptr(training_stage);
u8 res[4];
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
CHECK_STATUS(ddr3_tip_special_rx(dev_num));
/* save start/end pattern */
copy_start_pattern = start_pattern;
copy_end_pattern = end_pattern;
/* set vref as centralization pattern */
start_pattern = PATTERN_VREF;
end_pattern = PATTERN_VREF;
/* init params */
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (pup = 0;
pup < octets_per_if_num; pup++) {
current_vref[pup][if_id] = 0;
last_vref[pup][if_id] = 0;
lim_vref[pup][if_id] = 0;
current_valid_window[pup][if_id] = 0;
last_valid_window[pup][if_id] = 0;
if (vref_window_size[if_id][pup] >
vref_window_size_th) {
pup_st[pup][if_id] = VREF_CONVERGE;
DEBUG_TRAINING_HW_ALG(
DEBUG_LEVEL_INFO,
("VREF config, IF[ %d ]pup[ %d ] - Vref tune not requered (%d)\n",
if_id, pup, __LINE__));
} else {
pup_st[pup][if_id] = VREF_STEP_1;
CHECK_STATUS(ddr3_tip_bus_read
(dev_num, if_id,
ACCESS_TYPE_UNICAST, pup,
DDR_PHY_DATA, reg_addr, &val));
CHECK_STATUS(ddr3_tip_bus_write
(dev_num, ACCESS_TYPE_UNICAST,
if_id, ACCESS_TYPE_UNICAST,
pup, DDR_PHY_DATA, reg_addr,
(val & (~0xf)) | vref_map[0]));
DEBUG_TRAINING_HW_ALG(
DEBUG_LEVEL_INFO,
("VREF config, IF[ %d ]pup[ %d ] - Vref = %X (%d)\n",
if_id, pup,
(val & (~0xf)) | vref_map[0],
__LINE__));
}
}
interface_state[if_id] = 0;
}
/* TODO: Set number of active interfaces */
num_pup = octets_per_if_num * MAX_INTERFACE_NUM;
while ((algo_run_flag <= num_pup) & (while_count < 10)) {
while_count++;
for (rep = 1; rep < 4; rep++) {
ddr3_tip_centr_skip_min_win_check = 1;
ddr3_tip_centralization_rx(dev_num);
ddr3_tip_centr_skip_min_win_check = 0;
/* Read Valid window results only for non converge pups */
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
if (interface_state[if_id] != 4) {
get_valid_win_rx(dev_num, if_id, res);
for (pup = 0;
pup < octets_per_if_num;
pup++) {
VALIDATE_BUS_ACTIVE
(tm->bus_act_mask, pup);
if (pup_st[pup]
[if_id] ==
VREF_CONVERGE)
continue;
current_valid_window[pup]
[if_id] =
(current_valid_window[pup]
[if_id] * (rep - 1) +
1000 * res[pup]) / rep;
}
}
}
}
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
DEBUG_TRAINING_HW_ALG(
DEBUG_LEVEL_TRACE,
("current_valid_window: IF[ %d ] - ", if_id));
for (pup = 0;
pup < octets_per_if_num; pup++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup);
DEBUG_TRAINING_HW_ALG(DEBUG_LEVEL_TRACE,
("%d ",
current_valid_window
[pup][if_id]));
}
DEBUG_TRAINING_HW_ALG(DEBUG_LEVEL_TRACE, ("\n"));
}
/* Compare results and respond as function of state */
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (pup = 0;
pup < octets_per_if_num; pup++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup);
DEBUG_TRAINING_HW_ALG(DEBUG_LEVEL_TRACE,
("I/F[ %d ], pup[ %d ] STATE #%d (%d)\n",
if_id, pup,
pup_st[pup]
[if_id], __LINE__));
if (pup_st[pup][if_id] == VREF_CONVERGE)
continue;
DEBUG_TRAINING_HW_ALG(DEBUG_LEVEL_TRACE,
("I/F[ %d ], pup[ %d ] CHECK progress - Current %d Last %d, limit VREF %d (%d)\n",
if_id, pup,
current_valid_window[pup]
[if_id],
last_valid_window[pup]
[if_id], lim_vref[pup]
[if_id], __LINE__));
/*
* The -1 is for solution resolution +/- 1 tap
* of ADLL
*/
if (current_valid_window[pup][if_id] + 200 >=
(last_valid_window[pup][if_id])) {
if (pup_st[pup][if_id] == VREF_STEP_1) {
/*
* We stay in the same state and
* step just update the window
* size (take the max) and Vref
*/
if (current_vref[pup]
[if_id] == VREF_MAX_INDEX) {
/*
* If we step to the end
* and didn't converge
* to some particular
* better Vref value
* define the pup as
* converge and step
* back to nominal
* Vref.
*/
pup_st[pup]
[if_id] =
VREF_CONVERGE;
algo_run_flag++;
interface_state
[if_id]++;
DEBUG_TRAINING_HW_ALG
(DEBUG_LEVEL_TRACE,
("I/F[ %d ], pup[ %d ] VREF_CONVERGE - Vref = %X (%d)\n",
if_id, pup,
current_vref[pup]
[if_id],
__LINE__));
} else {
/* continue to update the Vref index */
current_vref[pup]
[if_id] =
((current_vref[pup]
[if_id] +
initial_step) >
VREF_MAX_INDEX) ?
VREF_MAX_INDEX
: (current_vref[pup]
[if_id] +
initial_step);
if (current_vref[pup]
[if_id] ==
VREF_MAX_INDEX) {
pup_st[pup]
[if_id]
=
VREF_STEP_2;
}
lim_vref[pup]
[if_id] =
last_vref[pup]
[if_id] =
current_vref[pup]
[if_id];
}
last_valid_window[pup]
[if_id] =
GET_MAX(current_valid_window
[pup][if_id],
last_valid_window
[pup]
[if_id]);
/* update the Vref for next stage */
currrent_vref =
current_vref[pup]
[if_id];
CHECK_STATUS
(ddr3_tip_bus_read
(dev_num, if_id,
ACCESS_TYPE_UNICAST, pup,
DDR_PHY_DATA, reg_addr,
&val));
CHECK_STATUS
(ddr3_tip_bus_write
(dev_num,
ACCESS_TYPE_UNICAST,
if_id,
ACCESS_TYPE_UNICAST, pup,
DDR_PHY_DATA, reg_addr,
(val & (~0xf)) |
vref_map[currrent_vref]));
DEBUG_TRAINING_HW_ALG
(DEBUG_LEVEL_TRACE,
("VREF config, IF[ %d ]pup[ %d ] - Vref = %X (%d)\n",
if_id, pup,
(val & (~0xf)) |
vref_map[currrent_vref],
__LINE__));
} else if (pup_st[pup][if_id]
== VREF_STEP_2) {
/*
* We keep on search back with
* the same step size.
*/
last_valid_window[pup]
[if_id] =
GET_MAX(current_valid_window
[pup][if_id],
last_valid_window
[pup]
[if_id]);
last_vref[pup][if_id] =
current_vref[pup]
[if_id];
/* we finish all search space */
if ((current_vref[pup]
[if_id] - second_step) == lim_vref[pup][if_id]) {
/*
* If we step to the end
* and didn't converge
* to some particular
* better Vref value
* define the pup as
* converge and step
* back to nominal
* Vref.
*/
pup_st[pup]
[if_id] =
VREF_CONVERGE;
algo_run_flag++;
interface_state
[if_id]++;
current_vref[pup]
[if_id] =
(current_vref[pup]
[if_id] -
second_step);
DEBUG_TRAINING_HW_ALG
(DEBUG_LEVEL_TRACE,
("I/F[ %d ], pup[ %d ] VREF_CONVERGE - Vref = %X (%d)\n",
if_id, pup,
current_vref[pup]
[if_id],
__LINE__));
} else
/* we finish all search space */
if (current_vref[pup]
[if_id] ==
lim_vref[pup]
[if_id]) {
/*
* If we step to the end
* and didn't converge
* to some particular
* better Vref value
* define the pup as
* converge and step
* back to nominal
* Vref.
*/
pup_st[pup]
[if_id] =
VREF_CONVERGE;
algo_run_flag++;
interface_state
[if_id]++;
DEBUG_TRAINING_HW_ALG
(DEBUG_LEVEL_TRACE,
("I/F[ %d ], pup[ %d ] VREF_CONVERGE - Vref = %X (%d)\n",
if_id, pup,
current_vref[pup]
[if_id],
__LINE__));
} else {
current_vref[pup]
[if_id] =
current_vref[pup]
[if_id] -
second_step;
}
/* Update the Vref for next stage */
currrent_vref =
current_vref[pup]
[if_id];
CHECK_STATUS
(ddr3_tip_bus_read
(dev_num, if_id,
ACCESS_TYPE_UNICAST, pup,
DDR_PHY_DATA, reg_addr,
&val));
CHECK_STATUS
(ddr3_tip_bus_write
(dev_num,
ACCESS_TYPE_UNICAST,
if_id,
ACCESS_TYPE_UNICAST, pup,
DDR_PHY_DATA, reg_addr,
(val & (~0xf)) |
vref_map[currrent_vref]));
DEBUG_TRAINING_HW_ALG
(DEBUG_LEVEL_TRACE,
("VREF config, IF[ %d ]pup[ %d ] - Vref = %X (%d)\n",
if_id, pup,
(val & (~0xf)) |
vref_map[currrent_vref],
__LINE__));
}
} else {
/* we change state and change step */
if (pup_st[pup][if_id] == VREF_STEP_1) {
pup_st[pup][if_id] =
VREF_STEP_2;
lim_vref[pup][if_id] =
current_vref[pup]
[if_id] - initial_step;
last_valid_window[pup]
[if_id] =
current_valid_window[pup]
[if_id];
last_vref[pup][if_id] =
current_vref[pup]
[if_id];
current_vref[pup][if_id] =
last_vref[pup][if_id] -
second_step;
/* Update the Vref for next stage */
CHECK_STATUS
(ddr3_tip_bus_read
(dev_num, if_id,
ACCESS_TYPE_UNICAST, pup,
DDR_PHY_DATA, reg_addr,
&val));
CHECK_STATUS
(ddr3_tip_bus_write
(dev_num,
ACCESS_TYPE_UNICAST,
if_id,
ACCESS_TYPE_UNICAST, pup,
DDR_PHY_DATA, reg_addr,
(val & (~0xf)) |
vref_map[current_vref[pup]
[if_id]]));
DEBUG_TRAINING_HW_ALG
(DEBUG_LEVEL_TRACE,
("VREF config, IF[ %d ]pup[ %d ] - Vref = %X (%d)\n",
if_id, pup,
(val & (~0xf)) |
vref_map[current_vref[pup]
[if_id]],
__LINE__));
} else if (pup_st[pup][if_id] == VREF_STEP_2) {
/*
* The last search was the max
* point set value and exit
*/
CHECK_STATUS
(ddr3_tip_bus_read
(dev_num, if_id,
ACCESS_TYPE_UNICAST, pup,
DDR_PHY_DATA, reg_addr,
&val));
CHECK_STATUS
(ddr3_tip_bus_write
(dev_num,
ACCESS_TYPE_UNICAST,
if_id,
ACCESS_TYPE_UNICAST, pup,
DDR_PHY_DATA, reg_addr,
(val & (~0xf)) |
vref_map[last_vref[pup]
[if_id]]));
DEBUG_TRAINING_HW_ALG
(DEBUG_LEVEL_TRACE,
("VREF config, IF[ %d ]pup[ %d ] - Vref = %X (%d)\n",
if_id, pup,
(val & (~0xf)) |
vref_map[last_vref[pup]
[if_id]],
__LINE__));
pup_st[pup][if_id] =
VREF_CONVERGE;
algo_run_flag++;
interface_state[if_id]++;
DEBUG_TRAINING_HW_ALG
(DEBUG_LEVEL_TRACE,
("I/F[ %d ], pup[ %d ] VREF_CONVERGE - Vref = %X (%d)\n",
if_id, pup,
current_vref[pup]
[if_id], __LINE__));
}
}
}
}
}
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
for (pup = 0;
pup < octets_per_if_num; pup++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup);
CHECK_STATUS(ddr3_tip_bus_read
(dev_num, if_id,
ACCESS_TYPE_UNICAST, pup,
DDR_PHY_DATA, reg_addr, &val));
DEBUG_TRAINING_HW_ALG(
DEBUG_LEVEL_INFO,
("FINAL values: I/F[ %d ], pup[ %d ] - Vref = %X (%d)\n",
if_id, pup, val, __LINE__));
}
}
flow_result[if_id] = TEST_SUCCESS;
/* restore start/end pattern */
start_pattern = copy_start_pattern;
end_pattern = copy_end_pattern;
return 0;
}
/*
* CK/CA Delay
*/
int ddr3_tip_cmd_addr_init_delay(u32 dev_num, u32 adll_tap)
{
u32 if_id = 0;
u32 ck_num_adll_tap = 0, ca_num_adll_tap = 0, data = 0;
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
/*
* ck_delay_table is delaying the of the clock signal only.
* (to overcome timing issues between_c_k & command/address signals)
*/
/*
* ca_delay is delaying the of the entire command & Address signals
* (include Clock signal to overcome DGL error on the Clock versus
* the DQS).
*/
/* Calc ADLL Tap */
if (ck_delay == PARAM_UNDEFINED)
DEBUG_TRAINING_HW_ALG(
DEBUG_LEVEL_ERROR,
("ERROR: ck_delay is not initialized!\n"));
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
/* Calc delay ps in ADLL tap */
ck_num_adll_tap = ck_delay / adll_tap;
ca_num_adll_tap = ca_delay / adll_tap;
data = (ck_num_adll_tap & 0x3f) +
((ca_num_adll_tap & 0x3f) << 10);
/*
* Set the ADLL number to the CK ADLL for Interfaces for
* all Pup
*/
DEBUG_TRAINING_HW_ALG(
DEBUG_LEVEL_TRACE,
("ck_num_adll_tap %d ca_num_adll_tap %d adll_tap %d\n",
ck_num_adll_tap, ca_num_adll_tap, adll_tap));
CHECK_STATUS(ddr3_tip_bus_write(dev_num, ACCESS_TYPE_UNICAST,
if_id, ACCESS_TYPE_MULTICAST,
PARAM_NOT_CARE, DDR_PHY_CONTROL,
0x0, data));
}
return MV_OK;
}
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR3_TRAINING_HW_ALGO_H_
#define _DDR3_TRAINING_HW_ALGO_H_
int ddr3_tip_vref(u32 dev_num);
int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id);
int ddr3_tip_cmd_addr_init_delay(u32 dev_num, u32 adll_tap);
#endif /* _DDR3_TRAINING_HW_ALGO_H_ */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training_ip.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR3_TRAINING_IP_H_
#define _DDR3_TRAINING_IP_H_
#include "ddr_topology_def.h"
#define TIP_ENG_LOCK 0x02000000
#define TIP_TX_DLL_RANGE_MAX 64
#define GET_MIN(arg1, arg2) ((arg1) < (arg2)) ? (arg1) : (arg2)
#define GET_MAX(arg1, arg2) ((arg1) < (arg2)) ? (arg2) : (arg1)
#define INIT_CONTROLLER_MASK_BIT 0x00000001
#define STATIC_LEVELING_MASK_BIT 0x00000002
#define SET_LOW_FREQ_MASK_BIT 0x00000004
#define LOAD_PATTERN_MASK_BIT 0x00000008
#define SET_MEDIUM_FREQ_MASK_BIT 0x00000010
#define WRITE_LEVELING_MASK_BIT 0x00000020
#define LOAD_PATTERN_2_MASK_BIT 0x00000040
#define READ_LEVELING_MASK_BIT 0x00000080
#define SW_READ_LEVELING_MASK_BIT 0x00000100
#define WRITE_LEVELING_SUPP_MASK_BIT 0x00000200
#define PBS_RX_MASK_BIT 0x00000400
#define PBS_TX_MASK_BIT 0x00000800
#define SET_TARGET_FREQ_MASK_BIT 0x00001000
#define ADJUST_DQS_MASK_BIT 0x00002000
#define WRITE_LEVELING_TF_MASK_BIT 0x00004000
#define LOAD_PATTERN_HIGH_MASK_BIT 0x00008000
#define READ_LEVELING_TF_MASK_BIT 0x00010000
#define WRITE_LEVELING_SUPP_TF_MASK_BIT 0x00020000
#define DM_PBS_TX_MASK_BIT 0x00040000
#define RL_DQS_BURST_MASK_BIT 0x00080000
#define CENTRALIZATION_RX_MASK_BIT 0x00100000
#define CENTRALIZATION_TX_MASK_BIT 0x00200000
#define TX_EMPHASIS_MASK_BIT 0x00400000
#define PER_BIT_READ_LEVELING_TF_MASK_BIT 0x00800000
#define VREF_CALIBRATION_MASK_BIT 0x01000000
#define WRITE_LEVELING_LF_MASK_BIT 0x02000000
/* DDR4 Specific Training Mask bits */
enum hws_result {
TEST_FAILED = 0,
TEST_SUCCESS = 1,
NO_TEST_DONE = 2
};
enum hws_training_result {
RESULT_PER_BIT,
RESULT_PER_BYTE
};
enum auto_tune_stage {
INIT_CONTROLLER,
STATIC_LEVELING,
SET_LOW_FREQ,
LOAD_PATTERN,
SET_MEDIUM_FREQ,
WRITE_LEVELING,
LOAD_PATTERN_2,
READ_LEVELING,
WRITE_LEVELING_SUPP,
PBS_RX,
PBS_TX,
SET_TARGET_FREQ,
ADJUST_DQS,
WRITE_LEVELING_TF,
READ_LEVELING_TF,
WRITE_LEVELING_SUPP_TF,
DM_PBS_TX,
VREF_CALIBRATION,
CENTRALIZATION_RX,
CENTRALIZATION_TX,
TX_EMPHASIS,
LOAD_PATTERN_HIGH,
PER_BIT_READ_LEVELING_TF,
WRITE_LEVELING_LF,
MAX_STAGE_LIMIT
};
enum hws_access_type {
ACCESS_TYPE_UNICAST = 0,
ACCESS_TYPE_MULTICAST = 1
};
enum hws_algo_type {
ALGO_TYPE_DYNAMIC,
ALGO_TYPE_STATIC
};
struct init_cntr_param {
int is_ctrl64_bit;
int do_mrs_phy;
int init_phy;
int msys_init;
};
struct pattern_info {
u8 num_of_phases_tx;
u8 tx_burst_size;
u8 delay_between_bursts;
u8 num_of_phases_rx;
u32 start_addr;
u8 pattern_len;
};
struct cs_element {
u8 cs_num;
u8 num_of_cs;
};
struct hws_tip_freq_config_info {
u8 is_supported;
u8 bw_per_freq;
u8 rate_per_freq;
};
struct hws_cs_config_info {
u32 cs_reg_value;
u32 cs_cbe_value;
};
struct dfx_access {
u8 pipe;
u8 client;
};
struct hws_xsb_info {
struct dfx_access *dfx_table;
};
int ddr3_tip_register_dq_table(u32 dev_num, u32 *table);
int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable);
int hws_ddr3_tip_init_controller(u32 dev_num,
struct init_cntr_param *init_cntr_prm);
int hws_ddr3_tip_load_topology_map(u32 dev_num,
struct mv_ddr_topology_map *topology);
int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode);
u8 ddr3_tip_get_buf_min(u8 *buf_ptr);
u8 ddr3_tip_get_buf_max(u8 *buf_ptr);
#endif /* _DDR3_TRAINING_IP_H_ */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training_ip_bist.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR3_TRAINING_IP_BIST_H_
#define _DDR3_TRAINING_IP_BIST_H_
#include "ddr3_training_ip.h"
enum hws_bist_operation {
BIST_STOP = 0,
BIST_START = 1
};
enum hws_stress_jump {
STRESS_NONE = 0,
STRESS_ENABLE = 1
};
enum hws_pattern_duration {
DURATION_SINGLE = 0,
DURATION_STOP_AT_FAIL = 1,
DURATION_ADDRESS = 2,
DURATION_CONT = 4
};
struct bist_result {
u32 bist_error_cnt;
u32 bist_fail_low;
u32 bist_fail_high;
u32 bist_last_fail_addr;
};
int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id,
struct bist_result *pst_bist_result);
int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern,
enum hws_access_type access_type,
u32 if_num, enum hws_dir direction,
enum hws_stress_jump addr_stress_jump,
enum hws_pattern_duration duration,
enum hws_bist_operation oper_type,
u32 offset, u32 cs_num, u32 pattern_addr_length);
int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result,
u32 cs_num);
int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction,
u32 mode);
int ddr3_tip_run_leveling_sweep_test(int dev_num, u32 repeat_num,
u32 direction, u32 mode);
int ddr3_tip_print_regs(u32 dev_num);
int ddr3_tip_reg_dump(u32 dev_num);
int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type,
u32 burst_length);
int mv_ddr_dm_to_dq_diff_get(u8 adll_byte_high, u8 adll_byte_low, u8 *vw_vector,
int *delta_h_adll, int *delta_l_adll);
int mv_ddr_dm_vw_get(enum hws_pattern pattern, u32 cs, u8 *vw_vector);
#endif /* _DDR3_TRAINING_IP_BIST_H_ */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training_ip_centralization.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR3_TRAINING_IP_CENTRALIZATION_H
#define _DDR3_TRAINING_IP_CENTRALIZATION_H
int ddr3_tip_centralization_tx(u32 dev_num);
int ddr3_tip_centralization_rx(u32 dev_num);
int ddr3_tip_print_centralization_result(u32 dev_num);
int ddr3_tip_special_rx(u32 dev_num);
#endif /* _DDR3_TRAINING_IP_CENTRALIZATION_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training_ip_db.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR3_TRAINING_IP_DB_H_
#define _DDR3_TRAINING_IP_DB_H_
enum hws_pattern {
PATTERN_PBS1,
PATTERN_PBS2,
PATTERN_PBS3,
PATTERN_TEST,
PATTERN_RL,
PATTERN_RL2,
PATTERN_STATIC_PBS,
PATTERN_KILLER_DQ0,
PATTERN_KILLER_DQ1,
PATTERN_KILLER_DQ2,
PATTERN_KILLER_DQ3,
PATTERN_KILLER_DQ4,
PATTERN_KILLER_DQ5,
PATTERN_KILLER_DQ6,
PATTERN_KILLER_DQ7,
PATTERN_VREF,
PATTERN_FULL_SSO0,
PATTERN_FULL_SSO1,
PATTERN_FULL_SSO2,
PATTERN_FULL_SSO3,
PATTERN_LAST,
PATTERN_SSO_FULL_XTALK_DQ0,
PATTERN_SSO_FULL_XTALK_DQ1,
PATTERN_SSO_FULL_XTALK_DQ2,
PATTERN_SSO_FULL_XTALK_DQ3,
PATTERN_SSO_FULL_XTALK_DQ4,
PATTERN_SSO_FULL_XTALK_DQ5,
PATTERN_SSO_FULL_XTALK_DQ6,
PATTERN_SSO_FULL_XTALK_DQ7,
PATTERN_SSO_XTALK_FREE_DQ0,
PATTERN_SSO_XTALK_FREE_DQ1,
PATTERN_SSO_XTALK_FREE_DQ2,
PATTERN_SSO_XTALK_FREE_DQ3,
PATTERN_SSO_XTALK_FREE_DQ4,
PATTERN_SSO_XTALK_FREE_DQ5,
PATTERN_SSO_XTALK_FREE_DQ6,
PATTERN_SSO_XTALK_FREE_DQ7,
PATTERN_ISI_XTALK_FREE
};
enum mv_wl_supp_mode {
WRITE_LEVELING_SUPP_REG_MODE,
WRITE_LEVELING_SUPP_ECC_MODE_DATA_PUPS,
WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP4,
WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP3,
WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP8
};
enum mv_ddr_dev_attribute {
MV_ATTR_TIP_REV,
MV_ATTR_PHY_EDGE,
MV_ATTR_OCTET_PER_INTERFACE,
MV_ATTR_PLL_BEFORE_INIT,
MV_ATTR_TUNE_MASK,
MV_ATTR_INIT_FREQ,
MV_ATTR_MID_FREQ,
MV_ATTR_DFS_LOW_FREQ,
MV_ATTR_DFS_LOW_PHY,
MV_ATTR_DELAY_ENABLE,
MV_ATTR_CK_DELAY,
MV_ATTR_CA_DELAY,
MV_ATTR_INTERLEAVE_WA,
MV_ATTR_LAST
};
enum mv_ddr_tip_revison {
MV_TIP_REV_NA,
MV_TIP_REV_1, /* NP5 */
MV_TIP_REV_2, /* BC2 */
MV_TIP_REV_3, /* AC3 */
MV_TIP_REV_4, /* A-380/A-390 */
MV_TIP_REV_LAST
};
enum mv_ddr_phy_edge {
MV_DDR_PHY_EDGE_POSITIVE,
MV_DDR_PHY_EDGE_NEGATIVE
};
/* Device attribute functions */
void ddr3_tip_dev_attr_init(u32 dev_num);
u32 ddr3_tip_dev_attr_get(u32 dev_num, enum mv_ddr_dev_attribute attr_id);
void ddr3_tip_dev_attr_set(u32 dev_num, enum mv_ddr_dev_attribute attr_id, u32 value);
#endif /* _DDR3_TRAINING_IP_DB_H_ */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR3_TRAINING_IP_DEF_H
#define _DDR3_TRAINING_IP_DEF_H
#define PATTERN_55 0x55555555
#define PATTERN_AA 0xaaaaaaaa
#define PATTERN_80 0x80808080
#define PATTERN_20 0x20202020
#define PATTERN_01 0x01010101
#define PATTERN_FF 0xffffffff
#define PATTERN_00 0x00000000
/* 16bit bus width patterns */
#define PATTERN_55AA 0x5555aaaa
#define PATTERN_00FF 0x0000ffff
#define PATTERN_0080 0x00008080
#define INVALID_VALUE 0xffffffff
#define MAX_NUM_OF_DUNITS 32
/*
* length *2 = length in words of pattern, first low address,
* second high address
*/
#define TEST_PATTERN_LENGTH 4
#define KILLER_PATTERN_DQ_NUMBER 8
#define SSO_DQ_NUMBER 4
#define PATTERN_MAXIMUM_LENGTH 64
#define ADLL_TX_LENGTH 64
#define ADLL_RX_LENGTH 32
#define PARAM_NOT_CARE 0
#define PARAM_UNDEFINED 0xffffffff
#define READ_LEVELING_PHY_OFFSET 2
#define WRITE_LEVELING_PHY_OFFSET 0
#define MASK_ALL_BITS 0xffffffff
#define CS_BIT_MASK 0xf
/* DFX access */
#define BROADCAST_ID 28
#define MULTICAST_ID 29
#define XSB_BASE_ADDR 0x00004000
#define XSB_CTRL_0_REG 0x00000000
#define XSB_CTRL_1_REG 0x00000004
#define XSB_CMD_REG 0x00000008
#define XSB_ADDRESS_REG 0x0000000c
#define XSB_DATA_REG 0x00000010
#define PIPE_ENABLE_ADDR 0x000f8000
#define ENABLE_DDR_TUNING_ADDR 0x000f829c
#define CLIENT_BASE_ADDR 0x00002000
#define CLIENT_CTRL_REG 0x00000000
#define TARGET_INT 0x1801
#define TARGET_EXT 0x180e
#define BYTE_EN 0
#define CMD_READ 0
#define CMD_WRITE 1
#define INTERNAL_ACCESS_PORT 1
#define EXECUTING 1
#define ACCESS_EXT 1
#define CS2_EXIST_BIT 2
#define TRAINING_ID 0xf
#define EXT_TRAINING_ID 1
#define EXT_MODE 0x4
#define GET_RESULT_STATE(res) (res)
#define SET_RESULT_STATE(res, state) (res = state)
#define ADDR_SIZE_512MB 0x04000000
#define ADDR_SIZE_1GB 0x08000000
#define ADDR_SIZE_2GB 0x10000000
#define ADDR_SIZE_4GB 0x20000000
#define ADDR_SIZE_8GB 0x40000000
enum hws_edge_compare {
EDGE_PF,
EDGE_FP,
EDGE_FPF,
EDGE_PFP
};
enum hws_control_element {
HWS_CONTROL_ELEMENT_ADLL, /* per bit 1 edge */
HWS_CONTROL_ELEMENT_DQ_SKEW,
HWS_CONTROL_ELEMENT_DQS_SKEW
};
enum hws_search_dir {
HWS_LOW2HIGH,
HWS_HIGH2LOW,
HWS_SEARCH_DIR_LIMIT
};
enum hws_operation {
OPERATION_READ = 0,
OPERATION_WRITE = 1
};
enum hws_training_ip_stat {
HWS_TRAINING_IP_STATUS_FAIL,
HWS_TRAINING_IP_STATUS_SUCCESS,
HWS_TRAINING_IP_STATUS_TIMEOUT
};
enum hws_ddr_cs {
CS_SINGLE,
CS_NON_SINGLE
};
enum hws_ddr_phy {
DDR_PHY_DATA = 0,
DDR_PHY_CONTROL = 1
};
enum hws_dir {
OPER_WRITE,
OPER_READ,
OPER_WRITE_AND_READ
};
enum hws_wl_supp {
PHASE_SHIFT,
CLOCK_SHIFT,
ALIGN_SHIFT
};
enum mv_ddr_tip_bit_state {
BIT_LOW_UI,
BIT_HIGH_UI,
BIT_SPLIT_IN,
BIT_SPLIT_OUT,
BIT_STATE_LAST
};
enum mv_ddr_tip_byte_state{
BYTE_NOT_DEFINED,
BYTE_HOMOGENEOUS_LOW = 0x1,
BYTE_HOMOGENEOUS_HIGH = 0x2,
BYTE_HOMOGENEOUS_SPLIT_IN = 0x4,
BYTE_HOMOGENEOUS_SPLIT_OUT = 0x8,
BYTE_SPLIT_OUT_MIX = 0x10,
BYTE_STATE_LAST
};
struct reg_data {
unsigned int reg_addr;
unsigned int reg_data;
unsigned int reg_mask;
};
enum dm_direction {
DM_DIR_INVERSE,
DM_DIR_DIRECT
};
#endif /* _DDR3_TRAINING_IP_DEF_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
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source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR3_TRAINING_IP_ENGINE_H_
#define _DDR3_TRAINING_IP_ENGINE_H_
#include "ddr3_training_ip_def.h"
#include "ddr3_training_ip_flow.h"
#include "ddr3_training_ip_pbs.h"
#define EDGE_1 0
#define EDGE_2 1
#define ALL_PUP_TRAINING 0xe
#define PUP_RESULT_EDGE_1_MASK 0xff
#define PUP_RESULT_EDGE_2_MASK (0xff << 8)
#define PUP_LOCK_RESULT_BIT 25
#define GET_TAP_RESULT(reg, edge) \
(((edge) == EDGE_1) ? ((reg) & PUP_RESULT_EDGE_1_MASK) : \
(((reg) & PUP_RESULT_EDGE_2_MASK) >> 8));
#define GET_LOCK_RESULT(reg) \
(((reg) & (1<<PUP_LOCK_RESULT_BIT)) >> PUP_LOCK_RESULT_BIT)
#define EDGE_FAILURE 128
#define ALL_BITS_PER_PUP 128
#define MIN_WINDOW_SIZE 6
#define MAX_WINDOW_SIZE_RX 32
#define MAX_WINDOW_SIZE_TX 64
int ddr3_tip_training_ip_test(u32 dev_num, enum hws_training_result result_type,
enum hws_search_dir search_dir,
enum hws_dir direction,
enum hws_edge_compare edge,
u32 init_val1, u32 init_val2,
u32 num_of_iterations, u32 start_pattern,
u32 end_pattern);
int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern pattern);
int ddr3_tip_load_all_pattern_to_mem(u32 dev_num);
int ddr3_tip_read_training_result(u32 dev_num, u32 if_id,
enum hws_access_type pup_access_type,
u32 pup_num, u32 bit_num,
enum hws_search_dir search,
enum hws_dir direction,
enum hws_training_result result_type,
enum hws_training_load_op operation,
u32 cs_num_type, u32 **load_res,
int is_read_from_db, u8 cons_tap,
int is_check_result_validity);
int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type,
u32 interface_num,
enum hws_access_type pup_access_type,
u32 pup_num, enum hws_training_result result_type,
enum hws_control_element control_element,
enum hws_search_dir search_dir, enum hws_dir direction,
u32 interface_mask, u32 init_value, u32 num_iter,
enum hws_pattern pattern,
enum hws_edge_compare edge_comp,
enum hws_ddr_cs cs_type, u32 cs_num,
enum hws_training_ip_stat *train_status);
int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type,
u32 if_id,
enum hws_access_type pup_access_type,
u32 pup_num,
enum hws_training_result result_type,
enum hws_control_element control_element,
enum hws_search_dir search_dir,
enum hws_dir direction,
u32 interface_mask, u32 init_value1,
u32 init_value2, u32 num_iter,
enum hws_pattern pattern,
enum hws_edge_compare edge_comp,
enum hws_ddr_cs train_cs_type, u32 cs_num,
enum hws_training_ip_stat *train_status);
u8 mv_ddr_tip_sub_phy_byte_status_get(u32 if_id, u32 subphy_id);
void mv_ddr_tip_sub_phy_byte_status_set(u32 if_id, u32 subphy_id, u8 byte_status_data);
void ddr3_tip_print_bist_res(void);
struct pattern_info *ddr3_tip_get_pattern_table(void);
u16 *ddr3_tip_get_mask_results_dq_reg(void);
u16 *ddr3_tip_get_mask_results_pup_reg_map(void);
int mv_ddr_load_dm_pattern_to_odpg(enum hws_access_type access_type, enum hws_pattern pattern,
enum dm_direction dm_dir);
int mv_ddr_pattern_start_addr_set(struct pattern_info *pattern_tbl, enum hws_pattern pattern, u32 addr);
#endif /* _DDR3_TRAINING_IP_ENGINE_H_ */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR3_TRAINING_IP_FLOW_H_
#define _DDR3_TRAINING_IP_FLOW_H_
#include "ddr3_training_ip.h"
#include "ddr3_training_ip_db.h"
#define KILLER_PATTERN_LENGTH 32
#define EXT_ACCESS_BURST_LENGTH 8
#define ECC_READ_BUS_0 0
#define ECC_PHY_ACCESS_3 3
#define ECC_PHY_ACCESS_4 4
#define ECC_PHY_ACCESS_8 8
#define BUS_WIDTH_IN_BITS 8
#define MAX_POLLING_ITERATIONS 1000000
#define ADLL_LENGTH 32
#define GP_RSVD0_REG 0x182e0
/*
* DFX address Space
* Table 2: DFX address space
* Address Bits Value Description
* [31 : 20] 0x? DFX base address bases PCIe mapping
* [19 : 15] 0...Number_of_client-1 Client Index inside pipe.
* See also Table 1 Multi_cast = 29 Broadcast = 28
* [14 : 13] 2'b01 Access to Client Internal Register
* [12 : 0] Client Internal Register offset See related Client Registers
* [14 : 13] 2'b00 Access to Ram Wrappers Internal Register
* [12 : 6] 0 Number_of_rams-1 Ram Index inside Client
* [5 : 0] Ram Wrapper Internal Register offset See related Ram Wrappers
* Registers
*/
/* nsec */
#define AUTO_ZQC_TIMING 15384
enum mr_number {
MR_CMD0,
MR_CMD1,
MR_CMD2,
MR_CMD3,
MR_LAST
};
struct mv_ddr_mr_data {
u32 cmd;
u32 reg_addr;
};
struct write_supp_result {
enum hws_wl_supp stage;
int is_pup_fail;
};
int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id,
enum mv_ddr_freq frequency,
u32 *round_trip_delay_arr);
int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id,
enum mv_ddr_freq frequency,
u32 *total_round_trip_delay_arr);
int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access,
u32 if_id, u32 reg_addr, u32 data_value, u32 mask);
int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type,
u32 if_id, u32 exp_value, u32 mask, u32 offset,
u32 poll_tries);
int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access,
u32 if_id, u32 reg_addr, u32 *data, u32 mask);
int ddr3_tip_bus_read_modify_write(u32 dev_num,
enum hws_access_type access_type,
u32 if_id, u32 phy_id,
enum hws_ddr_phy phy_type,
u32 reg_addr, u32 data_value, u32 reg_mask);
int ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access,
u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
u32 *data);
int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type e_interface_access,
u32 if_id, enum hws_access_type e_phy_access, u32 phy_id,
enum hws_ddr_phy e_phy_type, u32 reg_addr,
u32 data_value);
int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type e_access, u32 if_id,
enum mv_ddr_freq memory_freq);
int ddr3_tip_adjust_dqs(u32 dev_num);
int ddr3_tip_init_controller(u32 dev_num);
int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr,
u32 num_of_bursts, u32 *addr);
int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr,
u32 num_of_bursts, u32 *addr);
int ddr3_tip_dynamic_read_leveling(u32 dev_num, u32 ui_freq);
int mv_ddr_rl_dqs_burst(u32 dev_num, u32 if_id, u32 freq);
int ddr3_tip_legacy_dynamic_read_leveling(u32 dev_num);
int ddr3_tip_dynamic_per_bit_read_leveling(u32 dev_num, u32 ui_freq);
int ddr3_tip_legacy_dynamic_write_leveling(u32 dev_num);
int ddr3_tip_dynamic_write_leveling(u32 dev_num, int phase_remove);
int ddr3_tip_dynamic_write_leveling_supp(u32 dev_num);
int ddr3_tip_static_init_controller(u32 dev_num);
int ddr3_tip_configure_phy(u32 dev_num);
int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type,
u32 if_id, enum hws_pattern pattern,
u32 load_addr);
int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern e_pattern);
int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type,
u32 if_id, enum hws_dir direction, u32 tx_phases,
u32 tx_burst_size, u32 rx_phases,
u32 delay_between_burst, u32 rd_mode, u32 cs_num,
u32 addr_stress_jump, u32 single_pattern);
int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask);
int ddr3_tip_write_cs_result(u32 dev_num, u32 offset);
int ddr3_tip_reset_fifo_ptr(u32 dev_num);
int ddr3_tip_read_pup_value(u32 dev_num, u32 pup_values[], int reg_addr, u32 mask);
int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[], u32 reg_addr, u32 mask);
int ddr3_tip_write_adll_value(u32 dev_num, u32 pup_values[], u32 reg_addr);
int ddr3_tip_tune_training_params(u32 dev_num, struct tune_train_params *params);
#endif /* _DDR3_TRAINING_IP_FLOW_H_ */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training_ip_pbs.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR3_TRAINING_IP_PBS_H_
#define _DDR3_TRAINING_IP_PBS_H_
enum {
EBA_CONFIG,
EEBA_CONFIG,
SBA_CONFIG
};
enum hws_training_load_op {
TRAINING_LOAD_OPERATION_UNLOAD,
TRAINING_LOAD_OPERATION_LOAD
};
enum hws_edge {
TRAINING_EDGE_1,
TRAINING_EDGE_2
};
enum hws_edge_search {
TRAINING_EDGE_MAX,
TRAINING_EDGE_MIN
};
enum pbs_dir {
PBS_TX_MODE = 0,
PBS_RX_MODE,
NUM_OF_PBS_MODES
};
int ddr3_tip_pbs_rx(u32 dev_num);
int ddr3_tip_print_all_pbs_result(u32 dev_num);
int ddr3_tip_pbs_tx(u32 dev_num);
#endif /* _DDR3_TRAINING_IP_PBS_H_ */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR3_TRAINING_IP_PRV_IF_H
#define _DDR3_TRAINING_IP_PRV_IF_H
#include "ddr3_training_ip.h"
#include "ddr3_training_ip_flow.h"
#include "ddr3_training_ip_bist.h"
enum hws_static_config_type {
WRITE_LEVELING_STATIC,
READ_LEVELING_STATIC
};
struct ddr3_device_info {
u32 device_id;
u32 ck_delay;
};
typedef int (*HWS_TIP_DUNIT_MUX_SELECT_FUNC_PTR)(u8 dev_num, int enable);
typedef int (*HWS_TIP_DUNIT_REG_READ_FUNC_PTR)(
u8 dev_num, enum hws_access_type interface_access, u32 if_id,
u32 offset, u32 *data, u32 mask);
typedef int (*HWS_TIP_DUNIT_REG_WRITE_FUNC_PTR)(
u8 dev_num, enum hws_access_type interface_access, u32 if_id,
u32 offset, u32 data, u32 mask);
typedef int (*HWS_TIP_GET_FREQ_CONFIG_INFO)(
u8 dev_num, enum mv_ddr_freq freq,
struct hws_tip_freq_config_info *freq_config_info);
typedef int (*HWS_TIP_GET_DEVICE_INFO)(
u8 dev_num, struct ddr3_device_info *info_ptr);
typedef int (*HWS_GET_CS_CONFIG_FUNC_PTR)(
u8 dev_num, u32 cs_mask, struct hws_cs_config_info *cs_info);
typedef int (*HWS_SET_FREQ_DIVIDER_FUNC_PTR)(
u8 dev_num, u32 if_id, enum mv_ddr_freq freq);
typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum mv_ddr_freq *freq);
typedef int (*HWS_TRAINING_IP_IF_WRITE_FUNC_PTR)(
u32 dev_num, enum hws_access_type access_type, u32 dunit_id,
u32 reg_addr, u32 data, u32 mask);
typedef int (*HWS_TRAINING_IP_IF_READ_FUNC_PTR)(
u32 dev_num, enum hws_access_type access_type, u32 dunit_id,
u32 reg_addr, u32 *data, u32 mask);
typedef int (*HWS_TRAINING_IP_BUS_WRITE_FUNC_PTR)(
u32 dev_num, enum hws_access_type dunit_access_type, u32 if_id,
enum hws_access_type phy_access_type, u32 phy_id,
enum hws_ddr_phy phy_type, u32 reg_addr, u32 data);
typedef int (*HWS_TRAINING_IP_BUS_READ_FUNC_PTR)(
u32 dev_num, u32 if_id, enum hws_access_type phy_access_type,
u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr, u32 *data);
typedef int (*HWS_TRAINING_IP_ALGO_RUN_FUNC_PTR)(
u32 dev_num, enum hws_algo_type algo_type);
typedef int (*HWS_TRAINING_IP_SET_FREQ_FUNC_PTR)(
u32 dev_num, enum hws_access_type access_type, u32 if_id,
enum mv_ddr_freq frequency);
typedef int (*HWS_TRAINING_IP_INIT_CONTROLLER_FUNC_PTR)(
u32 dev_num, struct init_cntr_param *init_cntr_prm);
typedef int (*HWS_TRAINING_IP_PBS_RX_FUNC_PTR)(u32 dev_num);
typedef int (*HWS_TRAINING_IP_PBS_TX_FUNC_PTR)(u32 dev_num);
typedef int (*HWS_TRAINING_IP_SELECT_CONTROLLER_FUNC_PTR)(
u32 dev_num, int enable);
typedef int (*HWS_TRAINING_IP_TOPOLOGY_MAP_LOAD_FUNC_PTR)(
u32 dev_num, struct mv_ddr_topology_map *tm);
typedef int (*HWS_TRAINING_IP_STATIC_CONFIG_FUNC_PTR)(
u32 dev_num, enum mv_ddr_freq frequency,
enum hws_static_config_type static_config_type, u32 if_id);
typedef int (*HWS_TRAINING_IP_EXTERNAL_READ_PTR)(
u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data);
typedef int (*HWS_TRAINING_IP_EXTERNAL_WRITE_PTR)(
u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data);
typedef int (*HWS_TRAINING_IP_BIST_ACTIVATE)(
u32 dev_num, enum hws_pattern pattern, enum hws_access_type access_type,
u32 if_num, enum hws_dir direction,
enum hws_stress_jump addr_stress_jump,
enum hws_pattern_duration duration,
enum hws_bist_operation oper_type, u32 offset, u32 cs_num,
u32 pattern_addr_length);
typedef int (*HWS_TRAINING_IP_BIST_READ_RESULT)(
u32 dev_num, u32 if_id, struct bist_result *pst_bist_result);
typedef int (*HWS_TRAINING_IP_LOAD_TOPOLOGY)(u32 dev_num, u32 config_num);
typedef int (*HWS_TRAINING_IP_READ_LEVELING)(u32 dev_num, u32 config_num);
typedef int (*HWS_TRAINING_IP_WRITE_LEVELING)(u32 dev_num, u32 config_num);
typedef u32 (*HWS_TRAINING_IP_GET_TEMP)(u8 dev_num);
typedef u8 (*HWS_TRAINING_IP_GET_RATIO)(u32 freq);
struct hws_tip_config_func_db {
HWS_TIP_DUNIT_MUX_SELECT_FUNC_PTR tip_dunit_mux_select_func;
void (*mv_ddr_dunit_read)(u32 addr, u32 mask, u32 *data);
void (*mv_ddr_dunit_write)(u32 addr, u32 mask, u32 data);
HWS_TIP_GET_FREQ_CONFIG_INFO tip_get_freq_config_info_func;
HWS_TIP_GET_DEVICE_INFO tip_get_device_info_func;
HWS_SET_FREQ_DIVIDER_FUNC_PTR tip_set_freq_divider_func;
HWS_GET_CS_CONFIG_FUNC_PTR tip_get_cs_config_info;
HWS_TRAINING_IP_GET_TEMP tip_get_temperature;
HWS_TRAINING_IP_GET_RATIO tip_get_clock_ratio;
HWS_TRAINING_IP_EXTERNAL_READ_PTR tip_external_read;
HWS_TRAINING_IP_EXTERNAL_WRITE_PTR tip_external_write;
int (*mv_ddr_phy_read)(enum hws_access_type phy_access,
u32 phy, enum hws_ddr_phy phy_type,
u32 reg_addr, u32 *data);
int (*mv_ddr_phy_write)(enum hws_access_type phy_access,
u32 phy, enum hws_ddr_phy phy_type,
u32 reg_addr, u32 data,
enum hws_operation op_type);
};
int ddr3_tip_init_config_func(u32 dev_num,
struct hws_tip_config_func_db *config_func);
int ddr3_tip_register_xsb_info(u32 dev_num,
struct hws_xsb_info *xsb_info_table);
enum hws_result *ddr3_tip_get_result_ptr(u32 stage);
int ddr3_set_freq_config_info(struct hws_tip_freq_config_info *table);
int print_device_info(u8 dev_num);
#endif /* _DDR3_TRAINING_IP_PRV_IF_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training_leveling.c
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source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training_leveling.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR3_TRAINING_LEVELING_H_
#define _DDR3_TRAINING_LEVELING_H_
#define MAX_DQ_READ_LEVELING_DELAY 15
int ddr3_tip_print_wl_supp_result(u32 dev_num);
int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
u32 *cs_mask);
#endif /* _DDR3_TRAINING_LEVELING_H_ */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr3_training_pbs.c
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source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR_ML_WRAPPER_H
#define _DDR_ML_WRAPPER_H
#include <common.h>
#include <i2c.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
#define INTER_REGS_BASE SOC_REGS_PHY_BASE
#endif
/*
* MV_DEBUG_INIT need to be defines, otherwise the output of the
* DDR2 training code is not complete and misleading
*/
#define MV_DEBUG_INIT
#ifdef MV_DEBUG_INIT
#define DEBUG_INIT_S(s) puts(s)
#define DEBUG_INIT_D(d, l) printf("%x", d)
#define DEBUG_INIT_D_10(d, l) printf("%d", d)
#else
#define DEBUG_INIT_S(s)
#define DEBUG_INIT_D(d, l)
#define DEBUG_INIT_D_10(d, l)
#endif
#ifdef MV_DEBUG_INIT_FULL
#define DEBUG_INIT_FULL_S(s) puts(s)
#define DEBUG_INIT_FULL_D(d, l) printf("%x", d)
#define DEBUG_INIT_FULL_D_10(d, l) printf("%d", d)
#define DEBUG_WR_REG(reg, val) \
{ DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
#define DEBUG_RD_REG(reg, val) \
{ DEBUG_INIT_S("Read Reg: 0x"); DEBUG_INIT_D((reg), 8); \
DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
#else
#define DEBUG_INIT_FULL_S(s)
#define DEBUG_INIT_FULL_D(d, l)
#define DEBUG_INIT_FULL_D_10(d, l)
#define DEBUG_WR_REG(reg, val)
#define DEBUG_RD_REG(reg, val)
#endif
#define DEBUG_INIT_FULL_C(s, d, l) \
{ DEBUG_INIT_FULL_S(s); \
DEBUG_INIT_FULL_D(d, l); \
DEBUG_INIT_FULL_S("\n"); }
#define DEBUG_INIT_C(s, d, l) \
{ DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
/*
* Debug (Enable/Disable modules) and Error report
*/
#ifdef BASIC_DEBUG
#define MV_DEBUG_WL
#define MV_DEBUG_RL
#define MV_DEBUG_DQS_RESULTS
#endif
#ifdef FULL_DEBUG
#define MV_DEBUG_WL
#define MV_DEBUG_RL
#define MV_DEBUG_DQS
#define MV_DEBUG_PBS
#define MV_DEBUG_DFS
#define MV_DEBUG_MAIN_FULL
#define MV_DEBUG_DFS_FULL
#define MV_DEBUG_DQS_FULL
#define MV_DEBUG_RL_FULL
#define MV_DEBUG_WL_FULL
#endif
/* The following is a list of Marvell status */
#define MV_ERROR (-1)
#define MV_OK (0x00) /* Operation succeeded */
#define MV_FAIL (0x01) /* Operation failed */
#define MV_BAD_VALUE (0x02) /* Illegal value (general) */
#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */
#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */
#define MV_BAD_PTR (0x05) /* Illegal pointer value */
#define MV_BAD_SIZE (0x06) /* Illegal size */
#define MV_BAD_STATE (0x07) /* Illegal state of state machine */
#define MV_SET_ERROR (0x08) /* Set operation failed */
#define MV_GET_ERROR (0x09) /* Get operation failed */
#define MV_CREATE_ERROR (0x0a) /* Fail while creating an item */
#define MV_NOT_FOUND (0x0b) /* Item not found */
#define MV_NO_MORE (0x0c) /* No more items found */
#define MV_NO_SUCH (0x0d) /* No such item */
#define MV_TIMEOUT (0x0e) /* Time Out */
#define MV_NO_CHANGE (0x0f) /* Parameter(s) is already in this value */
#define MV_NOT_SUPPORTED (0x10) /* This request is not support */
#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/
#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */
#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */
#define MV_HW_ERROR (0x17) /* Hardware error */
#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
#define MV_NOT_READY (0x1a) /* The other side is not ready yet */
#define MV_ALREADY_EXIST (0x1b) /* Tried to create existing item */
#define MV_OUT_OF_CPU_MEM (0x1c) /* Cpu memory allocation failed. */
#define MV_NOT_STARTED (0x1d) /* Not started yet */
#define MV_BUSY (0x1e) /* Item is busy. */
#define MV_TERMINATE (0x1f) /* Item terminates it's work. */
#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */
#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */
#define MV_WRITE_PROTECT (0x22) /* Write protected */
#define MV_INVALID (int)(-1)
/*
* Accessor functions for the registers
*/
static inline void reg_write(u32 addr, u32 val)
{
writel(val, INTER_REGS_BASE + addr);
}
static inline u32 reg_read(u32 addr)
{
return readl(INTER_REGS_BASE + addr);
}
static inline void reg_bit_set(u32 addr, u32 mask)
{
setbits_le32(INTER_REGS_BASE + addr, mask);
}
static inline void reg_bit_clr(u32 addr, u32 mask)
{
clrbits_le32(INTER_REGS_BASE + addr, mask);
}
#endif /* _DDR_ML_WRAPPER_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr_topology_def.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR_TOPOLOGY_DEF_H
#define _DDR_TOPOLOGY_DEF_H
#include "ddr3_training_ip_def.h"
#include "mv_ddr_topology.h"
#include "mv_ddr_spd.h"
#include "ddr3_logging_def.h"
#define MV_DDR_MAX_BUS_NUM 9
#define MV_DDR_MAX_IFACE_NUM 1
struct bus_params {
/* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
u8 cs_bitmask;
/*
* mirror enable/disable
* (bits 0-CS0 mirroring, bit 1- CS1 mirroring ...)
*/
int mirror_enable_bitmask;
/* DQS Swap (polarity) - true if enable */
int is_dqs_swap;
/* CK swap (polarity) - true if enable */
int is_ck_swap;
};
struct if_params {
/* bus configuration */
struct bus_params as_bus_params[MV_DDR_MAX_BUS_NUM];
/* Speed Bin Table */
enum mv_ddr_speed_bin speed_bin_index;
/* sdram device width */
enum mv_ddr_dev_width bus_width;
/* total sdram capacity per die, megabits */
enum mv_ddr_die_capacity memory_size;
/* The DDR frequency for each interfaces */
enum mv_ddr_freq memory_freq;
/*
* delay CAS Write Latency
* - 0 for using default value (jedec suggested)
*/
u8 cas_wl;
/*
* delay CAS Latency
* - 0 for using default value (jedec suggested)
*/
u8 cas_l;
/* operation temperature */
enum mv_ddr_temperature interface_temp;
/* 2T vs 1T mode (by default computed from number of CSs) */
enum mv_ddr_timing timing;
};
/* memory electrical configuration */
struct mv_ddr_mem_edata {
enum mv_ddr_rtt_nom_park_evalue rtt_nom;
enum mv_ddr_rtt_nom_park_evalue rtt_park[MAX_CS_NUM];
enum mv_ddr_rtt_wr_evalue rtt_wr[MAX_CS_NUM];
enum mv_ddr_dic_evalue dic;
};
/* phy electrical configuration */
struct mv_ddr_phy_edata {
enum mv_ddr_ohm_evalue drv_data_p;
enum mv_ddr_ohm_evalue drv_data_n;
enum mv_ddr_ohm_evalue drv_ctrl_p;
enum mv_ddr_ohm_evalue drv_ctrl_n;
enum mv_ddr_ohm_evalue odt_p[MAX_CS_NUM];
enum mv_ddr_ohm_evalue odt_n[MAX_CS_NUM];
};
/* mac electrical configuration */
struct mv_ddr_mac_edata {
enum mv_ddr_odt_cfg_evalue odt_cfg_pat;
enum mv_ddr_odt_cfg_evalue odt_cfg_wr;
enum mv_ddr_odt_cfg_evalue odt_cfg_rd;
};
struct mv_ddr_edata {
struct mv_ddr_mem_edata mem_edata;
struct mv_ddr_phy_edata phy_edata;
struct mv_ddr_mac_edata mac_edata;
};
struct mv_ddr_topology_map {
/* debug level configuration */
enum mv_ddr_debug_level debug_level;
/* Number of interfaces (default is 12) */
u8 if_act_mask;
/* Controller configuration per interface */
struct if_params interface_params[MV_DDR_MAX_IFACE_NUM];
/* Bit mask for active buses */
u16 bus_act_mask;
/* source of ddr configuration data */
enum mv_ddr_cfg_src cfg_src;
/* raw spd data */
union mv_ddr_spd_data spd_data;
/* timing parameters */
unsigned int timing_data[MV_DDR_TDATA_LAST];
/* electrical configuration */
struct mv_ddr_edata edata;
/* electrical parameters */
unsigned int electrical_data[MV_DDR_EDATA_LAST];
};
enum mv_ddr_iface_mode {
MV_DDR_RAR_ENA,
MV_DDR_RAR_DIS,
};
enum mv_ddr_iface_state {
MV_DDR_IFACE_NRDY, /* not ready */
MV_DDR_IFACE_INIT, /* init'd */
MV_DDR_IFACE_RDY, /* ready */
MV_DDR_IFACE_DNE /* does not exist */
};
enum mv_ddr_validation {
MV_DDR_VAL_DIS,
MV_DDR_VAL_RX,
MV_DDR_VAL_TX,
MV_DDR_VAL_RX_TX
};
struct mv_ddr_iface {
/* base addr of ap ddr interface belongs to */
unsigned int ap_base;
/* ddr interface id */
unsigned int id;
/* ddr interface state */
enum mv_ddr_iface_state state;
/* ddr interface mode (rar enabled/disabled) */
enum mv_ddr_iface_mode iface_mode;
/* ddr interface base address */
unsigned long long iface_base_addr;
/* ddr interface size - ddr flow will update this parameter */
unsigned long long iface_byte_size;
/* ddr i2c spd data address */
unsigned int spd_data_addr;
/* ddr i2c spd page 0 select address */
unsigned int spd_page_sel_addr;
/* ddr interface validation mode */
enum mv_ddr_validation validation;
/* ddr interface topology map */
struct mv_ddr_topology_map tm;
};
struct mv_ddr_iface *mv_ddr_iface_get(void);
/* DDR3 training global configuration parameters */
struct tune_train_params {
u32 ck_delay;
u32 phy_reg3_val;
u32 g_zpri_data;
u32 g_znri_data;
u32 g_zpri_ctrl;
u32 g_znri_ctrl;
u32 g_zpodt_data;
u32 g_znodt_data;
u32 g_zpodt_ctrl;
u32 g_znodt_ctrl;
u32 g_dic;
u32 g_odt_config;
u32 g_rtt_nom;
u32 g_rtt_wr;
u32 g_rtt_park;
};
#endif /* _DDR_TOPOLOGY_DEF_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/ddr_training_ip_db.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR_TRAINING_IP_DB_H_
#define _DDR_TRAINING_IP_DB_H_
#include "ddr3_training_ip_db.h"
u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index);
#endif /* _DDR3_TRAINING_IP_DB_H_ */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/dram_if.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 Marvell International Ltd.
*/
#ifndef _DRAM_IF_H_
#define _DRAM_IF_H_
/* TODO: update atf to this new prototype */
int dram_init(void);
void dram_mmap_config(void);
unsigned long long dram_iface_mem_sz_get(void);
#endif /* _DRAM_IF_H_ */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
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// SPDX-License-Identifier: GPL-2.0
const char mv_ddr_build_message[] = "";
const char mv_ddr_version_string[] = "mv_ddr: mv_ddr-armada-18.09.2";
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/mv_ddr_common.c
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#include "mv_ddr_common.h"
#include "ddr_ml_wrapper.h"
void mv_ddr_ver_print(void)
{
printf("%s %s\n", mv_ddr_version_string, mv_ddr_build_message);
}
/* ceiling division for positive integers */
unsigned int ceil_div(unsigned int x, unsigned int y)
{
return (x % y) ? (x / y + 1) : (x / y);
}
/*
* time to number of clocks calculation based on the rounding algorithm
* using 97.4% inverse factor per JEDEC Standard No. 21-C, 4.1.2.L-4:
* Serial Presence Detect (SPD) for DDR4 SDRAM Modules
*/
unsigned int time_to_nclk(unsigned int t, unsigned int tclk)
{
/* t & tclk parameters are in ps */
return ((unsigned long)t * 1000 / tclk + 974) / 1000;
}
/* round division of two positive integers to the nearest whole number */
int round_div(unsigned int dividend, unsigned int divisor, unsigned int *quotient)
{
if (quotient == NULL) {
printf("%s: error: NULL quotient pointer found\n", __func__);
return MV_FAIL;
}
if (divisor == 0) {
printf("%s: error: division by zero\n", __func__);
return MV_FAIL;
} else {
*quotient = (dividend + divisor / 2) / divisor;
}
return MV_OK;
}
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/mv_ddr_common.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _MV_DDR_COMMON_H
#define _MV_DDR_COMMON_H
extern const char mv_ddr_build_message[];
extern const char mv_ddr_version_string[];
#define _1K 0x00000400
#define _4K 0x00001000
#define _8K 0x00002000
#define _16K 0x00004000
#define _32K 0x00008000
#define _64K 0x00010000
#define _128K 0x00020000
#define _256K 0x00040000
#define _512K 0x00080000
#define _1M 0x00100000
#define _2M 0x00200000
#define _4M 0x00400000
#define _8M 0x00800000
#define _16M 0x01000000
#define _32M 0x02000000
#define _64M 0x04000000
#define _128M 0x08000000
#define _256M 0x10000000
#define _512M 0x20000000
#define _1G 0x40000000
#define _2G 0x80000000
#define _4G 0x100000000
#define _8G 0x200000000
#define _16G 0x400000000
#define _32G 0x800000000
#define _64G 0x1000000000
#define _128G 0x2000000000
#define MEGA 1000000
#define MV_DDR_MEGABYTE (1024 * 1024)
#define MV_DDR_32_BITS_MASK 0xffffffff
#define GET_MAX_VALUE(x, y) \
(((x) > (y)) ? (x) : (y))
void mv_ddr_ver_print(void);
unsigned int ceil_div(unsigned int x, unsigned int y);
unsigned int time_to_nclk(unsigned int t, unsigned int tclk);
int round_div(unsigned int dividend, unsigned int divisor, unsigned int *quotient);
#endif /* _MV_DDR_COMMON_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/mv_ddr_plat.c
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source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/mv_ddr_plat.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _MV_DDR_PLAT_H
#define _MV_DDR_PLAT_H
#define MAX_DEVICE_NUM 1
#define MAX_INTERFACE_NUM 1
#define MAX_BUS_NUM 5
#define DDR_IF_CTRL_SUBPHYS_NUM 3
#define DFS_LOW_FREQ_VALUE 120
#define SDRAM_CS_SIZE 0xfffffff /* FIXME: implement a function for cs size for each platform */
#define INTER_REGS_BASE SOC_REGS_PHY_BASE
#define AP_INT_REG_START_ADDR 0xd0000000
#define AP_INT_REG_END_ADDR 0xd0100000
/* Controler bus divider 1 for 32 bit, 2 for 64 bit */
#define DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER 1
/* Tune internal training params values */
#define TUNE_TRAINING_PARAMS_CK_DELAY 160
#define TUNE_TRAINING_PARAMS_PHYREG3VAL 0xA
#define TUNE_TRAINING_PARAMS_PRI_DATA 123
#define TUNE_TRAINING_PARAMS_NRI_DATA 123
#define TUNE_TRAINING_PARAMS_PRI_CTRL 74
#define TUNE_TRAINING_PARAMS_NRI_CTRL 74
#define TUNE_TRAINING_PARAMS_P_ODT_DATA 45
#define TUNE_TRAINING_PARAMS_N_ODT_DATA 45
#define TUNE_TRAINING_PARAMS_P_ODT_CTRL 45
#define TUNE_TRAINING_PARAMS_N_ODT_CTRL 45
#define TUNE_TRAINING_PARAMS_DIC 0x2
#define TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS 0x120012
#define TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS 0x10000
#define TUNE_TRAINING_PARAMS_RTT_NOM 0x44
#define TUNE_TRAINING_PARAMS_RTT_WR_1CS 0x0 /*off*/
#define TUNE_TRAINING_PARAMS_RTT_WR_2CS 0x0 /*off*/
#define MARVELL_BOARD MARVELL_BOARD_ID_BASE
#define REG_DEVICE_SAR1_ADDR 0xe4204
#define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET 17
#define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK 0x1f
#define DEVICE_SAMPLE_AT_RESET2_REG 0x18604
#define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET 0
#define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ 0
#define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_40MHZ 1
/* DRAM Windows */
#define REG_XBAR_WIN_5_CTRL_ADDR 0x20050
#define REG_XBAR_WIN_5_BASE_ADDR 0x20054
/* DRAM Windows */
#define REG_XBAR_WIN_4_CTRL_ADDR 0x20040
#define REG_XBAR_WIN_4_BASE_ADDR 0x20044
#define REG_XBAR_WIN_4_REMAP_ADDR 0x20048
#define REG_XBAR_WIN_7_REMAP_ADDR 0x20078
#define REG_XBAR_WIN_16_CTRL_ADDR 0x200d0
#define REG_XBAR_WIN_16_BASE_ADDR 0x200d4
#define REG_XBAR_WIN_16_REMAP_ADDR 0x200dc
#define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8
#define REG_FASTPATH_WIN_BASE_ADDR(win) (0x20180 + (0x8 * win))
#define REG_FASTPATH_WIN_CTRL_ADDR(win) (0x20184 + (0x8 * win))
#define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100))
#define CPU_MRVL_ID_OFFSET 0x10
#define SAR1_CPU_CORE_MASK 0x00000018
#define SAR1_CPU_CORE_OFFSET 3
/* SatR defined too change topology busWidth and ECC configuration */
#define DDR_SATR_CONFIG_MASK_WIDTH 0x8
#define DDR_SATR_CONFIG_MASK_ECC 0x10
#define DDR_SATR_CONFIG_MASK_ECC_PUP 0x20
#define REG_SAMPLE_RESET_HIGH_ADDR 0x18600
#define MV_BOARD_REFCLK_25MHZ 25000000
#define MV_BOARD_REFCLK MV_BOARD_REFCLK_25MHZ
#define MAX_DQ_NUM 40
/* dram line buffer registers */
#define DLB_CTRL_REG 0x1700
#define DLB_EN_OFFS 0
#define DLB_EN_MASK 0x1
#define DLB_EN_ENA 1
#define DLB_EN_DIS 0
#define WR_COALESCE_EN_OFFS 2
#define WR_COALESCE_EN_MASK 0x1
#define WR_COALESCE_EN_ENA 1
#define WR_COALESCE_EN_DIS 0
#define AXI_PREFETCH_EN_OFFS 3
#define AXI_PREFETCH_EN_MASK 0x1
#define AXI_PREFETCH_EN_ENA 1
#define AXI_PREFETCH_EN_DIS 0
#define MBUS_PREFETCH_EN_OFFS 4
#define MBUS_PREFETCH_EN_MASK 0x1
#define MBUS_PREFETCH_EN_ENA 1
#define MBUS_PREFETCH_EN_DIS 0
#define PREFETCH_NXT_LN_SZ_TRIG_OFFS 6
#define PREFETCH_NXT_LN_SZ_TRIG_MASK 0x1
#define PREFETCH_NXT_LN_SZ_TRIG_ENA 1
#define PREFETCH_NXT_LN_SZ_TRIG_DIS 0
#define DLB_BUS_OPT_WT_REG 0x1704
#define DLB_AGING_REG 0x1708
#define DLB_EVICTION_CTRL_REG 0x170c
#define DLB_EVICTION_TIMERS_REG 0x1710
#define DLB_USER_CMD_REG 0x1714
#define DLB_WTS_DIFF_CS_REG 0x1770
#define DLB_WTS_DIFF_BG_REG 0x1774
#define DLB_WTS_SAME_BG_REG 0x1778
#define DLB_WTS_CMDS_REG 0x177c
#define DLB_WTS_ATTR_PRIO_REG 0x1780
#define DLB_QUEUE_MAP_REG 0x1784
#define DLB_SPLIT_REG 0x1788
/* ck swap control subphy number */
#define CK_SWAP_CTRL_PHY_NUM 2
/* Subphy result control per byte registers */
#define RESULT_CONTROL_BYTE_PUP_0_REG 0x1830
#define RESULT_CONTROL_BYTE_PUP_1_REG 0x1834
#define RESULT_CONTROL_BYTE_PUP_2_REG 0x1838
#define RESULT_CONTROL_BYTE_PUP_3_REG 0x183c
#define RESULT_CONTROL_BYTE_PUP_4_REG 0x18b0
/* Subphy result control per bit registers */
#define RESULT_CONTROL_PUP_0_BIT_0_REG 0x18b4
#define RESULT_CONTROL_PUP_0_BIT_1_REG 0x18b8
#define RESULT_CONTROL_PUP_0_BIT_2_REG 0x18bc
#define RESULT_CONTROL_PUP_0_BIT_3_REG 0x18c0
#define RESULT_CONTROL_PUP_0_BIT_4_REG 0x18c4
#define RESULT_CONTROL_PUP_0_BIT_5_REG 0x18c8
#define RESULT_CONTROL_PUP_0_BIT_6_REG 0x18cc
#define RESULT_CONTROL_PUP_0_BIT_7_REG 0x18f0
#define RESULT_CONTROL_PUP_1_BIT_0_REG 0x18f4
#define RESULT_CONTROL_PUP_1_BIT_1_REG 0x18f8
#define RESULT_CONTROL_PUP_1_BIT_2_REG 0x18fc
#define RESULT_CONTROL_PUP_1_BIT_3_REG 0x1930
#define RESULT_CONTROL_PUP_1_BIT_4_REG 0x1934
#define RESULT_CONTROL_PUP_1_BIT_5_REG 0x1938
#define RESULT_CONTROL_PUP_1_BIT_6_REG 0x193c
#define RESULT_CONTROL_PUP_1_BIT_7_REG 0x19b0
#define RESULT_CONTROL_PUP_2_BIT_0_REG 0x19b4
#define RESULT_CONTROL_PUP_2_BIT_1_REG 0x19b8
#define RESULT_CONTROL_PUP_2_BIT_2_REG 0x19bc
#define RESULT_CONTROL_PUP_2_BIT_3_REG 0x19c0
#define RESULT_CONTROL_PUP_2_BIT_4_REG 0x19c4
#define RESULT_CONTROL_PUP_2_BIT_5_REG 0x19c8
#define RESULT_CONTROL_PUP_2_BIT_6_REG 0x19cc
#define RESULT_CONTROL_PUP_2_BIT_7_REG 0x19f0
#define RESULT_CONTROL_PUP_3_BIT_0_REG 0x19f4
#define RESULT_CONTROL_PUP_3_BIT_1_REG 0x19f8
#define RESULT_CONTROL_PUP_3_BIT_2_REG 0x19fc
#define RESULT_CONTROL_PUP_3_BIT_3_REG 0x1a30
#define RESULT_CONTROL_PUP_3_BIT_4_REG 0x1a34
#define RESULT_CONTROL_PUP_3_BIT_5_REG 0x1a38
#define RESULT_CONTROL_PUP_3_BIT_6_REG 0x1a3c
#define RESULT_CONTROL_PUP_3_BIT_7_REG 0x1ab0
#define RESULT_CONTROL_PUP_4_BIT_0_REG 0x1ab4
#define RESULT_CONTROL_PUP_4_BIT_1_REG 0x1ab8
#define RESULT_CONTROL_PUP_4_BIT_2_REG 0x1abc
#define RESULT_CONTROL_PUP_4_BIT_3_REG 0x1ac0
#define RESULT_CONTROL_PUP_4_BIT_4_REG 0x1ac4
#define RESULT_CONTROL_PUP_4_BIT_5_REG 0x1ac8
#define RESULT_CONTROL_PUP_4_BIT_6_REG 0x1acc
#define RESULT_CONTROL_PUP_4_BIT_7_REG 0x1af0
/* CPU */
#define REG_BOOTROM_ROUTINE_ADDR 0x182d0
#define REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS 12
/* Matrix enables DRAM modes (bus width/ECC) per boardId */
#define TOPOLOGY_UPDATE_32BIT 0
#define TOPOLOGY_UPDATE_32BIT_ECC 1
#define TOPOLOGY_UPDATE_16BIT 2
#define TOPOLOGY_UPDATE_16BIT_ECC 3
#define TOPOLOGY_UPDATE_16BIT_ECC_PUP3 4
#define TOPOLOGY_UPDATE { \
/* 32Bit, 32bit ECC, 16bit, 16bit ECC PUP4, 16bit ECC PUP3 */ \
{1, 1, 1, 1, 1}, /* RD_NAS_68XX_ID */ \
{1, 1, 1, 1, 1}, /* DB_68XX_ID */ \
{1, 0, 1, 0, 1}, /* RD_AP_68XX_ID */ \
{1, 0, 1, 0, 1}, /* DB_AP_68XX_ID */ \
{1, 0, 1, 0, 1}, /* DB_GP_68XX_ID */ \
{0, 0, 1, 1, 0}, /* DB_BP_6821_ID */ \
{1, 1, 1, 1, 1} /* DB_AMC_6820_ID */ \
};
enum {
CPU_1066MHZ_DDR_400MHZ,
CPU_RESERVED_DDR_RESERVED0,
CPU_667MHZ_DDR_667MHZ,
CPU_800MHZ_DDR_800MHZ,
CPU_RESERVED_DDR_RESERVED1,
CPU_RESERVED_DDR_RESERVED2,
CPU_RESERVED_DDR_RESERVED3,
LAST_FREQ
};
/* struct used for DLB configuration array */
struct dlb_config {
u32 reg_addr;
u32 reg_data;
};
#define ACTIVE_INTERFACE_MASK 0x1
extern u32 dmin_phy_reg_table[][2];
extern u16 odt_slope[];
extern u16 odt_intercept[];
int mv_ddr_pre_training_soc_config(const char *ddr_type);
int mv_ddr_post_training_soc_config(const char *ddr_type);
void mv_ddr_mem_scrubbing(void);
u32 mv_ddr_init_freq_get(void);
void mv_ddr_odpg_enable(void);
void mv_ddr_odpg_disable(void);
void mv_ddr_odpg_done_clr(void);
int mv_ddr_is_odpg_done(u32 count);
void mv_ddr_training_enable(void);
int mv_ddr_is_training_done(u32 count, u32 *result);
u32 mv_ddr_dm_pad_get(void);
int mv_ddr_pre_training_fixup(void);
int mv_ddr_post_training_fixup(void);
int mv_ddr_manual_cal_do(void);
int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size);
#endif /* _MV_DDR_PLAT_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/mv_ddr_regs.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _MV_DDR_REGS_H
#define _MV_DDR_REGS_H
#define GLOB_CTRL_STATUS_REG 0x1030
#define TRAINING_TRIGGER_OFFS 0
#define TRAINING_TRIGGER_MASK 0x1
#define TRAINING_TRIGGER_ENA 1
#define TRAINING_DONE_OFFS 1
#define TRAINING_DONE_MASK 0x1
#define TRAINING_DONE_DONE 1
#define TRAINING_DONE_NOT_DONE 0
#define TRAINING_RESULT_OFFS 2
#define TRAINING_RESULT_MASK 0x1
#define TRAINING_RESULT_PASS 0
#define TRAINING_RESULT_FAIL 1
#define GENERAL_TRAINING_OPCODE_REG 0x1034
#define OPCODE_REG0_BASE 0x1038
#define OPCODE_REG0_REG(obj) (OPCODE_REG0_BASE + (obj) * 0x4)
#define OPCODE_REG1_BASE 0x10b0
#define OPCODE_REG1_REG(obj) (OPCODE_REG1_BASE + (obj) * 0x4)
#define CAL_PHY_BASE 0x10c0
#define CAL_PHY_REG(obj) (CAL_PHY_BASE + (obj) * 0x4)
#define WL_DONE_CNTR_REF_REG 0x10f8
#define ODPG_WR_RD_MODE_ENA_REG 0x10fc
#define SDRAM_CFG_REG 0x1400
#define REFRESH_OFFS 0
#define REFRESH_MASK 0x3fff
#define DRAM_TYPE_OFFS 14
#define DRAM_TYPE_MASK 0x1
#define BUS_IN_USE_OFFS 15
#define BUS_IN_USE_MASK 0x1
#define CPU_2DRAM_WR_BUFF_CUT_TH_OFFS 16
#define CPU_2DRAM_WR_BUFF_CUT_TH_MASK 0x1
#define REG_DIMM_OFFS 17
#define REG_DIMM_MASK 0x1
#define ECC_OFFS 18
#define ECC_MASK 0x1
#define IGNORE_ERRORS_OFFS 19
#define IGNORE_ERRORS_MASK 0x1
#define DRAM_TYPE_HIGH_OFFS 20
#define DRAM_TYPE_HIGH_MASK 0x1
#define SELF_REFRESH_MODE_OFFS 24
#define SELF_REFRESH_MODE_MASK 0x1
#define CPU_RD_PER_PROP_OFFS 25
#define CPU_RD_PER_PROP_MASK 0x1
#define DDR4_EMULATION_OFFS 26
#define DDR4_EMULATION_MASK 0x1
#define PHY_RF_RST_OFFS 27
#define PHY_RF_RST_MASK 0x1
#define PUP_RST_DIVIDER_OFFS 28
#define PUP_RST_DIVIDER_MASK 0x1
#define DATA_PUP_WR_RESET_OFFS 29
#define DATA_PUP_WR_RESET_MASK 0x1
#define DATA_PUP_RD_RESET_OFFS 30
#define DATA_PUP_RD_RESET_MASK 0x1
#define DATA_PUP_RD_RESET_ENA 0x0
#define DATA_PUP_RD_RESET_DIS 0x1
#define IO_BIST_OFFS 31
#define DATA_PUP_RD_RESET_MASK 0x1
#define DUNIT_CTRL_LOW_REG 0x1404
#define SDRAM_TIMING_LOW_REG 0x1408
#define SDRAM_TIMING_LOW_TRAS_OFFS 0
#define SDRAM_TIMING_LOW_TRAS_MASK 0xf
#define SDRAM_TIMING_LOW_TRCD_OFFS 4
#define SDRAM_TIMING_LOW_TRCD_MASK 0xf
#define SDRAM_TIMING_HIGH_TRCD_OFFS 22
#define SDRAM_TIMING_HIGH_TRCD_MASK 0x1
#define SDRAM_TIMING_LOW_TRP_OFFS 8
#define SDRAM_TIMING_LOW_TRP_MASK 0xf
#define SDRAM_TIMING_HIGH_TRP_OFFS 23
#define SDRAM_TIMING_HIGH_TRP_MASK 0x1
#define SDRAM_TIMING_LOW_TWR_OFFS 12
#define SDRAM_TIMING_LOW_TWR_MASK 0xf
#define SDRAM_TIMING_LOW_TWTR_OFFS 16
#define SDRAM_TIMING_LOW_TWTR_MASK 0xf
#define SDRAM_TIMING_LOW_TRAS_HIGH_OFFS 20
#define SDRAM_TIMING_LOW_TRAS_HIGH_MASK 0x3
#define SDRAM_TIMING_LOW_TRRD_OFFS 24
#define SDRAM_TIMING_LOW_TRRD_MASK 0xf
#define SDRAM_TIMING_LOW_TRTP_OFFS 28
#define SDRAM_TIMING_LOW_TRTP_MASK 0xf
#define SDRAM_TIMING_HIGH_REG 0x140c
#define SDRAM_TIMING_HIGH_TRFC_OFFS 0
#define SDRAM_TIMING_HIGH_TRFC_MASK 0x7f
#define SDRAM_TIMING_HIGH_TR2R_OFFS 7
#define SDRAM_TIMING_HIGH_TR2R_MASK 0x3
#define SDRAM_TIMING_HIGH_TR2W_W2R_OFFS 9
#define SDRAM_TIMING_HIGH_TR2W_W2R_MASK 0x3
#define SDRAM_TIMING_HIGH_TW2W_OFFS 11
#define SDRAM_TIMING_HIGH_TW2W_MASK 0x1f
#define SDRAM_TIMING_HIGH_TRFC_HIGH_OFFS 16
#define SDRAM_TIMING_HIGH_TRFC_HIGH_MASK 0x7
#define SDRAM_TIMING_HIGH_TR2R_HIGH_OFFS 19
#define SDRAM_TIMING_HIGH_TR2R_HIGH_MASK 0x7
#define SDRAM_TIMING_HIGH_TR2W_W2R_HIGH_OFFS 22
#define SDRAM_TIMING_HIGH_TR2W_W2R_HIGH_MASK 0x7
#define SDRAM_TIMING_HIGH_TMOD_OFFS 25
#define SDRAM_TIMING_HIGH_TMOD_MASK 0xf
#define SDRAM_TIMING_HIGH_TMOD_HIGH_OFFS 30
#define SDRAM_TIMING_HIGH_TMOD_HIGH_MASK 0x3
#define SDRAM_ADDR_CTRL_REG 0x1410
#define CS_STRUCT_BASE 0
#define CS_STRUCT_OFFS(cs) (CS_STRUCT_BASE + (cs) * 4)
#define CS_STRUCT_MASK 0x3
#define CS_SIZE_BASE 2
#define CS_SIZE_OFFS(cs) (CS_SIZE_BASE + (cs) * 4)
#define CS_SIZE_MASK 0x3
#define CS_SIZE_HIGH_BASE 20
#define CS_SIZE_HIGH_OFFS(cs) (CS_SIZE_HIGH_BASE + (cs))
#define CS_SIZE_HIGH_MASK 0x1
#define T_FAW_OFFS 24
#define T_FAW_MASK 0x7f
#define SDRAM_OPEN_PAGES_CTRL_REG 0x1414
#define SDRAM_OP_REG 0x1418
#define SDRAM_OP_CMD_OFFS 0
#define SDRAM_OP_CMD_MASK 0x1f
#define SDRAM_OP_CMD_CS_BASE 8
#define SDRAM_OP_CMD_CS_OFFS(cs) (SDRAM_OP_CMD_CS_BASE + (cs))
#define SDRAM_OP_CMD_CS_MASK 0x1
#define SDRAM_OP_CMD_ALL_CS_MASK 0xf
enum {
CMD_NORMAL,
CMD_PRECHARGE,
CMD_REFRESH,
CMD_DDR3_DDR4_MR0,
CMD_DDR3_DDR4_MR1,
CMD_NOP,
CMD_RES_0X6,
CMD_SELFREFRESH,
CMD_DDR3_DDR4_MR2,
CMD_DDR3_DDR4_MR3,
CMD_ACT_PDE,
CMD_PRE_PDE,
CMD_ZQCL,
CMD_ZQCS,
CMD_CWA,
CMD_RES_0XF,
CMD_DDR4_MR4,
CMD_DDR4_MR5,
CMD_DDR4_MR6,
DDR4_MPR_WR
};
#define DUNIT_CTRL_HIGH_REG 0x1424
#define CPU_INTERJECTION_ENA_OFFS 3
#define CPU_INTERJECTION_ENA_MASK 0x1
#define CPU_INTERJECTION_ENA_SPLIT_ENA 0
#define CPU_INTERJECTION_ENA_SPLIT_DIS 1
#define DDR_ODT_TIMING_LOW_REG 0x1428
#define DDR_TIMING_REG 0x142c
#define DDR_TIMING_TCCD_OFFS 18
#define DDR_TIMING_TCCD_MASK 0x7
#define DDR_TIMING_TPD_OFFS 0
#define DDR_TIMING_TPD_MASK 0xf
#define DDR_TIMING_TXPDLL_OFFS 4
#define DDR_TIMING_TXPDLL_MASK 0x1f
#define DDR_ODT_TIMING_HIGH_REG 0x147c
#define SDRAM_INIT_CTRL_REG 0x1480
#define DRAM_RESET_MASK_OFFS 1
#define DRAM_RESET_MASK_MASK 0x1
#define DRAM_RESET_MASK_NORMAL 0
#define DRAM_RESET_MASK_MASKED 1
#define SDRAM_ODT_CTRL_HIGH_REG 0x1498
#define DUNIT_ODT_CTRL_REG 0x149c
#define RD_BUFFER_SEL_REG 0x14a4
#define AXI_CTRL_REG 0x14a8
#define DUNIT_MMASK_REG 0x14b0
#define HORZ_SSTL_CAL_MACH_CTRL_REG 0x14c8
#define HORZ_POD_CAL_MACH_CTRL_REG 0x17c8
#define VERT_SSTL_CAL_MACH_CTRL_REG 0x1dc8
#define VERT_POD_CAL_MACH_CTRL_REG 0x1ec8
#define MAIN_PADS_CAL_MACH_CTRL_REG 0x14cc
#define DYN_PADS_CAL_ENABLE_OFFS 0
#define DYN_PADS_CAL_ENABLE_MASK 0x1
#define DYN_PADS_CAL_ENABLE_DIS 0
#define DYN_PADS_CAL_ENABLE_ENA 1
#define PADS_RECAL_OFFS 1
#define PADS_RECAL_MASK 0x1
#define DYN_PADS_CAL_BLOCK_OFFS 2
#define DYN_PADS_CAL_BLOCK_MASK 0x1
#define CAL_UPDATE_CTRL_OFFS 3
#define CAL_UPDATE_CTRL_MASK 0x3
#define CAL_UPDATE_CTRL_INT 1
#define CAL_UPDATE_CTRL_EXT 2
#define DYN_PADS_CAL_CNTR_OFFS 13
#define DYN_PADS_CAL_CNTR_MASK 0x3ffff
#define CAL_MACH_STATUS_OFFS 31
#define CAL_MACH_STATUS_MASK 0x1
#define CAL_MACH_BUSY 0
#define CAL_MACH_RDY 1
#define DRAM_DLL_TIMING_REG 0x14e0
#define DRAM_ZQ_INIT_TIMIMG_REG 0x14e4
#define DRAM_ZQ_TIMING_REG 0x14e8
#define DRAM_LONG_TIMING_REG 0x14ec
#define DDR4_TRRD_L_OFFS 0
#define DDR4_TRRD_L_MASK 0xf
#define DDR4_TWTR_L_OFFS 4
#define DDR4_TWTR_L_MASK 0xf
#define DDR_IO_REG 0x1524
#define DFS_REG 0x1528
#define RD_DATA_SMPL_DLYS_REG 0x1538
#define RD_SMPL_DLY_CS_BASE 0
#define RD_SMPL_DLY_CS_OFFS(cs) (RD_SMPL_DLY_CS_BASE + (cs) * 8)
#define RD_SMPL_DLY_CS_MASK 0x1f
#define RD_DATA_RDY_DLYS_REG 0x153c
#define RD_RDY_DLY_CS_BASE 0
#define RD_RDY_DLY_CS_OFFS(cs) (RD_RDY_DLY_CS_BASE + (cs) * 8)
#define RD_RDY_DLY_CS_MASK 0x1f
#define TRAINING_REG 0x15b0
#define TRN_START_OFFS 31
#define TRN_START_MASK 0x1
#define TRN_START_ENA 1
#define TRN_START_DIS 0
#define TRAINING_SW_1_REG 0x15b4
#define TRAINING_SW_2_REG 0x15b8
#define TRAINING_ECC_MUX_OFFS 1
#define TRAINING_ECC_MUX_MASK 0x1
#define TRAINING_ECC_MUX_DIS 0
#define TRAINING_ECC_MUX_ENA 1
#define TRAINING_SW_OVRD_OFFS 0
#define TRAINING_SW_OVRD_MASK 0x1
#define TRAINING_SW_OVRD_DIS 0
#define TRAINING_SW_OVRD_ENA 1
#define TRAINING_PATTERN_BASE_ADDR_REG 0x15bc
#define TRAINING_DBG_1_REG 0x15c0
#define TRAINING_DBG_2_REG 0x15c4
#define TRAINING_DBG_3_REG 0x15c8
#define TRN_DBG_RDY_INC_PH_2TO1_BASE 0
#define TRN_DBG_RDY_INC_PH_2TO1_OFFS(phase) (TRN_DBG_RDY_INC_PH_2TO1_BASE + (phase) * 3)
#define TRN_DBG_RDY_INC_PH_2TO1_MASK 0x7
#define DDR3_RANK_CTRL_REG 0x15e0
#define CS_EXIST_BASE 0
#define CS_EXIST_OFFS(cs) (CS_EXIST_BASE + (cs))
#define CS_EXIST_MASK 0x1
#define ZQC_CFG_REG 0x15e4
#define DRAM_PHY_CFG_REG 0x15ec
#define ODPG_CTRL_CTRL_REG 0x1600
#define ODPG_CTRL_AUTO_REFRESH_OFFS 21
#define ODPG_CTRL_AUTO_REFRESH_MASK 0x1
#define ODPG_CTRL_AUTO_REFRESH_DIS 1
#define ODPG_CTRL_AUTO_REFRESH_ENA 0
#define ODPG_DATA_CTRL_REG 0x1630
#define ODPG_WRBUF_WR_CTRL_OFFS 0
#define ODPG_WRBUF_WR_CTRL_MASK 0x1
#define ODPG_WRBUF_WR_CTRL_DIS 0
#define ODPG_WRBUF_WR_CTRL_ENA 1
#define ODPG_WRBUF_RD_CTRL_OFFS 1
#define ODPG_WRBUF_RD_CTRL_MASK 0x1
#define ODPG_WRBUF_RD_CTRL_DIS 0
#define ODPG_WRBUF_RD_CTRL_ENA 1
#define ODPG_DATA_CBDEL_OFFS 15
#define ODPG_DATA_CBDEL_MASK 0x3f
#define ODPG_MODE_OFFS 25
#define ODPG_MODE_MASK 0x1
#define ODPG_MODE_RX 0
#define ODPG_MODE_TX 1
#define ODPG_DATA_CS_OFFS 26
#define ODPG_DATA_CS_MASK 0x3
#define ODPG_DISABLE_OFFS 30
#define ODPG_DISABLE_MASK 0x1
#define ODPG_DISABLE_DIS 1
#define ODPG_ENABLE_OFFS 31
#define ODPG_ENABLE_MASK 0x1
#define ODPG_ENABLE_ENA 1
#define ODPG_DATA_BUFFER_OFFS_REG 0x1638
#define ODPG_DATA_BUFFER_SIZE_REG 0x163c
#define PHY_LOCK_STATUS_REG 0x1674
#define PHY_REG_FILE_ACCESS_REG 0x16a0
#define PRFA_DATA_OFFS 0
#define PRFA_DATA_MASK 0xffff
#define PRFA_REG_NUM_OFFS 16
#define PRFA_REG_NUM_MASK 0x3f
#define PRFA_PUP_NUM_OFFS 22
#define PRFA_PUP_NUM_MASK 0xf
#define PRFA_PUP_CTRL_DATA_OFFS 26
#define PRFA_PUP_CTRL_DATA_MASK 0x1
#define PRFA_PUP_BCAST_WR_ENA_OFFS 27
#define PRFA_PUP_BCAST_WR_ENA_MASK 0x1
#define PRFA_REG_NUM_HI_OFFS 28
#define PRFA_REG_NUM_HI_MASK 0x3
#define PRFA_TYPE_OFFS 30
#define PRFA_TYPE_MASK 0x1
#define PRFA_REQ_OFFS 31
#define PRFA_REQ_MASK 0x1
#define PRFA_REQ_DIS 0x0
#define PRFA_REQ_ENA 0x1
#define TRAINING_WL_REG 0x16ac
#define ODPG_DATA_WR_ADDR_REG 0x16b0
#define ODPG_DATA_WR_ACK_OFFS 0
#define ODPG_DATA_WR_ACK_MASK 0x7f
#define ODPG_DATA_WR_DATA_OFFS 8
#define ODPG_DATA_WR_DATA_MASK 0xff
#define ODPG_DATA_WR_DATA_HIGH_REG 0x16b4
#define ODPG_DATA_WR_DATA_LOW_REG 0x16b8
#define ODPG_DATA_RX_WORD_ERR_ADDR_REG 0x16bc
#define ODPG_DATA_RX_WORD_ERR_CNTR_REG 0x16c0
#define ODPG_DATA_RX_WORD_ERR_DATA_HIGH_REG 0x16c4
#define ODPG_DATA_RX_WORD_ERR_DATA_LOW_REG 0x16c8
#define ODPG_DATA_WR_DATA_ERR_REG 0x16cc
#define DUAL_DUNIT_CFG_REG 0x16d8
#define FC_SAMPLE_STAGES_OFFS 0
#define FC_SAMPLE_STAGES_MASK 0x7
#define SINGLE_CS_PIN_OFFS 3
#define SINGLE_CS_PIN_MASK 0x1
#define SINGLE_CS_ENA 1
#define TUNING_ACTIVE_SEL_OFFS 6
#define TUNING_ACTIVE_SEL_MASK 0x1
#define TUNING_ACTIVE_SEL_MC 0
#define TUNING_ACTIVE_SEL_TIP 1
#define WL_DQS_PATTERN_REG 0x16dc
#define ODPG_DONE_STATUS_REG 0x16fc
#define ODPG_DONE_STATUS_BIT_OFFS 0
#define ODPG_DONE_STATUS_BIT_MASK 0x1
#define ODPG_DONE_STATUS_BIT_CLR 0
#define ODPG_DONE_STATUS_BIT_SET 1
#define RESULT_CTRL_BASE 0x1830
#define BLOCK_STATUS_OFFS 25
#define BLOCK_STATUS_MASK 0x1
#define BLOCK_STATUS_LOCK 1
#define BLOCK_STATUS_NOT_LOCKED 0
#define MR0_REG 0x15d0
#define MR1_REG 0x15d4
#define MR2_REG 0x15d8
#define MR3_REG 0x15dc
#define MRS0_CMD 0x3
#define MRS1_CMD 0x4
#define MRS2_CMD 0x8
#define MRS3_CMD 0x9
#define DRAM_PINS_MUX_REG 0x19d4
#define CTRL_PINS_MUX_OFFS 0
#define CTRL_PINS_MUX_MASK 0x3
enum {
DUNIT_DDR3_ON_BOARD,
DUNIT_DDR3_DIMM,
DUNIT_DDR4_ON_BOARD,
DUNIT_DDR4_DIMM
};
/* ddr phy registers */
#define WL_PHY_BASE 0x0
#define WL_PHY_REG(cs) (WL_PHY_BASE + (cs) * 0x4)
#define WR_LVL_PH_SEL_OFFS 6
#define WR_LVL_PH_SEL_MASK 0x7
#define WR_LVL_PH_SEL_PHASE1 1
#define WR_LVL_REF_DLY_OFFS 0
#define WR_LVL_REF_DLY_MASK 0x1f
#define CTRL_CENTER_DLY_OFFS 10
#define CTRL_CENTER_DLY_MASK 0x1f
#define CTRL_CENTER_DLY_INV_OFFS 15
#define CTRL_CENTER_DLY_INV_MASK 0x1
#define CTX_PHY_BASE 0x1
#define CTX_PHY_REG(cs) (CTX_PHY_BASE + (cs) * 0x4)
#define RL_PHY_BASE 0x2
#define RL_PHY_REG(cs) (RL_PHY_BASE + (cs) * 0x4)
#define RL_REF_DLY_OFFS 0
#define RL_REF_DLY_MASK 0x1f
#define RL_PH_SEL_OFFS 6
#define RL_PH_SEL_MASK 0x7
#define CRX_PHY_BASE 0x3
#define CRX_PHY_REG(cs) (CRX_PHY_BASE + (cs) * 0x4)
#define PHY_CTRL_PHY_REG 0x90
#define INV_PAD0_OFFS 2
#define INV_PAD1_OFFS 3
#define INV_PAD2_OFFS 4
#define INV_PAD3_OFFS 5
#define INV_PAD4_OFFS 6
#define INV_PAD5_OFFS 7
#define INV_PAD6_OFFS 8
#define INV_PAD7_OFFS 9
#define INV_PAD8_OFFS 10
#define INV_PAD9_OFFS 11
#define INV_PAD10_OFFS 12
#define INV_PAD_MASK 0x1
#define INVERT_PAD 1
#define ADLL_CFG0_PHY_REG 0x92
#define ADLL_CFG1_PHY_REG 0x93
#define ADLL_CFG2_PHY_REG 0x94
#define CMOS_CONFIG_PHY_REG 0xa2
#define PAD_ZRI_CAL_PHY_REG 0xa4
#define PAD_ODT_CAL_PHY_REG 0xa6
#define PAD_CFG_PHY_REG 0xa8
#define PAD_PRE_DISABLE_PHY_REG 0xa9
#define TEST_ADLL_PHY_REG 0xbf
#define VREF_PHY_BASE 0xd0
#define VREF_PHY_REG(cs, bit) (VREF_PHY_BASE + (cs) * 12 + bit)
enum {
DQSP_PAD = 4,
DQSN_PAD
};
#define VREF_BCAST_PHY_BASE 0xdb
#define VREF_BCAST_PHY_REG(cs) (VREF_BCAST_PHY_BASE + (cs) * 12)
#define PBS_TX_PHY_BASE 0x10
#define PBS_TX_PHY_REG(cs, bit) (PBS_TX_PHY_BASE + (cs) * 0x10 + (bit))
#define PBS_TX_BCAST_PHY_BASE 0x1f
#define PBS_TX_BCAST_PHY_REG(cs) (PBS_TX_BCAST_PHY_BASE + (cs) * 0x10)
#define PBS_RX_PHY_BASE 0x50
#define PBS_RX_PHY_REG(cs, bit) (PBS_RX_PHY_BASE + (cs) * 0x10 + (bit))
#define PBS_RX_BCAST_PHY_BASE 0x5f
#define PBS_RX_BCAST_PHY_REG(cs) (PBS_RX_BCAST_PHY_BASE + (cs) * 0x10)
#define RESULT_PHY_REG 0xc0
#define RESULT_PHY_RX_OFFS 5
#define RESULT_PHY_TX_OFFS 0
#endif /* _MV_DDR_REGS_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/mv_ddr_spd.c
+375
View File
@@ -0,0 +1,375 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#include "mv_ddr_spd.h"
#define MV_DDR_SPD_DATA_MTB 125 /* medium timebase, ps */
#define MV_DDR_SPD_DATA_FTB 1 /* fine timebase, ps */
#define MV_DDR_SPD_MSB_OFFS 8 /* most significant byte offset, bits */
#define MV_DDR_SPD_SUPPORTED_CLS_NUM 30
static unsigned int mv_ddr_spd_supported_cls[MV_DDR_SPD_SUPPORTED_CLS_NUM];
int mv_ddr_spd_supported_cls_calc(union mv_ddr_spd_data *spd_data)
{
unsigned int byte, bit, start_cl;
start_cl = (spd_data->all_bytes[23] & 0x8) ? 23 : 7;
for (byte = 20; byte < 23; byte++) {
for (bit = 0; bit < 8; bit++) {
if (spd_data->all_bytes[byte] & (1 << bit))
mv_ddr_spd_supported_cls[(byte - 20) * 8 + bit] = start_cl + (byte - 20) * 8 + bit;
else
mv_ddr_spd_supported_cls[(byte - 20) * 8 + bit] = 0;
}
}
for (byte = 23, bit = 0; bit < 6; bit++) {
if (spd_data->all_bytes[byte] & (1 << bit))
mv_ddr_spd_supported_cls[(byte - 20) * 8 + bit] = start_cl + (byte - 20) * 8 + bit;
else
mv_ddr_spd_supported_cls[(byte - 20) * 8 + bit] = 0;
}
return 0;
}
unsigned int mv_ddr_spd_supported_cl_get(unsigned int cl)
{
unsigned int supported_cl;
int i = 0;
while (i < MV_DDR_SPD_SUPPORTED_CLS_NUM &&
mv_ddr_spd_supported_cls[i] < cl)
i++;
if (i < MV_DDR_SPD_SUPPORTED_CLS_NUM)
supported_cl = mv_ddr_spd_supported_cls[i];
else
supported_cl = 0;
return supported_cl;
}
int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_data[])
{
int calc_val;
/* t ck avg min, ps */
calc_val = spd_data->byte_fields.byte_18 * MV_DDR_SPD_DATA_MTB +
(signed char)spd_data->byte_fields.byte_125 * MV_DDR_SPD_DATA_FTB;
if (calc_val < 0)
return 1;
timing_data[MV_DDR_TCK_AVG_MIN] = calc_val;
/* t aa min, ps */
calc_val = spd_data->byte_fields.byte_24 * MV_DDR_SPD_DATA_MTB +
(signed char)spd_data->byte_fields.byte_123 * MV_DDR_SPD_DATA_FTB;
if (calc_val < 0)
return 1;
timing_data[MV_DDR_TAA_MIN] = calc_val;
/* t rfc1 min, ps */
timing_data[MV_DDR_TRFC1_MIN] = (spd_data->byte_fields.byte_30 +
(spd_data->byte_fields.byte_31 << MV_DDR_SPD_MSB_OFFS)) * MV_DDR_SPD_DATA_MTB;
/* t wr min, ps */
timing_data[MV_DDR_TWR_MIN] = (spd_data->byte_fields.byte_42 +
(spd_data->byte_fields.byte_41.bit_fields.t_wr_min_msn << MV_DDR_SPD_MSB_OFFS)) *
MV_DDR_SPD_DATA_MTB;
/* t rcd min, ps */
calc_val = spd_data->byte_fields.byte_25 * MV_DDR_SPD_DATA_MTB +
(signed char)spd_data->byte_fields.byte_122 * MV_DDR_SPD_DATA_FTB;
if (calc_val < 0)
return 1;
timing_data[MV_DDR_TRCD_MIN] = calc_val;
/* t rp min, ps */
calc_val = spd_data->byte_fields.byte_26 * MV_DDR_SPD_DATA_MTB +
(signed char)spd_data->byte_fields.byte_121 * MV_DDR_SPD_DATA_FTB;
if (calc_val < 0)
return 1;
timing_data[MV_DDR_TRP_MIN] = calc_val;
/* t rc min, ps */
calc_val = (spd_data->byte_fields.byte_29 +
(spd_data->byte_fields.byte_27.bit_fields.t_rc_min_msn << MV_DDR_SPD_MSB_OFFS)) *
MV_DDR_SPD_DATA_MTB +
(signed char)spd_data->byte_fields.byte_120 * MV_DDR_SPD_DATA_FTB;
if (calc_val < 0)
return 1;
timing_data[MV_DDR_TRC_MIN] = calc_val;
/* t ras min, ps */
timing_data[MV_DDR_TRAS_MIN] = (spd_data->byte_fields.byte_28 +
(spd_data->byte_fields.byte_27.bit_fields.t_ras_min_msn << MV_DDR_SPD_MSB_OFFS)) *
MV_DDR_SPD_DATA_MTB;
/* t rrd s min, ps */
calc_val = spd_data->byte_fields.byte_38 * MV_DDR_SPD_DATA_MTB +
(signed char)spd_data->byte_fields.byte_119 * MV_DDR_SPD_DATA_FTB;
if (calc_val < 0)
return 1;
timing_data[MV_DDR_TRRD_S_MIN] = calc_val;
/* t rrd l min, ps */
calc_val = spd_data->byte_fields.byte_39 * MV_DDR_SPD_DATA_MTB +
(signed char)spd_data->byte_fields.byte_118 * MV_DDR_SPD_DATA_FTB;
if (calc_val < 0)
return 1;
timing_data[MV_DDR_TRRD_L_MIN] = calc_val;
/* t ccd l min, ps */
calc_val = spd_data->byte_fields.byte_40 * MV_DDR_SPD_DATA_MTB +
(signed char)spd_data->byte_fields.byte_117 * MV_DDR_SPD_DATA_FTB;
if (calc_val < 0)
return 1;
timing_data[MV_DDR_TCCD_L_MIN] = calc_val;
/* t faw min, ps */
timing_data[MV_DDR_TFAW_MIN] = (spd_data->byte_fields.byte_37 +
(spd_data->byte_fields.byte_36.bit_fields.t_faw_min_msn << MV_DDR_SPD_MSB_OFFS)) *
MV_DDR_SPD_DATA_MTB;
/* t wtr s min, ps */
timing_data[MV_DDR_TWTR_S_MIN] = (spd_data->byte_fields.byte_44 +
(spd_data->byte_fields.byte_43.bit_fields.t_wtr_s_min_msn << MV_DDR_SPD_MSB_OFFS)) *
MV_DDR_SPD_DATA_MTB;
/* t wtr l min, ps */
timing_data[MV_DDR_TWTR_L_MIN] = (spd_data->byte_fields.byte_45 +
(spd_data->byte_fields.byte_43.bit_fields.t_wtr_l_min_msn << MV_DDR_SPD_MSB_OFFS)) *
MV_DDR_SPD_DATA_MTB;
return 0;
}
enum mv_ddr_dev_width mv_ddr_spd_dev_width_get(union mv_ddr_spd_data *spd_data)
{
unsigned char dev_width = spd_data->byte_fields.byte_12.bit_fields.device_width;
enum mv_ddr_dev_width ret_val;
switch (dev_width) {
case 0x00:
ret_val = MV_DDR_DEV_WIDTH_4BIT;
break;
case 0x01:
ret_val = MV_DDR_DEV_WIDTH_8BIT;
break;
case 0x02:
ret_val = MV_DDR_DEV_WIDTH_16BIT;
break;
case 0x03:
ret_val = MV_DDR_DEV_WIDTH_32BIT;
break;
default:
ret_val = MV_DDR_DEV_WIDTH_LAST;
}
return ret_val;
}
enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data *spd_data)
{
unsigned char die_cap = spd_data->byte_fields.byte_4.bit_fields.die_capacity;
enum mv_ddr_die_capacity ret_val;
switch (die_cap) {
case 0x00:
ret_val = MV_DDR_DIE_CAP_256MBIT;
break;
case 0x01:
ret_val = MV_DDR_DIE_CAP_512MBIT;
break;
case 0x02:
ret_val = MV_DDR_DIE_CAP_1GBIT;
break;
case 0x03:
ret_val = MV_DDR_DIE_CAP_2GBIT;
break;
case 0x04:
ret_val = MV_DDR_DIE_CAP_4GBIT;
break;
case 0x05:
ret_val = MV_DDR_DIE_CAP_8GBIT;
break;
case 0x06:
ret_val = MV_DDR_DIE_CAP_16GBIT;
break;
case 0x07:
ret_val = MV_DDR_DIE_CAP_32GBIT;
break;
case 0x08:
ret_val = MV_DDR_DIE_CAP_12GBIT;
break;
case 0x09:
ret_val = MV_DDR_DIE_CAP_24GBIT;
break;
default:
ret_val = MV_DDR_DIE_CAP_LAST;
}
return ret_val;
}
unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data)
{
unsigned char mem_mirror = spd_data->byte_fields.byte_131.bit_fields.rank_1_mapping;
return mem_mirror;
}
enum mv_ddr_pkg_rank mv_ddr_spd_pri_bus_width_get(union mv_ddr_spd_data *spd_data)
{
unsigned char pri_bus_width = spd_data->byte_fields.byte_13.bit_fields.primary_bus_width;
enum mv_ddr_pri_bus_width ret_val;
switch (pri_bus_width) {
case 0x00:
ret_val = MV_DDR_PRI_BUS_WIDTH_8;
break;
case 0x01:
ret_val = MV_DDR_PRI_BUS_WIDTH_16;
break;
case 0x02:
ret_val = MV_DDR_PRI_BUS_WIDTH_32;
break;
case 0x03:
ret_val = MV_DDR_PRI_BUS_WIDTH_64;
break;
default:
ret_val = MV_DDR_PRI_BUS_WIDTH_LAST;
}
return ret_val;
}
enum mv_ddr_pkg_rank mv_ddr_spd_bus_width_ext_get(union mv_ddr_spd_data *spd_data)
{
unsigned char bus_width_ext = spd_data->byte_fields.byte_13.bit_fields.bus_width_ext;
enum mv_ddr_bus_width_ext ret_val;
switch (bus_width_ext) {
case 0x00:
ret_val = MV_DDR_BUS_WIDTH_EXT_0;
break;
case 0x01:
ret_val = MV_DDR_BUS_WIDTH_EXT_8;
break;
default:
ret_val = MV_DDR_BUS_WIDTH_EXT_LAST;
}
return ret_val;
}
static enum mv_ddr_pkg_rank mv_ddr_spd_pkg_rank_get(union mv_ddr_spd_data *spd_data)
{
unsigned char pkg_rank = spd_data->byte_fields.byte_12.bit_fields.dimm_pkg_ranks_num;
enum mv_ddr_pkg_rank ret_val;
switch (pkg_rank) {
case 0x00:
ret_val = MV_DDR_PKG_RANK_1;
break;
case 0x01:
ret_val = MV_DDR_PKG_RANK_2;
break;
case 0x02:
ret_val = MV_DDR_PKG_RANK_3;
break;
case 0x03:
ret_val = MV_DDR_PKG_RANK_4;
break;
case 0x04:
ret_val = MV_DDR_PKG_RANK_5;
break;
case 0x05:
ret_val = MV_DDR_PKG_RANK_6;
break;
case 0x06:
ret_val = MV_DDR_PKG_RANK_7;
break;
case 0x07:
ret_val = MV_DDR_PKG_RANK_8;
break;
default:
ret_val = MV_DDR_PKG_RANK_LAST;
}
return ret_val;
}
static enum mv_ddr_die_count mv_ddr_spd_die_count_get(union mv_ddr_spd_data *spd_data)
{
unsigned char die_count = spd_data->byte_fields.byte_6.bit_fields.die_count;
enum mv_ddr_die_count ret_val;
switch (die_count) {
case 0x00:
ret_val = MV_DDR_DIE_CNT_1;
break;
case 0x01:
ret_val = MV_DDR_DIE_CNT_2;
break;
case 0x02:
ret_val = MV_DDR_DIE_CNT_3;
break;
case 0x03:
ret_val = MV_DDR_DIE_CNT_4;
break;
case 0x04:
ret_val = MV_DDR_DIE_CNT_5;
break;
case 0x05:
ret_val = MV_DDR_DIE_CNT_6;
break;
case 0x06:
ret_val = MV_DDR_DIE_CNT_7;
break;
case 0x07:
ret_val = MV_DDR_DIE_CNT_8;
break;
default:
ret_val = MV_DDR_DIE_CNT_LAST;
}
return ret_val;
}
unsigned char mv_ddr_spd_cs_bit_mask_get(union mv_ddr_spd_data *spd_data)
{
unsigned char cs_bit_mask = 0x0;
enum mv_ddr_pkg_rank pkg_rank = mv_ddr_spd_pkg_rank_get(spd_data);
enum mv_ddr_die_count die_cnt = mv_ddr_spd_die_count_get(spd_data);
if (pkg_rank == MV_DDR_PKG_RANK_1 && die_cnt == MV_DDR_DIE_CNT_1)
cs_bit_mask = 0x1;
else if (pkg_rank == MV_DDR_PKG_RANK_1 && die_cnt == MV_DDR_DIE_CNT_2)
cs_bit_mask = 0x3;
else if (pkg_rank == MV_DDR_PKG_RANK_2 && die_cnt == MV_DDR_DIE_CNT_1)
cs_bit_mask = 0x3;
else if (pkg_rank == MV_DDR_PKG_RANK_2 && die_cnt == MV_DDR_DIE_CNT_2)
cs_bit_mask = 0xf;
return cs_bit_mask;
}
unsigned char mv_ddr_spd_dev_type_get(union mv_ddr_spd_data *spd_data)
{
unsigned char dev_type = spd_data->byte_fields.byte_2;
return dev_type;
}
unsigned char mv_ddr_spd_module_type_get(union mv_ddr_spd_data *spd_data)
{
unsigned char module_type = spd_data->byte_fields.byte_3.bit_fields.module_type;
return module_type;
}
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/mv_ddr_spd.h
+289
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _MV_DDR_SPD_H
#define _MV_DDR_SPD_H
#include "mv_ddr_topology.h"
/*
* Based on JEDEC Standard No. 21-C, 4.1.2.L-4:
* Serial Presence Detect (SPD) for DDR4 SDRAM Modules
*/
/* block 0: base configuration and dram parameters */
#define MV_DDR_SPD_DATA_BLOCK0_SIZE 128
/* block 1: module specific parameters sub-block */
#define MV_DDR_SPD_DATA_BLOCK1M_SIZE 64
/* block 1: hybrid memory parameters sub-block */
#define MV_DDR_SPD_DATA_BLOCK1H_SIZE 64
/* block 2: extended function parameter block */
#define MV_DDR_SPD_DATA_BLOCK2E_SIZE 64
/* block 2: manufacturing information */
#define MV_DDR_SPD_DATA_BLOCK2M_SIZE 64
/* block 3: end user programmable */
#define MV_DDR_SPD_DATA_BLOCK3_SIZE 128
#define MV_DDR_SPD_DEV_TYPE_DDR4 0xc
#define MV_DDR_SPD_MODULE_TYPE_UDIMM 0x2
#define MV_DDR_SPD_MODULE_TYPE_SO_DIMM 0x3
#define MV_DDR_SPD_MODULE_TYPE_MINI_UDIMM 0x6
#define MV_DDR_SPD_MODULE_TYPE_72BIT_SO_UDIMM 0x9
#define MV_DDR_SPD_MODULE_TYPE_16BIT_SO_DIMM 0xc
#define MV_DDR_SPD_MODULE_TYPE_32BIT_SO_DIMM 0xd
/*
* TODO: For now, the struct contains block 0 & block 1 with module specific
* parameters for unbuffered memory module types only.
*/
union mv_ddr_spd_data {
unsigned char all_bytes[MV_DDR_SPD_DATA_BLOCK0_SIZE +
MV_DDR_SPD_DATA_BLOCK1M_SIZE];
struct {
/* block 0 */
union { /* num of bytes used/num of bytes in spd device/crc coverage */
unsigned char all_bits;
struct {
unsigned char spd_bytes_used:4,
spd_bytes_total:3,
reserved:1;
} bit_fields;
} byte_0;
union { /* spd revision */
unsigned char all_bits;
struct {
unsigned char addtions_level:4,
encoding_level:4;
} bit_fields;
} byte_1;
unsigned char byte_2; /* key_byte/dram device type */
union { /* key byte/module type */
unsigned char all_bits;
struct {
unsigned char module_type:4,
hybrid_media:3,
hybrid:1;
} bit_fields;
} byte_3;
union { /* sdram density & banks */
unsigned char all_bits;
struct {
unsigned char die_capacity:4,
bank_address:2,
bank_group:2;
} bit_fields;
} byte_4;
union { /* sdram addressing */
unsigned char all_bits;
struct {
unsigned char col_address:3,
row_address:3,
reserved:2;
} bit_fields;
} byte_5;
union { /* sdram package type */
unsigned char all_bits;
struct {
unsigned char signal_loading:2,
reserved:2,
die_count:3,
sdram_package_type:1;
} bit_fields;
} byte_6;
union { /* sdram optional features */
unsigned char all_bits;
struct {
unsigned char mac:4, /* max activate count */
t_maw:2, /* max activate window */
reserved:2; /* all 0s */
} bit_fields;
} byte_7;
unsigned char byte_8; /* sdram thermal & refresh options; reserved; 0x00 */
union { /* other sdram optional features */
unsigned char all_bits;
struct {
unsigned char reserved:5, /* all 0s */
soft_ppr:1,
ppr:2; /* post package repair */
} bit_fields;
} byte_9;
union { /* secondary sdram package type */
unsigned char all_bits;
struct {
unsigned char signal_loading:2,
density_ratio:2, /* dram density ratio */
die_count:3,
sdram_package_type:1;
} bit_fields;
} byte_10;
union { /* module nominal voltage, vdd */
unsigned char all_bits;
struct {
unsigned char operable:1,
endurant:1,
reserved:5; /* all 0s */
} bit_fields;
} byte_11;
union { /* module organization*/
unsigned char all_bits;
struct {
unsigned char device_width:3,
dimm_pkg_ranks_num:3, /* package ranks per dimm number */
rank_mix:1,
reserved:1; /* 0 */
} bit_fields;
} byte_12;
union { /* module memory bus width */
unsigned char all_bits;
struct {
unsigned char primary_bus_width:3, /* in bits */
bus_width_ext:2, /* in bits */
reserved:3; /* all 0s */
} bit_fields;
} byte_13;
union { /* module thernal sensor */
unsigned char all_bits;
struct {
unsigned char reserved:7,
thermal_sensor:1;
} bit_fields;
} byte_14;
union { /* extended module type */
unsigned char all_bits;
struct {
unsigned char ext_base_module_type:4,
reserved:4; /* all 0s */
} bit_fields;
} byte_15;
unsigned char byte_16; /* reserved; 0x00 */
union { /* timebases */
unsigned char all_bits;
struct {
unsigned char ftb:2, /* fine timebase */
mtb:2, /* medium timebase */
reserved:4; /* all 0s */
} bit_fields;
} byte_17;
unsigned char byte_18; /* sdram min cycle time (t ck avg min), mtb */
unsigned char byte_19; /* sdram max cycle time (t ck avg max), mtb */
unsigned char byte_20; /* cas latencies supported, first byte */
unsigned char byte_21; /* cas latencies supported, second byte */
unsigned char byte_22; /* cas latencies supported, third byte */
unsigned char byte_23; /* cas latencies supported, fourth byte */
unsigned char byte_24; /* min cas latency time (t aa min), mtb */
unsigned char byte_25; /* min ras to cas delay time (t rcd min), mtb */
unsigned char byte_26; /* min row precharge delay time (t rp min), mtb */
union { /* upper nibbles for t ras min & t rc min */
unsigned char all_bits;
struct {
unsigned char t_ras_min_msn:4, /* t ras min most significant nibble */
t_rc_min_msn:4; /* t rc min most significant nibble */
} bit_fields;
} byte_27;
unsigned char byte_28; /* min active to precharge delay time (t ras min), l-s-byte, mtb */
unsigned char byte_29; /* min active to active/refresh delay time (t rc min), l-s-byte, mtb */
unsigned char byte_30; /* min refresh recovery delay time (t rfc1 min), l-s-byte, mtb */
unsigned char byte_31; /* min refresh recovery delay time (t rfc1 min), m-s-byte, mtb */
unsigned char byte_32; /* min refresh recovery delay time (t rfc2 min), l-s-byte, mtb */
unsigned char byte_33; /* min refresh recovery delay time (t rfc2 min), m-s-byte, mtb */
unsigned char byte_34; /* min refresh recovery delay time (t rfc4 min), l-s-byte, mtb */
unsigned char byte_35; /* min refresh recovery delay time (t rfc4 min), m-s-byte, mtb */
union { /* upper nibble for t faw */
unsigned char all_bits;
struct {
unsigned char t_faw_min_msn:4, /* t faw min most significant nibble */
reserved:4;
} bit_fields;
} byte_36;
unsigned char byte_37; /* min four activate window delay time (t faw min), l-s-byte, mtb */
/* byte 38: min activate to activate delay time (t rrd_s min), diff bank group, mtb */
unsigned char byte_38;
/* byte 39: min activate to activate delay time (t rrd_l min), same bank group, mtb */
unsigned char byte_39;
unsigned char byte_40; /* min cas to cas delay time (t ccd_l min), same bank group, mtb */
union { /* upper nibble for t wr min */
unsigned char all_bits;
struct {
unsigned char t_wr_min_msn:4, /* t wr min most significant nibble */
reserved:4;
} bit_fields;
} byte_41;
unsigned char byte_42; /* min write recovery time (t wr min) */
union { /* upper nibbles for t wtr min */
unsigned char all_bits;
struct {
unsigned char t_wtr_s_min_msn:4, /* t wtr s min most significant nibble */
t_wtr_l_min_msn:4; /* t wtr l min most significant nibble */
} bit_fields;
} byte_43;
unsigned char byte_44; /* min write to read time (t wtr s min), diff bank group, mtb */
unsigned char byte_45; /* min write to read time (t wtr l min), same bank group, mtb */
unsigned char bytes_46_59[14]; /* reserved; all 0s */
unsigned char bytes_60_77[18]; /* TODO: connector to sdram bit mapping */
unsigned char bytes_78_116[39]; /* reserved; all 0s */
/* fine offset for min cas to cas delay time (t ccd_l min), same bank group, ftb */
unsigned char byte_117;
/* fine offset for min activate to activate delay time (t rrd_l min), same bank group, ftb */
unsigned char byte_118;
/* fine offset for min activate to activate delay time (t rrd_s min), diff bank group, ftb */
unsigned char byte_119;
/* fine offset for min active to active/refresh delay time (t rc min), ftb */
unsigned char byte_120;
unsigned char byte_121; /* fine offset for min row precharge delay time (t rp min), ftb */
unsigned char byte_122; /* fine offset for min ras to cas delay time (t rcd min), ftb */
unsigned char byte_123; /* fine offset for min cas latency time (t aa min), ftb */
unsigned char byte_124; /* fine offset for sdram max cycle time (t ck avg max), ftb */
unsigned char byte_125; /* fine offset for sdram min cycle time (t ck avg min), ftb */
unsigned char byte_126; /* crc for base configuration section, l-s-byte */
unsigned char byte_127; /* crc for base configuration section, m-s-byte */
/*
* block 1: module specific parameters for unbuffered memory module types only
*/
union { /* (unbuffered) raw card extension, module nominal height */
unsigned char all_bits;
struct {
unsigned char nom_height_max:5, /* in mm */
raw_cad_ext:3;
} bit_fields;
} byte_128;
union { /* (unbuffered) module maximum thickness */
unsigned char all_bits;
struct {
unsigned char front_thickness_max:4, /* in mm */
back_thickness_max:4; /* in mm */
} bit_fields;
} byte_129;
union { /* (unbuffered) reference raw card used */
unsigned char all_bits;
struct {
unsigned char ref_raw_card:5,
ref_raw_card_rev:2,
ref_raw_card_ext:1;
} bit_fields;
} byte_130;
union { /* (unbuffered) address mapping from edge connector to dram */
unsigned char all_bits;
struct {
unsigned char rank_1_mapping:1,
reserved:7;
} bit_fields;
} byte_131;
unsigned char bytes_132_191[60]; /* reserved; all 0s */
} byte_fields;
};
int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_data[]);
enum mv_ddr_dev_width mv_ddr_spd_dev_width_get(union mv_ddr_spd_data *spd_data);
enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data *spd_data);
unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data);
unsigned char mv_ddr_spd_cs_bit_mask_get(union mv_ddr_spd_data *spd_data);
unsigned char mv_ddr_spd_dev_type_get(union mv_ddr_spd_data *spd_data);
unsigned char mv_ddr_spd_module_type_get(union mv_ddr_spd_data *spd_data);
int mv_ddr_spd_supported_cls_calc(union mv_ddr_spd_data *spd_data);
unsigned int mv_ddr_spd_supported_cl_get(unsigned int cl);
enum mv_ddr_pkg_rank mv_ddr_spd_pri_bus_width_get(union mv_ddr_spd_data *spd_data);
enum mv_ddr_pkg_rank mv_ddr_spd_bus_width_ext_get(union mv_ddr_spd_data *spd_data);
#endif /* _MV_DDR_SPD_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.c
+102
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#include "mv_ddr_regs.h"
#include "mv_ddr_sys_env_lib.h"
static u32 mv_ddr_board_id_get(void)
{
#if defined(CONFIG_TARGET_DB_88F6820_GP)
return DB_GP_68XX_ID;
#else
/*
* Return 0 here for custom board as this should not be used
* for custom boards.
*/
return 0;
#endif
}
static u32 mv_ddr_board_id_index_get(u32 board_id)
{
/*
* Marvell Boards use 0x10 as base for Board ID:
* mask MSB to receive index for board ID
*/
return board_id & (MARVELL_BOARD_ID_MASK - 1);
}
/*
* read gpio input for suspend-wakeup indication
* return indicating suspend wakeup status:
* 0 - not supported,
* 1 - supported: read magic word detect wakeup,
* 2 - detected wakeup from gpio
*/
enum suspend_wakeup_status mv_ddr_sys_env_suspend_wakeup_check(void)
{
u32 reg, board_id_index, gpio;
struct board_wakeup_gpio board_gpio[] = MV_BOARD_WAKEUP_GPIO_INFO;
board_id_index = mv_ddr_board_id_index_get(mv_ddr_board_id_get());
if (!(sizeof(board_gpio) / sizeof(struct board_wakeup_gpio) >
board_id_index)) {
printf("\n_failed loading Suspend-Wakeup information (invalid board ID)\n");
return SUSPEND_WAKEUP_DISABLED;
}
/*
* - Detect if Suspend-Wakeup is supported on current board
* - Fetch the GPIO number for wakeup status input indication
*/
if (board_gpio[board_id_index].gpio_num == -1) {
/* Suspend to RAM is not supported */
return SUSPEND_WAKEUP_DISABLED;
} else if (board_gpio[board_id_index].gpio_num == -2) {
/*
* Suspend to RAM is supported but GPIO indication is
* not implemented - Skip
*/
return SUSPEND_WAKEUP_ENABLED;
} else {
gpio = board_gpio[board_id_index].gpio_num;
}
/* Initialize MPP for GPIO (set MPP = 0x0) */
reg = reg_read(MPP_CONTROL_REG(MPP_REG_NUM(gpio)));
/* reset MPP21 to 0x0, keep rest of MPP settings*/
reg &= ~MPP_MASK(gpio);
reg_write(MPP_CONTROL_REG(MPP_REG_NUM(gpio)), reg);
/* Initialize GPIO as input */
reg = reg_read(GPP_DATA_OUT_EN_REG(GPP_REG_NUM(gpio)));
reg |= GPP_MASK(gpio);
reg_write(GPP_DATA_OUT_EN_REG(GPP_REG_NUM(gpio)), reg);
/*
* Check GPP for input status from PIC: 0 - regular init,
* 1 - suspend wakeup
*/
reg = reg_read(GPP_DATA_IN_REG(GPP_REG_NUM(gpio)));
/* if GPIO is ON: wakeup from S2RAM indication detected */
return (reg & GPP_MASK(gpio)) ? SUSPEND_WAKEUP_ENABLED_GPIO_DETECTED :
SUSPEND_WAKEUP_DISABLED;
}
/*
* get bit mask of enabled cs
* return bit mask of enabled cs:
* 1 - only cs0 enabled,
* 3 - both cs0 and cs1 enabled
*/
u32 mv_ddr_sys_env_get_cs_ena_from_reg(void)
{
return reg_read(DDR3_RANK_CTRL_REG) &
((CS_EXIST_MASK << CS_EXIST_OFFS(0)) |
(CS_EXIST_MASK << CS_EXIST_OFFS(1)) |
(CS_EXIST_MASK << CS_EXIST_OFFS(2)) |
(CS_EXIST_MASK << CS_EXIST_OFFS(3)));
}
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h
+117
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _MV_DDR_SYS_ENV_LIB_H
#define _MV_DDR_SYS_ENV_LIB_H
#include "ddr_ml_wrapper.h"
/* device revision */
#define DEV_ID_REG 0x18238
#define DEV_VERSION_ID_REG 0x1823c
#define REVISON_ID_OFFS 8
#define REVISON_ID_MASK 0xf00
#define MPP_CONTROL_REG(id) (0x18000 + (id * 4))
#define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00)
#define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04)
#define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10)
#define MV_GPP_REGS_BASE(unit) (0x18100 + ((unit) * 0x40))
#define MPP_REG_NUM(GPIO_NUM) (GPIO_NUM / 8)
#define MPP_MASK(GPIO_NUM) (0xf << 4 * (GPIO_NUM - \
(MPP_REG_NUM(GPIO_NUM) * 8)));
#define GPP_REG_NUM(GPIO_NUM) (GPIO_NUM / 32)
#define GPP_MASK(GPIO_NUM) (1 << GPIO_NUM % 32)
/* device ID */
/* Board ID numbers */
#define MARVELL_BOARD_ID_MASK 0x10
/* Customer boards for A38x */
#define A38X_CUSTOMER_BOARD_ID_BASE 0x0
#define A38X_CUSTOMER_BOARD_ID0 (A38X_CUSTOMER_BOARD_ID_BASE + 0)
#define A38X_CUSTOMER_BOARD_ID1 (A38X_CUSTOMER_BOARD_ID_BASE + 1)
#define A38X_MV_MAX_CUSTOMER_BOARD_ID (A38X_CUSTOMER_BOARD_ID_BASE + 2)
#define A38X_MV_CUSTOMER_BOARD_NUM (A38X_MV_MAX_CUSTOMER_BOARD_ID - \
A38X_CUSTOMER_BOARD_ID_BASE)
/* Marvell boards for A38x */
#define A38X_MARVELL_BOARD_ID_BASE 0x10
#define RD_NAS_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 0)
#define DB_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 1)
#define RD_AP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 2)
#define DB_AP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 3)
#define DB_GP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 4)
#define DB_BP_6821_ID (A38X_MARVELL_BOARD_ID_BASE + 5)
#define DB_AMC_6820_ID (A38X_MARVELL_BOARD_ID_BASE + 6)
#define A38X_MV_MAX_MARVELL_BOARD_ID (A38X_MARVELL_BOARD_ID_BASE + 7)
#define A38X_MV_MARVELL_BOARD_NUM (A38X_MV_MAX_MARVELL_BOARD_ID - \
A38X_MARVELL_BOARD_ID_BASE)
/* Marvell boards for A39x */
#define A39X_MARVELL_BOARD_ID_BASE 0x30
#define A39X_DB_69XX_ID (A39X_MARVELL_BOARD_ID_BASE + 0)
#define A39X_RD_69XX_ID (A39X_MARVELL_BOARD_ID_BASE + 1)
#define A39X_MV_MAX_MARVELL_BOARD_ID (A39X_MARVELL_BOARD_ID_BASE + 2)
#define A39X_MV_MARVELL_BOARD_NUM (A39X_MV_MAX_MARVELL_BOARD_ID - \
A39X_MARVELL_BOARD_ID_BASE)
struct board_wakeup_gpio {
u32 board_id;
int gpio_num;
};
enum suspend_wakeup_status {
SUSPEND_WAKEUP_DISABLED,
SUSPEND_WAKEUP_ENABLED,
SUSPEND_WAKEUP_ENABLED_GPIO_DETECTED,
};
/*
* GPIO status indication for Suspend Wakeup:
* If suspend to RAM is supported and GPIO inidcation is implemented,
* set the gpio number
* If suspend to RAM is supported but GPIO indication is not implemented
* set '-2'
* If suspend to RAM is not supported set '-1'
*/
#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
#ifdef CONFIG_ARMADA_38X
#define MV_BOARD_WAKEUP_GPIO_INFO { \
{A38X_CUSTOMER_BOARD_ID0, -1 }, \
{A38X_CUSTOMER_BOARD_ID0, -1 }, \
};
#else
#define MV_BOARD_WAKEUP_GPIO_INFO { \
{A39X_CUSTOMER_BOARD_ID0, -1 }, \
{A39X_CUSTOMER_BOARD_ID0, -1 }, \
};
#endif /* CONFIG_ARMADA_38X */
#else
#ifdef CONFIG_ARMADA_38X
#define MV_BOARD_WAKEUP_GPIO_INFO { \
{RD_NAS_68XX_ID, -2 }, \
{DB_68XX_ID, -1 }, \
{RD_AP_68XX_ID, -2 }, \
{DB_AP_68XX_ID, -2 }, \
{DB_GP_68XX_ID, -2 }, \
{DB_BP_6821_ID, -2 }, \
{DB_AMC_6820_ID, -2 }, \
};
#else
#define MV_BOARD_WAKEUP_GPIO_INFO { \
{A39X_RD_69XX_ID, -1 }, \
{A39X_DB_69XX_ID, -1 }, \
};
#endif /* CONFIG_ARMADA_38X */
#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */
enum suspend_wakeup_status mv_ddr_sys_env_suspend_wakeup_check(void);
u32 mv_ddr_sys_env_get_cs_ena_from_reg(void);
#endif /* _MV_DDR_SYS_ENV_LIB_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/mv_ddr_topology.c
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#include "ddr_ml_wrapper.h"
#include "mv_ddr_plat.h"
#include "mv_ddr_topology.h"
#include "mv_ddr_common.h"
#include "mv_ddr_spd.h"
#include "ddr_topology_def.h"
#include "ddr3_training_ip_db.h"
#include "ddr3_training_ip.h"
#include "mv_ddr_training_db.h"
unsigned int mv_ddr_cl_calc(unsigned int taa_min, unsigned int tclk)
{
unsigned int cl = ceil_div(taa_min, tclk);
return mv_ddr_spd_supported_cl_get(cl);
}
unsigned int mv_ddr_cwl_calc(unsigned int tclk)
{
unsigned int cwl;
if (tclk >= 1250)
cwl = 9;
else if (tclk >= 1071)
cwl = 10;
else if (tclk >= 938)
cwl = 11;
else if (tclk >= 833)
cwl = 12;
else if (tclk >= 750)
cwl = 14;
else if (tclk >= 625)
cwl = 16;
else
cwl = 0;
return cwl;
}
int mv_ddr_topology_map_update(void)
{
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
struct if_params *iface_params = &(tm->interface_params[0]);
unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
enum mv_ddr_speed_bin speed_bin_index;
enum mv_ddr_freq freq = MV_DDR_FREQ_LAST;
unsigned int tclk;
unsigned char val = 0;
int i;
if (iface_params->memory_freq == MV_DDR_FREQ_SAR)
iface_params->memory_freq = mv_ddr_init_freq_get();
if (tm->cfg_src == MV_DDR_CFG_SPD) {
/* check dram device type */
val = mv_ddr_spd_dev_type_get(&tm->spd_data);
if (val != MV_DDR_SPD_DEV_TYPE_DDR4) {
printf("mv_ddr: unsupported dram device type found\n");
return -1;
}
/* update topology map with timing data */
if (mv_ddr_spd_timing_calc(&tm->spd_data, tm->timing_data) > 0) {
printf("mv_ddr: negative timing data found\n");
return -1;
}
/* update device width in topology map */
iface_params->bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data);
/* update die capacity in topology map */
iface_params->memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data);
/* update bus bit mask in topology map */
tm->bus_act_mask = mv_ddr_bus_bit_mask_get();
/* update cs bit mask in topology map */
val = mv_ddr_spd_cs_bit_mask_get(&tm->spd_data);
for (i = 0; i < octets_per_if_num; i++)
iface_params->as_bus_params[i].cs_bitmask = val;
/* check dram module type */
val = mv_ddr_spd_module_type_get(&tm->spd_data);
switch (val) {
case MV_DDR_SPD_MODULE_TYPE_UDIMM:
case MV_DDR_SPD_MODULE_TYPE_SO_DIMM:
case MV_DDR_SPD_MODULE_TYPE_MINI_UDIMM:
case MV_DDR_SPD_MODULE_TYPE_72BIT_SO_UDIMM:
case MV_DDR_SPD_MODULE_TYPE_16BIT_SO_DIMM:
case MV_DDR_SPD_MODULE_TYPE_32BIT_SO_DIMM:
break;
default:
printf("mv_ddr: unsupported dram module type found\n");
return -1;
}
/* update mirror bit mask in topology map */
val = mv_ddr_spd_mem_mirror_get(&tm->spd_data);
for (i = 0; i < octets_per_if_num; i++)
iface_params->as_bus_params[i].mirror_enable_bitmask = val << 1;
tclk = 1000000 / mv_ddr_freq_get(iface_params->memory_freq);
/* update cas write latency (cwl) */
val = mv_ddr_cwl_calc(tclk);
if (val == 0) {
printf("mv_ddr: unsupported cas write latency value found\n");
return -1;
}
iface_params->cas_wl = val;
/* update cas latency (cl) */
mv_ddr_spd_supported_cls_calc(&tm->spd_data);
val = mv_ddr_cl_calc(tm->timing_data[MV_DDR_TAA_MIN], tclk);
if (val == 0) {
printf("mv_ddr: unsupported cas latency value found\n");
return -1;
}
iface_params->cas_l = val;
} else if (tm->cfg_src == MV_DDR_CFG_DEFAULT) {
/* set cas and cas-write latencies per speed bin, if they unset */
speed_bin_index = iface_params->speed_bin_index;
freq = iface_params->memory_freq;
if (iface_params->cas_l == 0)
iface_params->cas_l = mv_ddr_cl_val_get(speed_bin_index, freq);
if (iface_params->cas_wl == 0)
iface_params->cas_wl = mv_ddr_cwl_val_get(speed_bin_index, freq);
}
return 0;
}
unsigned short mv_ddr_bus_bit_mask_get(void)
{
unsigned short pri_and_ext_bus_width = 0x0;
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
if (tm->cfg_src == MV_DDR_CFG_SPD) {
enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data);
enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data);
switch (pri_bus_width) {
case MV_DDR_PRI_BUS_WIDTH_16:
pri_and_ext_bus_width = BUS_MASK_16BIT;
break;
case MV_DDR_PRI_BUS_WIDTH_32:
pri_and_ext_bus_width = BUS_MASK_32BIT;
break;
case MV_DDR_PRI_BUS_WIDTH_64:
pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK;
break;
default:
pri_and_ext_bus_width = 0x0;
}
if (bus_width_ext == MV_DDR_BUS_WIDTH_EXT_8)
pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1);
}
return pri_and_ext_bus_width;
}
unsigned int mv_ddr_if_bus_width_get(void)
{
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
unsigned int bus_width;
switch (tm->bus_act_mask) {
case BUS_MASK_16BIT:
case BUS_MASK_16BIT_ECC:
case BUS_MASK_16BIT_ECC_PUP3:
bus_width = 16;
break;
case BUS_MASK_32BIT:
case BUS_MASK_32BIT_ECC:
case MV_DDR_32BIT_ECC_PUP8_BUS_MASK:
bus_width = 32;
break;
case MV_DDR_64BIT_BUS_MASK:
case MV_DDR_64BIT_ECC_PUP8_BUS_MASK:
bus_width = 64;
break;
default:
printf("mv_ddr: unsupported bus active mask parameter found\n");
bus_width = 0;
}
return bus_width;
}
unsigned int mv_ddr_cs_num_get(void)
{
unsigned int cs_num = 0;
unsigned int cs, sphy;
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
struct if_params *iface_params = &(tm->interface_params[0]);
unsigned int sphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
for (sphy = 0; sphy < sphy_max; sphy++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sphy);
break;
}
for (cs = 0; cs < MAX_CS_NUM; cs++) {
VALIDATE_ACTIVE(iface_params->as_bus_params[sphy].cs_bitmask, cs);
cs_num++;
}
return cs_num;
}
int mv_ddr_is_ecc_ena(void)
{
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask) ||
DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask) ||
DDR3_IS_ECC_PUP8_MODE(tm->bus_act_mask))
return 1;
else
return 0;
}
/* translate topology map definition to real memory size in bits */
static unsigned int mem_size[] = {
ADDR_SIZE_512MB,
ADDR_SIZE_1GB,
ADDR_SIZE_2GB,
ADDR_SIZE_4GB,
ADDR_SIZE_8GB
/* TODO: add capacity up to 256GB */
};
unsigned long long mv_ddr_mem_sz_per_cs_get(void)
{
unsigned long long mem_sz_per_cs;
unsigned int i, sphys, sphys_per_dunit;
unsigned int sphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
struct if_params *iface_params = &(tm->interface_params[0]);
/* calc number of active subphys excl. ecc one */
for (i = 0, sphys = 0; i < sphy_max - 1; i++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, i);
sphys++;
}
/* calc number of subphys per ddr unit */
if (iface_params->bus_width == MV_DDR_DEV_WIDTH_8BIT)
sphys_per_dunit = MV_DDR_ONE_SPHY_PER_DUNIT;
else if (iface_params->bus_width == MV_DDR_DEV_WIDTH_16BIT)
sphys_per_dunit = MV_DDR_TWO_SPHY_PER_DUNIT;
else {
printf("mv_ddr: unsupported bus width type found\n");
return 0;
}
/* calc dram size per cs */
mem_sz_per_cs = (unsigned long long)mem_size[iface_params->memory_size] *
(unsigned long long)sphys /
(unsigned long long)sphys_per_dunit;
return mem_sz_per_cs;
}
unsigned long long mv_ddr_mem_sz_get(void)
{
unsigned long long tot_mem_sz = 0;
unsigned long long mem_sz_per_cs = 0;
unsigned long long max_cs = mv_ddr_cs_num_get();
mem_sz_per_cs = mv_ddr_mem_sz_per_cs_get();
tot_mem_sz = max_cs * mem_sz_per_cs;
return tot_mem_sz;
}
unsigned int mv_ddr_rtt_nom_get(void)
{
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
unsigned int rtt_nom = tm->edata.mem_edata.rtt_nom;
if (rtt_nom >= MV_DDR_RTT_NOM_PARK_RZQ_LAST) {
printf("error: %s: unsupported rtt_nom parameter found\n", __func__);
rtt_nom = PARAM_UNDEFINED;
}
return rtt_nom;
}
unsigned int mv_ddr_rtt_park_get(void)
{
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
unsigned int cs_num = mv_ddr_cs_num_get();
unsigned int rtt_park = MV_DDR_RTT_NOM_PARK_RZQ_LAST;
if (cs_num > 0 && cs_num <= MAX_CS_NUM)
rtt_park = tm->edata.mem_edata.rtt_park[cs_num - 1];
if (rtt_park >= MV_DDR_RTT_NOM_PARK_RZQ_LAST) {
printf("error: %s: unsupported rtt_park parameter found\n", __func__);
rtt_park = PARAM_UNDEFINED;
}
return rtt_park;
}
unsigned int mv_ddr_rtt_wr_get(void)
{
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
unsigned int cs_num = mv_ddr_cs_num_get();
unsigned int rtt_wr = MV_DDR_RTT_WR_RZQ_LAST;
if (cs_num > 0 && cs_num <= MAX_CS_NUM)
rtt_wr = tm->edata.mem_edata.rtt_wr[cs_num - 1];
if (rtt_wr >= MV_DDR_RTT_WR_RZQ_LAST) {
printf("error: %s: unsupported rtt_wr parameter found\n", __func__);
rtt_wr = PARAM_UNDEFINED;
}
return rtt_wr;
}
unsigned int mv_ddr_dic_get(void)
{
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
unsigned int dic = tm->edata.mem_edata.dic;
if (dic >= MV_DDR_DIC_RZQ_LAST) {
printf("error: %s: unsupported dic parameter found\n", __func__);
dic = PARAM_UNDEFINED;
}
return dic;
}
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/mv_ddr_topology.h
+329
View File
@@ -0,0 +1,329 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _MV_DDR_TOPOLOGY_H
#define _MV_DDR_TOPOLOGY_H
#define MAX_CS_NUM 4
enum mv_ddr_speed_bin {
SPEED_BIN_DDR_800D,
SPEED_BIN_DDR_800E,
SPEED_BIN_DDR_1066E,
SPEED_BIN_DDR_1066F,
SPEED_BIN_DDR_1066G,
SPEED_BIN_DDR_1333F,
SPEED_BIN_DDR_1333G,
SPEED_BIN_DDR_1333H,
SPEED_BIN_DDR_1333J,
SPEED_BIN_DDR_1600G,
SPEED_BIN_DDR_1600H,
SPEED_BIN_DDR_1600J,
SPEED_BIN_DDR_1600K,
SPEED_BIN_DDR_1866J,
SPEED_BIN_DDR_1866K,
SPEED_BIN_DDR_1866L,
SPEED_BIN_DDR_1866M,
SPEED_BIN_DDR_2133K,
SPEED_BIN_DDR_2133L,
SPEED_BIN_DDR_2133M,
SPEED_BIN_DDR_2133N,
SPEED_BIN_DDR_1333H_EXT,
SPEED_BIN_DDR_1600K_EXT,
SPEED_BIN_DDR_1866M_EXT
};
enum mv_ddr_freq {
MV_DDR_FREQ_LOW_FREQ,
MV_DDR_FREQ_400,
MV_DDR_FREQ_533,
MV_DDR_FREQ_667,
MV_DDR_FREQ_800,
MV_DDR_FREQ_933,
MV_DDR_FREQ_1066,
MV_DDR_FREQ_311,
MV_DDR_FREQ_333,
MV_DDR_FREQ_467,
MV_DDR_FREQ_850,
MV_DDR_FREQ_600,
MV_DDR_FREQ_300,
MV_DDR_FREQ_900,
MV_DDR_FREQ_360,
MV_DDR_FREQ_1000,
MV_DDR_FREQ_LAST,
MV_DDR_FREQ_SAR
};
enum mv_ddr_speed_bin_timing {
SPEED_BIN_TRCD,
SPEED_BIN_TRP,
SPEED_BIN_TRAS,
SPEED_BIN_TRC,
SPEED_BIN_TRRD1K,
SPEED_BIN_TRRD2K,
SPEED_BIN_TPD,
SPEED_BIN_TFAW1K,
SPEED_BIN_TFAW2K,
SPEED_BIN_TWTR,
SPEED_BIN_TRTP,
SPEED_BIN_TWR,
SPEED_BIN_TMOD,
SPEED_BIN_TXPDLL,
SPEED_BIN_TXSDLL
};
/* ddr bus masks */
#define BUS_MASK_32BIT 0xf
#define BUS_MASK_32BIT_ECC 0x1f
#define BUS_MASK_16BIT 0x3
#define BUS_MASK_16BIT_ECC 0x13
#define BUS_MASK_16BIT_ECC_PUP3 0xb
#define MV_DDR_64BIT_BUS_MASK 0xff
#define MV_DDR_64BIT_ECC_PUP8_BUS_MASK 0x1ff
#define MV_DDR_32BIT_ECC_PUP8_BUS_MASK 0x10f
#define MV_DDR_CS_BITMASK_1CS 0x1
#define MV_DDR_CS_BITMASK_2CS 0x3
#define MV_DDR_ONE_SPHY_PER_DUNIT 1
#define MV_DDR_TWO_SPHY_PER_DUNIT 2
/* source of ddr configuration data */
enum mv_ddr_cfg_src {
MV_DDR_CFG_DEFAULT, /* based on data in mv_ddr_topology_map structure */
MV_DDR_CFG_SPD, /* based on data in spd */
MV_DDR_CFG_USER, /* based on data from user */
MV_DDR_CFG_STATIC, /* based on data from user in register-value format */
MV_DDR_CFG_LAST
};
enum mv_ddr_temperature {
MV_DDR_TEMP_LOW,
MV_DDR_TEMP_NORMAL,
MV_DDR_TEMP_HIGH
};
enum mv_ddr_timing {
MV_DDR_TIM_DEFAULT,
MV_DDR_TIM_1T,
MV_DDR_TIM_2T
};
enum mv_ddr_timing_data {
MV_DDR_TCK_AVG_MIN, /* sdram min cycle time (t ck avg min) */
MV_DDR_TAA_MIN, /* min cas latency time (t aa min) */
MV_DDR_TRFC1_MIN, /* min refresh recovery delay time (t rfc1 min) */
MV_DDR_TWR_MIN, /* min write recovery time (t wr min) */
MV_DDR_TRCD_MIN, /* min ras to cas delay time (t rcd min) */
MV_DDR_TRP_MIN, /* min row precharge delay time (t rp min) */
MV_DDR_TRC_MIN, /* min active to active/refresh delay time (t rc min) */
MV_DDR_TRAS_MIN, /* min active to precharge delay time (t ras min) */
MV_DDR_TRRD_S_MIN, /* min activate to activate delay time (t rrd_s min), diff bank group */
MV_DDR_TRRD_L_MIN, /* min activate to activate delay time (t rrd_l min), same bank group */
MV_DDR_TCCD_L_MIN, /* min cas to cas delay time (t ccd_l min), same bank group */
MV_DDR_TFAW_MIN, /* min four activate window delay time (t faw min) */
MV_DDR_TWTR_S_MIN, /* min write to read time (t wtr s min), diff bank group */
MV_DDR_TWTR_L_MIN, /* min write to read time (t wtr l min), same bank group */
MV_DDR_TDATA_LAST
};
enum mv_ddr_electrical_data {
MV_DDR_CK_DLY,
MV_DDR_PHY_REG3,
MV_DDR_ZPRI_DATA,
MV_DDR_ZNRI_DATA,
MV_DDR_ZPRI_CTRL,
MV_DDR_ZNRI_CTRL,
MV_DDR_ZPODT_DATA,
MV_DDR_ZNODT_DATA,
MV_DDR_ZPODT_CTRL,
MV_DDR_ZNODT_CTRL,
MV_DDR_DIC,
MV_DDR_ODT_CFG,
MV_DDR_RTT_NOM,
MV_DDR_RTT_WR,
MV_DDR_RTT_PARK,
MV_DDR_EDATA_LAST
};
/* memory electrical configuration values */
enum mv_ddr_rtt_nom_park_evalue {
MV_DDR_RTT_NOM_PARK_RZQ_DISABLE,
MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* 60-Ohm; RZQ = 240-Ohm */
MV_DDR_RTT_NOM_PARK_RZQ_DIV2, /* 120-Ohm; RZQ = 240-Ohm */
MV_DDR_RTT_NOM_PARK_RZQ_DIV6, /* 40-Ohm; RZQ = 240-Ohm */
MV_DDR_RTT_NOM_PARK_RZQ_DIV1, /* 240-Ohm; RZQ = 240-Ohm */
MV_DDR_RTT_NOM_PARK_RZQ_DIV5, /* 48-Ohm; RZQ = 240-Ohm */
MV_DDR_RTT_NOM_PARK_RZQ_DIV3, /* 80-Ohm; RZQ = 240-Ohm */
MV_DDR_RTT_NOM_PARK_RZQ_DIV7, /* 34-Ohm; RZQ = 240-Ohm */
MV_DDR_RTT_NOM_PARK_RZQ_LAST
};
enum mv_ddr_rtt_wr_evalue {
MV_DDR_RTT_WR_DYN_ODT_OFF,
MV_DDR_RTT_WR_RZQ_DIV2, /* 120-Ohm; RZQ = 240-Ohm */
MV_DDR_RTT_WR_RZQ_DIV1, /* 240-Ohm; RZQ = 240-Ohm */
MV_DDR_RTT_WR_HIZ,
MV_DDR_RTT_WR_RZQ_DIV3, /* 80-Ohm; RZQ = 240-Ohm */
MV_DDR_RTT_WR_RZQ_LAST
};
enum mv_ddr_dic_evalue {
MV_DDR_DIC_RZQ_DIV7, /* 34-Ohm; RZQ = 240-Ohm */
MV_DDR_DIC_RZQ_DIV5, /* 48-Ohm; RZQ = 240-Ohm */
MV_DDR_DIC_RZQ_LAST
};
/* phy electrical configuration values */
enum mv_ddr_ohm_evalue {
MV_DDR_OHM_30 = 30,
MV_DDR_OHM_48 = 48,
MV_DDR_OHM_60 = 60,
MV_DDR_OHM_80 = 80,
MV_DDR_OHM_120 = 120,
MV_DDR_OHM_240 = 240,
MV_DDR_OHM_LAST
};
/* mac electrical configuration values */
enum mv_ddr_odt_cfg_evalue {
MV_DDR_ODT_CFG_NORMAL,
MV_DDR_ODT_CFG_ALWAYS_ON,
MV_DDR_ODT_CFG_LAST
};
enum mv_ddr_dev_width { /* sdram device width */
MV_DDR_DEV_WIDTH_4BIT,
MV_DDR_DEV_WIDTH_8BIT,
MV_DDR_DEV_WIDTH_16BIT,
MV_DDR_DEV_WIDTH_32BIT,
MV_DDR_DEV_WIDTH_LAST
};
enum mv_ddr_die_capacity { /* total sdram capacity per die, megabits */
MV_DDR_DIE_CAP_256MBIT,
MV_DDR_DIE_CAP_512MBIT = 0,
MV_DDR_DIE_CAP_1GBIT,
MV_DDR_DIE_CAP_2GBIT,
MV_DDR_DIE_CAP_4GBIT,
MV_DDR_DIE_CAP_8GBIT,
MV_DDR_DIE_CAP_16GBIT,
MV_DDR_DIE_CAP_32GBIT,
MV_DDR_DIE_CAP_12GBIT,
MV_DDR_DIE_CAP_24GBIT,
MV_DDR_DIE_CAP_LAST
};
enum mv_ddr_pkg_rank { /* number of package ranks per dimm */
MV_DDR_PKG_RANK_1,
MV_DDR_PKG_RANK_2,
MV_DDR_PKG_RANK_3,
MV_DDR_PKG_RANK_4,
MV_DDR_PKG_RANK_5,
MV_DDR_PKG_RANK_6,
MV_DDR_PKG_RANK_7,
MV_DDR_PKG_RANK_8,
MV_DDR_PKG_RANK_LAST
};
enum mv_ddr_pri_bus_width { /* number of primary bus width bits */
MV_DDR_PRI_BUS_WIDTH_8,
MV_DDR_PRI_BUS_WIDTH_16,
MV_DDR_PRI_BUS_WIDTH_32,
MV_DDR_PRI_BUS_WIDTH_64,
MV_DDR_PRI_BUS_WIDTH_LAST
};
enum mv_ddr_bus_width_ext { /* number of extension bus width bits */
MV_DDR_BUS_WIDTH_EXT_0,
MV_DDR_BUS_WIDTH_EXT_8,
MV_DDR_BUS_WIDTH_EXT_LAST
};
enum mv_ddr_die_count {
MV_DDR_DIE_CNT_1,
MV_DDR_DIE_CNT_2,
MV_DDR_DIE_CNT_3,
MV_DDR_DIE_CNT_4,
MV_DDR_DIE_CNT_5,
MV_DDR_DIE_CNT_6,
MV_DDR_DIE_CNT_7,
MV_DDR_DIE_CNT_8,
MV_DDR_DIE_CNT_LAST
};
#define IS_ACTIVE(mask, id) \
((mask) & (1 << (id)))
#define VALIDATE_ACTIVE(mask, id) \
{ \
if (IS_ACTIVE(mask, id) == 0) \
continue; \
}
#define IS_IF_ACTIVE(if_mask, if_id) \
((if_mask) & (1 << (if_id)))
#define VALIDATE_IF_ACTIVE(mask, id) \
{ \
if (IS_IF_ACTIVE(mask, id) == 0) \
continue; \
}
#define IS_BUS_ACTIVE(if_mask , if_id) \
(((if_mask) >> (if_id)) & 1)
#define VALIDATE_BUS_ACTIVE(mask, id) \
{ \
if (IS_BUS_ACTIVE(mask, id) == 0) \
continue; \
}
#define DDR3_IS_ECC_PUP3_MODE(if_mask) \
(((if_mask) == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0)
#define DDR3_IS_ECC_PUP4_MODE(if_mask) \
(((if_mask) == BUS_MASK_32BIT_ECC || \
(if_mask) == BUS_MASK_16BIT_ECC) ? 1 : 0)
#define DDR3_IS_16BIT_DRAM_MODE(mask) \
(((mask) == BUS_MASK_16BIT || \
(mask) == BUS_MASK_16BIT_ECC || \
(mask) == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0)
#define DDR3_IS_ECC_PUP8_MODE(if_mask) \
(((if_mask) == MV_DDR_32BIT_ECC_PUP8_BUS_MASK || \
(if_mask) == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0)
#define MV_DDR_IS_64BIT_DRAM_MODE(mask) \
((((mask) & MV_DDR_64BIT_BUS_MASK) == MV_DDR_64BIT_BUS_MASK) || \
(((mask) & MV_DDR_64BIT_ECC_PUP8_BUS_MASK) == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0)
#define MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, sphys) \
(((sphys) == 9) && \
(((mask) == BUS_MASK_32BIT) || \
((mask) == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)) ? 1 : 0)
#define MV_DDR_IS_HALF_BUS_DRAM_MODE(mask, sphys) \
(MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, sphys) || \
DDR3_IS_16BIT_DRAM_MODE(mask))
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void);
unsigned int mv_ddr_cl_calc(unsigned int taa_min, unsigned int tclk);
unsigned int mv_ddr_cwl_calc(unsigned int tclk);
int mv_ddr_topology_map_update(void);
unsigned short mv_ddr_bus_bit_mask_get(void);
unsigned int mv_ddr_if_bus_width_get(void);
unsigned int mv_ddr_cs_num_get(void);
int mv_ddr_is_ecc_ena(void);
unsigned long long mv_ddr_mem_sz_per_cs_get(void);
unsigned long long mv_ddr_mem_sz_get(void);
unsigned int mv_ddr_rtt_nom_get(void);
unsigned int mv_ddr_rtt_park_get(void);
unsigned int mv_ddr_rtt_wr_get(void);
unsigned int mv_ddr_dic_get(void);
#endif /* _MV_DDR_TOPOLOGY_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/mv_ddr_training_db.h
+40
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 Marvell International Ltd.
*/
#ifndef _MV_DDR_TRAINING_DB_H
#define _MV_DDR_TRAINING_DB_H
#include "mv_ddr_topology.h"
/* in ns */
#define TREFI_LOW 7800
#define TREFI_HIGH 3900
enum mv_ddr_page_size {
MV_DDR_PAGE_SIZE_1K = 1,
MV_DDR_PAGE_SIZE_2K
};
struct mv_ddr_page_element {
/* 8-bit bus width page size */
enum mv_ddr_page_size page_size_8bit;
/* 16-bit bus width page size */
enum mv_ddr_page_size page_size_16bit;
};
/* cas latency value per frequency */
struct mv_ddr_cl_val_per_freq {
unsigned int cl_val[MV_DDR_FREQ_LAST];
};
u32 mv_ddr_rfc_get(u32 mem);
unsigned int *mv_ddr_freq_tbl_get(void);
u32 mv_ddr_freq_get(enum mv_ddr_freq freq);
u32 mv_ddr_page_size_get(enum mv_ddr_dev_width bus_width, enum mv_ddr_die_capacity mem_size);
unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_ddr_speed_bin_timing element);
u32 mv_ddr_cl_val_get(u32 index, u32 freq);
u32 mv_ddr_cwl_val_get(u32 index, u32 freq);
#endif /* _MV_DDR_TRAINING_DB_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/seq_exec.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _SEQ_EXEC_H
#define _SEQ_EXEC_H
#define NA 0xff
#define DEFAULT_PARAM 0
#define MV_BOARD_TCLK_ERROR 0xffffffff
#define NO_DATA 0xffffffff
#define MAX_DATA_ARRAY 5
#define FIRST_CELL 0
/* Operation types */
enum mv_op {
WRITE_OP,
DELAY_OP,
POLL_OP,
};
/* Operation parameters */
struct op_params {
u32 unit_base_reg;
u32 unit_offset;
u32 mask;
u32 data[MAX_DATA_ARRAY]; /* data array */
u8 wait_time; /* msec */
u16 num_of_loops; /* for polling only */
};
/*
* Sequence parameters. Each sequence contains:
* 1. Sequence id.
* 2. Sequence size (total amount of operations during the sequence)
* 3. a series of operations. operations can be write, poll or delay
* 4. index in the data array (the entry where the relevant data sits)
*/
struct cfg_seq {
struct op_params *op_params_ptr;
u8 cfg_seq_size;
u8 data_arr_idx;
};
extern struct cfg_seq serdes_seq_db[];
/*
* A generic function type for executing an operation (write, poll or delay)
*/
typedef int (*op_execute_func_ptr)(u32 serdes_num, struct op_params *params,
u32 data_arr_idx);
/* Specific functions for executing each operation */
int write_op_execute(u32 serdes_num, struct op_params *params,
u32 data_arr_idx);
int delay_op_execute(u32 serdes_num, struct op_params *params,
u32 data_arr_idx);
int poll_op_execute(u32 serdes_num, struct op_params *params, u32 data_arr_idx);
enum mv_op get_cfg_seq_op(struct op_params *params);
int mv_seq_exec(u32 serdes_num, u32 seq_id);
#endif /*_SEQ_EXEC_H*/
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/xor.c
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#include "ddr3_init.h"
#include "mv_ddr_common.h"
#include "xor_regs.h"
/* defines */
#ifdef MV_DEBUG
#define DB(x) x
#else
#define DB(x)
#endif
static u32 ui_xor_regs_ctrl_backup;
static u32 ui_xor_regs_base_backup[MAX_CS_NUM + 1];
static u32 ui_xor_regs_mask_backup[MAX_CS_NUM + 1];
void mv_sys_xor_init(u32 num_of_cs, u32 cs_ena, uint64_t cs_size, u32 base_delta)
{
u32 reg, ui, cs_count;
uint64_t base, size_mask;
ui_xor_regs_ctrl_backup = reg_read(XOR_WINDOW_CTRL_REG(0, 0));
for (ui = 0; ui < MAX_CS_NUM + 1; ui++)
ui_xor_regs_base_backup[ui] =
reg_read(XOR_BASE_ADDR_REG(0, ui));
for (ui = 0; ui < MAX_CS_NUM + 1; ui++)
ui_xor_regs_mask_backup[ui] =
reg_read(XOR_SIZE_MASK_REG(0, ui));
reg = 0;
for (ui = 0, cs_count = 0;
(cs_count < num_of_cs) && (ui < 8);
ui++, cs_count++) {
if (cs_ena & (1 << ui)) {
/* Enable Window x for each CS */
reg |= (0x1 << (ui));
/* Enable Window x for each CS */
reg |= (0x3 << ((ui * 2) + 16));
}
}
reg_write(XOR_WINDOW_CTRL_REG(0, 0), reg);
cs_count = 0;
for (ui = 0, cs_count = 0;
(cs_count < num_of_cs) && (ui < 8);
ui++, cs_count++) {
if (cs_ena & (1 << ui)) {
/*
* window x - Base - 0x00000000,
* Attribute 0x0e - DRAM
*/
base = cs_size * ui + base_delta;
/* fixed size 2GB for each CS */
size_mask = 0x7FFF0000;
switch (ui) {
case 0:
base |= 0xe00;
break;
case 1:
base |= 0xd00;
break;
case 2:
base |= 0xb00;
break;
case 3:
base |= 0x700;
break;
case 4: /* SRAM */
base = 0x40000000;
/* configure as shared transaction */
base |= 0x1F00;
size_mask = 0xF0000;
break;
}
reg_write(XOR_BASE_ADDR_REG(0, ui), (u32)base);
size_mask = (cs_size / _64K) - 1;
size_mask = (size_mask << XESMRX_SIZE_MASK_OFFS) & XESMRX_SIZE_MASK_MASK;
/* window x - Size */
reg_write(XOR_SIZE_MASK_REG(0, ui), (u32)size_mask);
}
}
mv_xor_hal_init(1);
return;
}
void mv_sys_xor_finish(void)
{
u32 ui;
reg_write(XOR_WINDOW_CTRL_REG(0, 0), ui_xor_regs_ctrl_backup);
for (ui = 0; ui < MAX_CS_NUM + 1; ui++)
reg_write(XOR_BASE_ADDR_REG(0, ui),
ui_xor_regs_base_backup[ui]);
for (ui = 0; ui < MAX_CS_NUM + 1; ui++)
reg_write(XOR_SIZE_MASK_REG(0, ui),
ui_xor_regs_mask_backup[ui]);
reg_write(XOR_ADDR_OVRD_REG(0, 0), 0);
}
/*
* mv_xor_hal_init - Initialize XOR engine
*
* DESCRIPTION:
* This function initialize XOR unit.
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
*/
void mv_xor_hal_init(u32 xor_chan_num)
{
u32 i;
/* Abort any XOR activity & set default configuration */
for (i = 0; i < xor_chan_num; i++) {
mv_xor_command_set(i, MV_STOP);
mv_xor_ctrl_set(i, (1 << XEXCR_REG_ACC_PROTECT_OFFS) |
(4 << XEXCR_DST_BURST_LIMIT_OFFS) |
(4 << XEXCR_SRC_BURST_LIMIT_OFFS));
}
}
/*
* mv_xor_ctrl_set - Set XOR channel control registers
*
* DESCRIPTION:
*
* INPUT:
*
* OUTPUT:
* None.
*
* RETURN:
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
* NOTE:
* This function does not modify the Operation_mode field of control register.
*/
int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl)
{
u32 old_value;
/* update the XOR Engine [0..1] Configuration Registers (XEx_c_r) */
old_value = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))) &
XEXCR_OPERATION_MODE_MASK;
xor_ctrl &= ~XEXCR_OPERATION_MODE_MASK;
xor_ctrl |= old_value;
reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xor_ctrl);
return MV_OK;
}
int mv_xor_mem_init(u32 chan, u32 start_ptr, unsigned long long block_size,
u32 init_val_high, u32 init_val_low)
{
u32 temp;
if (block_size == _4G)
block_size -= 1;
/* Parameter checking */
if (chan >= MV_XOR_MAX_CHAN)
return MV_BAD_PARAM;
if (MV_ACTIVE == mv_xor_state_get(chan))
return MV_BUSY;
if ((block_size < XEXBSR_BLOCK_SIZE_MIN_VALUE) ||
(block_size > XEXBSR_BLOCK_SIZE_MAX_VALUE))
return MV_BAD_PARAM;
/* set the operation mode to Memory Init */
temp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)));
temp &= ~XEXCR_OPERATION_MODE_MASK;
temp |= XEXCR_OPERATION_MODE_MEM_INIT;
reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), temp);
/*
* update the start_ptr field in XOR Engine [0..1] Destination Pointer
* Register
*/
reg_write(XOR_DST_PTR_REG(XOR_UNIT(chan), XOR_CHAN(chan)), start_ptr);
/*
* update the Block_size field in the XOR Engine[0..1] Block Size
* Registers
*/
reg_write(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
block_size);
/*
* update the field Init_val_l in the XOR Engine Initial Value Register
* Low (XEIVRL)
*/
reg_write(XOR_INIT_VAL_LOW_REG(XOR_UNIT(chan)), init_val_low);
/*
* update the field Init_val_h in the XOR Engine Initial Value Register
* High (XEIVRH)
*/
reg_write(XOR_INIT_VAL_HIGH_REG(XOR_UNIT(chan)), init_val_high);
/* start transfer */
reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
XEXACTR_XESTART_MASK);
return MV_OK;
}
/*
* mv_xor_state_get - Get XOR channel state.
*
* DESCRIPTION:
* XOR channel activity state can be active, idle, paused.
* This function retrunes the channel activity state.
*
* INPUT:
* chan - the channel number
*
* OUTPUT:
* None.
*
* RETURN:
* XOR_CHANNEL_IDLE - If the engine is idle.
* XOR_CHANNEL_ACTIVE - If the engine is busy.
* XOR_CHANNEL_PAUSED - If the engine is paused.
* MV_UNDEFINED_STATE - If the engine state is undefind or there is no
* such engine
*/
enum mv_state mv_xor_state_get(u32 chan)
{
u32 state;
/* Parameter checking */
if (chan >= MV_XOR_MAX_CHAN) {
DB(printf("%s: ERR. Invalid chan num %d\n", __func__, chan));
return MV_UNDEFINED_STATE;
}
/* read the current state */
state = reg_read(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)));
state &= XEXACTR_XESTATUS_MASK;
/* return the state */
switch (state) {
case XEXACTR_XESTATUS_IDLE:
return MV_IDLE;
case XEXACTR_XESTATUS_ACTIVE:
return MV_ACTIVE;
case XEXACTR_XESTATUS_PAUSED:
return MV_PAUSED;
}
return MV_UNDEFINED_STATE;
}
/*
* mv_xor_command_set - Set command of XOR channel
*
* DESCRIPTION:
* XOR channel can be started, idle, paused and restarted.
* Paused can be set only if channel is active.
* Start can be set only if channel is idle or paused.
* Restart can be set only if channel is paused.
* Stop can be set only if channel is active.
*
* INPUT:
* chan - The channel number
* command - The command type (start, stop, restart, pause)
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK on success , MV_BAD_PARAM on erroneous parameter, MV_ERROR on
* undefind XOR engine mode
*/
int mv_xor_command_set(u32 chan, enum mv_command command)
{
enum mv_state state;
/* Parameter checking */
if (chan >= MV_XOR_MAX_CHAN) {
DB(printf("%s: ERR. Invalid chan num %d\n", __func__, chan));
return MV_BAD_PARAM;
}
/* get the current state */
state = mv_xor_state_get(chan);
if ((command == MV_START) && (state == MV_IDLE)) {
/* command is start and current state is idle */
reg_bit_set(XOR_ACTIVATION_REG
(XOR_UNIT(chan), XOR_CHAN(chan)),
XEXACTR_XESTART_MASK);
return MV_OK;
} else if ((command == MV_STOP) && (state == MV_ACTIVE)) {
/* command is stop and current state is active */
reg_bit_set(XOR_ACTIVATION_REG
(XOR_UNIT(chan), XOR_CHAN(chan)),
XEXACTR_XESTOP_MASK);
return MV_OK;
} else if (((enum mv_state)command == MV_PAUSED) &&
(state == MV_ACTIVE)) {
/* command is paused and current state is active */
reg_bit_set(XOR_ACTIVATION_REG
(XOR_UNIT(chan), XOR_CHAN(chan)),
XEXACTR_XEPAUSE_MASK);
return MV_OK;
} else if ((command == MV_RESTART) && (state == MV_PAUSED)) {
/* command is restart and current state is paused */
reg_bit_set(XOR_ACTIVATION_REG
(XOR_UNIT(chan), XOR_CHAN(chan)),
XEXACTR_XERESTART_MASK);
return MV_OK;
} else if ((command == MV_STOP) && (state == MV_IDLE)) {
/* command is stop and current state is active */
return MV_OK;
}
/* illegal command */
DB(printf("%s: ERR. Illegal command\n", __func__));
return MV_BAD_PARAM;
}
void ddr3_new_tip_ecc_scrub(void)
{
u32 cs_c, max_cs;
u32 cs_ena = 0;
uint64_t total_mem_size, cs_mem_size = 0;
printf("DDR Training Sequence - Start scrubbing\n");
max_cs = mv_ddr_cs_num_get();
for (cs_c = 0; cs_c < max_cs; cs_c++)
cs_ena |= 1 << cs_c;
#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
/* all chip-selects are of same size */
ddr3_calc_mem_cs_size(0, &cs_mem_size);
#endif
mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0);
total_mem_size = max_cs * cs_mem_size;
mv_xor_mem_init(0, 0, total_mem_size, 0xdeadbeef, 0xdeadbeef);
/* wait for previous transfer completion */
while (mv_xor_state_get(0) != MV_IDLE)
;
/* Return XOR State */
mv_sys_xor_finish();
printf("DDR3 Training Sequence - End scrubbing\n");
}
/*
* mv_xor_transfer - Transfer data from source to destination in one of
* three modes: XOR, CRC32 or DMA
*
* DESCRIPTION:
* This function initiates XOR channel, according to function parameters,
* in order to perform XOR, CRC32 or DMA transaction.
* To gain maximum performance the user is asked to keep the following
* restrictions:
* 1) Selected engine is available (not busy).
* 2) This module does not take into consideration CPU MMU issues.
* In order for the XOR engine to access the appropriate source
* and destination, address parameters must be given in system
* physical mode.
* 3) This API does not take care of cache coherency issues. The source,
* destination and, in case of chain, the descriptor list are assumed
* to be cache coherent.
* 4) Parameters validity.
*
* INPUT:
* chan - XOR channel number.
* type - One of three: XOR, CRC32 and DMA operations.
* xor_chain_ptr - address of chain pointer
*
* OUTPUT:
* None.
*
* RETURN:
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
*
*******************************************************************************/
int mv_xor_transfer(u32 chan, enum xor_type type, u32 xor_chain_ptr)
{
u32 temp;
/* Parameter checking */
if (chan >= MV_XOR_MAX_CHAN) {
DB(printf("%s: ERR. Invalid chan num %d\n", __func__, chan));
return MV_BAD_PARAM;
}
if (mv_xor_state_get(chan) == MV_ACTIVE) {
DB(printf("%s: ERR. Channel is already active\n", __func__));
return MV_BUSY;
}
if (xor_chain_ptr == 0x0) {
DB(printf("%s: ERR. xor_chain_ptr is NULL pointer\n", __func__));
return MV_BAD_PARAM;
}
/* read configuration register and mask the operation mode field */
temp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)));
temp &= ~XEXCR_OPERATION_MODE_MASK;
switch (type) {
case MV_XOR:
if ((xor_chain_ptr & XEXDPR_DST_PTR_XOR_MASK) != 0) {
DB(printf("%s: ERR. Invalid chain pointer (bits [5:0] must be cleared)\n",
__func__));
return MV_BAD_PARAM;
}
/* set the operation mode to XOR */
temp |= XEXCR_OPERATION_MODE_XOR;
break;
case MV_DMA:
if ((xor_chain_ptr & XEXDPR_DST_PTR_DMA_MASK) != 0) {
DB(printf("%s: ERR. Invalid chain pointer (bits [4:0] must be cleared)\n",
__func__));
return MV_BAD_PARAM;
}
/* set the operation mode to DMA */
temp |= XEXCR_OPERATION_MODE_DMA;
break;
case MV_CRC32:
if ((xor_chain_ptr & XEXDPR_DST_PTR_CRC_MASK) != 0) {
DB(printf("%s: ERR. Invalid chain pointer (bits [4:0] must be cleared)\n",
__func__));
return MV_BAD_PARAM;
}
/* set the operation mode to CRC32 */
temp |= XEXCR_OPERATION_MODE_CRC;
break;
default:
return MV_BAD_PARAM;
}
/* write the operation mode to the register */
reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), temp);
/*
* update the NextDescPtr field in the XOR Engine [0..1] Next Descriptor
* Pointer Register (XExNDPR)
*/
reg_write(XOR_NEXT_DESC_PTR_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
xor_chain_ptr);
/* start transfer */
reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
XEXACTR_XESTART_MASK);
return MV_OK;
}
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/xor.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _XOR_H
#define _XOR_H
#define SRAM_BASE 0x40000000
#define MV_XOR_MAX_UNIT 2 /* XOR unit == XOR engine */
#define MV_XOR_MAX_CHAN 4 /* total channels for all units */
#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */
#define MV_IS_POWER_OF_2(num) (((num) != 0) && (((num) & ((num) - 1)) == 0))
/*
* This structure describes address space window. Window base can be
* 64 bit, window size up to 4GB
*/
struct addr_win {
u32 base_low; /* 32bit base low */
u32 base_high; /* 32bit base high */
u32 size; /* 32bit size */
};
/* This structure describes SoC units address decode window */
struct unit_win_info {
struct addr_win addr_win; /* An address window */
int enable; /* Address decode window is enabled/disabled */
u8 attrib; /* chip select attributes */
u8 target_id; /* Target Id of this MV_TARGET */
};
/*
* This enumerator describes the type of functionality the XOR channel
* can have while using the same data structures.
*/
enum xor_type {
MV_XOR, /* XOR channel functions as XOR accelerator */
MV_DMA, /* XOR channel functions as IDMA channel */
MV_CRC32 /* XOR channel functions as CRC 32 calculator */
};
enum mv_state {
MV_IDLE,
MV_ACTIVE,
MV_PAUSED,
MV_UNDEFINED_STATE
};
/*
* This enumerator describes the set of commands that can be applied on
* an engine (e.g. IDMA, XOR). Appling a comman depends on the current
* status (see MV_STATE enumerator)
*
* Start can be applied only when status is IDLE
* Stop can be applied only when status is IDLE, ACTIVE or PAUSED
* Pause can be applied only when status is ACTIVE
* Restart can be applied only when status is PAUSED
*/
enum mv_command {
MV_START, /* Start */
MV_STOP, /* Stop */
MV_PAUSE, /* Pause */
MV_RESTART /* Restart */
};
enum xor_override_target {
SRC_ADDR0, /* Source Address #0 Control */
SRC_ADDR1, /* Source Address #1 Control */
SRC_ADDR2, /* Source Address #2 Control */
SRC_ADDR3, /* Source Address #3 Control */
SRC_ADDR4, /* Source Address #4 Control */
SRC_ADDR5, /* Source Address #5 Control */
SRC_ADDR6, /* Source Address #6 Control */
SRC_ADDR7, /* Source Address #7 Control */
XOR_DST_ADDR, /* Destination Address Control */
XOR_NEXT_DESC /* Next Descriptor Address Control */
};
enum mv_state mv_xor_state_get(u32 chan);
void mv_xor_hal_init(u32 xor_chan_num);
int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl);
int mv_xor_command_set(u32 chan, enum mv_command command);
int mv_xor_override_set(u32 chan, enum xor_override_target target, u32 win_num,
int enable);
int mv_xor_transfer(u32 chan, enum xor_type type, u32 xor_chain_ptr);
#endif
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/a38x/xor_regs.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _XOR_REGS_h
#define _XOR_REGS_h
/*
* For controllers that have two XOR units, then chans 2 & 3 will be
* mapped to channels 0 & 1 of unit 1
*/
#define XOR_UNIT(chan) ((chan) >> 1)
#define XOR_CHAN(chan) ((chan) & 1)
#define MV_XOR_REGS_OFFSET(unit) (0x60900)
#define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit))
/* XOR Engine Control Register Map */
#define XOR_CHANNEL_ARBITER_REG(unit) (MV_XOR_REGS_BASE(unit))
#define XOR_CONFIG_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \
(0x10 + ((chan) * 4)))
#define XOR_ACTIVATION_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \
(0x20 + ((chan) * 4)))
/* XOR Engine Interrupt Register Map */
#define XOR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x30))
#define XOR_MASK_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x40))
#define XOR_ERROR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x50))
#define XOR_ERROR_ADDR_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x60))
/* XOR Engine Descriptor Register Map */
#define XOR_NEXT_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \
(0x200 + ((chan) * 4)))
#define XOR_CURR_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \
(0x210 + ((chan) * 4)))
#define XOR_BYTE_COUNT_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \
(0x220 + ((chan) * 4)))
/* XOR Engine ECC/Mem_init Register Map */
#define XOR_DST_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \
(0x2b0 + ((chan) * 4)))
#define XOR_BLOCK_SIZE_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \
(0x2c0 + ((chan) * 4)))
#define XOR_TIMER_MODE_CTRL_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2d0))
#define XOR_TIMER_MODE_INIT_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2d4))
#define XOR_TIMER_MODE_CURR_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2d8))
#define XOR_INIT_VAL_LOW_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2e0))
#define XOR_INIT_VAL_HIGH_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2e4))
/* XOR Engine Debug Register Map */
#define XOR_DEBUG_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x70))
/* XOR register fileds */
/* XOR Engine Channel Arbiter Register */
#define XECAR_SLICE_OFFS(slice_num) (slice_num)
#define XECAR_SLICE_MASK(slice_num) (1 << (XECAR_SLICE_OFFS(slice_num)))
/* XOR Engine [0..1] Configuration Registers */
#define XEXCR_OPERATION_MODE_OFFS (0)
#define XEXCR_OPERATION_MODE_MASK (7 << XEXCR_OPERATION_MODE_OFFS)
#define XEXCR_OPERATION_MODE_XOR (0 << XEXCR_OPERATION_MODE_OFFS)
#define XEXCR_OPERATION_MODE_CRC (1 << XEXCR_OPERATION_MODE_OFFS)
#define XEXCR_OPERATION_MODE_DMA (2 << XEXCR_OPERATION_MODE_OFFS)
#define XEXCR_OPERATION_MODE_ECC (3 << XEXCR_OPERATION_MODE_OFFS)
#define XEXCR_OPERATION_MODE_MEM_INIT (4 << XEXCR_OPERATION_MODE_OFFS)
#define XEXCR_SRC_BURST_LIMIT_OFFS (4)
#define XEXCR_SRC_BURST_LIMIT_MASK (7 << XEXCR_SRC_BURST_LIMIT_OFFS)
#define XEXCR_DST_BURST_LIMIT_OFFS (8)
#define XEXCR_DST_BURST_LIMIT_MASK (7 << XEXCR_DST_BURST_LIMIT_OFFS)
#define XEXCR_DRD_RES_SWP_OFFS (12)
#define XEXCR_DRD_RES_SWP_MASK (1 << XEXCR_DRD_RES_SWP_OFFS)
#define XEXCR_DWR_REQ_SWP_OFFS (13)
#define XEXCR_DWR_REQ_SWP_MASK (1 << XEXCR_DWR_REQ_SWP_OFFS)
#define XEXCR_DES_SWP_OFFS (14)
#define XEXCR_DES_SWP_MASK (1 << XEXCR_DES_SWP_OFFS)
#define XEXCR_REG_ACC_PROTECT_OFFS (15)
#define XEXCR_REG_ACC_PROTECT_MASK (1 << XEXCR_REG_ACC_PROTECT_OFFS)
/* XOR Engine [0..1] Activation Registers */
#define XEXACTR_XESTART_OFFS (0)
#define XEXACTR_XESTART_MASK (1 << XEXACTR_XESTART_OFFS)
#define XEXACTR_XESTOP_OFFS (1)
#define XEXACTR_XESTOP_MASK (1 << XEXACTR_XESTOP_OFFS)
#define XEXACTR_XEPAUSE_OFFS (2)
#define XEXACTR_XEPAUSE_MASK (1 << XEXACTR_XEPAUSE_OFFS)
#define XEXACTR_XERESTART_OFFS (3)
#define XEXACTR_XERESTART_MASK (1 << XEXACTR_XERESTART_OFFS)
#define XEXACTR_XESTATUS_OFFS (4)
#define XEXACTR_XESTATUS_MASK (3 << XEXACTR_XESTATUS_OFFS)
#define XEXACTR_XESTATUS_IDLE (0 << XEXACTR_XESTATUS_OFFS)
#define XEXACTR_XESTATUS_ACTIVE (1 << XEXACTR_XESTATUS_OFFS)
#define XEXACTR_XESTATUS_PAUSED (2 << XEXACTR_XESTATUS_OFFS)
/* XOR Engine Interrupt Cause Register (XEICR) */
#define XEICR_CHAN_OFFS 16
#define XEICR_CAUSE_OFFS(chan) (chan * XEICR_CHAN_OFFS)
#define XEICR_CAUSE_MASK(chan, cause) (1 << (cause + XEICR_CAUSE_OFFS(chan)))
#define XEICR_COMP_MASK_ALL 0x000f000f
#define XEICR_COMP_MASK(chan) (0x000f << XEICR_CAUSE_OFFS(chan))
#define XEICR_ERR_MASK 0x03800380
/* XOR Engine Error Cause Register (XEECR) */
#define XEECR_ERR_TYPE_OFFS 0
#define XEECR_ERR_TYPE_MASK (0x1f << XEECR_ERR_TYPE_OFFS)
/* XOR Engine Error Address Register (XEEAR) */
#define XEEAR_ERR_ADDR_OFFS (0)
#define XEEAR_ERR_ADDR_MASK (0xffffffff << XEEAR_ERR_ADDR_OFFS)
/* XOR Engine [0..1] Next Descriptor Pointer Register */
#define XEXNDPR_NEXT_DESC_PTR_OFFS (0)
#define XEXNDPR_NEXT_DESC_PTR_MASK (0xffffffff << \
XEXNDPR_NEXT_DESC_PTR_OFFS)
/* XOR Engine [0..1] Current Descriptor Pointer Register */
#define XEXCDPR_CURRENT_DESC_PTR_OFFS (0)
#define XEXCDPR_CURRENT_DESC_PTR_MASK (0xffffffff << \
XEXCDPR_CURRENT_DESC_PTR_OFFS)
/* XOR Engine [0..1] Byte Count Register */
#define XEXBCR_BYTE_CNT_OFFS (0)
#define XEXBCR_BYTE_CNT_MASK (0xffffffff << XEXBCR_BYTE_CNT_OFFS)
/* XOR Engine [0..1] Destination Pointer Register */
#define XEXDPR_DST_PTR_OFFS (0)
#define XEXDPR_DST_PTR_MASK (0xffffffff << XEXDPR_DST_PTR_OFFS)
#define XEXDPR_DST_PTR_XOR_MASK (0x3f)
#define XEXDPR_DST_PTR_DMA_MASK (0x1f)
#define XEXDPR_DST_PTR_CRC_MASK (0x1f)
/* XOR Engine[0..1] Block Size Registers */
#define XEXBSR_BLOCK_SIZE_OFFS (0)
#define XEXBSR_BLOCK_SIZE_MASK (0xffffffff << XEXBSR_BLOCK_SIZE_OFFS)
#define XEXBSR_BLOCK_SIZE_MIN_VALUE (128)
#define XEXBSR_BLOCK_SIZE_MAX_VALUE (0xffffffff)
/* XOR Engine Timer Mode Control Register (XETMCR) */
#define XETMCR_TIMER_EN_OFFS (0)
#define XETMCR_TIMER_EN_MASK (1 << XETMCR_TIMER_EN_OFFS)
#define XETMCR_TIMER_EN_ENABLE (1 << XETMCR_TIMER_EN_OFFS)
#define XETMCR_TIMER_EN_DISABLE (0 << XETMCR_TIMER_EN_OFFS)
#define XETMCR_SECTION_SIZE_CTRL_OFFS (8)
#define XETMCR_SECTION_SIZE_CTRL_MASK (0x1f << XETMCR_SECTION_SIZE_CTRL_OFFS)
#define XETMCR_SECTION_SIZE_MIN_VALUE (7)
#define XETMCR_SECTION_SIZE_MAX_VALUE (31)
/* XOR Engine Timer Mode Initial Value Register (XETMIVR) */
#define XETMIVR_TIMER_INIT_VAL_OFFS (0)
#define XETMIVR_TIMER_INIT_VAL_MASK (0xffffffff << \
XETMIVR_TIMER_INIT_VAL_OFFS)
/* XOR Engine Timer Mode Current Value Register (XETMCVR) */
#define XETMCVR_TIMER_CRNT_VAL_OFFS (0)
#define XETMCVR_TIMER_CRNT_VAL_MASK (0xffffffff << \
XETMCVR_TIMER_CRNT_VAL_OFFS)
/* XOR Engine Initial Value Register Low (XEIVRL) */
#define XEIVRL_INIT_VAL_L_OFFS (0)
#define XEIVRL_INIT_VAL_L_MASK (0xffffffff << XEIVRL_INIT_VAL_L_OFFS)
/* XOR Engine Initial Value Register High (XEIVRH) */
#define XEIVRH_INIT_VAL_H_OFFS (0)
#define XEIVRH_INIT_VAL_H_MASK (0xffffffff << XEIVRH_INIT_VAL_H_OFFS)
/* XOR Engine Debug Register (XEDBR) */
#define XEDBR_PARITY_ERR_INSR_OFFS (0)
#define XEDBR_PARITY_ERR_INSR_MASK (1 << XEDBR_PARITY_ERR_INSR_OFFS)
#define XEDBR_XBAR_ERR_INSR_OFFS (1)
#define XEDBR_XBAR_ERR_INSR_MASK (1 << XEDBR_XBAR_ERR_INSR_OFFS)
/* XOR Engine address decode registers. */
/* Maximum address decode windows */
#define XOR_MAX_ADDR_DEC_WIN 8
/* Maximum address arbiter windows */
#define XOR_MAX_REMAP_WIN 4
/* XOR Engine Address Decoding Register Map */
#define XOR_WINDOW_CTRL_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \
(0x240 + ((chan) * 4)))
#define XOR_BASE_ADDR_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \
(0x250 + ((win_num) * 4)))
#define XOR_SIZE_MASK_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \
(0x270 + ((win_num) * 4)))
#define XOR_HIGH_ADDR_REMAP_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \
(0x290 + ((win_num) * 4)))
#define XOR_ADDR_OVRD_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \
(0x2a0 + ((win_num) * 4)))
/* XOR Engine [0..1] Window Control Registers */
#define XEXWCR_WIN_EN_OFFS(win_num) (win_num)
#define XEXWCR_WIN_EN_MASK(win_num) (1 << (XEXWCR_WIN_EN_OFFS(win_num)))
#define XEXWCR_WIN_EN_ENABLE(win_num) (1 << (XEXWCR_WIN_EN_OFFS(win_num)))
#define XEXWCR_WIN_EN_DISABLE(win_num) (0 << (XEXWCR_WIN_EN_OFFS(win_num)))
#define XEXWCR_WIN_ACC_OFFS(win_num) ((2 * win_num) + 16)
#define XEXWCR_WIN_ACC_MASK(win_num) (3 << (XEXWCR_WIN_ACC_OFFS(win_num)))
#define XEXWCR_WIN_ACC_NO_ACC(win_num) (0 << (XEXWCR_WIN_ACC_OFFS(win_num)))
#define XEXWCR_WIN_ACC_RO(win_num) (1 << (XEXWCR_WIN_ACC_OFFS(win_num)))
#define XEXWCR_WIN_ACC_RW(win_num) (3 << (XEXWCR_WIN_ACC_OFFS(win_num)))
/* XOR Engine Base Address Registers (XEBARx) */
#define XEBARX_TARGET_OFFS (0)
#define XEBARX_TARGET_MASK (0xf << XEBARX_TARGET_OFFS)
#define XEBARX_ATTR_OFFS (8)
#define XEBARX_ATTR_MASK (0xff << XEBARX_ATTR_OFFS)
#define XEBARX_BASE_OFFS (16)
#define XEBARX_BASE_MASK (0xffff << XEBARX_BASE_OFFS)
/* XOR Engine Size Mask Registers (XESMRx) */
#define XESMRX_SIZE_MASK_OFFS (16)
#define XESMRX_SIZE_MASK_MASK (0xffff << XESMRX_SIZE_MASK_OFFS)
#define XOR_WIN_SIZE_ALIGN _64K
/* XOR Engine High Address Remap Register (XEHARRx1) */
#define XEHARRX_REMAP_OFFS (0)
#define XEHARRX_REMAP_MASK (0xffffffff << XEHARRX_REMAP_OFFS)
#define XOR_OVERRIDE_CTRL_REG(chan) (MV_XOR_REGS_BASE(XOR_UNIT(chan)) + \
(0x2a0 + ((XOR_CHAN(chan)) * 4)))
/* XOR Engine [0..1] Address Override Control Register */
#define XEXAOCR_OVR_EN_OFFS(target) (3 * target)
#define XEXAOCR_OVR_EN_MASK(target) (1 << (XEXAOCR_OVR_EN_OFFS(target)))
#define XEXAOCR_OVR_PTR_OFFS(target) ((3 * target) + 1)
#define XEXAOCR_OVR_PTR_MASK(target) (3 << (XEXAOCR_OVR_PTR_OFFS(target)))
#define XEXAOCR_OVR_BAR(win_num, target) (win_num << \
(XEXAOCR_OVR_PTR_OFFS(target)))
/* Maximum address override windows */
#define XOR_MAX_OVERRIDE_WIN 4
#endif /* _XOR_REGS_h */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/Makefile
+12
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@@ -0,0 +1,12 @@
# SPDX-License-Identifier: GPL-2.0+
obj-$(CONFIG_SPL_BUILD) += ddr3_dfs.o
obj-$(CONFIG_SPL_BUILD) += ddr3_dqs.o
obj-$(CONFIG_SPL_BUILD) += ddr3_hw_training.o
obj-$(CONFIG_SPL_BUILD) += ddr3_init.o
obj-$(CONFIG_SPL_BUILD) += ddr3_pbs.o
obj-$(CONFIG_SPL_BUILD) += ddr3_read_leveling.o
obj-$(CONFIG_SPL_BUILD) += ddr3_sdram.o
obj-$(CONFIG_SPL_BUILD) += ddr3_spd.o
obj-$(CONFIG_SPL_BUILD) += ddr3_write_leveling.o
obj-$(CONFIG_SPL_BUILD) += xor.o
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/ddr3_axp.h
+512
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@@ -0,0 +1,512 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef __DDR3_AXP_H
#define __DDR3_AXP_H
#define MV_78XX0_Z1_REV 0x0
#define MV_78XX0_A0_REV 0x1
#define MV_78XX0_B0_REV 0x2
#define SAR_DDR3_FREQ_MASK 0xFE00000
#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24))
#define MAX_CS 4
#define MIN_DIMM_ADDR 0x50
#define FAR_END_DIMM_ADDR 0x50
#define MAX_DIMM_ADDR 0x60
#ifndef CONFIG_DDR_FIXED_SIZE
#define SDRAM_CS_SIZE 0xFFFFFFF
#else
#define SDRAM_CS_SIZE (CONFIG_DDR_FIXED_SIZE - 1)
#endif
#define SDRAM_CS_BASE 0x0
#define SDRAM_DIMM_SIZE 0x80000000
#define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100))
#define CPU_MRVL_ID_OFFSET 0x10
#define SAR1_CPU_CORE_MASK 0x00000018
#define SAR1_CPU_CORE_OFFSET 3
/* Only enable ECC if the board selects it */
#ifdef CONFIG_BOARD_ECC_SUPPORT
#define ECC_SUPPORT
#endif
#define NEW_FABRIC_TWSI_ADDR 0x4E
#ifdef CONFIG_DB_784MP_GP
#define BUS_WIDTH_ECC_TWSI_ADDR 0x4E
#else
#define BUS_WIDTH_ECC_TWSI_ADDR 0x4F
#endif
#define MV_MAX_DDR3_STATIC_SIZE 50
#define MV_DDR3_MODES_NUMBER 30
#define RESUME_RL_PATTERNS_ADDR (0xFE0000)
#define RESUME_RL_PATTERNS_SIZE (0x100)
#define RESUME_TRAINING_VALUES_ADDR (RESUME_RL_PATTERNS_ADDR + RESUME_RL_PATTERNS_SIZE)
#define RESUME_TRAINING_VALUES_MAX (0xCD0)
#define BOOT_INFO_ADDR (RESUME_RL_PATTERNS_ADDR + 0x1000)
#define CHECKSUM_RESULT_ADDR (BOOT_INFO_ADDR + 0x1000)
#define NUM_OF_REGISTER_ADDR (CHECKSUM_RESULT_ADDR + 4)
#define SUSPEND_MAGIC_WORD (0xDEADB002)
#define REGISTER_LIST_END (0xFFFFFFFF)
/*
* Registers offset
*/
#define REG_SAMPLE_RESET_LOW_ADDR 0x18230
#define REG_SAMPLE_RESET_HIGH_ADDR 0x18234
#define REG_SAMPLE_RESET_CPU_FREQ_OFFS 21
#define REG_SAMPLE_RESET_CPU_FREQ_MASK 0x00E00000
#define REG_SAMPLE_RESET_FAB_OFFS 24
#define REG_SAMPLE_RESET_FAB_MASK 0xF000000
#define REG_SAMPLE_RESET_TCLK_OFFS 28
#define REG_SAMPLE_RESET_CPU_ARCH_OFFS 31
#define REG_SAMPLE_RESET_HIGH_CPU_FREQ_OFFS 20
/* MISC */
/*
* In mainline U-Boot we're re-configuring the mvebu base address
* register to 0xf1000000. So need to use this value for the DDR
* training code as well.
*/
#define INTER_REGS_BASE SOC_REGS_PHY_BASE
/* DDR */
#define REG_SDRAM_CONFIG_ADDR 0x1400
#define REG_SDRAM_CONFIG_MASK 0x9FFFFFFF
#define REG_SDRAM_CONFIG_RFRS_MASK 0x3FFF
#define REG_SDRAM_CONFIG_WIDTH_OFFS 15
#define REG_SDRAM_CONFIG_REGDIMM_OFFS 17
#define REG_SDRAM_CONFIG_ECC_OFFS 18
#define REG_SDRAM_CONFIG_IERR_OFFS 19
#define REG_SDRAM_CONFIG_PUPRSTDIV_OFFS 28
#define REG_SDRAM_CONFIG_RSTRD_OFFS 30
#define REG_DUNIT_CTRL_LOW_ADDR 0x1404
#define REG_DUNIT_CTRL_LOW_2T_OFFS 3
#define REG_DUNIT_CTRL_LOW_2T_MASK 0x3
#define REG_DUNIT_CTRL_LOW_DPDE_OFFS 14
#define REG_SDRAM_TIMING_LOW_ADDR 0x1408
#define REG_SDRAM_TIMING_HIGH_ADDR 0x140C
#define REG_SDRAM_TIMING_H_R2R_OFFS 7
#define REG_SDRAM_TIMING_H_R2R_MASK 0x3
#define REG_SDRAM_TIMING_H_R2W_W2R_OFFS 9
#define REG_SDRAM_TIMING_H_R2W_W2R_MASK 0x3
#define REG_SDRAM_TIMING_H_W2W_OFFS 11
#define REG_SDRAM_TIMING_H_W2W_MASK 0x1F
#define REG_SDRAM_TIMING_H_R2R_H_OFFS 19
#define REG_SDRAM_TIMING_H_R2R_H_MASK 0x7
#define REG_SDRAM_TIMING_H_R2W_W2R_H_OFFS 22
#define REG_SDRAM_TIMING_H_R2W_W2R_H_MASK 0x7
#define REG_SDRAM_ADDRESS_CTRL_ADDR 0x1410
#define REG_SDRAM_ADDRESS_SIZE_OFFS 2
#define REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS 18
#define REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS 4
#define REG_SDRAM_OPEN_PAGES_ADDR 0x1414
#define REG_SDRAM_OPERATION_CS_OFFS 8
#define REG_SDRAM_OPERATION_ADDR 0x1418
#define REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS 24
#define REG_SDRAM_OPERATION_CWA_DATA_OFFS 20
#define REG_SDRAM_OPERATION_CWA_DATA_MASK 0xF
#define REG_SDRAM_OPERATION_CWA_RC_OFFS 16
#define REG_SDRAM_OPERATION_CWA_RC_MASK 0xF
#define REG_SDRAM_OPERATION_CMD_MR0 0xF03
#define REG_SDRAM_OPERATION_CMD_MR1 0xF04
#define REG_SDRAM_OPERATION_CMD_MR2 0xF08
#define REG_SDRAM_OPERATION_CMD_MR3 0xF09
#define REG_SDRAM_OPERATION_CMD_RFRS 0xF02
#define REG_SDRAM_OPERATION_CMD_CWA 0xF0E
#define REG_SDRAM_OPERATION_CMD_RFRS_DONE 0xF
#define REG_SDRAM_OPERATION_CMD_MASK 0xF
#define REG_SDRAM_OPERATION_CS_OFFS 8
#define REG_OUDDR3_TIMING_ADDR 0x142C
#define REG_SDRAM_MODE_ADDR 0x141C
#define REG_SDRAM_EXT_MODE_ADDR 0x1420
#define REG_DDR_CONT_HIGH_ADDR 0x1424
#define REG_ODT_TIME_LOW_ADDR 0x1428
#define REG_ODT_ON_CTL_RD_OFFS 12
#define REG_ODT_OFF_CTL_RD_OFFS 16
#define REG_SDRAM_ERROR_ADDR 0x1454
#define REG_SDRAM_AUTO_PWR_SAVE_ADDR 0x1474
#define REG_ODT_TIME_HIGH_ADDR 0x147C
#define REG_SDRAM_INIT_CTRL_ADDR 0x1480
#define REG_SDRAM_INIT_CTRL_OFFS 0
#define REG_SDRAM_INIT_CKE_ASSERT_OFFS 2
#define REG_SDRAM_INIT_RESET_DEASSERT_OFFS 3
#define REG_SDRAM_ODT_CTRL_LOW_ADDR 0x1494
#define REG_SDRAM_ODT_CTRL_HIGH_ADDR 0x1498
/*#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_MASK 0xFFFFFF55 */
#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_MASK 0x0
#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_ENA 0x3
#define REG_DUNIT_ODT_CTRL_ADDR 0x149C
#define REG_DUNIT_ODT_CTRL_OVRD_OFFS 8
#define REG_DUNIT_ODT_CTRL_OVRD_VAL_OFFS 9
#define REG_DRAM_FIFO_CTRL_ADDR 0x14A0
#define REG_DRAM_AXI_CTRL_ADDR 0x14A8
#define REG_DRAM_AXI_CTRL_AXIDATABUSWIDTH_OFFS 0
#define REG_METAL_MASK_ADDR 0x14B0
#define REG_METAL_MASK_MASK 0xDFFFFFFF
#define REG_METAL_MASK_RETRY_OFFS 0
#define REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR 0x14C0
#define REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR 0x14C4
#define REG_DRAM_VER_CAL_MACHINE_CTRL_ADDR 0x14c8
#define REG_DRAM_MAIN_PADS_CAL_ADDR 0x14CC
#define REG_DRAM_HOR_CAL_MACHINE_CTRL_ADDR 0x17c8
#define REG_CS_SIZE_SCRATCH_ADDR 0x1504
#define REG_DYNAMIC_POWER_SAVE_ADDR 0x1520
#define REG_DDR_IO_ADDR 0x1524
#define REG_DDR_IO_CLK_RATIO_OFFS 15
#define REG_DFS_ADDR 0x1528
#define REG_DFS_DLLNEXTSTATE_OFFS 0
#define REG_DFS_BLOCK_OFFS 1
#define REG_DFS_SR_OFFS 2
#define REG_DFS_ATSR_OFFS 3
#define REG_DFS_RECONF_OFFS 4
#define REG_DFS_CL_NEXT_STATE_OFFS 8
#define REG_DFS_CL_NEXT_STATE_MASK 0xF
#define REG_DFS_CWL_NEXT_STATE_OFFS 12
#define REG_DFS_CWL_NEXT_STATE_MASK 0x7
#define REG_READ_DATA_SAMPLE_DELAYS_ADDR 0x1538
#define REG_READ_DATA_SAMPLE_DELAYS_MASK 0x1F
#define REG_READ_DATA_SAMPLE_DELAYS_OFFS 8
#define REG_READ_DATA_READY_DELAYS_ADDR 0x153C
#define REG_READ_DATA_READY_DELAYS_MASK 0x1F
#define REG_READ_DATA_READY_DELAYS_OFFS 8
#define START_BURST_IN_ADDR 1
#define REG_DRAM_TRAINING_SHADOW_ADDR 0x18488
#define REG_DRAM_TRAINING_ADDR 0x15B0
#define REG_DRAM_TRAINING_LOW_FREQ_OFFS 0
#define REG_DRAM_TRAINING_PATTERNS_OFFS 4
#define REG_DRAM_TRAINING_MED_FREQ_OFFS 2
#define REG_DRAM_TRAINING_WL_OFFS 3
#define REG_DRAM_TRAINING_RL_OFFS 6
#define REG_DRAM_TRAINING_DQS_RX_OFFS 15
#define REG_DRAM_TRAINING_DQS_TX_OFFS 16
#define REG_DRAM_TRAINING_CS_OFFS 20
#define REG_DRAM_TRAINING_RETEST_OFFS 24
#define REG_DRAM_TRAINING_DFS_FREQ_OFFS 27
#define REG_DRAM_TRAINING_DFS_REQ_OFFS 29
#define REG_DRAM_TRAINING_ERROR_OFFS 30
#define REG_DRAM_TRAINING_AUTO_OFFS 31
#define REG_DRAM_TRAINING_RETEST_PAR 0x3
#define REG_DRAM_TRAINING_RETEST_MASK 0xF8FFFFFF
#define REG_DRAM_TRAINING_CS_MASK 0xFF0FFFFF
#define REG_DRAM_TRAINING_PATTERNS_MASK 0xFF0F0000
#define REG_DRAM_TRAINING_1_ADDR 0x15B4
#define REG_DRAM_TRAINING_1_TRNBPOINT_OFFS 16
#define REG_DRAM_TRAINING_2_ADDR 0x15B8
#define REG_DRAM_TRAINING_2_OVERRUN_OFFS 17
#define REG_DRAM_TRAINING_2_FIFO_RST_OFFS 4
#define REG_DRAM_TRAINING_2_RL_MODE_OFFS 3
#define REG_DRAM_TRAINING_2_WL_MODE_OFFS 2
#define REG_DRAM_TRAINING_2_ECC_MUX_OFFS 1
#define REG_DRAM_TRAINING_2_SW_OVRD_OFFS 0
#define REG_DRAM_TRAINING_PATTERN_BASE_ADDR 0x15BC
#define REG_DRAM_TRAINING_PATTERN_BASE_OFFS 3
#define REG_TRAINING_DEBUG_2_ADDR 0x15C4
#define REG_TRAINING_DEBUG_2_OFFS 16
#define REG_TRAINING_DEBUG_2_MASK 0x3
#define REG_TRAINING_DEBUG_3_ADDR 0x15C8
#define REG_TRAINING_DEBUG_3_OFFS 3
#define REG_TRAINING_DEBUG_3_MASK 0x7
#define MR_CS_ADDR_OFFS 4
#define REG_DDR3_MR0_ADDR 0x15D0
#define REG_DDR3_MR0_CS_ADDR 0x1870
#define REG_DDR3_MR0_CL_MASK 0x74
#define REG_DDR3_MR0_CL_OFFS 2
#define REG_DDR3_MR0_CL_HIGH_OFFS 3
#define CL_MASK 0xF
#define REG_DDR3_MR1_ADDR 0x15D4
#define REG_DDR3_MR1_CS_ADDR 0x1874
#define REG_DDR3_MR1_RTT_MASK 0xFFFFFDBB
#define REG_DDR3_MR1_DLL_ENA_OFFS 0
#define REG_DDR3_MR1_RTT_DISABLED 0x0
#define REG_DDR3_MR1_RTT_RZQ2 0x40
#define REG_DDR3_MR1_RTT_RZQ4 0x2
#define REG_DDR3_MR1_RTT_RZQ6 0x42
#define REG_DDR3_MR1_RTT_RZQ8 0x202
#define REG_DDR3_MR1_RTT_RZQ12 0x4
#define REG_DDR3_MR1_OUTBUF_WL_MASK 0xFFFFEF7F /* WL-disabled,OB-enabled */
#define REG_DDR3_MR1_OUTBUF_DIS_OFFS 12 /* Output Buffer Disabled */
#define REG_DDR3_MR1_WL_ENA_OFFS 7
#define REG_DDR3_MR1_WL_ENA 0x80 /* WL Enabled */
#define REG_DDR3_MR1_ODT_MASK 0xFFFFFDBB
#define REG_DDR3_MR2_ADDR 0x15D8
#define REG_DDR3_MR2_CS_ADDR 0x1878
#define REG_DDR3_MR2_CWL_OFFS 3
#define REG_DDR3_MR2_CWL_MASK 0x7
#define REG_DDR3_MR2_ODT_MASK 0xFFFFF9FF
#define REG_DDR3_MR3_ADDR 0x15DC
#define REG_DDR3_MR3_CS_ADDR 0x187C
#define REG_DDR3_RANK_CTRL_ADDR 0x15E0
#define REG_DDR3_RANK_CTRL_CS_ENA_MASK 0xF
#define REG_DDR3_RANK_CTRL_MIRROR_OFFS 4
#define REG_ZQC_CONF_ADDR 0x15E4
#define REG_DRAM_PHY_CONFIG_ADDR 0x15EC
#define REG_DRAM_PHY_CONFIG_MASK 0x3FFFFFFF
#define REG_ODPG_CNTRL_ADDR 0x1600
#define REG_ODPG_CNTRL_OFFS 21
#define REG_PHY_LOCK_MASK_ADDR 0x1670
#define REG_PHY_LOCK_MASK_MASK 0xFFFFF000
#define REG_PHY_LOCK_STATUS_ADDR 0x1674
#define REG_PHY_LOCK_STATUS_LOCK_OFFS 9
#define REG_PHY_LOCK_STATUS_LOCK_MASK 0xFFF
#define REG_PHY_LOCK_APLL_ADLL_STATUS_MASK 0x7FF
#define REG_PHY_REGISTRY_FILE_ACCESS_ADDR 0x16A0
#define REG_PHY_REGISTRY_FILE_ACCESS_OP_WR 0xC0000000
#define REG_PHY_REGISTRY_FILE_ACCESS_OP_RD 0x80000000
#define REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE 0x80000000
#define REG_PHY_BC_OFFS 27
#define REG_PHY_CNTRL_OFFS 26
#define REG_PHY_CS_OFFS 16
#define REG_PHY_DQS_REF_DLY_OFFS 10
#define REG_PHY_PHASE_OFFS 8
#define REG_PHY_PUP_OFFS 22
#define REG_TRAINING_WL_ADDR 0x16AC
#define REG_TRAINING_WL_CS_MASK 0xFFFFFFFC
#define REG_TRAINING_WL_UPD_OFFS 2
#define REG_TRAINING_WL_CS_DONE_OFFS 3
#define REG_TRAINING_WL_RATIO_MASK 0xFFFFFF0F
#define REG_TRAINING_WL_1TO1 0x50
#define REG_TRAINING_WL_2TO1 0x10
#define REG_TRAINING_WL_DELAYEXP_MASK 0x20000000
#define REG_TRAINING_WL_RESULTS_MASK 0x000001FF
#define REG_TRAINING_WL_RESULTS_OFFS 20
#define REG_REGISTERED_DRAM_CTRL_ADDR 0x16D0
#define REG_REGISTERED_DRAM_CTRL_SR_FLOAT_OFFS 15
#define REG_REGISTERED_DRAM_CTRL_PARITY_MASK 0x3F
/* DLB*/
#define REG_STATIC_DRAM_DLB_CONTROL 0x1700
#define DLB_BUS_OPTIMIZATION_WEIGHTS_REG 0x1704
#define DLB_AGING_REGISTER 0x1708
#define DLB_EVICTION_CONTROL_REG 0x170c
#define DLB_EVICTION_TIMERS_REGISTER_REG 0x1710
#define DLB_ENABLE 0x1
#define DLB_WRITE_COALESING (0x1 << 2)
#define DLB_AXI_PREFETCH_EN (0x1 << 3)
#define DLB_MBUS_PREFETCH_EN (0x1 << 4)
#define PREFETCH_NLNSZTR (0x1 << 6)
/* CPU */
#define REG_BOOTROM_ROUTINE_ADDR 0x182D0
#define REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS 12
#define REG_DRAM_INIT_CTRL_STATUS_ADDR 0x18488
#define REG_DRAM_INIT_CTRL_TRN_CLK_OFFS 16
#define REG_CPU_DIV_CLK_CTRL_0_NEW_RATIO 0x000200FF
#define REG_DRAM_INIT_CTRL_STATUS_2_ADDR 0x1488
#define REG_CPU_DIV_CLK_CTRL_0_ADDR 0x18700
#define REG_CPU_DIV_CLK_CTRL_1_ADDR 0x18704
#define REG_CPU_DIV_CLK_CTRL_2_ADDR 0x18708
#define REG_CPU_DIV_CLK_CTRL_3_ADDR 0x1870C
#define REG_CPU_DIV_CLK_CTRL_3_FREQ_MASK 0xFFFFC0FF
#define REG_CPU_DIV_CLK_CTRL_3_FREQ_OFFS 8
#define REG_CPU_DIV_CLK_CTRL_4_ADDR 0x18710
#define REG_CPU_DIV_CLK_STATUS_0_ADDR 0x18718
#define REG_CPU_DIV_CLK_ALL_STABLE_OFFS 8
#define REG_CPU_PLL_CTRL_0_ADDR 0x1871C
#define REG_CPU_PLL_STATUS_0_ADDR 0x18724
#define REG_CORE_DIV_CLK_CTRL_ADDR 0x18740
#define REG_CORE_DIV_CLK_STATUS_ADDR 0x18744
#define REG_DDRPHY_APLL_CTRL_ADDR 0x18780
#define REG_DDRPHY_APLL_CTRL_2_ADDR 0x18784
#define REG_SFABRIC_CLK_CTRL_ADDR 0x20858
#define REG_SFABRIC_CLK_CTRL_SMPL_OFFS 8
/* DRAM Windows */
#define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8
#define REG_XBAR_WIN_4_CTRL_ADDR 0x20040
#define REG_XBAR_WIN_4_BASE_ADDR 0x20044
#define REG_XBAR_WIN_4_REMAP_ADDR 0x20048
#define REG_FASTPATH_WIN_0_CTRL_ADDR 0x20184
#define REG_XBAR_WIN_7_REMAP_ADDR 0x20078
/* SRAM */
#define REG_CDI_CONFIG_ADDR 0x20220
#define REG_SRAM_WINDOW_0_ADDR 0x20240
#define REG_SRAM_WINDOW_0_ENA_OFFS 0
#define REG_SRAM_WINDOW_1_ADDR 0x20244
#define REG_SRAM_L2_ENA_ADDR 0x8500
#define REG_SRAM_CLEAN_BY_WAY_ADDR 0x87BC
/* PMU */
#define REG_PMU_I_F_CTRL_ADDR 0x1C090
#define REG_PMU_DUNIT_BLK_OFFS 16
#define REG_PMU_DUNIT_RFRS_OFFS 20
#define REG_PMU_DUNIT_ACK_OFFS 24
/* MBUS*/
#define MBUS_UNITS_PRIORITY_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x420)
#define FABRIC_UNITS_PRIORITY_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x424)
#define MBUS_UNITS_PREFETCH_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x428)
#define FABRIC_UNITS_PREFETCH_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x42c)
#define REG_PM_STAT_MASK_ADDR 0x2210C
#define REG_PM_STAT_MASK_CPU0_IDLE_MASK_OFFS 16
#define REG_PM_EVENT_STAT_MASK_ADDR 0x22120
#define REG_PM_EVENT_STAT_MASK_DFS_DONE_OFFS 17
#define REG_PM_CTRL_CONFIG_ADDR 0x22104
#define REG_PM_CTRL_CONFIG_DFS_REQ_OFFS 18
#define REG_FABRIC_LOCAL_IRQ_MASK_ADDR 0x218C4
#define REG_FABRIC_LOCAL_IRQ_PMU_MASK_OFFS 18
/* Controller revision info */
#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
#define PCCRIR_REVID_OFFS 0 /* Revision ID */
#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS)
/* Power Management Clock Gating Control Register */
#define MV_PEX_IF_REGS_OFFSET(if) \
(if < 8 ? (0x40000 + ((if) / 4) * 0x40000 + ((if) % 4) * 0x4000) \
: (0x42000 + ((if) % 8) * 0x40000))
#define MV_PEX_IF_REGS_BASE(unit) (MV_PEX_IF_REGS_OFFSET(unit))
#define POWER_MNG_CTRL_REG 0x18220
#define PEX_DEVICE_AND_VENDOR_ID 0x000
#define PEX_CFG_DIRECT_ACCESS(if, reg) (MV_PEX_IF_REGS_BASE(if) + (reg))
#define PMC_PEXSTOPCLOCK_OFFS(port) ((port) < 8 ? (5 + (port)) : (18 + (port)))
#define PMC_PEXSTOPCLOCK_MASK(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port))
#define PMC_PEXSTOPCLOCK_EN(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port))
#define PMC_PEXSTOPCLOCK_STOP(port) (0 << PMC_PEXSTOPCLOCK_OFFS(port))
/* TWSI */
#define TWSI_DATA_ADDR_MASK 0x7
#define TWSI_DATA_ADDR_OFFS 1
/* General */
#define MAX_CS 4
/* Frequencies */
#define FAB_OPT 21
#define CLK_CPU 12
#define CLK_VCO (2 * CLK_CPU)
#define CLK_DDR 12
/* Cpu Frequencies: */
#define CLK_CPU_1000 0
#define CLK_CPU_1066 1
#define CLK_CPU_1200 2
#define CLK_CPU_1333 3
#define CLK_CPU_1500 4
#define CLK_CPU_1666 5
#define CLK_CPU_1800 6
#define CLK_CPU_2000 7
#define CLK_CPU_600 8
#define CLK_CPU_667 9
#define CLK_CPU_800 0xa
/* Extra Cpu Frequencies: */
#define CLK_CPU_1600 11
#define CLK_CPU_2133 12
#define CLK_CPU_2200 13
#define CLK_CPU_2400 14
/* DDR3 Frequencies: */
#define DDR_100 0
#define DDR_300 1
#define DDR_333 1
#define DDR_360 2
#define DDR_400 3
#define DDR_444 4
#define DDR_500 5
#define DDR_533 6
#define DDR_600 7
#define DDR_640 8
#define DDR_666 8
#define DDR_720 9
#define DDR_750 9
#define DDR_800 10
#define DDR_833 11
#define DDR_HCLK 20
#define DDR_S 12
#define DDR_S_1TO1 13
#define MARGIN_FREQ DDR_400
#define DFS_MARGIN DDR_100
#define ODT_OPT 16
#define ODT20 0x200
#define ODT30 0x204
#define ODT40 0x44
#define ODT120 0x40
#define ODT120D 0x400
#define MRS_DELAY 100
#define SDRAM_WL_SW_OFFS 0x100
#define SDRAM_RL_OFFS 0x0
#define SDRAM_PBS_I_OFFS 0x140
#define SDRAM_PBS_II_OFFS 0x180
#define SDRAM_PBS_NEXT_OFFS (SDRAM_PBS_II_OFFS - SDRAM_PBS_I_OFFS)
#define SDRAM_PBS_TX_OFFS 0x180
#define SDRAM_PBS_TX_DM_OFFS 576
#define SDRAM_DQS_RX_OFFS 1024
#define SDRAM_DQS_TX_OFFS 2048
#define SDRAM_DQS_RX_SPECIAL_OFFS 5120
#define LEN_STD_PATTERN 16
#define LEN_KILLER_PATTERN 128
#define LEN_SPECIAL_PATTERN 128
#define LEN_PBS_PATTERN 16
#endif /* __DDR3_AXP_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/ddr3_axp_config.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef __DDR3_AXP_CONFIG_H
#define __DDR3_AXP_CONFIG_H
/*
* DDR3_LOG_LEVEL Information
*
* Level 0: Provides an error code in a case of failure, RL, WL errors
* and other algorithm failure
* Level 1: Provides the D-Unit setup (SPD/Static configuration)
* Level 2: Provides the windows margin as a results of DQS centeralization
* Level 3: Provides the windows margin of each DQ as a results of DQS
* centeralization
*/
#ifdef CONFIG_DDR_LOG_LEVEL
#define DDR3_LOG_LEVEL CONFIG_DDR_LOG_LEVEL
#else
#define DDR3_LOG_LEVEL 0
#endif
#define DDR3_PBS 1
/* This flag allows the execution of SW WL/RL upon HW failure */
#define DDR3_RUN_SW_WHEN_HW_FAIL 1
/*
* General Configurations
*
* The following parameters are required for proper setup:
*
* DDR_TARGET_FABRIC - Set desired fabric configuration
* (for sample@Reset fabfreq parameter)
* DRAM_ECC - Set ECC support 1/0
* BUS_WIDTH - 64/32 bit
* CONFIG_SPD_EEPROM - Enables auto detection of DIMMs and their timing values
* DQS_CLK_ALIGNED - Set this if CLK and DQS signals are aligned on board
* MIXED_DIMM_STATIC - Mixed DIMM + On board devices support (ODT registers
* values are taken statically)
* DDR3_TRAINING_DEBUG - Debug prints of internal code
*/
#define DDR_TARGET_FABRIC 5
/* Only enable ECC if the board selects it */
#ifdef CONFIG_BOARD_ECC_SUPPORT
#define DRAM_ECC 1
#else
#define DRAM_ECC 0
#endif
#ifdef CONFIG_DDR_32BIT
#define BUS_WIDTH 32
#else
#define BUS_WIDTH 64
#endif
#undef DQS_CLK_ALIGNED
#undef MIXED_DIMM_STATIC
#define DDR3_TRAINING_DEBUG 0
#define REG_DIMM_SKIP_WL 0
/* Marvell boards specific configurations */
#if defined(DB_78X60_PCAC)
#undef CONFIG_SPD_EEPROM
#define STATIC_TRAINING
#endif
#if defined(DB_78X60_AMC)
#undef CONFIG_SPD_EEPROM
#undef DRAM_ECC
#define DRAM_ECC 1
#endif
#ifdef CONFIG_SPD_EEPROM
/*
* DIMM support parameters:
* DRAM_2T - Set Desired 2T Mode - 0 - 1T, 0x1 - 2T, 0x2 - 3T
* DIMM_CS_BITMAP - bitmap representing the optional CS in DIMMs
* (0xF=CS0+CS1+CS2+CS3, 0xC=CS2+CS3...)
*/
#define DRAM_2T 0x0
#define DIMM_CS_BITMAP 0xF
#define DUNIT_SPD
#endif
#ifdef DRAM_ECC
/*
* ECC support parameters:
*
* U_BOOT_START_ADDR, U_BOOT_SCRUB_SIZE - relevant when using ECC and need
* to configure the scrubbing area
*/
#define TRAINING_SIZE 0x20000
#define U_BOOT_START_ADDR 0
#define U_BOOT_SCRUB_SIZE 0x1000000 /* TRAINING_SIZE */
#endif
/*
* Registered DIMM Support - In case registered DIMM is attached,
* please supply the following values:
* (see JEDEC - JESD82-29A "Definition of the SSTE32882 Registering Clock
* Driver with Parity and Quad Chip
* Selects for DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V Applications")
* RC0: Global Features Control Word
* RC1: Clock Driver Enable Control Word
* RC2: Timing Control Word
* RC3-RC5 - taken from SPD
* RC8: Additional IBT Setting Control Word
* RC9: Power Saving Settings Control Word
* RC10: Encoding for RDIMM Operating Speed
* RC11: Operating Voltage VDD and VREFCA Control Word
*/
#define RDIMM_RC0 0
#define RDIMM_RC1 0
#define RDIMM_RC2 0
#define RDIMM_RC8 0
#define RDIMM_RC9 0
#define RDIMM_RC10 0x2
#define RDIMM_RC11 0x0
#if defined(MIXED_DIMM_STATIC) || !defined(CONFIG_SPD_EEPROM)
#define DUNIT_STATIC
#endif
#if defined(MIXED_DIMM_STATIC) || defined(CONFIG_SPD_EEPROM)
/*
* This flag allows the user to change the dram refresh cycle in ps,
* only in case of SPD or MIX DIMM topology
*/
#define TREFI_USER_EN
#ifdef TREFI_USER_EN
#define TREFI_USER 3900000
#endif
#endif
#ifdef CONFIG_SPD_EEPROM
/*
* AUTO_DETECTION_SUPPORT - relevant ONLY for Marvell DB boards.
* Enables I2C auto detection different options
*/
#if defined(CONFIG_DB_88F78X60) || defined(CONFIG_DB_88F78X60_REV2) || \
defined(CONFIG_DB_784MP_GP)
#define AUTO_DETECTION_SUPPORT
#endif
#endif
#endif /* __DDR3_AXP_CONFIG_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef __AXP_MC_STATIC_H
#define __AXP_MC_STATIC_H
MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = {
#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
#else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
#endif
{0x00001404, 0x3630b800}, /*Dunit Control Low Register */
{0x00001408, 0x43149775}, /*DDR SDRAM Timing (Low) Register */
/* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
{0x0000140C, 0x38d83fe0}, /*DDR SDRAM Timing (High) Register */
#ifdef DB_78X60_PCAC
{0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */
#else
{0x00001410, 0x040F0000}, /*DDR SDRAM Open Pages Control Register */
#endif
{0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
{0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
{0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
{0x00001424, 0x0000D3FF}, /*Dunit Control High Register */
{0x00001428, 0x000F8830}, /*Dunit Control High Register */
{0x0000142C, 0x214C2F38}, /*Dunit Control High Register */
{0x0000147C, 0x0000c671},
{0x000014a0, 0x000002A9},
{0x000014a8, 0x00000101}, /*2:1 */
{0x00020220, 0x00000007},
{0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
{0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
{0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */
{0x000014C0, 0x192434e9}, /* DRAM address and Control Driving Strenght */
{0x000014C4, 0x092434e9}, /* DRAM Data and DQS Driving Strenght */
{0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
{0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
{0x0001504, 0x7FFFFFF1}, /* CS0 Size */
{0x000150C, 0x00000000}, /* CS1 Size */
{0x0001514, 0x00000000}, /* CS2 Size */
{0x000151C, 0x00000000}, /* CS3 Size */
/* {0x00001524, 0x0000C800}, */
{0x00001538, 0x0000000b}, /*Read Data Sample Delays Register */
{0x0000153C, 0x0000000d}, /*Read Data Ready Delay Register */
{0x000015D0, 0x00000640}, /*MR0 */
{0x000015D4, 0x00000046}, /*MR1 */
{0x000015D8, 0x00000010}, /*MR2 */
{0x000015DC, 0x00000000}, /*MR3 */
{0x000015E4, 0x00203c18}, /*ZQC Configuration Register */
{0x000015EC, 0xd800aa25}, /*DDR PHY */
{0x0, 0x0}
};
MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = {
#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
#else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
#endif
{0x00001404, 0x3630b800}, /*Dunit Control Low Register */
{0x00001408, 0x43149775}, /*DDR SDRAM Timing (Low) Register */
/* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
{0x0000140C, 0x38d83fe0}, /*DDR SDRAM Timing (High) Register */
#ifdef DB_78X60_PCAC
{0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */
#else
{0x00001410, 0x040F000C}, /*DDR SDRAM Open Pages Control Register */
#endif
{0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
{0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
{0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
{0x00001424, 0x0000D3FF}, /*Dunit Control High Register */
{0x00001428, 0x000F8830}, /*Dunit Control High Register */
{0x0000142C, 0x214C2F38}, /*Dunit Control High Register */
{0x0000147C, 0x0000c671},
{0x000014a0, 0x000002A9},
{0x000014a8, 0x00000101}, /*2:1 */
{0x00020220, 0x00000007},
{0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
{0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
{0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */
{0x000014C0, 0x192434e9}, /* DRAM address and Control Driving Strenght */
{0x000014C4, 0x092434e9}, /* DRAM Data and DQS Driving Strenght */
{0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
{0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
{0x0001504, 0x3FFFFFF1}, /* CS0 Size */
{0x000150C, 0x00000000}, /* CS1 Size */
{0x0001514, 0x00000000}, /* CS2 Size */
{0x000151C, 0x00000000}, /* CS3 Size */
/* {0x00001524, 0x0000C800}, */
{0x00001538, 0x0000000b}, /*Read Data Sample Delays Register */
{0x0000153C, 0x0000000d}, /*Read Data Ready Delay Register */
{0x000015D0, 0x00000640}, /*MR0 */
{0x000015D4, 0x00000046}, /*MR1 */
{0x000015D8, 0x00000010}, /*MR2 */
{0x000015DC, 0x00000000}, /*MR3 */
{0x000015E4, 0x00203c18}, /*ZQC Configuration Register */
{0x000015EC, 0xd800aa25}, /*DDR PHY */
{0x0, 0x0}
};
MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = {
#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */
#else /* CONFIG_DDR_64BIT */
{0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */
#endif
{0x00001404, 0x3630B840}, /*Dunit Control Low Register */
{0x00001408, 0x33137663}, /*DDR SDRAM Timing (Low) Register */
{0x0000140C, 0x38000C55}, /*DDR SDRAM Timing (High) Register */
{0x00001410, 0x040F0000}, /*DDR SDRAM Address Control Register */
{0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
{0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
{0x0000141C, 0x00000672}, /*DDR SDRAM Mode Register */
{0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
{0x00001424, 0x0100D3FF}, /*Dunit Control High Register */
{0x00001428, 0x000D6720}, /*Dunit Control High Register */
{0x0000142C, 0x014C2F38}, /*Dunit Control High Register */
{0x0000147C, 0x00006571},
{0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
{0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
{0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */
{0x000014a0, 0x000002A9},
{0x000014a8, 0x00000101}, /*2:1 */
{0x00020220, 0x00000007},
{0x000014C0, 0x192424C8}, /* DRAM address and Control Driving Strenght */
{0x000014C4, 0xEFB24C8}, /* DRAM Data and DQS Driving Strenght */
{0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
{0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
{0x0001504, 0x7FFFFFF1}, /* CS0 Size */
{0x000150C, 0x00000000}, /* CS1 Size */
{0x0001514, 0x00000000}, /* CS2 Size */
{0x000151C, 0x00000000}, /* CS3 Size */
{0x00001538, 0x00000008}, /*Read Data Sample Delays Register */
{0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */
{0x000015D0, 0x00000630}, /*MR0 */
{0x000015D4, 0x00000046}, /*MR1 */
{0x000015D8, 0x00000008}, /*MR2 */
{0x000015DC, 0x00000000}, /*MR3 */
{0x000015E4, 0x00203c18}, /*ZQDS Configuration Register */
/* {0x000015EC, 0xDE000025}, *//*DDR PHY */
{0x000015EC, 0xF800AA25}, /*DDR PHY */
{0x0, 0x0}
};
MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = {
#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */
#else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
#endif
{0x00001404, 0x3630B040}, /*Dunit Control Low Register */
{0x00001408, 0x44149887}, /*DDR SDRAM Timing (Low) Register */
/* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
{0x0000140C, 0x38D83FE0}, /*DDR SDRAM Timing (High) Register */
#ifdef DB_78X60_PCAC
{0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */
#else
{0x00001410, 0x040F0000}, /*DDR SDRAM Open Pages Control Register */
#endif
{0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
{0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
{0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
{0x00001424, 0x0100D1FF}, /*Dunit Control High Register */
{0x00001428, 0x000F8830}, /*Dunit Control High Register */
{0x0000142C, 0x214C2F38}, /*Dunit Control High Register */
{0x0000147C, 0x0000c671},
{0x000014a8, 0x00000101}, /*2:1 */
{0x00020220, 0x00000007},
{0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
{0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
{0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */
{0x000014C0, 0x192424C8}, /* DRAM address and Control Driving Strenght */
{0x000014C4, 0xEFB24C8}, /* DRAM Data and DQS Driving Strenght */
{0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
{0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
{0x0001504, 0x7FFFFFF1}, /* CS0 Size */
{0x000150C, 0x00000000}, /* CS1 Size */
{0x0001514, 0x00000000}, /* CS2 Size */
{0x000151C, 0x00000000}, /* CS3 Size */
/* {0x00001524, 0x0000C800}, */
{0x00001538, 0x0000000b}, /*Read Data Sample Delays Register */
{0x0000153C, 0x0000000d}, /*Read Data Ready Delay Register */
{0x000015D0, 0x00000650}, /*MR0 */
{0x000015D4, 0x00000046}, /*MR1 */
{0x000015D8, 0x00000010}, /*MR2 */
{0x000015DC, 0x00000000}, /*MR3 */
{0x000015E4, 0x00203c18}, /*ZQC Configuration Register */
{0x000015EC, 0xDE000025}, /*DDR PHY */
{0x0, 0x0}
};
MV_DRAM_MC_INIT ddr3_Z1_db_300[MV_MAX_DDR3_STATIC_SIZE] = {
#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */
#else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */
/*{0x00001400, 0x7304CC30}, *//*DDR SDRAM Configuration Register */
#endif
{0x00001404, 0x3630B840}, /*Dunit Control Low Register */
{0x00001408, 0x33137663}, /*DDR SDRAM Timing (Low) Register */
{0x0000140C, 0x38000C55}, /*DDR SDRAM Timing (High) Register */
{0x00001410, 0x040F0000}, /*DDR SDRAM Address Control Register */
{0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
{0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
{0x0000141C, 0x00000672}, /*DDR SDRAM Mode Register */
{0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
{0x00001424, 0x0100F1FF}, /*Dunit Control High Register */
{0x00001428, 0x000D6720}, /*Dunit Control High Register */
{0x0000142C, 0x014C2F38}, /*Dunit Control High Register */
{0x0000147C, 0x00006571},
{0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
{0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
{0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */
{0x000014C0, 0x192424C8}, /* DRAM address and Control Driving Strenght */
{0x000014C4, 0xEFB24C8}, /* DRAM Data and DQS Driving Strenght */
{0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
{0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
{0x0001504, 0x7FFFFFF1}, /* CS0 Size */
{0x000150C, 0x00000000}, /* CS1 Size */
{0x0001514, 0x00000000}, /* CS2 Size */
{0x000151C, 0x00000000}, /* CS3 Size */
{0x00001538, 0x00000008}, /*Read Data Sample Delays Register */
{0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */
{0x000015D0, 0x00000630}, /*MR0 */
{0x000015D4, 0x00000046}, /*MR1 */
{0x000015D8, 0x00000008}, /*MR2 */
{0x000015DC, 0x00000000}, /*MR3 */
{0x000015E4, 0x00203c18}, /*ZQDS Configuration Register */
{0x000015EC, 0xDE000025}, /*DDR PHY */
{0x0, 0x0}
};
#endif /* __AXP_MC_STATIC_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/ddr3_axp_training_static.h
+769
View File
@@ -0,0 +1,769 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef __AXP_TRAINING_STATIC_H
#define __AXP_TRAINING_STATIC_H
/*
* STATIC_TRAINING - Set only if static parameters for training are set and
* required
*/
MV_DRAM_TRAINING_INIT ddr3_db_rev2_667[MV_MAX_DDR3_STATIC_SIZE] = {
/* Read Leveling */
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
/*0 */
{0x000016A0, 0xC002011A},
/*1 */
{0x000016A0, 0xC0420100},
/*2 */
{0x000016A0, 0xC082020A},
/*3 */
{0x000016A0, 0xC0C20017},
/*4 */
{0x000016A0, 0xC1020113},
/*5 */
{0x000016A0, 0xC1420107},
/*6 */
{0x000016A0, 0xC182011F},
/*7 */
{0x000016A0, 0xC1C2001C},
/*8 */
{0x000016A0, 0xC202010D},
/* Write Leveling */
/*0 */
{0x000016A0, 0xC0004A06},
/*1 */
{0x000016A0, 0xC040690D},
/*2 */
{0x000016A0, 0xC0806A0D},
/*3 */
{0x000016A0, 0xC0C0A01B},
/*4 */
{0x000016A0, 0xC1003A01},
/*5 */
{0x000016A0, 0xC1408113},
/*6 */
{0x000016A0, 0xC1805609},
/*7 */
{0x000016A0, 0xC1C04504},
/*8 */
{0x000016A0, 0xC2009518},
/*center DQS on read cycle */
{0x000016A0, 0xC803000F},
{0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
{0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
/*init DRAM */
{0x00001480, 0x00000001},
{0x0, 0x0}
};
MV_DRAM_TRAINING_INIT ddr3_db_rev2_800[MV_MAX_DDR3_STATIC_SIZE] = {
/* Read Leveling */
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
/*0 */
{0x000016A0, 0xC0020301},
/*1 */
{0x000016A0, 0xC0420202},
/*2 */
{0x000016A0, 0xC0820314},
/*3 */
{0x000016A0, 0xC0C20117},
/*4 */
{0x000016A0, 0xC1020219},
/*5 */
{0x000016A0, 0xC142020B},
/*6 */
{0x000016A0, 0xC182030A},
/*7 */
{0x000016A0, 0xC1C2011D},
/*8 */
{0x000016A0, 0xC2020212},
/* Write Leveling */
/*0 */
{0x000016A0, 0xC0007A12},
/*1 */
{0x000016A0, 0xC0408D16},
/*2 */
{0x000016A0, 0xC0809E1B},
/*3 */
{0x000016A0, 0xC0C0AC1F},
/*4 */
{0x000016A0, 0xC1005E0A},
/*5 */
{0x000016A0, 0xC140A91D},
/*6 */
{0x000016A0, 0xC1808E17},
/*7 */
{0x000016A0, 0xC1C05509},
/*8 */
{0x000016A0, 0xC2003A01},
/* PBS Leveling */
/*0 */
{0x000016A0, 0xC0007A12},
/*1 */
{0x000016A0, 0xC0408D16},
/*2 */
{0x000016A0, 0xC0809E1B},
/*3 */
{0x000016A0, 0xC0C0AC1F},
/*4 */
{0x000016A0, 0xC1005E0A},
/*5 */
{0x000016A0, 0xC140A91D},
/*6 */
{0x000016A0, 0xC1808E17},
/*7 */
{0x000016A0, 0xC1C05509},
/*8 */
{0x000016A0, 0xC2003A01},
/*center DQS on read cycle */
{0x000016A0, 0xC803000B},
{0x00001538, 0x0000000D}, /*Read Data Sample Delays Register */
{0x0000153C, 0x00000011}, /*Read Data Ready Delay Register */
/*init DRAM */
{0x00001480, 0x00000001},
{0x0, 0x0}
};
MV_DRAM_TRAINING_INIT ddr3_db_400[MV_MAX_DDR3_STATIC_SIZE] = {
/* Read Leveling */
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
/*0 2 4 15 */
{0x000016A0, 0xC002010C},
/*1 2 4 2 */
{0x000016A0, 0xC042001C},
/*2 2 4 27 */
{0x000016A0, 0xC0820115},
/*3 2 4 0 */
{0x000016A0, 0xC0C20019},
/*4 2 4 13 */
{0x000016A0, 0xC1020108},
/*5 2 4 5 */
{0x000016A0, 0xC1420100},
/*6 2 4 19 */
{0x000016A0, 0xC1820111},
/*7 2 4 0 */
{0x000016A0, 0xC1C2001B},
/*8 2 4 10 */
/*{0x000016A0, 0xC2020117}, */
{0x000016A0, 0xC202010C},
/* Write Leveling */
/*0 */
{0x000016A0, 0xC0005508},
/*1 */
{0x000016A0, 0xC0409819},
/*2 */
{0x000016A0, 0xC080650C},
/*3 */
{0x000016A0, 0xC0C0700F},
/*4 */
{0x000016A0, 0xC1004103},
/*5 */
{0x000016A0, 0xC140A81D},
/*6 */
{0x000016A0, 0xC180650C},
/*7 */
{0x000016A0, 0xC1C08013},
/*8 */
{0x000016A0, 0xC2005508},
/*center DQS on read cycle */
{0x000016A0, 0xC803000F},
{0x00001538, 0x00000008}, /*Read Data Sample Delays Register */
{0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */
/*init DRAM */
{0x00001480, 0x00000001},
{0x0, 0x0}
};
MV_DRAM_TRAINING_INIT ddr3_db_533[MV_MAX_DDR3_STATIC_SIZE] = {
/* Read Leveling */
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
/*0 2 4 15 */
{0x000016A0, 0xC002040C},
/*1 2 4 2 */
{0x000016A0, 0xC0420117},
/*2 2 4 27 */
{0x000016A0, 0xC082041B},
/*3 2 4 0 */
{0x000016A0, 0xC0C20117},
/*4 2 4 13 */
{0x000016A0, 0xC102040A},
/*5 2 4 5 */
{0x000016A0, 0xC1420117},
/*6 2 4 19 */
{0x000016A0, 0xC1820419},
/*7 2 4 0 */
{0x000016A0, 0xC1C20117},
/*8 2 4 10 */
{0x000016A0, 0xC2020117},
/* Write Leveling */
/*0 */
{0x000016A0, 0xC0008113},
/*1 */
{0x000016A0, 0xC0404504},
/*2 */
{0x000016A0, 0xC0808514},
/*3 */
{0x000016A0, 0xC0C09418},
/*4 */
{0x000016A0, 0xC1006D0E},
/*5 */
{0x000016A0, 0xC1405508},
/*6 */
{0x000016A0, 0xC1807D12},
/*7 */
{0x000016A0, 0xC1C0b01F},
/*8 */
{0x000016A0, 0xC2005D0A},
/*center DQS on read cycle */
{0x000016A0, 0xC803000F},
{0x00001538, 0x00000008}, /*Read Data Sample Delays Register */
{0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */
/*init DRAM */
{0x00001480, 0x00000001},
{0x0, 0x0}
};
MV_DRAM_TRAINING_INIT ddr3_db_600[MV_MAX_DDR3_STATIC_SIZE] = {
/* Read Leveling */
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
/*0 2 3 1 */
{0x000016A0, 0xC0020104},
/*1 2 2 6 */
{0x000016A0, 0xC0420010},
/*2 2 3 16 */
{0x000016A0, 0xC0820112},
/*3 2 1 26 */
{0x000016A0, 0xC0C20009},
/*4 2 2 29 */
{0x000016A0, 0xC102001F},
/*5 2 2 13 */
{0x000016A0, 0xC1420014},
/*6 2 3 6 */
{0x000016A0, 0xC1820109},
/*7 2 1 31 */
{0x000016A0, 0xC1C2000C},
/*8 2 2 22 */
{0x000016A0, 0xC2020112},
/* Write Leveling */
/*0 */
{0x000016A0, 0xC0009919},
/*1 */
{0x000016A0, 0xC0405508},
/*2 */
{0x000016A0, 0xC0809919},
/*3 */
{0x000016A0, 0xC0C09C1A},
/*4 */
{0x000016A0, 0xC1008113},
/*5 */
{0x000016A0, 0xC140650C},
/*6 */
{0x000016A0, 0xC1809518},
/*7 */
{0x000016A0, 0xC1C04103},
/*8 */
{0x000016A0, 0xC2006D0E},
/*center DQS on read cycle */
{0x000016A0, 0xC803000F},
{0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
{0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
/*init DRAM */
{0x00001480, 0x00000001},
{0x0, 0x0}
};
MV_DRAM_TRAINING_INIT ddr3_db_667[MV_MAX_DDR3_STATIC_SIZE] = {
/* Read Leveling */
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
/*0 2 3 1 */
{0x000016A0, 0xC0020103},
/*1 2 2 6 */
{0x000016A0, 0xC0420012},
/*2 2 3 16 */
{0x000016A0, 0xC0820113},
/*3 2 1 26 */
{0x000016A0, 0xC0C20012},
/*4 2 2 29 */
{0x000016A0, 0xC1020100},
/*5 2 2 13 */
{0x000016A0, 0xC1420016},
/*6 2 3 6 */
{0x000016A0, 0xC1820109},
/*7 2 1 31 */
{0x000016A0, 0xC1C20010},
/*8 2 2 22 */
{0x000016A0, 0xC2020112},
/* Write Leveling */
/*0 */
{0x000016A0, 0xC000b11F},
/*1 */
{0x000016A0, 0xC040690D},
/*2 */
{0x000016A0, 0xC0803600},
/*3 */
{0x000016A0, 0xC0C0a81D},
/*4 */
{0x000016A0, 0xC1009919},
/*5 */
{0x000016A0, 0xC1407911},
/*6 */
{0x000016A0, 0xC180ad1e},
/*7 */
{0x000016A0, 0xC1C04d06},
/*8 */
{0x000016A0, 0xC2008514},
/*center DQS on read cycle */
{0x000016A0, 0xC803000F},
{0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
{0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
/*init DRAM */
{0x00001480, 0x00000001},
{0x0, 0x0}
};
MV_DRAM_TRAINING_INIT ddr3_db_800[MV_MAX_DDR3_STATIC_SIZE] = {
/* Read Leveling */
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
/*0 2 3 1 */
{0x000016A0, 0xC0020213},
/*1 2 2 6 */
{0x000016A0, 0xC0420108},
/*2 2 3 16 */
{0x000016A0, 0xC0820210},
/*3 2 1 26 */
{0x000016A0, 0xC0C20108},
/*4 2 2 29 */
{0x000016A0, 0xC102011A},
/*5 2 2 13 */
{0x000016A0, 0xC1420300},
/*6 2 3 6 */
{0x000016A0, 0xC1820204},
/*7 2 1 31 */
{0x000016A0, 0xC1C20106},
/*8 2 2 22 */
{0x000016A0, 0xC2020112},
/* Write Leveling */
/*0 */
{0x000016A0, 0xC000620B},
/*1 */
{0x000016A0, 0xC0408D16},
/*2 */
{0x000016A0, 0xC0806A0D},
/*3 */
{0x000016A0, 0xC0C03D02},
/*4 */
{0x000016A0, 0xC1004a05},
/*5 */
{0x000016A0, 0xC140A11B},
/*6 */
{0x000016A0, 0xC1805E0A},
/*7 */
{0x000016A0, 0xC1C06D0E},
/*8 */
{0x000016A0, 0xC200AD1E},
/*center DQS on read cycle */
{0x000016A0, 0xC803000F},
{0x00001538, 0x0000000C}, /*Read Data Sample Delays Register */
{0x0000153C, 0x0000000E}, /*Read Data Ready Delay Register */
/*init DRAM */
{0x00001480, 0x00000001},
{0x0, 0x0}
};
MV_DRAM_TRAINING_INIT ddr3_rd_667_0[MV_MAX_DDR3_STATIC_SIZE] = {
/* Read Leveling */
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
/*0 */
{0x000016A0, 0xC002010E},
/*1 */
{0x000016A0, 0xC042001E},
/*2 */
{0x000016A0, 0xC0820118},
/*3 */
{0x000016A0, 0xC0C2001E},
/*4 */
{0x000016A0, 0xC102010C},
/*5 */
{0x000016A0, 0xC1420102},
/*6 */
{0x000016A0, 0xC1820111},
/*7 */
{0x000016A0, 0xC1C2001C},
/*8 */
{0x000016A0, 0xC2020109},
/* Write Leveling */
/*0 */
{0x000016A0, 0xC0003600},
/*1 */
{0x000016A0, 0xC040690D},
/*2 */
{0x000016A0, 0xC0805207},
/*3 */
{0x000016A0, 0xC0C0A81D},
/*4 */
{0x000016A0, 0xC1009919},
/*5 */
{0x000016A0, 0xC1407911},
/*6 */
{0x000016A0, 0xC1803E02},
/*7 */
{0x000016A0, 0xC1C05107},
/*8 */
{0x000016A0, 0xC2008113},
/*center DQS on read cycle */
{0x000016A0, 0xC803000F},
{0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
{0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
/*init DRAM */
{0x00001480, 0x00000001},
{0x0, 0x0}
};
MV_DRAM_TRAINING_INIT ddr3_rd_667_1[MV_MAX_DDR3_STATIC_SIZE] = {
/* Read Leveling */
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
/*0 */
{0x000016A0, 0xC0020106},
/*1 */
{0x000016A0, 0xC0420016},
/*2 */
{0x000016A0, 0xC0820117},
/*3 */
{0x000016A0, 0xC0C2000F},
/*4 */
{0x000016A0, 0xC1020105},
/*5 */
{0x000016A0, 0xC142001B},
/*6 */
{0x000016A0, 0xC182010C},
/*7 */
{0x000016A0, 0xC1C20011},
/*8 */
{0x000016A0, 0xC2020101},
/* Write Leveling */
/*0 */
{0x000016A0, 0xC0003600},
/*1 */
{0x000016A0, 0xC0406D0E},
/*2 */
{0x000016A0, 0xC0803600},
/*3 */
{0x000016A0, 0xC0C04504},
/*4 */
{0x000016A0, 0xC1009919},
/*5 */
{0x000016A0, 0xC1407911},
/*6 */
{0x000016A0, 0xC1803600},
/*7 */
{0x000016A0, 0xC1C0610B},
/*8 */
{0x000016A0, 0xC2008113},
/*center DQS on read cycle */
{0x000016A0, 0xC803000F},
{0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
{0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
/*init DRAM */
{0x00001480, 0x00000001},
{0x0, 0x0}
};
MV_DRAM_TRAINING_INIT ddr3_rd_667_2[MV_MAX_DDR3_STATIC_SIZE] = {
/* Read Leveling */
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
/*0 */
{0x000016A0, 0xC002010C},
/*1 */
{0x000016A0, 0xC042001B},
/*2 */
{0x000016A0, 0xC082011D},
/*3 */
{0x000016A0, 0xC0C20015},
/*4 */
{0x000016A0, 0xC102010B},
/*5 */
{0x000016A0, 0xC1420101},
/*6 */
{0x000016A0, 0xC1820113},
/*7 */
{0x000016A0, 0xC1C20017},
/*8 */
{0x000016A0, 0xC2020107},
/* Write Leveling */
/*0 */
{0x000016A0, 0xC0003600},
/*1 */
{0x000016A0, 0xC0406D0E},
/*2 */
{0x000016A0, 0xC0803600},
/*3 */
{0x000016A0, 0xC0C04504},
/*4 */
{0x000016A0, 0xC1009919},
/*5 */
{0x000016A0, 0xC1407911},
/*6 */
{0x000016A0, 0xC180B11F},
/*7 */
{0x000016A0, 0xC1C0610B},
/*8 */
{0x000016A0, 0xC2008113},
/*center DQS on read cycle */
{0x000016A0, 0xC803000F},
{0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
{0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
/*init DRAM */
{0x00001480, 0x00000001},
{0x0, 0x0}
};
MV_DRAM_TRAINING_INIT ddr3_db_667_M[MV_MAX_DDR3_STATIC_SIZE] = {
/* Read Leveling */
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
/* CS 0 */
/*0 2 3 1 */
{0x000016A0, 0xC0020103},
/*1 2 2 6 */
{0x000016A0, 0xC0420012},
/*2 2 3 16 */
{0x000016A0, 0xC0820113},
/*3 2 1 26 */
{0x000016A0, 0xC0C20012},
/*4 2 2 29 */
{0x000016A0, 0xC1020100},
/*5 2 2 13 */
{0x000016A0, 0xC1420016},
/*6 2 3 6 */
{0x000016A0, 0xC1820109},
/*7 2 1 31 */
{0x000016A0, 0xC1C20010},
/*8 2 2 22 */
{0x000016A0, 0xC2020112},
/* Write Leveling */
/*0 */
{0x000016A0, 0xC000b11F},
/*1 */
{0x000016A0, 0xC040690D},
/*2 */
{0x000016A0, 0xC0803600},
/*3 */
{0x000016A0, 0xC0C0a81D},
/*4 */
{0x000016A0, 0xC1009919},
/*5 */
{0x000016A0, 0xC1407911},
/*6 */
{0x000016A0, 0xC180ad1e},
/*7 */
{0x000016A0, 0xC1C04d06},
/*8 */
{0x000016A0, 0xC2008514},
/*center DQS on read cycle */
{0x000016A0, 0xC803000F},
/* CS 1 */
{0x000016A0, 0xC0060103},
/*1 2 2 6 */
{0x000016A0, 0xC0460012},
/*2 2 3 16 */
{0x000016A0, 0xC0860113},
/*3 2 1 26 */
{0x000016A0, 0xC0C60012},
/*4 2 2 29 */
{0x000016A0, 0xC1060100},
/*5 2 2 13 */
{0x000016A0, 0xC1460016},
/*6 2 3 6 */
{0x000016A0, 0xC1860109},
/*7 2 1 31 */
{0x000016A0, 0xC1C60010},
/*8 2 2 22 */
{0x000016A0, 0xC2060112},
/* Write Leveling */
/*0 */
{0x000016A0, 0xC004b11F},
/*1 */
{0x000016A0, 0xC044690D},
/*2 */
{0x000016A0, 0xC0843600},
/*3 */
{0x000016A0, 0xC0C4a81D},
/*4 */
{0x000016A0, 0xC1049919},
/*5 */
{0x000016A0, 0xC1447911},
/*6 */
{0x000016A0, 0xC184ad1e},
/*7 */
{0x000016A0, 0xC1C44d06},
/*8 */
{0x000016A0, 0xC2048514},
/*center DQS on read cycle */
{0x000016A0, 0xC807000F},
/* Both CS */
{0x00001538, 0x00000B0B}, /*Read Data Sample Delays Register */
{0x0000153C, 0x00000F0F}, /*Read Data Ready Delay Register */
/*init DRAM */
{0x00001480, 0x00000001},
{0x0, 0x0}
};
MV_DRAM_TRAINING_INIT ddr3_rd_667_3[MV_MAX_DDR3_STATIC_SIZE] = {
/* Read Leveling */
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
/*0 */
{0x000016A0, 0xC0020118},
/*1 */
{0x000016A0, 0xC0420108},
/*2 */
{0x000016A0, 0xC0820202},
/*3 */
{0x000016A0, 0xC0C20108},
/*4 */
{0x000016A0, 0xC1020117},
/*5 */
{0x000016A0, 0xC142010C},
/*6 */
{0x000016A0, 0xC182011B},
/*7 */
{0x000016A0, 0xC1C20107},
/*8 */
{0x000016A0, 0xC2020113},
/* Write Leveling */
/*0 */
{0x000016A0, 0xC0003600},
/*1 */
{0x000016A0, 0xC0406D0E},
/*2 */
{0x000016A0, 0xC0805207},
/*3 */
{0x000016A0, 0xC0C0A81D},
/*4 */
{0x000016A0, 0xC1009919},
/*5 */
{0x000016A0, 0xC1407911},
/*6 */
{0x000016A0, 0xC1803E02},
/*7 */
{0x000016A0, 0xC1C04D06},
/*8 */
{0x000016A0, 0xC2008113},
/*center DQS on read cycle */
{0x000016A0, 0xC803000F},
{0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
{0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
/*init DRAM */
{0x00001480, 0x00000001},
{0x0, 0x0}
};
MV_DRAM_TRAINING_INIT ddr3_pcac_600[MV_MAX_DDR3_STATIC_SIZE] = {
/* Read Leveling */
/*PUP RdSampleDly (+CL) Phase RL ADLL value */
/*0 */
{0x000016A0, 0xC0020404},
/* 1 2 2 6 */
{0x000016A0, 0xC042031E},
/* 2 2 3 16 */
{0x000016A0, 0xC0820411},
/* 3 2 1 26 */
{0x000016A0, 0xC0C20400},
/* 4 2 2 29 */
{0x000016A0, 0xC1020404},
/* 5 2 2 13 */
{0x000016A0, 0xC142031D},
/* 6 2 3 6 */
{0x000016A0, 0xC182040C},
/* 7 2 1 31 */
{0x000016A0, 0xC1C2031B},
/* 8 2 2 22 */
{0x000016A0, 0xC2020112},
/* Write Leveling */
/* 0 */
{0x000016A0, 0xC0004905},
/* 1 */
{0x000016A0, 0xC040A81D},
/* 2 */
{0x000016A0, 0xC0804504},
/* 3 */
{0x000016A0, 0xC0C08013},
/* 4 */
{0x000016A0, 0xC1004504},
/* 5 */
{0x000016A0, 0xC140A81D},
/* 6 */
{0x000016A0, 0xC1805909},
/* 7 */
{0x000016A0, 0xC1C09418},
/* 8 */
{0x000016A0, 0xC2006D0E},
/*center DQS on read cycle */
{0x000016A0, 0xC803000F},
{0x00001538, 0x00000009}, /*Read Data Sample Delays Register */
{0x0000153C, 0x0000000D}, /*Read Data Ready Delay Register */
/* init DRAM */
{0x00001480, 0x00000001},
{0x0, 0x0}
};
#endif /* __AXP_TRAINING_STATIC_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/ddr3_axp_vars.h
+225
View File
@@ -0,0 +1,225 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef __AXP_VARS_H
#define __AXP_VARS_H
#include "ddr3_axp_config.h"
#include "ddr3_axp_mc_static.h"
#include "ddr3_axp_training_static.h"
MV_DRAM_MODES ddr_modes[MV_DDR3_MODES_NUMBER] = {
/* Conf name CPUFreq FabFreq Chip ID Chip/Board MC regs Training Values */
/* db board values: */
{"db_800-400", 0xA, 0x5, 0x0, A0, ddr3_A0_db_400, NULL},
{"db_1200-300", 0x2, 0xC, 0x0, A0, ddr3_A0_db_400, NULL},
{"db_1200-600", 0x2, 0x5, 0x0, A0, NULL, NULL},
{"db_1333-667", 0x3, 0x5, 0x0, A0, ddr3_A0_db_667, ddr3_db_rev2_667},
{"db_1600-800", 0xB, 0x5, 0x0, A0, ddr3_A0_db_667, ddr3_db_rev2_800},
{"amc_1333-667", 0x3, 0x5, 0x0, A0_AMC, ddr3_A0_AMC_667, NULL},
{"db_667-667", 0x9, 0x13, 0x0, Z1, ddr3_Z1_db_600, ddr3_db_667},
{"db_800-400", 0xA, 0x1, 0x0, Z1, ddr3_Z1_db_300, ddr3_db_400},
{"db_1066-533", 0x1, 0x1, 0x0, Z1, ddr3_Z1_db_300, ddr3_db_533},
{"db_1200-300", 0x2, 0xC, 0x0, Z1, ddr3_Z1_db_300, ddr3_db_667},
{"db_1200-600", 0x2, 0x5, 0x0, Z1, ddr3_Z1_db_600, NULL},
{"db_1333-333", 0x3, 0xC, 0x0, Z1, ddr3_Z1_db_300, ddr3_db_400},
{"db_1333-667", 0x3, 0x5, 0x0, Z1, ddr3_Z1_db_600, ddr3_db_667},
/* pcac board values (Z1 device): */
{"pcac_1200-600", 0x2, 0x5, 0x0, Z1_PCAC, ddr3_Z1_db_600,
ddr3_pcac_600},
/* rd board values (Z1 device): */
{"rd_667_0", 0x3, 0x5, 0x0, Z1_RD_SLED, ddr3_Z1_db_600, ddr3_rd_667_0},
{"rd_667_1", 0x3, 0x5, 0x1, Z1_RD_SLED, ddr3_Z1_db_600, ddr3_rd_667_1},
{"rd_667_2", 0x3, 0x5, 0x2, Z1_RD_SLED, ddr3_Z1_db_600, ddr3_rd_667_2},
{"rd_667_3", 0x3, 0x5, 0x3, Z1_RD_SLED, ddr3_Z1_db_600, ddr3_rd_667_3}
};
/* ODT settings - if needed update the following tables: (ODT_OPT - represents the CS configuration bitmap) */
u16 odt_static[ODT_OPT][MAX_CS] = { /* NearEnd/FarEnd */
{0, 0, 0, 0}, /* 0000 0/0 - Not supported */
{ODT40, 0, 0, 0}, /* 0001 0/1 */
{0, 0, 0, 0}, /* 0010 0/0 - Not supported */
{ODT40, ODT40, 0, 0}, /* 0011 0/2 */
{0, 0, ODT40, 0}, /* 0100 1/0 */
{ODT30, 0, ODT30, 0}, /* 0101 1/1 */
{0, 0, 0, 0}, /* 0110 0/0 - Not supported */
{ODT120, ODT20, ODT20, 0}, /* 0111 1/2 */
{0, 0, 0, 0}, /* 1000 0/0 - Not supported */
{0, 0, 0, 0}, /* 1001 0/0 - Not supported */
{0, 0, 0, 0}, /* 1010 0/0 - Not supported */
{0, 0, 0, 0}, /* 1011 0/0 - Not supported */
{0, 0, ODT40, 0}, /* 1100 2/0 */
{ODT20, 0, ODT120, ODT20}, /* 1101 2/1 */
{0, 0, 0, 0}, /* 1110 0/0 - Not supported */
{ODT120, ODT30, ODT120, ODT30} /* 1111 2/2 */
};
u16 odt_dynamic[ODT_OPT][MAX_CS] = { /* NearEnd/FarEnd */
{0, 0, 0, 0}, /* 0000 0/0 */
{0, 0, 0, 0}, /* 0001 0/1 */
{0, 0, 0, 0}, /* 0010 0/0 - Not supported */
{0, 0, 0, 0}, /* 0011 0/2 */
{0, 0, 0, 0}, /* 0100 1/0 */
{ODT120D, 0, ODT120D, 0}, /* 0101 1/1 */
{0, 0, 0, 0}, /* 0110 0/0 - Not supported */
{0, 0, ODT120D, 0}, /* 0111 1/2 */
{0, 0, 0, 0}, /* 1000 0/0 - Not supported */
{0, 0, 0, 0}, /* 1001 0/0 - Not supported */
{0, 0, 0, 0}, /* 1010 0/0 - Not supported */
{0, 0, 0, 0}, /* 1011 0/0 - Not supported */
{0, 0, 0, 0}, /* 1100 2/0 */
{ODT120D, 0, 0, 0}, /* 1101 2/1 */
{0, 0, 0, 0}, /* 1110 0/0 - Not supported */
{0, 0, 0, 0} /* 1111 2/2 */
};
u32 odt_config[ODT_OPT] = {
0, 0x00010000, 0, 0x00030000, 0x04000000, 0x05050104, 0, 0x07430340, 0,
0, 0, 0,
0x30000, 0x1C0D100C, 0, 0x3CC330C0
};
/*
* User can manually set SPD values (in case SPD is not available on
* DIMM/System).
* SPD Values can simplify calculating the DUNIT registers values
*/
u8 spd_data[SPD_SIZE] = {
/* AXP DB Board DIMM SPD Values - manually set */
0x92, 0x10, 0x0B, 0x2, 0x3, 0x19, 0x0, 0x9, 0x09, 0x52, 0x1, 0x8, 0x0C,
0x0, 0x7E, 0x0, 0x69, 0x78,
0x69, 0x30, 0x69, 0x11, 0x20, 0x89, 0x0, 0x5, 0x3C, 0x3C, 0x0, 0xF0,
0x82, 0x5, 0x80, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0F, 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x80, 0x2C, 0x1, 0x10, 0x23, 0x35, 0x28, 0xEB, 0xCA, 0x19, 0x8F
};
/*
* Controller Specific configurations Starts Here - DO NOT MODIFY
*/
/* Frequency - values are 1/HCLK in ps */
u32 cpu_fab_clk_to_hclk[FAB_OPT][CLK_CPU] =
/* CPU Frequency:
1000 1066 1200 1333 1500 1666 1800 2000 600 667 800 1600 Fabric */
{
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 3000, 2500, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 4500, 3750, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 2500, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{4000, 3750, 3333, 3000, 2666, 2400, 0, 0, 0, 0, 5000, 2500},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 3000, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{2500, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 5000, 0, 4000, 0, 0, 0, 0, 0, 0, 3750},
{5000, 0, 0, 3750, 3333, 0, 0, 0, 0, 0, 0, 3125},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 3330, 3000, 0, 0, 0, 0, 0, 0, 0, 2500},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3750},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 3000, 2500, 0},
{3000, 0, 2500, 0, 0, 0, 0, 0, 0, 0, 3750, 0}
};
u32 cpu_ddr_ratios[FAB_OPT][CLK_CPU] =
/* CPU Frequency:
1000 1066 1200 1333 1500 1666 1800 2000 600 667 800 1600 Fabric */
{
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, DDR_333, DDR_400, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, DDR_444, DDR_533, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, DDR_400, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{DDR_500, DDR_533, DDR_600, DDR_666, DDR_750, DDR_833, 0, 0, 0, 0,
DDR_400, DDR_800},
{0, 0, 0, 0, 0, 0, 0, 0, 0, DDR_333, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{DDR_400, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, DDR_400, 0, DDR_500, 0, 0, 0, 0, 0, 0, DDR_533},
{DDR_400, 0, 0, DDR_533, DDR_600, 0, 0, 0, 0, 0, 0, DDR_640},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, DDR_300, DDR_333, 0, 0, 0, 0, 0, 0, 0, DDR_400},
{0, 0, 0, 0, 0, 0, DDR_600, DDR_666, 0, 0, 0, DDR_533},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, DDR_666, DDR_800, 0},
{DDR_666, 0, DDR_800, 0, 0, 0, 0, 0, 0, 0, DDR_533, 0}
};
u8 div_ratio1to1[CLK_VCO][CLK_DDR] =
/* DDR Frequency:
100 300 360 400 444 500 533 600 666 750 800 833 */
{ {0xA, 3, 0, 3, 0, 2, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1000 */
{0xB, 3, 0, 3, 0, 0, 2, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1066 */
{0xC, 4, 0, 3, 0, 0, 0, 2, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1200 */
{0xD, 4, 0, 4, 0, 0, 0, 0, 2, 0, 0, 0}, /* 1:1 CLK_CPU_1333 */
{0xF, 5, 0, 4, 0, 3, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1500 */
{0x11, 5, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1666 */
{0x12, 6, 5, 4, 0, 0, 0, 3, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1800 */
{0x14, 7, 0, 5, 0, 4, 0, 0, 3, 0, 0, 0}, /* 1:1 CLK_CPU_2000 */
{0x6, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_600 */
{0x6, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_667 */
{0x8, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_800 */
{0x10, 5, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1600 */
{0x14, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1000 VCO_2000 */
{0x15, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1066 VCO_2133 */
{0x18, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1200 VCO_2400 */
{0x1A, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1333 VCO_2666 */
{0x1E, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1500 VCO_3000 */
{0x21, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1666 VCO_3333 */
{0x24, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_1800 VCO_3600 */
{0x28, 0, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_2000 VCO_4000 */
{0xC, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_600 VCO_1200 */
{0xD, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_667 VCO_1333 */
{0x10, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1:1 CLK_CPU_800 VCO_1600 */
{0x20, 10, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0} /* 1:1 CLK_CPU_1600 VCO_3200 */
};
u8 div_ratio2to1[CLK_VCO][CLK_DDR] =
/* DDR Frequency:
100 300 360 400 444 500 533 600 666 750 800 833 */
{ {0, 0, 0, 0, 0, 2, 0, 0, 3, 0, 0, 0}, /* 2:1 CLK_CPU_1000 */
{0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_1066 */
{0, 0, 0, 3, 5, 0, 0, 2, 0, 0, 3, 3}, /* 2:1 CLK_CPU_1200 */
{0, 0, 0, 0, 0, 0, 5, 0, 2, 0, 3, 0}, /* 2:1 CLK_CPU_1333 */
{0, 0, 0, 0, 0, 3, 0, 5, 0, 2, 0, 0}, /* 2:1 CLK_CPU_1500 */
{0, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 2}, /* 2:1 CLK_CPU_1666 */
{0, 0, 0, 0, 0, 0, 0, 3, 0, 5, 0, 0}, /* 2:1 CLK_CPU_1800 */
{0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 5}, /* 2:1 CLK_CPU_2000 */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_600 */
{0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0}, /* 2:1 CLK_CPU_667 */
{0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 1, 0}, /* 2:1 CLK_CPU_800 */
{0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 2, 0}, /* 2:1 CLK_CPU_1600 */
{0, 0, 0, 5, 0, 0, 0, 0, 3, 0, 0, 0}, /* 2:1 CLK_CPU_1000 VCO_2000 */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_1066 VCO_2133 */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0}, /* 2:1 CLK_CPU_1200 VCO_2400 */
{0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_1333 VCO_2666 */
{0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0}, /* 2:1 CLK_CPU_1500 VCO_3000 */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_1666 VCO_3333 */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_1800 VCO_3600 */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_2000 VCO_4000 */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_600 VCO_1200 */
{0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_667 VCO_1333 */
{0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0}, /* 2:1 CLK_CPU_800 VCO_1600 */
{0, 0, 0, 0, 0, 0, 0, 5, 5, 0, 0, 0} /* 2:1 CLK_CPU_1600 VCO_3200 */
};
#endif /* __AXP_VARS_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/ddr3_dfs.c
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source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/ddr3_dqs.c
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source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/ddr3_hw_training.c
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source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/ddr3_hw_training.h
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@@ -0,0 +1,391 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef __DDR3_TRAINING_H
#define __DDR3_TRAINING_H
#include "ddr3_init.h"
#ifdef MV88F78X60
#include "ddr3_axp.h"
#elif defined(MV88F67XX)
#include "ddr3_a370.h"
#elif defined(MV88F672X)
#include "ddr3_a375.h"
#endif
/* The following is a list of Marvell status */
#define MV_ERROR (-1)
#define MV_OK (0x00) /* Operation succeeded */
#define MV_FAIL (0x01) /* Operation failed */
#define MV_BAD_VALUE (0x02) /* Illegal value (general) */
#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */
#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */
#define MV_BAD_PTR (0x05) /* Illegal pointer value */
#define MV_BAD_SIZE (0x06) /* Illegal size */
#define MV_BAD_STATE (0x07) /* Illegal state of state machine */
#define MV_SET_ERROR (0x08) /* Set operation failed */
#define MV_GET_ERROR (0x09) /* Get operation failed */
#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */
#define MV_NOT_FOUND (0x0B) /* Item not found */
#define MV_NO_MORE (0x0C) /* No more items found */
#define MV_NO_SUCH (0x0D) /* No such item */
#define MV_TIMEOUT (0x0E) /* Time Out */
#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */
#define MV_NOT_SUPPORTED (0x10) /* This request is not support */
#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/
#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */
#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
#define MV_INIT_ERROR (0x16) /* Error occurred while INIT process */
#define MV_HW_ERROR (0x17) /* Hardware error */
#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
#define MV_NOT_READY (0x1A) /* The other side is not ready yet */
#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */
#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */
#define MV_NOT_STARTED (0x1D) /* Not started yet */
#define MV_BUSY (0x1E) /* Item is busy. */
#define MV_TERMINATE (0x1F) /* Item terminates it's work. */
#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */
#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */
#define MV_WRITE_PROTECT (0x22) /* Write protected */
#define MV_INVALID (int)(-1)
/*
* Debug (Enable/Disable modules) and Error report
*/
#ifdef BASIC_DEBUG
#define MV_DEBUG_WL
#define MV_DEBUG_RL
#define MV_DEBUG_DQS_RESULTS
#endif
#ifdef FULL_DEBUG
#define MV_DEBUG_WL
#define MV_DEBUG_RL
#define MV_DEBUG_DQS
#define MV_DEBUG_PBS
#define MV_DEBUG_DFS
#define MV_DEBUG_MAIN_FULL
#define MV_DEBUG_DFS_FULL
#define MV_DEBUG_DQS_FULL
#define MV_DEBUG_RL_FULL
#define MV_DEBUG_WL_FULL
#endif
/*
* General Consts
*/
#define SDRAM_READ_WRITE_LEN_IN_WORDS 16
#define SDRAM_READ_WRITE_LEN_IN_DOUBLE_WORDS 8
#define CACHE_LINE_SIZE 0x20
#define SDRAM_CS_BASE 0x0
#define SRAM_BASE 0x40000000
#define SRAM_SIZE 0xFFF
#define LEN_64BIT_STD_PATTERN 16
#define LEN_64BIT_KILLER_PATTERN 128
#define LEN_64BIT_SPECIAL_PATTERN 128
#define LEN_64BIT_PBS_PATTERN 16
#define LEN_WL_SUP_PATTERN 32
#define LEN_16BIT_STD_PATTERN 4
#define LEN_16BIT_KILLER_PATTERN 128
#define LEN_16BIT_SPECIAL_PATTERN 128
#define LEN_16BIT_PBS_PATTERN 4
#define CMP_BYTE_SHIFT 8
#define CMP_BYTE_MASK 0xFF
#define PUP_SIZE 8
#define S 0
#define C 1
#define P 2
#define D 3
#define DQS 6
#define PS 2
#define DS 3
#define PE 4
#define DE 5
#define CS0 0
#define MAX_DIMM_NUM 2
#define MAX_DELAY 0x1F
/*
* Invertion limit and phase1 limit are WA for the RL @ 1:1 design bug -
* Armada 370 & AXP Z1
*/
#define MAX_DELAY_INV_LIMIT 0x5
#define MIN_DELAY_PHASE_1_LIMIT 0x10
#define MAX_DELAY_INV (0x3F - MAX_DELAY_INV_LIMIT)
#define MIN_DELAY 0
#define MAX_PUP_NUM 9
#define ECC_PUP 8
#define DQ_NUM 8
#define DQS_DQ_NUM 8
#define INIT_WL_DELAY 13
#define INIT_RL_DELAY 15
#define TWLMRD_DELAY 20
#define TCLK_3_DELAY 3
#define ECC_BIT 8
#define DMA_SIZE 64
#define MV_DMA_0 0
#define MAX_TRAINING_RETRY 10
#define PUP_RL_MODE 0x2
#define PUP_WL_MODE 0
#define PUP_PBS_TX 0x10
#define PUP_PBS_TX_DM 0x1A
#define PUP_PBS_RX 0x30
#define PUP_DQS_WR 0x1
#define PUP_DQS_RD 0x3
#define PUP_BC 10
#define PUP_DELAY_MASK 0x1F
#define PUP_PHASE_MASK 0x7
#define PUP_NUM_64BIT 8
#define PUP_NUM_32BIT 4
#define PUP_NUM_16BIT 2
/* control PHY registers */
#define CNTRL_PUP_DESKEW 0x10
/* WL */
#define COUNT_WL_HI_FREQ 2
#define COUNT_WL 2
#define COUNT_WL_RFRS 9
#define WL_HI_FREQ_SHIFT 2
#define WL_HI_FREQ_STATE 1
#define COUNT_HW_WL 2
/* RL */
/*
* RL_MODE - this define uses the RL mode SW RL instead of the functional
* window SW RL
*/
#define RL_MODE
#define RL_WINDOW_WA
#define MAX_PHASE_1TO1 2
#define MAX_PHASE_2TO1 4
#define MAX_PHASE_RL_UL_1TO1 0
#define MAX_PHASE_RL_L_1TO1 4
#define MAX_PHASE_RL_UL_2TO1 3
#define MAX_PHASE_RL_L_2TO1 7
#define RL_UNLOCK_STATE 0
#define RL_WINDOW_STATE 1
#define RL_FINAL_STATE 2
#define RL_RETRY_COUNT 2
#define COUNT_HW_RL 2
/* PBS */
#define MAX_PBS 31
#define MIN_PBS 0
#define COUNT_PBS_PATTERN 2
#define COUNT_PBS_STARTOVER 2
#define COUNT_PBS_REPEAT 3
#define COUNT_PBS_COMP_RETRY_NUM 2
#define PBS_DIFF_LIMIT 31
#define PATTERN_PBS_TX_A 0x55555555
#define PATTERN_PBS_TX_B 0xAAAAAAAA
/* DQS */
#define ADLL_ERROR 0x55
#define ADLL_MAX 31
#define ADLL_MIN 0
#define MIN_WIN_SIZE 4
#define VALID_WIN_THRS MIN_WIN_SIZE
#define MODE_2TO1 1
#define MODE_1TO1 0
/*
* Macros
*/
#define IS_PUP_ACTIVE(_data_, _pup_) (((_data_) >> (_pup_)) & 0x1)
/*
* Internal ERROR codes
*/
#define MV_DDR3_TRAINING_ERR_WR_LVL_HW 0xDD302001
#define MV_DDR3_TRAINING_ERR_LOAD_PATTERNS 0xDD302002
#define MV_DDR3_TRAINING_ERR_WR_LVL_HI_FREQ 0xDD302003
#define MV_DDR3_TRAINING_ERR_DFS_H2L 0xDD302004
#define MV_DDR3_TRAINING_ERR_DRAM_COMPARE 0xDD302005
#define MV_DDR3_TRAINING_ERR_WIN_LIMITS 0xDD302006
#define MV_DDR3_TRAINING_ERR_PUP_RANGE 0xDD302025
#define MV_DDR3_TRAINING_ERR_DQS_LOW_LIMIT_SEARCH 0xDD302007
#define MV_DDR3_TRAINING_ERR_DQS_HIGH_LIMIT_SEARCH 0xDD302008
#define MV_DDR3_TRAINING_ERR_DQS_PATTERN 0xDD302009
#define MV_DDR3_TRAINING_ERR_PBS_ADLL_SHR_1PHASE 0xDD302010
#define MV_DDR3_TRAINING_ERR_PBS_TX_MAX_VAL 0xDD302011
#define MV_DDR3_TRAINING_ERR_PBS_RX_PER_BIT 0xDD302012
#define MV_DDR3_TRAINING_ERR_PBS_TX_PER_BIT 0xDD302013
#define MV_DDR3_TRAINING_ERR_PBS_RX_MAX_VAL 0xDD302014
#define MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_SRAM_CMP 0xDD302015
#define MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_MAX_VAL 0xDD302016
#define MV_DDR3_TRAINING_ERR_RD_LVL_RL_PATTERN 0xDD302017
#define MV_DDR3_TRAINING_ERR_RD_LVL_RL_PUP_UNLOCK 0xDD302018
#define MV_DDR3_TRAINING_ERR_RD_LVL_PUP_UNLOCK 0xDD302019
#define MV_DDR3_TRAINING_ERR_WR_LVL_SW 0xDD302020
#define MV_DDR3_TRAINING_ERR_PRBS_RX 0xDD302021
#define MV_DDR3_TRAINING_ERR_DQS_RX 0xDD302022
#define MV_DDR3_TRAINING_ERR_PRBS_TX 0xDD302023
#define MV_DDR3_TRAINING_ERR_DQS_TX 0xDD302024
/*
* DRAM information structure
*/
typedef struct dram_info {
u32 num_cs;
u32 cs_ena;
u32 num_of_std_pups; /* Q value = ddrWidth/8 - Without ECC!! */
u32 num_of_total_pups; /* numOfStdPups + eccEna */
u32 target_frequency; /* DDR Frequency */
u32 ddr_width; /* 32/64 Bit or 16/32 Bit */
u32 ecc_ena; /* 0/1 */
u32 wl_val[MAX_CS][MAX_PUP_NUM][7];
u32 rl_val[MAX_CS][MAX_PUP_NUM][7];
u32 rl_max_phase;
u32 rl_min_phase;
u32 wl_max_phase;
u32 wl_min_phase;
u32 rd_smpl_dly;
u32 rd_rdy_dly;
u32 cl;
u32 cwl;
u32 mode_2t;
int rl400_bug;
int multi_cs_mr_support;
int reg_dimm;
} MV_DRAM_INFO;
enum training_modes {
DQS_WR_MODE,
WL_MODE_,
RL_MODE_,
DQS_RD_MODE,
PBS_TX_DM_MODE,
PBS_TX_MODE,
PBS_RX_MODE,
MAX_TRAINING_MODE,
};
typedef struct dram_training_init {
u32 reg_addr;
u32 reg_value;
} MV_DRAM_TRAINING_INIT;
typedef struct dram_mv_init {
u32 reg_addr;
u32 reg_value;
} MV_DRAM_MC_INIT;
/* Board/Soc revisions define */
enum board_rev {
Z1,
Z1_PCAC,
Z1_RD_SLED,
A0,
A0_AMC
};
typedef struct dram_modes {
char *mode_name;
u8 cpu_freq;
u8 fab_freq;
u8 chip_id;
int chip_board_rev;
MV_DRAM_MC_INIT *regs;
MV_DRAM_TRAINING_INIT *vals;
} MV_DRAM_MODES;
/*
* Function Declarations
*/
u32 cache_inv(u32 addr);
void flush_l1_v7(u32 line);
void flush_l1_v6(u32 line);
u32 ddr3_cl_to_valid_cl(u32 cl);
u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl);
void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay);
u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup);
int ddr3_sdram_pbs_compare(MV_DRAM_INFO *dram_info, u32 pup_locked, int is_tx,
u32 pbs_pattern_idx, u32 pbs_curr_val,
u32 pbs_lock_val, u32 *skew_array,
u8 *unlock_pup_dq_array, u32 ecc);
int ddr3_sdram_dqs_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
u32 *new_locked_pup, u32 *pattern,
u32 pattern_len, u32 sdram_offset, int write,
int mask, u32 *mask_pattern, int b_special_compare);
int ddr3_sdram_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
u32 *new_locked_pup, u32 *pattern, u32 pattern_len,
u32 sdram_offset, int write, int mask,
u32 *mask_pattern, int b_special_compare);
int ddr3_sdram_direct_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
u32 *new_locked_pup, u32 *pattern,
u32 pattern_len, u32 sdram_offset, int write,
int mask, u32 *mask_pattern);
int ddr3_sdram_dm_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
u32 *new_locked_pup, u32 *pattern,
u32 sdram_offset);
int ddr3_dram_sram_read(u32 src, u32 dst, u32 len);
int ddr3_load_patterns(MV_DRAM_INFO *dram_info, int resume);
int ddr3_read_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info);
int ddr3_read_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
int ddr3_write_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info);
int ddr3_write_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
int ddr3_write_leveling_hw_reg_dimm(u32 freq, MV_DRAM_INFO *dram_info);
int ddr3_wl_supplement(MV_DRAM_INFO *dram_info);
int ddr3_dfs_high_2_low(u32 freq, MV_DRAM_INFO *dram_info);
int ddr3_dfs_low_2_high(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
int ddr3_pbs_tx(MV_DRAM_INFO *dram_info);
int ddr3_pbs_rx(MV_DRAM_INFO *dram_info);
int ddr3_load_pbs_patterns(MV_DRAM_INFO *dram_info);
int ddr3_dqs_centralization_rx(MV_DRAM_INFO *dram_info);
int ddr3_dqs_centralization_tx(MV_DRAM_INFO *dram_info);
int ddr3_load_dqs_patterns(MV_DRAM_INFO *dram_info);
void ddr3_static_training_init(void);
u8 ddr3_get_eprom_fabric(void);
void ddr3_set_performance_params(MV_DRAM_INFO *dram_info);
int ddr3_dram_sram_burst(u32 src, u32 dst, u32 len);
void ddr3_save_training(MV_DRAM_INFO *dram_info);
int ddr3_read_training_results(void);
int ddr3_training_suspend_resume(MV_DRAM_INFO *dram_info);
int ddr3_get_min_max_read_sample_delay(u32 cs_enable, u32 reg, u32 *min,
u32 *max, u32 *cs_max);
int ddr3_get_min_max_rl_phase(MV_DRAM_INFO *dram_info, u32 *min, u32 *max,
u32 cs);
int ddr3_odt_activate(int activate);
int ddr3_odt_read_dynamic_config(MV_DRAM_INFO *dram_info);
void ddr3_print_freq(u32 freq);
void ddr3_reset_phy_read_fifo(void);
#endif /* __DDR3_TRAINING_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/ddr3_init.c
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source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/ddr3_init.h
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@@ -0,0 +1,142 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef __DDR3_INIT_H
#define __DDR3_INIT_H
/*
* Debug
*/
/*
* MV_DEBUG_INIT need to be defines, otherwise the output of the
* DDR2 training code is not complete and misleading
*/
#define MV_DEBUG_INIT
#ifdef MV_DEBUG_INIT
#define DEBUG_INIT_S(s) puts(s)
#define DEBUG_INIT_D(d, l) printf("%x", d)
#define DEBUG_INIT_D_10(d, l) printf("%d", d)
#else
#define DEBUG_INIT_S(s)
#define DEBUG_INIT_D(d, l)
#define DEBUG_INIT_D_10(d, l)
#endif
#ifdef MV_DEBUG_INIT_FULL
#define DEBUG_INIT_FULL_S(s) puts(s)
#define DEBUG_INIT_FULL_D(d, l) printf("%x", d)
#define DEBUG_INIT_FULL_D_10(d, l) printf("%d", d)
#define DEBUG_WR_REG(reg, val) \
{ DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
#define DEBUG_RD_REG(reg, val) \
{ DEBUG_INIT_S("Read Reg: 0x"); DEBUG_INIT_D((reg), 8); \
DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
#else
#define DEBUG_INIT_FULL_S(s)
#define DEBUG_INIT_FULL_D(d, l)
#define DEBUG_INIT_FULL_D_10(d, l)
#define DEBUG_WR_REG(reg, val)
#define DEBUG_RD_REG(reg, val)
#endif
#define DEBUG_INIT_FULL_C(s, d, l) \
{ DEBUG_INIT_FULL_S(s); DEBUG_INIT_FULL_D(d, l); DEBUG_INIT_FULL_S("\n"); }
#define DEBUG_INIT_C(s, d, l) \
{ DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
#define MV_MBUS_REGS_OFFSET (0x20000)
#include "ddr3_hw_training.h"
#define MAX_DIMM_NUM 2
#define SPD_SIZE 128
#ifdef MV88F78X60
#include "ddr3_axp.h"
#elif defined(MV88F67XX)
#include "ddr3_a370.h"
#elif defined(MV88F672X)
#include "ddr3_a375.h"
#endif
/* DRR training Error codes */
/* Stage 0 errors */
#define MV_DDR3_TRAINING_ERR_BAD_SAR 0xDD300001
/* Stage 1 errors */
#define MV_DDR3_TRAINING_ERR_TWSI_FAIL 0xDD301001
#define MV_DDR3_TRAINING_ERR_DIMM_TYPE_NO_MATCH 0xDD301001
#define MV_DDR3_TRAINING_ERR_TWSI_BAD_TYPE 0xDD301003
#define MV_DDR3_TRAINING_ERR_BUS_WIDTH_NOT_MATCH 0xDD301004
#define MV_DDR3_TRAINING_ERR_BAD_DIMM_SETUP 0xDD301005
#define MV_DDR3_TRAINING_ERR_MAX_CS_LIMIT 0xDD301006
#define MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT 0xDD301007
#define MV_DDR3_TRAINING_ERR_BAD_R_DIMM_SETUP 0xDD301008
/* Stage 2 errors */
#define MV_DDR3_TRAINING_ERR_HW_FAIL_BASE 0xDD302000
typedef enum config_type {
CONFIG_ECC,
CONFIG_MULTI_CS,
CONFIG_BUS_WIDTH
} MV_CONFIG_TYPE;
enum log_level {
MV_LOG_LEVEL_0,
MV_LOG_LEVEL_1,
MV_LOG_LEVEL_2,
MV_LOG_LEVEL_3
};
int ddr3_hw_training(u32 target_freq, u32 ddr_width,
int xor_bypass, u32 scrub_offs, u32 scrub_size,
int dqs_clk_aligned, int debug_mode, int reg_dimm_skip_wl);
void ddr3_print_version(void);
void fix_pll_val(u8 target_fab);
u8 ddr3_get_eprom_fabric(void);
u32 ddr3_get_fab_opt(void);
u32 ddr3_get_cpu_freq(void);
u32 ddr3_get_vco_freq(void);
int ddr3_check_config(u32 addr, MV_CONFIG_TYPE config_type);
u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1, u32 offset2,
u32 mask2);
u32 ddr3_cl_to_valid_cl(u32 cl);
u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl);
u32 ddr3_get_cs_num_from_reg(void);
u32 ddr3_get_cs_ena_from_reg(void);
u8 mv_ctrl_rev_get(void);
u32 ddr3_get_log_level(void);
/* SPD */
int ddr3_dunit_setup(u32 ecc_ena, u32 hclk_time, u32 *ddr_width);
/*
* Accessor functions for the registers
*/
static inline void reg_write(u32 addr, u32 val)
{
writel(val, INTER_REGS_BASE + addr);
}
static inline u32 reg_read(u32 addr)
{
return readl(INTER_REGS_BASE + addr);
}
static inline void reg_bit_set(u32 addr, u32 mask)
{
setbits_le32(INTER_REGS_BASE + addr, mask);
}
static inline void reg_bit_clr(u32 addr, u32 mask)
{
clrbits_le32(INTER_REGS_BASE + addr, mask);
}
#endif /* __DDR3_INIT_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/ddr3_patterns_64bit.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef __DDR3_PATTERNS_64_H
#define __DDR3_PATTERNS_64_H
/*
* Patterns Declerations
*/
u32 wl_sup_pattern[LEN_WL_SUP_PATTERN] __aligned(32) = {
0x04030201, 0x08070605, 0x0c0b0a09, 0x100f0e0d,
0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d,
0x24232221, 0x28272625, 0x2c2b2a29, 0x302f2e2d,
0x34333231, 0x38373635, 0x3c3b3a39, 0x403f3e3d,
0x44434241, 0x48474645, 0x4c4b4a49, 0x504f4e4d,
0x54535251, 0x58575655, 0x5c5b5a59, 0x605f5e5d,
0x64636261, 0x68676665, 0x6c6b6a69, 0x706f6e6d,
0x74737271, 0x78777675, 0x7c7b7a79, 0x807f7e7d
};
u32 pbs_pattern_32b[2][LEN_PBS_PATTERN] __aligned(32) = {
{
0xAAAAAAAA, 0x55555555, 0xAAAAAAAA, 0x55555555,
0xAAAAAAAA, 0x55555555, 0xAAAAAAAA, 0x55555555,
0xAAAAAAAA, 0x55555555, 0xAAAAAAAA, 0x55555555,
0xAAAAAAAA, 0x55555555, 0xAAAAAAAA, 0x55555555
},
{
0x55555555, 0xAAAAAAAA, 0x55555555, 0xAAAAAAAA,
0x55555555, 0xAAAAAAAA, 0x55555555, 0xAAAAAAAA,
0x55555555, 0xAAAAAAAA, 0x55555555, 0xAAAAAAAA,
0x55555555, 0xAAAAAAAA, 0x55555555, 0xAAAAAAAA
}
};
u32 pbs_pattern_64b[2][LEN_PBS_PATTERN] __aligned(32) = {
{
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555
},
{
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA
}
};
u32 rl_pattern[LEN_STD_PATTERN] __aligned(32) = {
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x01010101, 0x01010101, 0x01010101, 0x01010101
};
u32 killer_pattern_32b[DQ_NUM][LEN_KILLER_PATTERN] __aligned(32) = {
{
0x01010101, 0x00000000, 0x01010101, 0xFFFFFFFF,
0x01010101, 0x00000000, 0x01010101, 0xFFFFFFFF,
0xFEFEFEFE, 0xFEFEFEFE, 0x01010101, 0xFEFEFEFE,
0xFEFEFEFE, 0xFEFEFEFE, 0x01010101, 0xFEFEFEFE,
0x01010101, 0xFEFEFEFE, 0x01010101, 0x01010101,
0x01010101, 0xFEFEFEFE, 0x01010101, 0x01010101,
0xFEFEFEFE, 0x01010101, 0xFEFEFEFE, 0x00000000,
0xFEFEFEFE, 0x01010101, 0xFEFEFEFE, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x01010101,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x01010101,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0xFEFEFEFE,
0x00000000, 0x00000000, 0x00000000, 0xFEFEFEFE,
0xFEFEFEFE, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFEFEFEFE, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0xFEFEFEFE, 0x00000000, 0xFEFEFEFE, 0x00000000,
0xFEFEFEFE, 0x00000000, 0xFEFEFEFE, 0x00000000,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x01010101,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x01010101,
0xFFFFFFFF, 0xFFFFFFFF, 0x01010101, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x01010101, 0x00000000,
0x01010101, 0xFFFFFFFF, 0xFEFEFEFE, 0xFEFEFEFE,
0x01010101, 0xFFFFFFFF, 0xFEFEFEFE, 0xFEFEFEFE
},
{
0x02020202, 0x00000000, 0x02020202, 0xFFFFFFFF,
0x02020202, 0x00000000, 0x02020202, 0xFFFFFFFF,
0xFDFDFDFD, 0xFDFDFDFD, 0x02020202, 0xFDFDFDFD,
0xFDFDFDFD, 0xFDFDFDFD, 0x02020202, 0xFDFDFDFD,
0x02020202, 0xFDFDFDFD, 0x02020202, 0x02020202,
0x02020202, 0xFDFDFDFD, 0x02020202, 0x02020202,
0xFDFDFDFD, 0x02020202, 0xFDFDFDFD, 0x00000000,
0xFDFDFDFD, 0x02020202, 0xFDFDFDFD, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x02020202,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x02020202,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0xFDFDFDFD,
0x00000000, 0x00000000, 0x00000000, 0xFDFDFDFD,
0xFDFDFDFD, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFDFDFDFD, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0xFDFDFDFD, 0x00000000, 0xFDFDFDFD, 0x00000000,
0xFDFDFDFD, 0x00000000, 0xFDFDFDFD, 0x00000000,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x02020202,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x02020202,
0xFFFFFFFF, 0xFFFFFFFF, 0x02020202, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x02020202, 0x00000000,
0x02020202, 0xFFFFFFFF, 0xFDFDFDFD, 0xFDFDFDFD,
0x02020202, 0xFFFFFFFF, 0xFDFDFDFD, 0xFDFDFDFD
},
{
0x04040404, 0x00000000, 0x04040404, 0xFFFFFFFF,
0x04040404, 0x00000000, 0x04040404, 0xFFFFFFFF,
0xFBFBFBFB, 0xFBFBFBFB, 0x04040404, 0xFBFBFBFB,
0xFBFBFBFB, 0xFBFBFBFB, 0x04040404, 0xFBFBFBFB,
0x04040404, 0xFBFBFBFB, 0x04040404, 0x04040404,
0x04040404, 0xFBFBFBFB, 0x04040404, 0x04040404,
0xFBFBFBFB, 0x04040404, 0xFBFBFBFB, 0x00000000,
0xFBFBFBFB, 0x04040404, 0xFBFBFBFB, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x04040404,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x04040404,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0xFBFBFBFB,
0x00000000, 0x00000000, 0x00000000, 0xFBFBFBFB,
0xFBFBFBFB, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFBFBFBFB, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0xFBFBFBFB, 0x00000000, 0xFBFBFBFB, 0x00000000,
0xFBFBFBFB, 0x00000000, 0xFBFBFBFB, 0x00000000,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x04040404,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x04040404,
0xFFFFFFFF, 0xFFFFFFFF, 0x04040404, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x04040404, 0x00000000,
0x04040404, 0xFFFFFFFF, 0xFBFBFBFB, 0xFBFBFBFB,
0x04040404, 0xFFFFFFFF, 0xFBFBFBFB, 0xFBFBFBFB
},
{
0x08080808, 0x00000000, 0x08080808, 0xFFFFFFFF,
0x08080808, 0x00000000, 0x08080808, 0xFFFFFFFF,
0xF7F7F7F7, 0xF7F7F7F7, 0x08080808, 0xF7F7F7F7,
0xF7F7F7F7, 0xF7F7F7F7, 0x08080808, 0xF7F7F7F7,
0x08080808, 0xF7F7F7F7, 0x08080808, 0x08080808,
0x08080808, 0xF7F7F7F7, 0x08080808, 0x08080808,
0xF7F7F7F7, 0x08080808, 0xF7F7F7F7, 0x00000000,
0xF7F7F7F7, 0x08080808, 0xF7F7F7F7, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x08080808,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x08080808,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0xF7F7F7F7,
0x00000000, 0x00000000, 0x00000000, 0xF7F7F7F7,
0xF7F7F7F7, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xF7F7F7F7, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0xF7F7F7F7, 0x00000000, 0xF7F7F7F7, 0x00000000,
0xF7F7F7F7, 0x00000000, 0xF7F7F7F7, 0x00000000,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x08080808,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x08080808,
0xFFFFFFFF, 0xFFFFFFFF, 0x08080808, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x08080808, 0x00000000,
0x08080808, 0xFFFFFFFF, 0xF7F7F7F7, 0xF7F7F7F7,
0x08080808, 0xFFFFFFFF, 0xF7F7F7F7, 0xF7F7F7F7
},
{
0x10101010, 0x00000000, 0x10101010, 0xFFFFFFFF,
0x10101010, 0x00000000, 0x10101010, 0xFFFFFFFF,
0xEFEFEFEF, 0xEFEFEFEF, 0x10101010, 0xEFEFEFEF,
0xEFEFEFEF, 0xEFEFEFEF, 0x10101010, 0xEFEFEFEF,
0x10101010, 0xEFEFEFEF, 0x10101010, 0x10101010,
0x10101010, 0xEFEFEFEF, 0x10101010, 0x10101010,
0xEFEFEFEF, 0x10101010, 0xEFEFEFEF, 0x00000000,
0xEFEFEFEF, 0x10101010, 0xEFEFEFEF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x10101010,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x10101010,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0xEFEFEFEF,
0x00000000, 0x00000000, 0x00000000, 0xEFEFEFEF,
0xEFEFEFEF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xEFEFEFEF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0xEFEFEFEF, 0x00000000, 0xEFEFEFEF, 0x00000000,
0xEFEFEFEF, 0x00000000, 0xEFEFEFEF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x10101010,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x10101010,
0xFFFFFFFF, 0xFFFFFFFF, 0x10101010, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x10101010, 0x00000000,
0x10101010, 0xFFFFFFFF, 0xEFEFEFEF, 0xEFEFEFEF,
0x10101010, 0xFFFFFFFF, 0xEFEFEFEF, 0xEFEFEFEF
},
{
0x20202020, 0x00000000, 0x20202020, 0xFFFFFFFF,
0x20202020, 0x00000000, 0x20202020, 0xFFFFFFFF,
0xDFDFDFDF, 0xDFDFDFDF, 0x20202020, 0xDFDFDFDF,
0xDFDFDFDF, 0xDFDFDFDF, 0x20202020, 0xDFDFDFDF,
0x20202020, 0xDFDFDFDF, 0x20202020, 0x20202020,
0x20202020, 0xDFDFDFDF, 0x20202020, 0x20202020,
0xDFDFDFDF, 0x20202020, 0xDFDFDFDF, 0x00000000,
0xDFDFDFDF, 0x20202020, 0xDFDFDFDF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x20202020,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x20202020,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0xDFDFDFDF,
0x00000000, 0x00000000, 0x00000000, 0xDFDFDFDF,
0xDFDFDFDF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xDFDFDFDF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0xDFDFDFDF, 0x00000000, 0xDFDFDFDF, 0x00000000,
0xDFDFDFDF, 0x00000000, 0xDFDFDFDF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x20202020,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x20202020,
0xFFFFFFFF, 0xFFFFFFFF, 0x20202020, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x20202020, 0x00000000,
0x20202020, 0xFFFFFFFF, 0xDFDFDFDF, 0xDFDFDFDF,
0x20202020, 0xFFFFFFFF, 0xDFDFDFDF, 0xDFDFDFDF
},
{
0x40404040, 0x00000000, 0x40404040, 0xFFFFFFFF,
0x40404040, 0x00000000, 0x40404040, 0xFFFFFFFF,
0xBFBFBFBF, 0xBFBFBFBF, 0x40404040, 0xBFBFBFBF,
0xBFBFBFBF, 0xBFBFBFBF, 0x40404040, 0xBFBFBFBF,
0x40404040, 0xBFBFBFBF, 0x40404040, 0x40404040,
0x40404040, 0xBFBFBFBF, 0x40404040, 0x40404040,
0xBFBFBFBF, 0x40404040, 0xBFBFBFBF, 0x00000000,
0xBFBFBFBF, 0x40404040, 0xBFBFBFBF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x40404040,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x40404040,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0xBFBFBFBF,
0x00000000, 0x00000000, 0x00000000, 0xBFBFBFBF,
0xBFBFBFBF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xBFBFBFBF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0xBFBFBFBF, 0x00000000, 0xBFBFBFBF, 0x00000000,
0xBFBFBFBF, 0x00000000, 0xBFBFBFBF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x40404040,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x40404040,
0xFFFFFFFF, 0xFFFFFFFF, 0x40404040, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x40404040, 0x00000000,
0x40404040, 0xFFFFFFFF, 0xBFBFBFBF, 0xBFBFBFBF,
0x40404040, 0xFFFFFFFF, 0xBFBFBFBF, 0xBFBFBFBF
},
{
0x80808080, 0x00000000, 0x80808080, 0xFFFFFFFF,
0x80808080, 0x00000000, 0x80808080, 0xFFFFFFFF,
0x7F7F7F7F, 0x7F7F7F7F, 0x80808080, 0x7F7F7F7F,
0x7F7F7F7F, 0x7F7F7F7F, 0x80808080, 0x7F7F7F7F,
0x80808080, 0x7F7F7F7F, 0x80808080, 0x80808080,
0x80808080, 0x7F7F7F7F, 0x80808080, 0x80808080,
0x7F7F7F7F, 0x80808080, 0x7F7F7F7F, 0x00000000,
0x7F7F7F7F, 0x80808080, 0x7F7F7F7F, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x80808080,
0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x80808080,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x7F7F7F7F,
0x00000000, 0x00000000, 0x00000000, 0x7F7F7F7F,
0x7F7F7F7F, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x7F7F7F7F, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x00000000, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
0x7F7F7F7F, 0x00000000, 0x7F7F7F7F, 0x00000000,
0x7F7F7F7F, 0x00000000, 0x7F7F7F7F, 0x00000000,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x80808080,
0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x80808080,
0xFFFFFFFF, 0xFFFFFFFF, 0x80808080, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x80808080, 0x00000000,
0x80808080, 0xFFFFFFFF, 0x7F7F7F7F, 0x7F7F7F7F,
0x80808080, 0xFFFFFFFF, 0x7F7F7F7F, 0x7F7F7F7F
}
};
u32 killer_pattern_64b[DQ_NUM][LEN_KILLER_PATTERN] __aligned(32) = {
{
0x01010101, 0x01010101, 0x00000000, 0x00000000,
0x01010101, 0x01010101, 0xFFFFFFFF, 0xFFFFFFFF,
0xFEFEFEFE, 0xFEFEFEFE, 0xFEFEFEFE, 0xFEFEFEFE,
0x01010101, 0x01010101, 0xFEFEFEFE, 0xFEFEFEFE,
0x01010101, 0x01010101, 0xFEFEFEFE, 0xFEFEFEFE,
0x01010101, 0x01010101, 0x01010101, 0x01010101,
0xFEFEFEFE, 0xFEFEFEFE, 0x01010101, 0x01010101,
0xFEFEFEFE, 0xFEFEFEFE, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x01010101, 0x01010101,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFEFEFEFE, 0xFEFEFEFE,
0xFEFEFEFE, 0xFEFEFEFE, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFEFEFEFE, 0xFEFEFEFE, 0x00000000, 0x00000000,
0xFEFEFEFE, 0xFEFEFEFE, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x01010101, 0x01010101,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x01010101, 0x01010101, 0x00000000, 0x00000000,
0x01010101, 0x01010101, 0xFFFFFFFF, 0xFFFFFFFF,
0xFEFEFEFE, 0xFEFEFEFE, 0xFEFEFEFE, 0xFEFEFEFE
},
{
0x02020202, 0x02020202, 0x00000000, 0x00000000,
0x02020202, 0x02020202, 0xFFFFFFFF, 0xFFFFFFFF,
0xFDFDFDFD, 0xFDFDFDFD, 0xFDFDFDFD, 0xFDFDFDFD,
0x02020202, 0x02020202, 0xFDFDFDFD, 0xFDFDFDFD,
0x02020202, 0x02020202, 0xFDFDFDFD, 0xFDFDFDFD,
0x02020202, 0x02020202, 0x02020202, 0x02020202,
0xFDFDFDFD, 0xFDFDFDFD, 0x02020202, 0x02020202,
0xFDFDFDFD, 0xFDFDFDFD, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x02020202, 0x02020202,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFDFDFDFD, 0xFDFDFDFD,
0xFDFDFDFD, 0xFDFDFDFD, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFDFDFDFD, 0xFDFDFDFD, 0x00000000, 0x00000000,
0xFDFDFDFD, 0xFDFDFDFD, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x02020202, 0x02020202,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x02020202, 0x02020202, 0x00000000, 0x00000000,
0x02020202, 0x02020202, 0xFFFFFFFF, 0xFFFFFFFF,
0xFDFDFDFD, 0xFDFDFDFD, 0xFDFDFDFD, 0xFDFDFDFD
},
{
0x04040404, 0x04040404, 0x00000000, 0x00000000,
0x04040404, 0x04040404, 0xFFFFFFFF, 0xFFFFFFFF,
0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB,
0x04040404, 0x04040404, 0xFBFBFBFB, 0xFBFBFBFB,
0x04040404, 0x04040404, 0xFBFBFBFB, 0xFBFBFBFB,
0x04040404, 0x04040404, 0x04040404, 0x04040404,
0xFBFBFBFB, 0xFBFBFBFB, 0x04040404, 0x04040404,
0xFBFBFBFB, 0xFBFBFBFB, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x04040404, 0x04040404,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFBFBFBFB, 0xFBFBFBFB,
0xFBFBFBFB, 0xFBFBFBFB, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFBFBFBFB, 0xFBFBFBFB, 0x00000000, 0x00000000,
0xFBFBFBFB, 0xFBFBFBFB, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x04040404, 0x04040404,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x04040404, 0x04040404, 0x00000000, 0x00000000,
0x04040404, 0x04040404, 0xFFFFFFFF, 0xFFFFFFFF,
0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB
},
{
0x08080808, 0x08080808, 0x00000000, 0x00000000,
0x08080808, 0x08080808, 0xFFFFFFFF, 0xFFFFFFFF,
0xF7F7F7F7, 0xF7F7F7F7, 0xF7F7F7F7, 0xF7F7F7F7,
0x08080808, 0x08080808, 0xF7F7F7F7, 0xF7F7F7F7,
0x08080808, 0x08080808, 0xF7F7F7F7, 0xF7F7F7F7,
0x08080808, 0x08080808, 0x08080808, 0x08080808,
0xF7F7F7F7, 0xF7F7F7F7, 0x08080808, 0x08080808,
0xF7F7F7F7, 0xF7F7F7F7, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x08080808, 0x08080808,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xF7F7F7F7, 0xF7F7F7F7,
0xF7F7F7F7, 0xF7F7F7F7, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xF7F7F7F7, 0xF7F7F7F7, 0x00000000, 0x00000000,
0xF7F7F7F7, 0xF7F7F7F7, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x08080808, 0x08080808,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x08080808, 0x08080808, 0x00000000, 0x00000000,
0x08080808, 0x08080808, 0xFFFFFFFF, 0xFFFFFFFF,
0xF7F7F7F7, 0xF7F7F7F7, 0xF7F7F7F7, 0xF7F7F7F7
},
{
0x10101010, 0x10101010, 0x00000000, 0x00000000,
0x10101010, 0x10101010, 0xFFFFFFFF, 0xFFFFFFFF,
0xEFEFEFEF, 0xEFEFEFEF, 0xEFEFEFEF, 0xEFEFEFEF,
0x10101010, 0x10101010, 0xEFEFEFEF, 0xEFEFEFEF,
0x10101010, 0x10101010, 0xEFEFEFEF, 0xEFEFEFEF,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0xEFEFEFEF, 0xEFEFEFEF, 0x10101010, 0x10101010,
0xEFEFEFEF, 0xEFEFEFEF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x10101010, 0x10101010,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xEFEFEFEF, 0xEFEFEFEF,
0xEFEFEFEF, 0xEFEFEFEF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xEFEFEFEF, 0xEFEFEFEF, 0x00000000, 0x00000000,
0xEFEFEFEF, 0xEFEFEFEF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x10101010, 0x10101010,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x10101010, 0x10101010, 0x00000000, 0x00000000,
0x10101010, 0x10101010, 0xFFFFFFFF, 0xFFFFFFFF,
0xEFEFEFEF, 0xEFEFEFEF, 0xEFEFEFEF, 0xEFEFEFEF
},
{
0x20202020, 0x20202020, 0x00000000, 0x00000000,
0x20202020, 0x20202020, 0xFFFFFFFF, 0xFFFFFFFF,
0xDFDFDFDF, 0xDFDFDFDF, 0xDFDFDFDF, 0xDFDFDFDF,
0x20202020, 0x20202020, 0xDFDFDFDF, 0xDFDFDFDF,
0x20202020, 0x20202020, 0xDFDFDFDF, 0xDFDFDFDF,
0x20202020, 0x20202020, 0x20202020, 0x20202020,
0xDFDFDFDF, 0xDFDFDFDF, 0x20202020, 0x20202020,
0xDFDFDFDF, 0xDFDFDFDF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x20202020, 0x20202020,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xDFDFDFDF, 0xDFDFDFDF,
0xDFDFDFDF, 0xDFDFDFDF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xDFDFDFDF, 0xDFDFDFDF, 0x00000000, 0x00000000,
0xDFDFDFDF, 0xDFDFDFDF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x20202020, 0x20202020,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x20202020, 0x20202020, 0x00000000, 0x00000000,
0x20202020, 0x20202020, 0xFFFFFFFF, 0xFFFFFFFF,
0xDFDFDFDF, 0xDFDFDFDF, 0xDFDFDFDF, 0xDFDFDFDF
},
{
0x40404040, 0x40404040, 0x00000000, 0x00000000,
0x40404040, 0x40404040, 0xFFFFFFFF, 0xFFFFFFFF,
0xBFBFBFBF, 0xBFBFBFBF, 0xBFBFBFBF, 0xBFBFBFBF,
0x40404040, 0x40404040, 0xBFBFBFBF, 0xBFBFBFBF,
0x40404040, 0x40404040, 0xBFBFBFBF, 0xBFBFBFBF,
0x40404040, 0x40404040, 0x40404040, 0x40404040,
0xBFBFBFBF, 0xBFBFBFBF, 0x40404040, 0x40404040,
0xBFBFBFBF, 0xBFBFBFBF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x40404040, 0x40404040,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xBFBFBFBF, 0xBFBFBFBF,
0xBFBFBFBF, 0xBFBFBFBF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xBFBFBFBF, 0xBFBFBFBF, 0x00000000, 0x00000000,
0xBFBFBFBF, 0xBFBFBFBF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x40404040, 0x40404040,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x40404040, 0x40404040, 0x00000000, 0x00000000,
0x40404040, 0x40404040, 0xFFFFFFFF, 0xFFFFFFFF,
0xBFBFBFBF, 0xBFBFBFBF, 0xBFBFBFBF, 0xBFBFBFBF
},
{
0x80808080, 0x80808080, 0x00000000, 0x00000000,
0x80808080, 0x80808080, 0xFFFFFFFF, 0xFFFFFFFF,
0x7F7F7F7F, 0x7F7F7F7F, 0x7F7F7F7F, 0x7F7F7F7F,
0x80808080, 0x80808080, 0x7F7F7F7F, 0x7F7F7F7F,
0x80808080, 0x80808080, 0x7F7F7F7F, 0x7F7F7F7F,
0x80808080, 0x80808080, 0x80808080, 0x80808080,
0x7F7F7F7F, 0x7F7F7F7F, 0x80808080, 0x80808080,
0x7F7F7F7F, 0x7F7F7F7F, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x80808080, 0x80808080,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x7F7F7F7F, 0x7F7F7F7F,
0x7F7F7F7F, 0x7F7F7F7F, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x7F7F7F7F, 0x7F7F7F7F, 0x00000000, 0x00000000,
0x7F7F7F7F, 0x7F7F7F7F, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x80808080, 0x80808080,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x80808080, 0x80808080, 0x00000000, 0x00000000,
0x80808080, 0x80808080, 0xFFFFFFFF, 0xFFFFFFFF,
0x7F7F7F7F, 0x7F7F7F7F, 0x7F7F7F7F, 0x7F7F7F7F
}
};
u32 special_pattern[DQ_NUM][LEN_SPECIAL_PATTERN] __aligned(32) = {
{
0x00000000, 0x00000000, 0x01010101, 0x01010101,
0xFFFFFFFF, 0xFFFFFFFF, 0xFEFEFEFE, 0xFEFEFEFE,
0xFEFEFEFE, 0xFEFEFEFE, 0x01010101, 0x01010101,
0xFEFEFEFE, 0xFEFEFEFE, 0x01010101, 0x01010101,
0xFEFEFEFE, 0xFEFEFEFE, 0x01010101, 0x01010101,
0x01010101, 0x01010101, 0xFEFEFEFE, 0xFEFEFEFE,
0x01010101, 0x01010101, 0xFEFEFEFE, 0xFEFEFEFE,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x01010101, 0x01010101, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFEFEFEFE, 0xFEFEFEFE, 0xFEFEFEFE, 0xFEFEFEFE,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFEFEFEFE, 0xFEFEFEFE,
0x00000000, 0x00000000, 0xFEFEFEFE, 0xFEFEFEFE,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x01010101, 0x01010101, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x01010101, 0x01010101,
0x00000000, 0x00000000, 0x01010101, 0x01010101,
0xFFFFFFFF, 0xFFFFFFFF, 0xFEFEFEFE, 0xFEFEFEFE,
0xFEFEFEFE, 0xFEFEFEFE, 0x00000000, 0x00000000
},
{
0x00000000, 0x00000000, 0x02020202, 0x02020202,
0xFFFFFFFF, 0xFFFFFFFF, 0xFDFDFDFD, 0xFDFDFDFD,
0xFDFDFDFD, 0xFDFDFDFD, 0x02020202, 0x02020202,
0xFDFDFDFD, 0xFDFDFDFD, 0x02020202, 0x02020202,
0xFDFDFDFD, 0xFDFDFDFD, 0x02020202, 0x02020202,
0x02020202, 0x02020202, 0xFDFDFDFD, 0xFDFDFDFD,
0x02020202, 0x02020202, 0xFDFDFDFD, 0xFDFDFDFD,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x02020202, 0x02020202, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFDFDFDFD, 0xFDFDFDFD, 0xFDFDFDFD, 0xFDFDFDFD,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFDFDFDFD, 0xFDFDFDFD,
0x00000000, 0x00000000, 0xFDFDFDFD, 0xFDFDFDFD,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x02020202, 0x02020202, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x02020202, 0x02020202,
0x00000000, 0x00000000, 0x02020202, 0x02020202,
0xFFFFFFFF, 0xFFFFFFFF, 0xFDFDFDFD, 0xFDFDFDFD,
0xFDFDFDFD, 0xFDFDFDFD, 0x00000000, 0x00000000
},
{
0x00000000, 0x00000000, 0x04040404, 0x04040404,
0xFFFFFFFF, 0xFFFFFFFF, 0xFBFBFBFB, 0xFBFBFBFB,
0xFBFBFBFB, 0xFBFBFBFB, 0x04040404, 0x04040404,
0xFBFBFBFB, 0xFBFBFBFB, 0x04040404, 0x04040404,
0xFBFBFBFB, 0xFBFBFBFB, 0x04040404, 0x04040404,
0x04040404, 0x04040404, 0xFBFBFBFB, 0xFBFBFBFB,
0x04040404, 0x04040404, 0xFBFBFBFB, 0xFBFBFBFB,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x04040404, 0x04040404, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFBFBFBFB, 0xFBFBFBFB,
0x00000000, 0x00000000, 0xFBFBFBFB, 0xFBFBFBFB,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x04040404, 0x04040404, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x04040404, 0x04040404,
0x00000000, 0x00000000, 0x04040404, 0x04040404,
0xFFFFFFFF, 0xFFFFFFFF, 0xFBFBFBFB, 0xFBFBFBFB,
0xFBFBFBFB, 0xFBFBFBFB, 0x00000000, 0x00000000
},
{
0x00000000, 0x00000000, 0x08080808, 0x08080808,
0xFFFFFFFF, 0xFFFFFFFF, 0xF7F7F7F7, 0xF7F7F7F7,
0xF7F7F7F7, 0xF7F7F7F7, 0x08080808, 0x08080808,
0xF7F7F7F7, 0xF7F7F7F7, 0x08080808, 0x08080808,
0xF7F7F7F7, 0xF7F7F7F7, 0x08080808, 0x08080808,
0x08080808, 0x08080808, 0xF7F7F7F7, 0xF7F7F7F7,
0x08080808, 0x08080808, 0xF7F7F7F7, 0xF7F7F7F7,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x08080808, 0x08080808, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xF7F7F7F7, 0xF7F7F7F7, 0xF7F7F7F7, 0xF7F7F7F7,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xF7F7F7F7, 0xF7F7F7F7,
0x00000000, 0x00000000, 0xF7F7F7F7, 0xF7F7F7F7,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x08080808, 0x08080808, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x08080808, 0x08080808,
0x00000000, 0x00000000, 0x08080808, 0x08080808,
0xFFFFFFFF, 0xFFFFFFFF, 0xF7F7F7F7, 0xF7F7F7F7,
0xF7F7F7F7, 0xF7F7F7F7, 0x00000000, 0x00000000
},
{
0x00000000, 0x00000000, 0x10101010, 0x10101010,
0xFFFFFFFF, 0xFFFFFFFF, 0xEFEFEFEF, 0xEFEFEFEF,
0xEFEFEFEF, 0xEFEFEFEF, 0x10101010, 0x10101010,
0xEFEFEFEF, 0xEFEFEFEF, 0x10101010, 0x10101010,
0xEFEFEFEF, 0xEFEFEFEF, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0xEFEFEFEF, 0xEFEFEFEF,
0x10101010, 0x10101010, 0xEFEFEFEF, 0xEFEFEFEF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x10101010, 0x10101010, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xEFEFEFEF, 0xEFEFEFEF, 0xEFEFEFEF, 0xEFEFEFEF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xEFEFEFEF, 0xEFEFEFEF,
0x00000000, 0x00000000, 0xEFEFEFEF, 0xEFEFEFEF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x10101010, 0x10101010, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x10101010, 0x10101010,
0x00000000, 0x00000000, 0x10101010, 0x10101010,
0xFFFFFFFF, 0xFFFFFFFF, 0xEFEFEFEF, 0xEFEFEFEF,
0xEFEFEFEF, 0xEFEFEFEF, 0x00000000, 0x00000000
},
{
0x00000000, 0x00000000, 0x20202020, 0x20202020,
0xFFFFFFFF, 0xFFFFFFFF, 0xDFDFDFDF, 0xDFDFDFDF,
0xDFDFDFDF, 0xDFDFDFDF, 0x20202020, 0x20202020,
0xDFDFDFDF, 0xDFDFDFDF, 0x20202020, 0x20202020,
0xDFDFDFDF, 0xDFDFDFDF, 0x20202020, 0x20202020,
0x20202020, 0x20202020, 0xDFDFDFDF, 0xDFDFDFDF,
0x20202020, 0x20202020, 0xDFDFDFDF, 0xDFDFDFDF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x20202020, 0x20202020, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xDFDFDFDF, 0xDFDFDFDF, 0xDFDFDFDF, 0xDFDFDFDF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xDFDFDFDF, 0xDFDFDFDF,
0x00000000, 0x00000000, 0xDFDFDFDF, 0xDFDFDFDF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x20202020, 0x20202020, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x20202020, 0x20202020,
0x00000000, 0x00000000, 0x20202020, 0x20202020,
0xFFFFFFFF, 0xFFFFFFFF, 0xDFDFDFDF, 0xDFDFDFDF,
0xDFDFDFDF, 0xDFDFDFDF, 0x00000000, 0x00000000
},
{
0x00000000, 0x00000000, 0x40404040, 0x40404040,
0xFFFFFFFF, 0xFFFFFFFF, 0xBFBFBFBF, 0xBFBFBFBF,
0xBFBFBFBF, 0xBFBFBFBF, 0x40404040, 0x40404040,
0xBFBFBFBF, 0xBFBFBFBF, 0x40404040, 0x40404040,
0xBFBFBFBF, 0xBFBFBFBF, 0x40404040, 0x40404040,
0x40404040, 0x40404040, 0xBFBFBFBF, 0xBFBFBFBF,
0x40404040, 0x40404040, 0xBFBFBFBF, 0xBFBFBFBF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x40404040, 0x40404040, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xBFBFBFBF, 0xBFBFBFBF, 0xBFBFBFBF, 0xBFBFBFBF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xBFBFBFBF, 0xBFBFBFBF,
0x00000000, 0x00000000, 0xBFBFBFBF, 0xBFBFBFBF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x40404040, 0x40404040, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x40404040, 0x40404040,
0x00000000, 0x00000000, 0x40404040, 0x40404040,
0xFFFFFFFF, 0xFFFFFFFF, 0xBFBFBFBF, 0xBFBFBFBF,
0xBFBFBFBF, 0xBFBFBFBF, 0x00000000, 0x00000000
},
{
0x00000000, 0x00000000, 0x80808080, 0x80808080,
0xFFFFFFFF, 0xFFFFFFFF, 0x7F7F7F7F, 0x7F7F7F7F,
0x7F7F7F7F, 0x7F7F7F7F, 0x80808080, 0x80808080,
0x7F7F7F7F, 0x7F7F7F7F, 0x80808080, 0x80808080,
0x7F7F7F7F, 0x7F7F7F7F, 0x80808080, 0x80808080,
0x80808080, 0x80808080, 0x7F7F7F7F, 0x7F7F7F7F,
0x80808080, 0x80808080, 0x7F7F7F7F, 0x7F7F7F7F,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x80808080, 0x80808080, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x7F7F7F7F, 0x7F7F7F7F, 0x7F7F7F7F, 0x7F7F7F7F,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x7F7F7F7F, 0x7F7F7F7F,
0x00000000, 0x00000000, 0x7F7F7F7F, 0x7F7F7F7F,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0x80808080, 0x80808080, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x80808080, 0x80808080,
0x00000000, 0x00000000, 0x80808080, 0x80808080,
0xFFFFFFFF, 0xFFFFFFFF, 0x7F7F7F7F, 0x7F7F7F7F,
0x7F7F7F7F, 0x7F7F7F7F, 0x00000000, 0x00000000
}
};
/* Fabric ratios table */
u32 fabric_ratio[FAB_OPT] = {
0x04010204,
0x04020202,
0x08020306,
0x08020303,
0x04020303,
0x04020204,
0x04010202,
0x08030606,
0x08030505,
0x04020306,
0x0804050A,
0x04030606,
0x04020404,
0x04030306,
0x04020505,
0x08020505,
0x04010303,
0x08050A0A,
0x04030408,
0x04010102,
0x08030306
};
u32 pbs_dq_mapping[PUP_NUM_64BIT + 1][DQ_NUM] = {
{3, 2, 5, 7, 1, 0, 6, 4},
{2, 3, 6, 7, 1, 0, 4, 5},
{1, 3, 5, 6, 0, 2, 4, 7},
{0, 2, 4, 7, 1, 3, 5, 6},
{3, 0, 4, 6, 1, 2, 5, 7},
{0, 3, 5, 7, 1, 2, 4, 6},
{2, 3, 5, 7, 1, 0, 4, 6},
{0, 2, 5, 4, 1, 3, 6, 7},
{2, 3, 4, 7, 0, 1, 5, 6}
};
#endif /* __DDR3_PATTERNS_64_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/ddr3_pbs.c
+1591
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File diff suppressed because it is too large Load Diff
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/ddr3_read_leveling.c
+1213
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File diff suppressed because it is too large Load Diff
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/ddr3_sdram.c
+668
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@@ -0,0 +1,668 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#include <common.h>
#include <i2c.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include "ddr3_hw_training.h"
#include "xor.h"
#include "xor_regs.h"
static void ddr3_flush_l1_line(u32 line);
extern u32 pbs_pattern[2][LEN_16BIT_PBS_PATTERN];
extern u32 pbs_pattern_32b[2][LEN_PBS_PATTERN];
#if defined(MV88F78X60)
extern u32 pbs_pattern_64b[2][LEN_PBS_PATTERN];
#endif
extern u32 pbs_dq_mapping[PUP_NUM_64BIT][DQ_NUM];
#if defined(MV88F78X60) || defined(MV88F672X)
/* PBS locked dq (per pup) */
u32 pbs_locked_dq[MAX_PUP_NUM][DQ_NUM] = { { 0 } };
u32 pbs_locked_dm[MAX_PUP_NUM] = { 0 };
u32 pbs_locked_value[MAX_PUP_NUM][DQ_NUM] = { { 0 } };
int per_bit_data[MAX_PUP_NUM][DQ_NUM];
#endif
static u32 sdram_data[LEN_KILLER_PATTERN] __aligned(32) = { 0 };
static struct crc_dma_desc dma_desc __aligned(32) = { 0 };
#define XOR_TIMEOUT 0x8000000
struct xor_channel_t {
struct crc_dma_desc *desc;
unsigned long desc_phys_addr;
};
#define XOR_CAUSE_DONE_MASK(chan) ((0x1 | 0x2) << (chan * 16))
void xor_waiton_eng(int chan)
{
int timeout;
timeout = 0;
while (!(reg_read(XOR_CAUSE_REG(XOR_UNIT(chan))) &
XOR_CAUSE_DONE_MASK(XOR_CHAN(chan)))) {
if (timeout > XOR_TIMEOUT)
goto timeout;
timeout++;
}
timeout = 0;
while (mv_xor_state_get(chan) != MV_IDLE) {
if (timeout > XOR_TIMEOUT)
goto timeout;
timeout++;
}
/* Clear int */
reg_write(XOR_CAUSE_REG(XOR_UNIT(chan)),
~(XOR_CAUSE_DONE_MASK(XOR_CHAN(chan))));
timeout:
return;
}
static int special_compare_pattern(u32 uj)
{
if ((uj == 30) || (uj == 31) || (uj == 61) || (uj == 62) ||
(uj == 93) || (uj == 94) || (uj == 126) || (uj == 127))
return 1;
return 0;
}
/*
* Compare code extracted as its used by multiple functions. This
* reduces code-size and makes it easier to maintain it. Additionally
* the code is not indented that much and therefore easier to read.
*/
static void compare_pattern_v1(u32 uj, u32 *pup, u32 *pattern,
u32 pup_groups, int debug_dqs)
{
u32 val;
u32 uk;
u32 var1;
u32 var2;
__maybe_unused u32 dq;
if (((sdram_data[uj]) != (pattern[uj])) && (*pup != 0xFF)) {
for (uk = 0; uk < PUP_NUM_32BIT; uk++) {
val = CMP_BYTE_SHIFT * uk;
var1 = ((sdram_data[uj] >> val) & CMP_BYTE_MASK);
var2 = ((pattern[uj] >> val) & CMP_BYTE_MASK);
if (var1 != var2) {
*pup |= (1 << (uk + (PUP_NUM_32BIT *
(uj % pup_groups))));
#ifdef MV_DEBUG_DQS
if (!debug_dqs)
continue;
for (dq = 0; dq < DQ_NUM; dq++) {
val = uk + (PUP_NUM_32BIT *
(uj % pup_groups));
if (((var1 >> dq) & 0x1) !=
((var2 >> dq) & 0x1))
per_bit_data[val][dq] = 1;
else
per_bit_data[val][dq] = 0;
}
#endif
}
}
}
}
static void compare_pattern_v2(u32 uj, u32 *pup, u32 *pattern)
{
u32 val;
u32 uk;
u32 var1;
u32 var2;
if (((sdram_data[uj]) != (pattern[uj])) && (*pup != 0x3)) {
/* Found error */
for (uk = 0; uk < PUP_NUM_32BIT; uk++) {
val = CMP_BYTE_SHIFT * uk;
var1 = (sdram_data[uj] >> val) & CMP_BYTE_MASK;
var2 = (pattern[uj] >> val) & CMP_BYTE_MASK;
if (var1 != var2)
*pup |= (1 << (uk % PUP_NUM_16BIT));
}
}
}
/*
* Name: ddr3_sdram_compare
* Desc: Execute compare per PUP
* Args: unlock_pup Bit array of the unlock pups
* new_locked_pup Output bit array of the pups with failed compare
* pattern Pattern to compare
* pattern_len Length of pattern (in bytes)
* sdram_offset offset address to the SDRAM
* write write to the SDRAM before read
* mask compare pattern with mask;
* mask_pattern Mask to compare pattern
*
* Notes:
* Returns: MV_OK if success, other error code if fail.
*/
int ddr3_sdram_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
u32 *new_locked_pup, u32 *pattern,
u32 pattern_len, u32 sdram_offset, int write,
int mask, u32 *mask_pattern,
int special_compare)
{
u32 uj;
__maybe_unused u32 pup_groups;
__maybe_unused u32 dq;
#if !defined(MV88F67XX)
if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
pup_groups = 2;
else
pup_groups = 1;
#endif
ddr3_reset_phy_read_fifo();
/* Check if need to write to sdram before read */
if (write == 1)
ddr3_dram_sram_burst((u32)pattern, sdram_offset, pattern_len);
ddr3_dram_sram_burst(sdram_offset, (u32)sdram_data, pattern_len);
/* Compare read result to write */
for (uj = 0; uj < pattern_len; uj++) {
if (special_compare && special_compare_pattern(uj))
continue;
#if defined(MV88F78X60) || defined(MV88F672X)
compare_pattern_v1(uj, new_locked_pup, pattern, pup_groups, 1);
#elif defined(MV88F67XX)
compare_pattern_v2(uj, new_locked_pup, pattern);
#endif
}
return MV_OK;
}
#if defined(MV88F78X60) || defined(MV88F672X)
/*
* Name: ddr3_sdram_dm_compare
* Desc: Execute compare per PUP
* Args: unlock_pup Bit array of the unlock pups
* new_locked_pup Output bit array of the pups with failed compare
* pattern Pattern to compare
* pattern_len Length of pattern (in bytes)
* sdram_offset offset address to the SDRAM
* write write to the SDRAM before read
* mask compare pattern with mask;
* mask_pattern Mask to compare pattern
*
* Notes:
* Returns: MV_OK if success, other error code if fail.
*/
int ddr3_sdram_dm_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
u32 *new_locked_pup, u32 *pattern,
u32 sdram_offset)
{
u32 uj, uk, var1, var2, pup_groups;
u32 val;
u32 pup = 0;
if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
pup_groups = 2;
else
pup_groups = 1;
ddr3_dram_sram_burst((u32)pattern, SDRAM_PBS_TX_OFFS,
LEN_PBS_PATTERN);
ddr3_dram_sram_burst(SDRAM_PBS_TX_OFFS, (u32)sdram_data,
LEN_PBS_PATTERN);
/* Validate the correctness of the results */
for (uj = 0; uj < LEN_PBS_PATTERN; uj++)
compare_pattern_v1(uj, &pup, pattern, pup_groups, 0);
/* Test the DM Signals */
*(u32 *)(SDRAM_PBS_TX_OFFS + 0x10) = 0x12345678;
*(u32 *)(SDRAM_PBS_TX_OFFS + 0x14) = 0x12345678;
sdram_data[0] = *(u32 *)(SDRAM_PBS_TX_OFFS + 0x10);
sdram_data[1] = *(u32 *)(SDRAM_PBS_TX_OFFS + 0x14);
for (uj = 0; uj < 2; uj++) {
if (((sdram_data[uj]) != (pattern[uj])) &&
(*new_locked_pup != 0xFF)) {
for (uk = 0; uk < PUP_NUM_32BIT; uk++) {
val = CMP_BYTE_SHIFT * uk;
var1 = ((sdram_data[uj] >> val) & CMP_BYTE_MASK);
var2 = ((pattern[uj] >> val) & CMP_BYTE_MASK);
if (var1 != var2) {
*new_locked_pup |= (1 << (uk +
(PUP_NUM_32BIT * (uj % pup_groups))));
*new_locked_pup |= pup;
}
}
}
}
return MV_OK;
}
/*
* Name: ddr3_sdram_pbs_compare
* Desc: Execute SRAM compare per PUP and DQ.
* Args: pup_locked bit array of locked pups
* is_tx Indicate whether Rx or Tx
* pbs_pattern_idx Index of PBS pattern
* pbs_curr_val The PBS value
* pbs_lock_val The value to set to locked PBS
* skew_array Global array to update with the compare results
* ai_unlock_pup_dq_array bit array of the locked / unlocked pups per dq.
* Notes:
* Returns: MV_OK if success, other error code if fail.
*/
int ddr3_sdram_pbs_compare(MV_DRAM_INFO *dram_info, u32 pup_locked,
int is_tx, u32 pbs_pattern_idx,
u32 pbs_curr_val, u32 pbs_lock_val,
u32 *skew_array, u8 *unlock_pup_dq_array,
u32 ecc)
{
/* bit array failed dq per pup for current compare */
u32 pbs_write_pup[DQ_NUM] = { 0 };
u32 update_pup; /* pup as HW convention */
u32 max_pup; /* maximal pup index */
u32 pup_addr;
u32 ui, dq, pup;
int var1, var2;
u32 sdram_offset, pup_groups, tmp_pup;
u32 *pattern_ptr;
u32 val;
/* Choose pattern */
switch (dram_info->ddr_width) {
#if defined(MV88F672X)
case 16:
pattern_ptr = (u32 *)&pbs_pattern[pbs_pattern_idx];
break;
#endif
case 32:
pattern_ptr = (u32 *)&pbs_pattern_32b[pbs_pattern_idx];
break;
#if defined(MV88F78X60)
case 64:
pattern_ptr = (u32 *)&pbs_pattern_64b[pbs_pattern_idx];
break;
#endif
default:
return MV_FAIL;
}
max_pup = dram_info->num_of_std_pups;
sdram_offset = SDRAM_PBS_I_OFFS + pbs_pattern_idx * SDRAM_PBS_NEXT_OFFS;
if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
pup_groups = 2;
else
pup_groups = 1;
ddr3_reset_phy_read_fifo();
/* Check if need to write to sdram before read */
if (is_tx == 1) {
ddr3_dram_sram_burst((u32)pattern_ptr, sdram_offset,
LEN_PBS_PATTERN);
}
ddr3_dram_sram_read(sdram_offset, (u32)sdram_data, LEN_PBS_PATTERN);
/* Compare read result to write */
for (ui = 0; ui < LEN_PBS_PATTERN; ui++) {
if ((sdram_data[ui]) != (pattern_ptr[ui])) {
/* found error */
/* error in low pup group */
for (pup = 0; pup < PUP_NUM_32BIT; pup++) {
val = CMP_BYTE_SHIFT * pup;
var1 = ((sdram_data[ui] >> val) &
CMP_BYTE_MASK);
var2 = ((pattern_ptr[ui] >> val) &
CMP_BYTE_MASK);
if (var1 != var2) {
if (dram_info->ddr_width > 16) {
tmp_pup = (pup + PUP_NUM_32BIT *
(ui % pup_groups));
} else {
tmp_pup = (pup % PUP_NUM_16BIT);
}
update_pup = (1 << tmp_pup);
if (ecc && (update_pup != 0x1))
continue;
/*
* Pup is failed - Go over all DQs and
* look for failures
*/
for (dq = 0; dq < DQ_NUM; dq++) {
val = tmp_pup * (1 - ecc) +
ecc * ECC_PUP;
if (((var1 >> dq) & 0x1) !=
((var2 >> dq) & 0x1)) {
if (pbs_locked_dq[val][dq] == 1 &&
pbs_locked_value[val][dq] != pbs_curr_val)
continue;
/*
* Activate write to
* update PBS to
* pbs_lock_val
*/
pbs_write_pup[dq] |=
update_pup;
/*
* Update the
* unlock_pup_dq_array
*/
unlock_pup_dq_array[dq] &=
~update_pup;
/*
* Lock PBS value for
* failed bits in
* compare operation
*/
skew_array[tmp_pup * DQ_NUM + dq] =
pbs_curr_val;
}
}
}
}
}
}
pup_addr = (is_tx == 1) ? PUP_PBS_TX : PUP_PBS_RX;
/* Set last failed bits PBS to min / max pbs value */
for (dq = 0; dq < DQ_NUM; dq++) {
for (pup = 0; pup < max_pup; pup++) {
if (pbs_write_pup[dq] & (1 << pup)) {
val = pup * (1 - ecc) + ecc * ECC_PUP;
if (pbs_locked_dq[val][dq] == 1 &&
pbs_locked_value[val][dq] != pbs_curr_val)
continue;
/* Mark the dq as locked */
pbs_locked_dq[val][dq] = 1;
pbs_locked_value[val][dq] = pbs_curr_val;
ddr3_write_pup_reg(pup_addr +
pbs_dq_mapping[val][dq],
CS0, val, 0, pbs_lock_val);
}
}
}
return MV_OK;
}
#endif
/*
* Name: ddr3_sdram_direct_compare
* Desc: Execute compare per PUP without DMA (no burst mode)
* Args: unlock_pup Bit array of the unlock pups
* new_locked_pup Output bit array of the pups with failed compare
* pattern Pattern to compare
* pattern_len Length of pattern (in bytes)
* sdram_offset offset address to the SDRAM
* write write to the SDRAM before read
* mask compare pattern with mask;
* auiMaskPatter Mask to compare pattern
*
* Notes:
* Returns: MV_OK if success, other error code if fail.
*/
int ddr3_sdram_direct_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
u32 *new_locked_pup, u32 *pattern,
u32 pattern_len, u32 sdram_offset,
int write, int mask, u32 *mask_pattern)
{
u32 uj, uk, pup_groups;
u32 *sdram_addr; /* used to read from SDRAM */
sdram_addr = (u32 *)sdram_offset;
if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
pup_groups = 2;
else
pup_groups = 1;
/* Check if need to write before read */
if (write == 1) {
for (uk = 0; uk < pattern_len; uk++) {
*sdram_addr = pattern[uk];
sdram_addr++;
}
}
sdram_addr = (u32 *)sdram_offset;
for (uk = 0; uk < pattern_len; uk++) {
sdram_data[uk] = *sdram_addr;
sdram_addr++;
}
/* Compare read result to write */
for (uj = 0; uj < pattern_len; uj++) {
if (dram_info->ddr_width > 16) {
compare_pattern_v1(uj, new_locked_pup, pattern,
pup_groups, 0);
} else {
compare_pattern_v2(uj, new_locked_pup, pattern);
}
}
return MV_OK;
}
/*
* Name: ddr3_dram_sram_burst
* Desc: Read from the SDRAM in burst of 64 bytes
* Args: src
* dst
* Notes: Using the XOR mechanism
* Returns: MV_OK if success, other error code if fail.
*/
int ddr3_dram_sram_burst(u32 src, u32 dst, u32 len)
{
u32 chan, byte_count, cs_num, byte;
struct xor_channel_t channel;
chan = 0;
byte_count = len * 4;
/* Wait for previous transfer completion */
while (mv_xor_state_get(chan) != MV_IDLE)
;
/* Build the channel descriptor */
channel.desc = &dma_desc;
/* Enable Address Override and set correct src and dst */
if (src < SRAM_BASE) {
/* src is DRAM CS, dst is SRAM */
cs_num = (src / (1 + SDRAM_CS_SIZE));
reg_write(XOR_ADDR_OVRD_REG(0, 0),
((cs_num << 1) | (1 << 0)));
channel.desc->src_addr0 = (src % (1 + SDRAM_CS_SIZE));
channel.desc->dst_addr = dst;
} else {
/* src is SRAM, dst is DRAM CS */
cs_num = (dst / (1 + SDRAM_CS_SIZE));
reg_write(XOR_ADDR_OVRD_REG(0, 0),
((cs_num << 25) | (1 << 24)));
channel.desc->src_addr0 = (src);
channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE));
channel.desc->src_addr0 = src;
channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE));
}
channel.desc->src_addr1 = 0;
channel.desc->byte_cnt = byte_count;
channel.desc->next_desc_ptr = 0;
channel.desc->status = 1 << 31;
channel.desc->desc_cmd = 0x0;
channel.desc_phys_addr = (unsigned long)&dma_desc;
ddr3_flush_l1_line((u32)&dma_desc);
/* Issue the transfer */
if (mv_xor_transfer(chan, MV_DMA, channel.desc_phys_addr) != MV_OK)
return MV_FAIL;
/* Wait for completion */
xor_waiton_eng(chan);
if (dst > SRAM_BASE) {
for (byte = 0; byte < byte_count; byte += 0x20)
cache_inv(dst + byte);
}
return MV_OK;
}
/*
* Name: ddr3_flush_l1_line
* Desc:
* Args:
* Notes:
* Returns: MV_OK if success, other error code if fail.
*/
static void ddr3_flush_l1_line(u32 line)
{
u32 reg;
#if defined(MV88F672X)
reg = 1;
#else
reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR) &
(1 << REG_SAMPLE_RESET_CPU_ARCH_OFFS);
#ifdef MV88F67XX
reg = ~reg & (1 << REG_SAMPLE_RESET_CPU_ARCH_OFFS);
#endif
#endif
if (reg) {
/* V7 Arch mode */
flush_l1_v7(line);
flush_l1_v7(line + CACHE_LINE_SIZE);
} else {
/* V6 Arch mode */
flush_l1_v6(line);
flush_l1_v6(line + CACHE_LINE_SIZE);
}
}
int ddr3_dram_sram_read(u32 src, u32 dst, u32 len)
{
u32 ui;
u32 *dst_ptr, *src_ptr;
dst_ptr = (u32 *)dst;
src_ptr = (u32 *)src;
for (ui = 0; ui < len; ui++) {
*dst_ptr = *src_ptr;
dst_ptr++;
src_ptr++;
}
return MV_OK;
}
int ddr3_sdram_dqs_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
u32 *new_locked_pup, u32 *pattern,
u32 pattern_len, u32 sdram_offset, int write,
int mask, u32 *mask_pattern,
int special_compare)
{
u32 uj, pup_groups;
if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
pup_groups = 2;
else
pup_groups = 1;
ddr3_reset_phy_read_fifo();
/* Check if need to write to sdram before read */
if (write == 1)
ddr3_dram_sram_burst((u32)pattern, sdram_offset, pattern_len);
ddr3_dram_sram_burst(sdram_offset, (u32)sdram_data, pattern_len);
/* Compare read result to write */
for (uj = 0; uj < pattern_len; uj++) {
if (special_compare && special_compare_pattern(uj))
continue;
if (dram_info->ddr_width > 16) {
compare_pattern_v1(uj, new_locked_pup, pattern,
pup_groups, 1);
} else {
compare_pattern_v2(uj, new_locked_pup, pattern);
}
}
return MV_OK;
}
void ddr3_reset_phy_read_fifo(void)
{
u32 reg;
/* reset read FIFO */
reg = reg_read(REG_DRAM_TRAINING_ADDR);
/* Start Auto Read Leveling procedure */
reg |= (1 << REG_DRAM_TRAINING_RL_OFFS);
/* 0x15B0 - Training Register */
reg_write(REG_DRAM_TRAINING_ADDR, reg);
reg = reg_read(REG_DRAM_TRAINING_2_ADDR);
reg |= ((1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS) +
(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS));
/* [0] = 1 - Enable SW override, [4] = 1 - FIFO reset */
/* 0x15B8 - Training SW 2 Register */
reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
do {
reg = reg_read(REG_DRAM_TRAINING_2_ADDR) &
(1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS);
} while (reg); /* Wait for '0' */
reg = reg_read(REG_DRAM_TRAINING_ADDR);
/* Clear Auto Read Leveling procedure */
reg &= ~(1 << REG_DRAM_TRAINING_RL_OFFS);
/* 0x15B0 - Training Register */
reg_write(REG_DRAM_TRAINING_ADDR, reg);
}
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/ddr3_spd.c
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source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/ddr3_write_leveling.c
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source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/xor.c
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#include <common.h>
#include <i2c.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include "xor.h"
#include "xor_regs.h"
static u32 xor_regs_ctrl_backup;
static u32 xor_regs_base_backup[MAX_CS];
static u32 xor_regs_mask_backup[MAX_CS];
static int mv_xor_cmd_set(u32 chan, int command);
static int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl);
void mv_sys_xor_init(MV_DRAM_INFO *dram_info)
{
u32 reg, ui, base, cs_count;
xor_regs_ctrl_backup = reg_read(XOR_WINDOW_CTRL_REG(0, 0));
for (ui = 0; ui < MAX_CS; ui++)
xor_regs_base_backup[ui] = reg_read(XOR_BASE_ADDR_REG(0, ui));
for (ui = 0; ui < MAX_CS; ui++)
xor_regs_mask_backup[ui] = reg_read(XOR_SIZE_MASK_REG(0, ui));
reg = 0;
for (ui = 0; ui < (dram_info->num_cs + 1); ui++) {
/* Enable Window x for each CS */
reg |= (0x1 << (ui));
/* Enable Window x for each CS */
reg |= (0x3 << ((ui * 2) + 16));
}
reg_write(XOR_WINDOW_CTRL_REG(0, 0), reg);
/* Last window - Base - 0x40000000, Attribute 0x1E - SRAM */
base = (SRAM_BASE & 0xFFFF0000) | 0x1E00;
reg_write(XOR_BASE_ADDR_REG(0, dram_info->num_cs), base);
/* Last window - Size - 64 MB */
reg_write(XOR_SIZE_MASK_REG(0, dram_info->num_cs), 0x03FF0000);
cs_count = 0;
for (ui = 0; ui < MAX_CS; ui++) {
if (dram_info->cs_ena & (1 << ui)) {
/*
* Window x - Base - 0x00000000, Attribute 0x0E - DRAM
*/
base = 0;
switch (ui) {
case 0:
base |= 0xE00;
break;
case 1:
base |= 0xD00;
break;
case 2:
base |= 0xB00;
break;
case 3:
base |= 0x700;
break;
}
reg_write(XOR_BASE_ADDR_REG(0, cs_count), base);
/* Window x - Size - 256 MB */
reg_write(XOR_SIZE_MASK_REG(0, cs_count), 0x0FFF0000);
cs_count++;
}
}
mv_xor_hal_init(1);
return;
}
void mv_sys_xor_finish(void)
{
u32 ui;
reg_write(XOR_WINDOW_CTRL_REG(0, 0), xor_regs_ctrl_backup);
for (ui = 0; ui < MAX_CS; ui++)
reg_write(XOR_BASE_ADDR_REG(0, ui), xor_regs_base_backup[ui]);
for (ui = 0; ui < MAX_CS; ui++)
reg_write(XOR_SIZE_MASK_REG(0, ui), xor_regs_mask_backup[ui]);
reg_write(XOR_ADDR_OVRD_REG(0, 0), 0);
}
/*
* mv_xor_hal_init - Initialize XOR engine
*
* DESCRIPTION:
* This function initialize XOR unit.
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
*/
void mv_xor_hal_init(u32 chan_num)
{
u32 i;
/* Abort any XOR activity & set default configuration */
for (i = 0; i < chan_num; i++) {
mv_xor_cmd_set(i, MV_STOP);
mv_xor_ctrl_set(i, (1 << XEXCR_REG_ACC_PROTECT_OFFS) |
(4 << XEXCR_DST_BURST_LIMIT_OFFS) |
(4 << XEXCR_SRC_BURST_LIMIT_OFFS));
}
}
/*
* mv_xor_ctrl_set - Set XOR channel control registers
*
* DESCRIPTION:
*
* INPUT:
*
* OUTPUT:
* None.
*
* RETURN:
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
* NOTE:
* This function does not modify the OperationMode field of control register.
*
*/
static int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl)
{
u32 val;
/* Update the XOR Engine [0..1] Configuration Registers (XExCR) */
val = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)))
& XEXCR_OPERATION_MODE_MASK;
xor_ctrl &= ~XEXCR_OPERATION_MODE_MASK;
xor_ctrl |= val;
reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xor_ctrl);
return MV_OK;
}
int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high,
u32 init_val_low)
{
u32 tmp;
/* Parameter checking */
if (chan >= MV_XOR_MAX_CHAN)
return MV_BAD_PARAM;
if (MV_ACTIVE == mv_xor_state_get(chan))
return MV_BUSY;
if ((block_size < XEXBSR_BLOCK_SIZE_MIN_VALUE) ||
(block_size > XEXBSR_BLOCK_SIZE_MAX_VALUE))
return MV_BAD_PARAM;
/* Set the operation mode to Memory Init */
tmp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)));
tmp &= ~XEXCR_OPERATION_MODE_MASK;
tmp |= XEXCR_OPERATION_MODE_MEM_INIT;
reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), tmp);
/*
* Update the start_ptr field in XOR Engine [0..1] Destination Pointer
* Register (XExDPR0)
*/
reg_write(XOR_DST_PTR_REG(XOR_UNIT(chan), XOR_CHAN(chan)), start_ptr);
/*
* Update the BlockSize field in the XOR Engine[0..1] Block Size
* Registers (XExBSR)
*/
reg_write(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
block_size);
/*
* Update the field InitValL in the XOR Engine Initial Value Register
* Low (XEIVRL)
*/
reg_write(XOR_INIT_VAL_LOW_REG(XOR_UNIT(chan)), init_val_low);
/*
* Update the field InitValH in the XOR Engine Initial Value Register
* High (XEIVRH)
*/
reg_write(XOR_INIT_VAL_HIGH_REG(XOR_UNIT(chan)), init_val_high);
/* Start transfer */
reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
XEXACTR_XESTART_MASK);
return MV_OK;
}
/*
* mv_xor_transfer - Transfer data from source to destination on one of
* three modes (XOR,CRC32,DMA)
*
* DESCRIPTION:
* This function initiates XOR channel, according to function parameters,
* in order to perform XOR or CRC32 or DMA transaction.
* To gain maximum performance the user is asked to keep the following
* restrictions:
* 1) Selected engine is available (not busy).
* 1) This module does not take into consideration CPU MMU issues.
* In order for the XOR engine to access the appropreate source
* and destination, address parameters must be given in system
* physical mode.
* 2) This API does not take care of cache coherency issues. The source,
* destination and in case of chain the descriptor list are assumed
* to be cache coherent.
* 4) Parameters validity. For example, does size parameter exceeds
* maximum byte count of descriptor mode (16M or 64K).
*
* INPUT:
* chan - XOR channel number. See MV_XOR_CHANNEL enumerator.
* xor_type - One of three: XOR, CRC32 and DMA operations.
* xor_chain_ptr - address of chain pointer
*
* OUTPUT:
* None.
*
* RETURS:
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
*
*/
int mv_xor_transfer(u32 chan, int xor_type, u32 xor_chain_ptr)
{
u32 tmp;
/* Parameter checking */
if (chan >= MV_XOR_MAX_CHAN) {
debug("%s: ERR. Invalid chan num %d\n", __func__, chan);
return MV_BAD_PARAM;
}
if (MV_ACTIVE == mv_xor_state_get(chan)) {
debug("%s: ERR. Channel is already active\n", __func__);
return MV_BUSY;
}
if (0x0 == xor_chain_ptr) {
debug("%s: ERR. xor_chain_ptr is NULL pointer\n", __func__);
return MV_BAD_PARAM;
}
/* Read configuration register and mask the operation mode field */
tmp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)));
tmp &= ~XEXCR_OPERATION_MODE_MASK;
switch (xor_type) {
case MV_XOR:
if (0 != (xor_chain_ptr & XEXDPR_DST_PTR_XOR_MASK)) {
debug("%s: ERR. Invalid chain pointer (bits [5:0] must be cleared)\n",
__func__);
return MV_BAD_PARAM;
}
/* Set the operation mode to XOR */
tmp |= XEXCR_OPERATION_MODE_XOR;
break;
case MV_DMA:
if (0 != (xor_chain_ptr & XEXDPR_DST_PTR_DMA_MASK)) {
debug("%s: ERR. Invalid chain pointer (bits [4:0] must be cleared)\n",
__func__);
return MV_BAD_PARAM;
}
/* Set the operation mode to DMA */
tmp |= XEXCR_OPERATION_MODE_DMA;
break;
case MV_CRC32:
if (0 != (xor_chain_ptr & XEXDPR_DST_PTR_CRC_MASK)) {
debug("%s: ERR. Invalid chain pointer (bits [4:0] must be cleared)\n",
__func__);
return MV_BAD_PARAM;
}
/* Set the operation mode to CRC32 */
tmp |= XEXCR_OPERATION_MODE_CRC;
break;
default:
return MV_BAD_PARAM;
}
/* Write the operation mode to the register */
reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), tmp);
/*
* Update the NextDescPtr field in the XOR Engine [0..1] Next Descriptor
* Pointer Register (XExNDPR)
*/
reg_write(XOR_NEXT_DESC_PTR_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
xor_chain_ptr);
/* Start transfer */
reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
XEXACTR_XESTART_MASK);
return MV_OK;
}
/*
* mv_xor_state_get - Get XOR channel state.
*
* DESCRIPTION:
* XOR channel activity state can be active, idle, paused.
* This function retrunes the channel activity state.
*
* INPUT:
* chan - the channel number
*
* OUTPUT:
* None.
*
* RETURN:
* XOR_CHANNEL_IDLE - If the engine is idle.
* XOR_CHANNEL_ACTIVE - If the engine is busy.
* XOR_CHANNEL_PAUSED - If the engine is paused.
* MV_UNDEFINED_STATE - If the engine state is undefind or there is no
* such engine
*
*/
int mv_xor_state_get(u32 chan)
{
u32 state;
/* Parameter checking */
if (chan >= MV_XOR_MAX_CHAN) {
debug("%s: ERR. Invalid chan num %d\n", __func__, chan);
return MV_UNDEFINED_STATE;
}
/* Read the current state */
state = reg_read(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)));
state &= XEXACTR_XESTATUS_MASK;
/* Return the state */
switch (state) {
case XEXACTR_XESTATUS_IDLE:
return MV_IDLE;
case XEXACTR_XESTATUS_ACTIVE:
return MV_ACTIVE;
case XEXACTR_XESTATUS_PAUSED:
return MV_PAUSED;
}
return MV_UNDEFINED_STATE;
}
/*
* mv_xor_cmd_set - Set command of XOR channel
*
* DESCRIPTION:
* XOR channel can be started, idle, paused and restarted.
* Paused can be set only if channel is active.
* Start can be set only if channel is idle or paused.
* Restart can be set only if channel is paused.
* Stop can be set only if channel is active.
*
* INPUT:
* chan - The channel number
* command - The command type (start, stop, restart, pause)
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK on success , MV_BAD_PARAM on erroneous parameter, MV_ERROR on
* undefind XOR engine mode
*
*/
static int mv_xor_cmd_set(u32 chan, int command)
{
int state;
/* Parameter checking */
if (chan >= MV_XOR_MAX_CHAN) {
debug("%s: ERR. Invalid chan num %d\n", __func__, chan);
return MV_BAD_PARAM;
}
/* Get the current state */
state = mv_xor_state_get(chan);
/* Command is start and current state is idle */
if ((command == MV_START) && (state == MV_IDLE)) {
reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
XEXACTR_XESTART_MASK);
return MV_OK;
}
/* Command is stop and current state is active */
else if ((command == MV_STOP) && (state == MV_ACTIVE)) {
reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
XEXACTR_XESTOP_MASK);
return MV_OK;
}
/* Command is paused and current state is active */
else if ((command == MV_PAUSED) && (state == MV_ACTIVE)) {
reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
XEXACTR_XEPAUSE_MASK);
return MV_OK;
}
/* Command is restart and current state is paused */
else if ((command == MV_RESTART) && (state == MV_PAUSED)) {
reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)),
XEXACTR_XERESTART_MASK);
return MV_OK;
}
/* Command is stop and current state is active */
else if ((command == MV_STOP) && (state == MV_IDLE))
return MV_OK;
/* Illegal command */
debug("%s: ERR. Illegal command\n", __func__);
return MV_BAD_PARAM;
}
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/xor.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef __XOR_H
#define __XOR_H
#include "ddr3_hw_training.h"
#define MV_XOR_MAX_CHAN 4 /* total channels for all units together */
/*
* This enumerator describes the type of functionality the XOR channel
* can have while using the same data structures.
*/
enum xor_type {
MV_XOR, /* XOR channel functions as XOR accelerator */
MV_DMA, /* XOR channel functions as IDMA channel */
MV_CRC32 /* XOR channel functions as CRC 32 calculator */
};
/*
* This enumerator describes the set of commands that can be applied on
* an engine (e.g. IDMA, XOR). Appling a comman depends on the current
* status (see MV_STATE enumerator)
* Start can be applied only when status is IDLE
* Stop can be applied only when status is IDLE, ACTIVE or PAUSED
* Pause can be applied only when status is ACTIVE
* Restart can be applied only when status is PAUSED
*/
enum mv_command {
MV_START, /* Start */
MV_STOP, /* Stop */
MV_PAUSE, /* Pause */
MV_RESTART /* Restart */
};
/*
* This enumerator describes the set of state conditions.
* Moving from one state to other is stricted.
*/
enum mv_state {
MV_IDLE,
MV_ACTIVE,
MV_PAUSED,
MV_UNDEFINED_STATE
};
/* XOR descriptor structure for CRC and DMA descriptor */
struct crc_dma_desc {
u32 status; /* Successful descriptor execution indication */
u32 crc32_result; /* Result of CRC-32 calculation */
u32 desc_cmd; /* type of operation to be carried out on the data */
u32 next_desc_ptr; /* Next descriptor address pointer */
u32 byte_cnt; /* Size of source block part represented by the descriptor */
u32 dst_addr; /* Destination Block address pointer (not used in CRC32 */
u32 src_addr0; /* Mode: Source Block address pointer */
u32 src_addr1; /* Mode: Source Block address pointer */
} __packed;
void mv_xor_hal_init(u32 chan_num);
int mv_xor_state_get(u32 chan);
void mv_sys_xor_init(MV_DRAM_INFO *dram_info);
void mv_sys_xor_finish(void);
int mv_xor_transfer(u32 chan, int xor_type, u32 xor_chain_ptr);
int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high,
u32 init_val_low);
#endif /* __XOR_H */
source/bootloader/u-boot-2020.01/drivers/ddr/marvell/axp/xor_regs.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef __XOR_REGS_H
#define __XOR_REGS_H
/*
* For controllers that have two XOR units, then chans 2 & 3 will be mapped
* to channels 0 & 1 of unit 1
*/
#define XOR_UNIT(chan) ((chan) >> 1)
#define XOR_CHAN(chan) ((chan) & 1)
#ifdef CONFIG_ARMADA_MSYS
#define MV_XOR_REGS_OFFSET(unit) (0xF0800)
#else
#define MV_XOR_REGS_OFFSET(unit) (0x60900)
#endif
#define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit))
/* XOR Engine Control Register Map */
#define XOR_CHANNEL_ARBITER_REG(unit) (MV_XOR_REGS_BASE(unit))
#define XOR_CONFIG_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x10 + ((chan) * 4)))
#define XOR_ACTIVATION_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x20 + ((chan) * 4)))
/* XOR Engine Interrupt Register Map */
#define XOR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x30)
#define XOR_MASK_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x40)
#define XOR_ERROR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x50)
#define XOR_ERROR_ADDR_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x60)
/* XOR Engine Descriptor Register Map */
#define XOR_NEXT_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x200 + ((chan) * 4)))
#define XOR_CURR_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x210 + ((chan) * 4)))
#define XOR_BYTE_COUNT_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x220 + ((chan) * 4)))
#define XOR_DST_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x2B0 + ((chan) * 4)))
#define XOR_BLOCK_SIZE_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x2C0 + ((chan) * 4)))
#define XOR_TIMER_MODE_CTRL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D0)
#define XOR_TIMER_MODE_INIT_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D4)
#define XOR_TIMER_MODE_CURR_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D8)
#define XOR_INIT_VAL_LOW_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2E0)
#define XOR_INIT_VAL_HIGH_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2E4)
/* XOR register fileds */
/* XOR Engine [0..1] Configuration Registers (XExCR) */
#define XEXCR_OPERATION_MODE_OFFS (0)
#define XEXCR_OPERATION_MODE_MASK (7 << XEXCR_OPERATION_MODE_OFFS)
#define XEXCR_OPERATION_MODE_XOR (0 << XEXCR_OPERATION_MODE_OFFS)
#define XEXCR_OPERATION_MODE_CRC (1 << XEXCR_OPERATION_MODE_OFFS)
#define XEXCR_OPERATION_MODE_DMA (2 << XEXCR_OPERATION_MODE_OFFS)
#define XEXCR_OPERATION_MODE_ECC (3 << XEXCR_OPERATION_MODE_OFFS)
#define XEXCR_OPERATION_MODE_MEM_INIT (4 << XEXCR_OPERATION_MODE_OFFS)
#define XEXCR_SRC_BURST_LIMIT_OFFS (4)
#define XEXCR_SRC_BURST_LIMIT_MASK (7 << XEXCR_SRC_BURST_LIMIT_OFFS)
#define XEXCR_DST_BURST_LIMIT_OFFS (8)
#define XEXCR_DST_BURST_LIMIT_MASK (7 << XEXCR_DST_BURST_LIMIT_OFFS)
#define XEXCR_DRD_RES_SWP_OFFS (12)
#define XEXCR_DRD_RES_SWP_MASK (1 << XEXCR_DRD_RES_SWP_OFFS)
#define XEXCR_DWR_REQ_SWP_OFFS (13)
#define XEXCR_DWR_REQ_SWP_MASK (1 << XEXCR_DWR_REQ_SWP_OFFS)
#define XEXCR_DES_SWP_OFFS (14)
#define XEXCR_DES_SWP_MASK (1 << XEXCR_DES_SWP_OFFS)
#define XEXCR_REG_ACC_PROTECT_OFFS (15)
#define XEXCR_REG_ACC_PROTECT_MASK (1 << XEXCR_REG_ACC_PROTECT_OFFS)
/* XOR Engine [0..1] Activation Registers (XExACTR) */
#define XEXACTR_XESTART_OFFS (0)
#define XEXACTR_XESTART_MASK (1 << XEXACTR_XESTART_OFFS)
#define XEXACTR_XESTOP_OFFS (1)
#define XEXACTR_XESTOP_MASK (1 << XEXACTR_XESTOP_OFFS)
#define XEXACTR_XEPAUSE_OFFS (2)
#define XEXACTR_XEPAUSE_MASK (1 << XEXACTR_XEPAUSE_OFFS)
#define XEXACTR_XERESTART_OFFS (3)
#define XEXACTR_XERESTART_MASK (1 << XEXACTR_XERESTART_OFFS)
#define XEXACTR_XESTATUS_OFFS (4)
#define XEXACTR_XESTATUS_MASK (3 << XEXACTR_XESTATUS_OFFS)
#define XEXACTR_XESTATUS_IDLE (0 << XEXACTR_XESTATUS_OFFS)
#define XEXACTR_XESTATUS_ACTIVE (1 << XEXACTR_XESTATUS_OFFS)
#define XEXACTR_XESTATUS_PAUSED (2 << XEXACTR_XESTATUS_OFFS)
/* XOR Engine [0..1] Destination Pointer Register (XExDPR0) */
#define XEXDPR_DST_PTR_OFFS (0)
#define XEXDPR_DST_PTR_MASK (0xFFFFFFFF << XEXDPR_DST_PTR_OFFS)
#define XEXDPR_DST_PTR_XOR_MASK (0x3F)
#define XEXDPR_DST_PTR_DMA_MASK (0x1F)
#define XEXDPR_DST_PTR_CRC_MASK (0x1F)
/* XOR Engine[0..1] Block Size Registers (XExBSR) */
#define XEXBSR_BLOCK_SIZE_OFFS (0)
#define XEXBSR_BLOCK_SIZE_MASK (0xFFFFFFFF << XEXBSR_BLOCK_SIZE_OFFS)
#define XEXBSR_BLOCK_SIZE_MIN_VALUE (128)
#define XEXBSR_BLOCK_SIZE_MAX_VALUE (0xFFFFFFFF)
/* XOR Engine Address Decoding Register Map */
#define XOR_WINDOW_CTRL_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x240 + ((chan) * 4)))
#define XOR_BASE_ADDR_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x250 + ((win) * 4)))
#define XOR_SIZE_MASK_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x270 + ((win) * 4)))
#define XOR_HIGH_ADDR_REMAP_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x290 + ((win) * 4)))
#define XOR_ADDR_OVRD_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x2A0 + ((win) * 4)))
#endif /* __XOR_REGS_H */