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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
21813 changed files with 4413081 additions and 0 deletions
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source/bootloader/u-boot-2020.01/drivers/net/fm/Makefile
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# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2009-2011 Freescale Semiconductor, Inc.
obj-y += dtsec.o
obj-y += eth.o
obj-y += fdt.o
obj-y += fm.o
obj-y += init.o
obj-y += tgec.o
obj-y += tgec_phy.o
# Soc have FMAN v3 with mEMAC
obj-$(CONFIG_SYS_FMAN_V3) += memac_phy.o
obj-$(CONFIG_SYS_FMAN_V3) += memac.o
# SoC specific SERDES support
obj-$(CONFIG_ARCH_P1023) += p1023.o
# The P204x, P304x, and P5020 are the same
obj-$(CONFIG_ARCH_P2041) += p5020.o
obj-$(CONFIG_ARCH_P3041) += p5020.o
obj-$(CONFIG_ARCH_P4080) += p4080.o
obj-$(CONFIG_ARCH_P5020) += p5020.o
obj-$(CONFIG_ARCH_P5040) += p5040.o
obj-$(CONFIG_ARCH_T1040) += t1040.o
obj-$(CONFIG_ARCH_T1042) += t1040.o
obj-$(CONFIG_ARCH_T1023) += t1024.o
obj-$(CONFIG_ARCH_T1024) += t1024.o
obj-$(CONFIG_ARCH_T2080) += t2080.o
obj-$(CONFIG_ARCH_T2081) += t2080.o
obj-$(CONFIG_ARCH_T4240) += t4240.o
obj-$(CONFIG_ARCH_T4160) += t4240.o
obj-$(CONFIG_ARCH_B4420) += b4860.o
obj-$(CONFIG_ARCH_B4860) += b4860.o
obj-$(CONFIG_ARCH_LS1043A) += ls1043.o
obj-$(CONFIG_ARCH_LS1046A) += ls1046.o
source/bootloader/u-boot-2020.01/drivers/net/fm/b4860.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2012 Freescale Semiconductor, Inc.
* Roy Zang <tie-fei.zang@freescale.com>
*/
#include <common.h>
#include <env.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
#include <hwconfig.h>
u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
[FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
[FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
};
static int is_device_disabled(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
}
void fman_disable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
void fman_enable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
u32 serdes2_prtcl;
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
/*B4860 has two 10Gig Mac*/
if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
((is_serdes_configured(XAUI_FM1_MAC9)) ||
#if (!defined(CONFIG_TARGET_B4860QDS) && \
!defined(CONFIG_TARGET_B4R420QDS))
(is_serdes_configured(XFI_FM1_MAC9)) ||
(is_serdes_configured(XFI_FM1_MAC10)) ||
#endif
(is_serdes_configured(XAUI_FM1_MAC10))
))
return PHY_INTERFACE_MODE_XGMII;
#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
if (serdes2_prtcl) {
serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
switch (serdes2_prtcl) {
case 0x80:
case 0x81:
case 0x82:
case 0x83:
case 0x84:
case 0x85:
case 0x86:
case 0x87:
case 0x88:
case 0x89:
case 0x8a:
case 0x8b:
case 0x8c:
case 0x8d:
case 0x8e:
case 0xb1:
case 0xb2:
/*
* Extract hwconfig from environment since environment
* is not setup yet
*/
env_get_f("hwconfig", buffer, sizeof(buffer));
buf = buffer;
/* check if XFI interface enable in hwconfig for 10g */
if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
"sfp_amc", "sfp", buf)) {
if ((port == FM1_10GEC1 ||
port == FM1_10GEC2) &&
((is_serdes_configured(XFI_FM1_MAC9)) ||
(is_serdes_configured(XFI_FM1_MAC10))))
return PHY_INTERFACE_MODE_XGMII;
else if ((port == FM1_DTSEC1) ||
(port == FM1_DTSEC2) ||
(port == FM1_DTSEC3) ||
(port == FM1_DTSEC4))
return PHY_INTERFACE_MODE_NONE;
}
}
}
#endif
/* Fix me need to handle RGMII here first */
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC3:
case FM1_DTSEC4:
case FM1_DTSEC5:
case FM1_DTSEC6:
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
default:
return PHY_INTERFACE_MODE_NONE;
}
return PHY_INTERFACE_MODE_NONE;
}
source/bootloader/u-boot-2020.01/drivers/net/fm/dtsec.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/types.h>
#include <asm/io.h>
#include <fsl_dtsec.h>
#include <fsl_mdio.h>
#include <phy.h>
#include "fm.h"
#define RCTRL_INIT (RCTRL_GRS | RCTRL_UPROM)
#define TCTRL_INIT TCTRL_GTS
#define MACCFG1_INIT MACCFG1_SOFT_RST
#define MACCFG2_INIT (MACCFG2_PRE_LEN(0x7) | MACCFG2_LEN_CHECK | \
MACCFG2_PAD_CRC | MACCFG2_FULL_DUPLEX | \
MACCFG2_IF_MODE_NIBBLE)
/* MAXFRM - maximum frame length register */
#define MAXFRM_MASK 0x00003fff
static void dtsec_init_mac(struct fsl_enet_mac *mac)
{
struct dtsec *regs = mac->base;
/* soft reset */
out_be32(&regs->maccfg1, MACCFG1_SOFT_RST);
udelay(1000);
/* clear soft reset, Rx/Tx MAC disable */
out_be32(&regs->maccfg1, 0);
/* graceful stop rx */
out_be32(&regs->rctrl, RCTRL_INIT);
udelay(1000);
/* graceful stop tx */
out_be32(&regs->tctrl, TCTRL_INIT);
udelay(1000);
/* disable all interrupts */
out_be32(&regs->imask, IMASK_MASK_ALL);
/* clear all events */
out_be32(&regs->ievent, IEVENT_CLEAR_ALL);
/* set the max Rx length */
out_be32(&regs->maxfrm, mac->max_rx_len & MAXFRM_MASK);
/* set the ecntrl to reset value */
out_be32(&regs->ecntrl, ECNTRL_DEFAULT);
/*
* Rx length check, no strip CRC for Rx, pad and append CRC for Tx,
* full duplex
*/
out_be32(&regs->maccfg2, MACCFG2_INIT);
}
static void dtsec_enable_mac(struct fsl_enet_mac *mac)
{
struct dtsec *regs = mac->base;
/* enable Rx/Tx MAC */
setbits_be32(&regs->maccfg1, MACCFG1_RXTX_EN);
/* clear the graceful Rx stop */
clrbits_be32(&regs->rctrl, RCTRL_GRS);
/* clear the graceful Tx stop */
clrbits_be32(&regs->tctrl, TCTRL_GTS);
}
static void dtsec_disable_mac(struct fsl_enet_mac *mac)
{
struct dtsec *regs = mac->base;
/* graceful Rx stop */
setbits_be32(&regs->rctrl, RCTRL_GRS);
/* graceful Tx stop */
setbits_be32(&regs->tctrl, TCTRL_GTS);
/* disable Rx/Tx MAC */
clrbits_be32(&regs->maccfg1, MACCFG1_RXTX_EN);
}
static void dtsec_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr)
{
struct dtsec *regs = mac->base;
u32 mac_addr1, mac_addr2;
/*
* if a station address of 0x12345678ABCD, perform a write to
* MACSTNADDR1 of 0xCDAB7856, MACSTNADDR2 of 0x34120000
*/
mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
(mac_addr[3] << 8) | (mac_addr[2]);
out_be32(&regs->macstnaddr1, mac_addr1);
mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
out_be32(&regs->macstnaddr2, mac_addr2);
}
static void dtsec_set_interface_mode(struct fsl_enet_mac *mac,
phy_interface_t type, int speed)
{
struct dtsec *regs = mac->base;
u32 ecntrl, maccfg2;
/* clear all bits relative with interface mode */
ecntrl = in_be32(&regs->ecntrl);
ecntrl &= ~(ECNTRL_TBIM | ECNTRL_GMIIM | ECNTRL_RPM |
ECNTRL_R100M | ECNTRL_SGMIIM);
maccfg2 = in_be32(&regs->maccfg2);
maccfg2 &= ~MACCFG2_IF_MODE_MASK;
if (speed == SPEED_1000)
maccfg2 |= MACCFG2_IF_MODE_BYTE;
else
maccfg2 |= MACCFG2_IF_MODE_NIBBLE;
/* set interface mode */
switch (type) {
case PHY_INTERFACE_MODE_GMII:
ecntrl |= ECNTRL_GMIIM;
break;
case PHY_INTERFACE_MODE_RGMII:
ecntrl |= (ECNTRL_GMIIM | ECNTRL_RPM);
if (speed == SPEED_100)
ecntrl |= ECNTRL_R100M;
break;
case PHY_INTERFACE_MODE_RMII:
if (speed == SPEED_100)
ecntrl |= ECNTRL_R100M;
break;
case PHY_INTERFACE_MODE_SGMII:
ecntrl |= (ECNTRL_SGMIIM | ECNTRL_TBIM);
if (speed == SPEED_100)
ecntrl |= ECNTRL_R100M;
break;
default:
break;
}
out_be32(&regs->ecntrl, ecntrl);
out_be32(&regs->maccfg2, maccfg2);
}
void init_dtsec(struct fsl_enet_mac *mac, void *base,
void *phyregs, int max_rx_len)
{
mac->base = base;
mac->phyregs = phyregs;
mac->max_rx_len = max_rx_len;
mac->init_mac = dtsec_init_mac;
mac->enable_mac = dtsec_enable_mac;
mac->disable_mac = dtsec_disable_mac;
mac->set_mac_addr = dtsec_set_mac_addr;
mac->set_if_mode = dtsec_set_interface_mode;
}
source/bootloader/u-boot-2020.01/drivers/net/fm/eth.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2009-2012 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*/
#include <common.h>
#include <asm/io.h>
#include <malloc.h>
#include <net.h>
#include <hwconfig.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include <fsl_dtsec.h>
#include <fsl_tgec.h>
#include <fsl_memac.h>
#include "fm.h"
static struct eth_device *devlist[NUM_FM_PORTS];
static int num_controllers;
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
#define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
TBIANA_FULL_DUPLEX)
#define TBIANA_SGMII_ACK 0x4001
#define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
/* Configure the TBI for SGMII operation */
static void dtsec_configure_serdes(struct fm_eth *priv)
{
#ifdef CONFIG_SYS_FMAN_V3
u32 value;
struct mii_dev bus;
bus.priv = priv->mac->phyregs;
bool sgmii_2500 = (priv->enet_if ==
PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
int i = 0;
qsgmii_loop:
/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
if (sgmii_2500)
value = PHY_SGMII_CR_PHY_RESET |
PHY_SGMII_IF_SPEED_GIGABIT |
PHY_SGMII_IF_MODE_SGMII;
else
value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
/* Dev ability according to SGMII specification */
value = PHY_SGMII_DEV_ABILITY_SGMII;
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
if (sgmii_2500) {
/* Adjust link timer for 2.5G SGMII,
* 1.6 ms in units of 3.2 ns:
* 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
*/
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
} else {
/* Adjust link timer for SGMII,
* 1.6 ms in units of 8 ns:
* 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
*/
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0003);
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0x0d40);
}
/* Restart AN */
value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
i++;
goto qsgmii_loop;
}
#else
struct dtsec *regs = priv->mac->base;
struct tsec_mii_mng *phyregs = priv->mac->phyregs;
/*
* Access TBI PHY registers at given TSEC register offset as
* opposed to the register offset used for external PHY accesses
*/
tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_TBICON,
TBICON_CLK_SELECT);
tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_ANA,
TBIANA_SGMII_ACK);
tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0,
TBI_CR, TBICR_SETTINGS);
#endif
}
static void dtsec_init_phy(struct eth_device *dev)
{
struct fm_eth *fm_eth = dev->priv;
#ifndef CONFIG_SYS_FMAN_V3
struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
/* Assign a Physical address to the TBI */
out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
#endif
if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
dtsec_configure_serdes(fm_eth);
}
#ifdef CONFIG_PHYLIB
static int tgec_is_fibre(struct eth_device *dev)
{
struct fm_eth *fm = dev->priv;
char phyopt[20];
sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
return hwconfig_arg_cmp(phyopt, "xfi");
}
#endif
#endif
static u16 muram_readw(u16 *addr)
{
ulong base = (ulong)addr & ~0x3UL;
u32 val32 = in_be32((void *)base);
int byte_pos;
u16 ret;
byte_pos = (ulong)addr & 0x3UL;
if (byte_pos)
ret = (u16)(val32 & 0x0000ffff);
else
ret = (u16)((val32 & 0xffff0000) >> 16);
return ret;
}
static void muram_writew(u16 *addr, u16 val)
{
ulong base = (ulong)addr & ~0x3UL;
u32 org32 = in_be32((void *)base);
u32 val32;
int byte_pos;
byte_pos = (ulong)addr & 0x3UL;
if (byte_pos)
val32 = (org32 & 0xffff0000) | val;
else
val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
out_be32((void *)base, val32);
}
static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
{
int timeout = 1000000;
clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
/* wait until the rx port is not busy */
while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
;
}
static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
{
/* set BMI to independent mode, Rx port disable */
out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
/* clear FOF in IM case */
out_be32(&rx_port->fmbm_rim, 0);
/* Rx frame next engine -RISC */
out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
/* Rx command attribute - no order, MR[3] = 1 */
clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
/* enable Rx statistic counters */
out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
/* disable Rx performance counters */
out_be32(&rx_port->fmbm_rpc, 0);
}
static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
{
int timeout = 1000000;
clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
/* wait until the tx port is not busy */
while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
;
}
static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
{
/* set BMI to independent mode, Tx port disable */
out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
/* Tx frame next engine -RISC */
out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
/* Tx command attribute - no order, MR[3] = 1 */
clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
/* enable Tx statistic counters */
out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
/* disable Tx performance counters */
out_be32(&tx_port->fmbm_tpc, 0);
}
static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
{
struct fm_port_global_pram *pram;
u32 pram_page_offset;
void *rx_bd_ring_base;
void *rx_buf_pool;
u32 bd_ring_base_lo, bd_ring_base_hi;
u32 buf_lo, buf_hi;
struct fm_port_bd *rxbd;
struct fm_port_qd *rxqd;
struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
int i;
/* alloc global parameter ram at MURAM */
pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
FM_PRAM_SIZE, FM_PRAM_ALIGN);
if (!pram) {
printf("%s: No muram for Rx global parameter\n", __func__);
return -ENOMEM;
}
fm_eth->rx_pram = pram;
/* parameter page offset to MURAM */
pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
/* enable global mode- snooping data buffers and BDs */
out_be32(&pram->mode, PRAM_MODE_GLOBAL);
/* init the Rx queue descriptor pionter */
out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
/* set the max receive buffer length, power of 2 */
muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
/* alloc Rx buffer descriptors from main memory */
rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
if (!rx_bd_ring_base)
return -ENOMEM;
memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
/* alloc Rx buffer from main memory */
rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
if (!rx_buf_pool)
return -ENOMEM;
memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
/* save them to fm_eth */
fm_eth->rx_bd_ring = rx_bd_ring_base;
fm_eth->cur_rxbd = rx_bd_ring_base;
fm_eth->rx_buf = rx_buf_pool;
/* init Rx BDs ring */
rxbd = (struct fm_port_bd *)rx_bd_ring_base;
for (i = 0; i < RX_BD_RING_SIZE; i++) {
muram_writew(&rxbd->status, RxBD_EMPTY);
muram_writew(&rxbd->len, 0);
buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
i * MAX_RXBUF_LEN));
buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
i * MAX_RXBUF_LEN));
muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
out_be32(&rxbd->buf_ptr_lo, buf_lo);
rxbd++;
}
/* set the Rx queue descriptor */
rxqd = &pram->rxqd;
muram_writew(&rxqd->gen, 0);
bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo);
muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
muram_writew(&rxqd->offset_in, 0);
muram_writew(&rxqd->offset_out, 0);
/* set IM parameter ram pointer to Rx Frame Queue ID */
out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
return 0;
}
static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
{
struct fm_port_global_pram *pram;
u32 pram_page_offset;
void *tx_bd_ring_base;
u32 bd_ring_base_lo, bd_ring_base_hi;
struct fm_port_bd *txbd;
struct fm_port_qd *txqd;
struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
int i;
/* alloc global parameter ram at MURAM */
pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
FM_PRAM_SIZE, FM_PRAM_ALIGN);
if (!pram) {
printf("%s: No muram for Tx global parameter\n", __func__);
return -ENOMEM;
}
fm_eth->tx_pram = pram;
/* parameter page offset to MURAM */
pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
/* enable global mode- snooping data buffers and BDs */
out_be32(&pram->mode, PRAM_MODE_GLOBAL);
/* init the Tx queue descriptor pionter */
out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
/* alloc Tx buffer descriptors from main memory */
tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
* TX_BD_RING_SIZE);
if (!tx_bd_ring_base)
return -ENOMEM;
memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
* TX_BD_RING_SIZE);
/* save it to fm_eth */
fm_eth->tx_bd_ring = tx_bd_ring_base;
fm_eth->cur_txbd = tx_bd_ring_base;
/* init Tx BDs ring */
txbd = (struct fm_port_bd *)tx_bd_ring_base;
for (i = 0; i < TX_BD_RING_SIZE; i++) {
muram_writew(&txbd->status, TxBD_LAST);
muram_writew(&txbd->len, 0);
muram_writew(&txbd->buf_ptr_hi, 0);
out_be32(&txbd->buf_ptr_lo, 0);
txbd++;
}
/* set the Tx queue decriptor */
txqd = &pram->txqd;
bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base));
bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base));
muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo);
muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
* TX_BD_RING_SIZE);
muram_writew(&txqd->offset_in, 0);
muram_writew(&txqd->offset_out, 0);
/* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
return 0;
}
static int fm_eth_init(struct fm_eth *fm_eth)
{
int ret;
ret = fm_eth_rx_port_parameter_init(fm_eth);
if (ret)
return ret;
ret = fm_eth_tx_port_parameter_init(fm_eth);
if (ret)
return ret;
return 0;
}
static int fm_eth_startup(struct fm_eth *fm_eth)
{
struct fsl_enet_mac *mac;
int ret;
mac = fm_eth->mac;
/* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
ret = fm_eth_init(fm_eth);
if (ret)
return ret;
/* setup the MAC controller */
mac->init_mac(mac);
/* For some reason we need to set SPEED_100 */
if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
(fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
(fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
mac->set_if_mode)
mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
/* init bmi rx port, IM mode and disable */
bmi_rx_port_init(fm_eth->rx_port);
/* init bmi tx port, IM mode and disable */
bmi_tx_port_init(fm_eth->tx_port);
return 0;
}
static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
{
struct fm_port_global_pram *pram;
pram = fm_eth->tx_pram;
/* graceful stop transmission of frames */
setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
sync();
}
static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
{
struct fm_port_global_pram *pram;
pram = fm_eth->tx_pram;
/* re-enable transmission of frames */
clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
sync();
}
static int fm_eth_open(struct eth_device *dev, bd_t *bd)
{
struct fm_eth *fm_eth;
struct fsl_enet_mac *mac;
#ifdef CONFIG_PHYLIB
int ret;
#endif
fm_eth = (struct fm_eth *)dev->priv;
mac = fm_eth->mac;
/* setup the MAC address */
if (dev->enetaddr[0] & 0x01) {
printf("%s: MacAddress is multcast address\n", __func__);
return 1;
}
mac->set_mac_addr(mac, dev->enetaddr);
/* enable bmi Rx port */
setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
/* enable MAC rx/tx port */
mac->enable_mac(mac);
/* enable bmi Tx port */
setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
/* re-enable transmission of frame */
fmc_tx_port_graceful_stop_disable(fm_eth);
#ifdef CONFIG_PHYLIB
if (fm_eth->phydev) {
ret = phy_startup(fm_eth->phydev);
if (ret) {
printf("%s: Could not initialize\n",
fm_eth->phydev->dev->name);
return ret;
}
} else {
return 0;
}
#else
fm_eth->phydev->speed = SPEED_1000;
fm_eth->phydev->link = 1;
fm_eth->phydev->duplex = DUPLEX_FULL;
#endif
/* set the MAC-PHY mode */
mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
if (!fm_eth->phydev->link)
printf("%s: No link.\n", fm_eth->phydev->dev->name);
return fm_eth->phydev->link ? 0 : -1;
}
static void fm_eth_halt(struct eth_device *dev)
{
struct fm_eth *fm_eth;
struct fsl_enet_mac *mac;
fm_eth = (struct fm_eth *)dev->priv;
mac = fm_eth->mac;
/* graceful stop the transmission of frames */
fmc_tx_port_graceful_stop_enable(fm_eth);
/* disable bmi Tx port */
bmi_tx_port_disable(fm_eth->tx_port);
/* disable MAC rx/tx port */
mac->disable_mac(mac);
/* disable bmi Rx port */
bmi_rx_port_disable(fm_eth->rx_port);
#ifdef CONFIG_PHYLIB
if (fm_eth->phydev)
phy_shutdown(fm_eth->phydev);
#endif
}
static int fm_eth_send(struct eth_device *dev, void *buf, int len)
{
struct fm_eth *fm_eth;
struct fm_port_global_pram *pram;
struct fm_port_bd *txbd, *txbd_base;
u16 offset_in;
int i;
fm_eth = (struct fm_eth *)dev->priv;
pram = fm_eth->tx_pram;
txbd = fm_eth->cur_txbd;
/* find one empty TxBD */
for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
udelay(100);
if (i > 0x1000) {
printf("%s: Tx buffer not ready, txbd->status = 0x%x\n",
dev->name, muram_readw(&txbd->status));
return 0;
}
}
/* setup TxBD */
muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf)));
out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf)));
muram_writew(&txbd->len, len);
sync();
muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
sync();
/* update TxQD, let RISC to send the packet */
offset_in = muram_readw(&pram->txqd.offset_in);
offset_in += sizeof(struct fm_port_bd);
if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
offset_in = 0;
muram_writew(&pram->txqd.offset_in, offset_in);
sync();
/* wait for buffer to be transmitted */
for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
udelay(100);
if (i > 0x10000) {
printf("%s: Tx error, txbd->status = 0x%x\n",
dev->name, muram_readw(&txbd->status));
return 0;
}
}
/* advance the TxBD */
txbd++;
txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
if (txbd >= (txbd_base + TX_BD_RING_SIZE))
txbd = txbd_base;
/* update current txbd */
fm_eth->cur_txbd = (void *)txbd;
return 1;
}
static int fm_eth_recv(struct eth_device *dev)
{
struct fm_eth *fm_eth;
struct fm_port_global_pram *pram;
struct fm_port_bd *rxbd, *rxbd_base;
u16 status, len;
u32 buf_lo, buf_hi;
u8 *data;
u16 offset_out;
int ret = 1;
fm_eth = (struct fm_eth *)dev->priv;
pram = fm_eth->rx_pram;
rxbd = fm_eth->cur_rxbd;
status = muram_readw(&rxbd->status);
while (!(status & RxBD_EMPTY)) {
if (!(status & RxBD_ERROR)) {
buf_hi = muram_readw(&rxbd->buf_ptr_hi);
buf_lo = in_be32(&rxbd->buf_ptr_lo);
data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
len = muram_readw(&rxbd->len);
net_process_received_packet(data, len);
} else {
printf("%s: Rx error\n", dev->name);
ret = 0;
}
/* clear the RxBDs */
muram_writew(&rxbd->status, RxBD_EMPTY);
muram_writew(&rxbd->len, 0);
sync();
/* advance RxBD */
rxbd++;
rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
rxbd = rxbd_base;
/* read next status */
status = muram_readw(&rxbd->status);
/* update RxQD */
offset_out = muram_readw(&pram->rxqd.offset_out);
offset_out += sizeof(struct fm_port_bd);
if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
offset_out = 0;
muram_writew(&pram->rxqd.offset_out, offset_out);
sync();
}
fm_eth->cur_rxbd = (void *)rxbd;
return ret;
}
static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
{
struct fsl_enet_mac *mac;
int num;
void *base, *phyregs = NULL;
num = fm_eth->num;
#ifdef CONFIG_SYS_FMAN_V3
#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
if (fm_eth->type == FM_ETH_10G_E) {
/* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
* 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
* 10GEC1 uses mEMAC1 on T1024.
* so it needs to change the num.
*/
if (fm_eth->num >= 2)
num -= 2;
else
num += 8;
}
#endif
base = &reg->memac[num].fm_memac;
phyregs = &reg->memac[num].fm_memac_mdio;
#else
/* Get the mac registers base address */
if (fm_eth->type == FM_ETH_1G_E) {
base = &reg->mac_1g[num].fm_dtesc;
phyregs = &reg->mac_1g[num].fm_mdio.miimcfg;
} else {
base = &reg->mac_10g[num].fm_10gec;
phyregs = &reg->mac_10g[num].fm_10gec_mdio;
}
#endif
/* alloc mac controller */
mac = malloc(sizeof(struct fsl_enet_mac));
if (!mac)
return -ENOMEM;
memset(mac, 0, sizeof(struct fsl_enet_mac));
/* save the mac to fm_eth struct */
fm_eth->mac = mac;
#ifdef CONFIG_SYS_FMAN_V3
init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
#else
if (fm_eth->type == FM_ETH_1G_E)
init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
else
init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
#endif
return 0;
}
static int init_phy(struct eth_device *dev)
{
struct fm_eth *fm_eth = dev->priv;
#ifdef CONFIG_PHYLIB
struct phy_device *phydev = NULL;
u32 supported;
#endif
if (fm_eth->type == FM_ETH_1G_E)
dtsec_init_phy(dev);
#ifdef CONFIG_PHYLIB
if (fm_eth->bus) {
phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev,
fm_eth->enet_if);
if (!phydev) {
printf("Failed to connect\n");
return -1;
}
} else {
return 0;
}
if (fm_eth->type == FM_ETH_1G_E) {
supported = (SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half |
SUPPORTED_100baseT_Full |
SUPPORTED_1000baseT_Full);
} else {
supported = SUPPORTED_10000baseT_Full;
if (tgec_is_fibre(dev))
phydev->port = PORT_FIBRE;
}
phydev->supported &= supported;
phydev->advertising = phydev->supported;
fm_eth->phydev = phydev;
phy_config(phydev);
#endif
return 0;
}
int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
{
struct eth_device *dev;
struct fm_eth *fm_eth;
int i, num = info->num;
int ret;
/* alloc eth device */
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (!dev)
return -ENOMEM;
memset(dev, 0, sizeof(struct eth_device));
/* alloc the FMan ethernet private struct */
fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
if (!fm_eth)
return -ENOMEM;
memset(fm_eth, 0, sizeof(struct fm_eth));
/* save off some things we need from the info struct */
fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
fm_eth->num = num;
fm_eth->type = info->type;
fm_eth->rx_port = (void *)&reg->port[info->rx_port_id - 1].fm_bmi;
fm_eth->tx_port = (void *)&reg->port[info->tx_port_id - 1].fm_bmi;
/* set the ethernet max receive length */
fm_eth->max_rx_len = MAX_RXBUF_LEN;
/* init global mac structure */
ret = fm_eth_init_mac(fm_eth, reg);
if (ret)
return ret;
/* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
if (fm_eth->type == FM_ETH_1G_E)
sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
else
sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
devlist[num_controllers++] = dev;
dev->iobase = 0;
dev->priv = (void *)fm_eth;
dev->init = fm_eth_open;
dev->halt = fm_eth_halt;
dev->send = fm_eth_send;
dev->recv = fm_eth_recv;
fm_eth->dev = dev;
fm_eth->bus = info->bus;
fm_eth->phyaddr = info->phy_addr;
fm_eth->enet_if = info->enet_if;
/* startup the FM im */
ret = fm_eth_startup(fm_eth);
if (ret)
return ret;
init_phy(dev);
/* clear the ethernet address */
for (i = 0; i < 6; i++)
dev->enetaddr[i] = 0;
eth_register(dev);
return 0;
}
source/bootloader/u-boot-2020.01/drivers/net/fm/fdt.c
+130
View File
@@ -0,0 +1,130 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
*/
#include <asm/io.h>
#include <env.h>
#include <fsl_qe.h> /* For struct qe_firmware */
#include <u-boot/crc.h>
#ifdef CONFIG_SYS_DPAA_FMAN
/**
* fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree
*
* The binding for an Fman firmware node is documented in
* Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains
* the actual Fman firmware binary data. The operating system is expected to
* be able to parse the binary data to determine any attributes it needs.
*/
void fdt_fixup_fman_firmware(void *blob)
{
int rc, fmnode, fwnode = -1;
uint32_t phandle;
struct qe_firmware *fmanfw;
const struct qe_header *hdr;
unsigned int length;
uint32_t crc;
const char *p;
/* The first Fman we find will contain the actual firmware. */
fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman");
if (fmnode < 0)
/* Exit silently if there are no Fman devices */
return;
/* If we already have a firmware node, then also exit silently. */
if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0)
return;
/* If the environment variable is not set, then exit silently */
p = env_get("fman_ucode");
if (!p)
return;
fmanfw = (struct qe_firmware *)simple_strtoul(p, NULL, 16);
if (!fmanfw)
return;
hdr = &fmanfw->header;
length = fdt32_to_cpu(hdr->length);
/* Verify the firmware. */
if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
(hdr->magic[2] != 'F')) {
printf("Data at %p is not an Fman firmware\n", fmanfw);
return;
}
if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) {
printf("Fman firmware at %p is too large (size=%u)\n",
fmanfw, length);
return;
}
length -= sizeof(u32); /* Subtract the size of the CRC */
crc = fdt32_to_cpu(*(u32 *)((void *)fmanfw + length));
if (crc != crc32_no_comp(0, (void *)fmanfw, length)) {
printf("Fman firmware at %p has invalid CRC\n", fmanfw);
return;
}
length += sizeof(u32);
/* Increase the size of the fdt to make room for the node. */
rc = fdt_increase_size(blob, length);
if (rc < 0) {
printf("Unable to make room for Fman firmware: %s\n",
fdt_strerror(rc));
return;
}
/* Create the firmware node. */
fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware");
if (fwnode < 0) {
char s[64];
fdt_get_path(blob, fmnode, s, sizeof(s));
printf("Could not add firmware node to %s: %s\n", s,
fdt_strerror(fwnode));
return;
}
rc = fdt_setprop_string(blob, fwnode, "compatible",
"fsl,fman-firmware");
if (rc < 0) {
char s[64];
fdt_get_path(blob, fwnode, s, sizeof(s));
printf("Could not add compatible property to node %s: %s\n", s,
fdt_strerror(rc));
return;
}
phandle = fdt_create_phandle(blob, fwnode);
if (!phandle) {
char s[64];
fdt_get_path(blob, fwnode, s, sizeof(s));
printf("Could not add phandle property to node %s: %s\n", s,
fdt_strerror(rc));
return;
}
rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, length);
if (rc < 0) {
char s[64];
fdt_get_path(blob, fwnode, s, sizeof(s));
printf("Could not add firmware property to node %s: %s\n", s,
fdt_strerror(rc));
return;
}
/* Find all other Fman nodes and point them to the firmware node. */
while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode,
"fsl,fman")) > 0) {
rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle",
phandle);
if (rc < 0) {
char s[64];
fdt_get_path(blob, fmnode, s, sizeof(s));
printf("Could not add pointer property to node %s: %s\n",
s, fdt_strerror(rc));
return;
}
}
}
#endif
source/bootloader/u-boot-2020.01/drivers/net/fm/fm.c
+529
View File
@@ -0,0 +1,529 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*/
#include <common.h>
#include <env.h>
#include <malloc.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <u-boot/crc.h>
#include "fm.h"
#include <fsl_qe.h> /* For struct qe_firmware */
#include <nand.h>
#include <spi_flash.h>
#include <mmc.h>
#ifdef CONFIG_ARM64
#include <asm/armv8/mmu.h>
#include <asm/arch/cpu.h>
#endif
struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
void *fm_muram_base(int fm_idx)
{
return muram[fm_idx].base;
}
void *fm_muram_alloc(int fm_idx, size_t size, ulong align)
{
void *ret;
ulong align_mask;
size_t off;
void *save;
align_mask = align - 1;
save = muram[fm_idx].alloc;
off = (ulong)save & align_mask;
if (off != 0)
muram[fm_idx].alloc += (align - off);
off = size & align_mask;
if (off != 0)
size += (align - off);
if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) {
muram[fm_idx].alloc = save;
printf("%s: run out of ram.\n", __func__);
return NULL;
}
ret = muram[fm_idx].alloc;
muram[fm_idx].alloc += size;
memset((void *)ret, 0, size);
return ret;
}
static void fm_init_muram(int fm_idx, void *reg)
{
void *base = reg;
muram[fm_idx].base = base;
muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE;
muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE;
}
/*
* fm_upload_ucode - Fman microcode upload worker function
*
* This function does the actual uploading of an Fman microcode
* to an Fman.
*/
static void fm_upload_ucode(int fm_idx, struct fm_imem *imem,
u32 *ucode, unsigned int size)
{
unsigned int i;
unsigned int timeout = 1000000;
/* enable address auto increase */
out_be32(&imem->iadd, IRAM_IADD_AIE);
/* write microcode to IRAM */
for (i = 0; i < size / 4; i++)
out_be32(&imem->idata, (be32_to_cpu(ucode[i])));
/* verify if the writing is over */
out_be32(&imem->iadd, 0);
while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout)
;
if (!timeout)
printf("Fman%u: microcode upload timeout\n", fm_idx + 1);
/* enable microcode from IRAM */
out_be32(&imem->iready, IRAM_READY);
}
/*
* Upload an Fman firmware
*
* This function is similar to qe_upload_firmware(), exception that it uploads
* a microcode to the Fman instead of the QE.
*
* Because the process for uploading a microcode to the Fman is similar for
* that of the QE, the QE firmware binary format is used for Fman microcode.
* It should be possible to unify these two functions, but for now we keep them
* separate.
*/
static int fman_upload_firmware(int fm_idx,
struct fm_imem *fm_imem,
const struct qe_firmware *firmware)
{
unsigned int i;
u32 crc;
size_t calc_size = sizeof(struct qe_firmware);
size_t length;
const struct qe_header *hdr;
if (!firmware) {
printf("Fman%u: Invalid address for firmware\n", fm_idx + 1);
return -EINVAL;
}
hdr = &firmware->header;
length = be32_to_cpu(hdr->length);
/* Check the magic */
if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
(hdr->magic[2] != 'F')) {
printf("Fman%u: Data at %p is not a firmware\n", fm_idx + 1,
firmware);
return -EPERM;
}
/* Check the version */
if (hdr->version != 1) {
printf("Fman%u: Unsupported firmware version %u\n", fm_idx + 1,
hdr->version);
return -EPERM;
}
/* Validate some of the fields */
if ((firmware->count != 1)) {
printf("Fman%u: Invalid data in firmware header\n", fm_idx + 1);
return -EINVAL;
}
/* Validate the length and check if there's a CRC */
calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
for (i = 0; i < firmware->count; i++)
/*
* For situations where the second RISC uses the same microcode
* as the first, the 'code_offset' and 'count' fields will be
* zero, so it's okay to add those.
*/
calc_size += sizeof(u32) *
be32_to_cpu(firmware->microcode[i].count);
/* Validate the length */
if (length != calc_size + sizeof(u32)) {
printf("Fman%u: Invalid length in firmware header\n",
fm_idx + 1);
return -EPERM;
}
/*
* Validate the CRC. We would normally call crc32_no_comp(), but that
* function isn't available unless you turn on JFFS support.
*/
crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
printf("Fman%u: Firmware CRC is invalid\n", fm_idx + 1);
return -EIO;
}
/* Loop through each microcode. */
for (i = 0; i < firmware->count; i++) {
const struct qe_microcode *ucode = &firmware->microcode[i];
/* Upload a microcode if it's present */
if (be32_to_cpu(ucode->code_offset)) {
u32 ucode_size;
u32 *code;
printf("Fman%u: Uploading microcode version %u.%u.%u\n",
fm_idx + 1, ucode->major, ucode->minor,
ucode->revision);
code = (void *)firmware +
be32_to_cpu(ucode->code_offset);
ucode_size = sizeof(u32) * be32_to_cpu(ucode->count);
fm_upload_ucode(fm_idx, fm_imem, code, ucode_size);
}
}
return 0;
}
static u32 fm_assign_risc(int port_id)
{
u32 risc_sel, val;
risc_sel = (port_id & 0x1) ? FMFPPRC_RISC2 : FMFPPRC_RISC1;
val = (port_id << FMFPPRC_PORTID_SHIFT) & FMFPPRC_PORTID_MASK;
val |= ((risc_sel << FMFPPRC_ORA_SHIFT) | risc_sel);
return val;
}
static void fm_init_fpm(struct fm_fpm *fpm)
{
int i, port_id;
u32 val;
setbits_be32(&fpm->fmfpee, FMFPEE_EHM | FMFPEE_UEC |
FMFPEE_CER | FMFPEE_DER);
/* IM mode, each even port ID to RISC#1, each odd port ID to RISC#2 */
/* offline/parser port */
for (i = 0; i < MAX_NUM_OH_PORT; i++) {
port_id = OH_PORT_ID_BASE + i;
val = fm_assign_risc(port_id);
out_be32(&fpm->fpmprc, val);
}
/* Rx 1G port */
for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
port_id = RX_PORT_1G_BASE + i;
val = fm_assign_risc(port_id);
out_be32(&fpm->fpmprc, val);
}
/* Tx 1G port */
for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
port_id = TX_PORT_1G_BASE + i;
val = fm_assign_risc(port_id);
out_be32(&fpm->fpmprc, val);
}
/* Rx 10G port */
port_id = RX_PORT_10G_BASE;
val = fm_assign_risc(port_id);
out_be32(&fpm->fpmprc, val);
/* Tx 10G port */
port_id = TX_PORT_10G_BASE;
val = fm_assign_risc(port_id);
out_be32(&fpm->fpmprc, val);
/* disable the dispatch limit in IM case */
out_be32(&fpm->fpmflc, FMFP_FLC_DISP_LIM_NONE);
/* clear events */
out_be32(&fpm->fmfpee, FMFPEE_CLEAR_EVENT);
/* clear risc events */
for (i = 0; i < 4; i++)
out_be32(&fpm->fpmcev[i], 0xffffffff);
/* clear error */
out_be32(&fpm->fpmrcr, FMFP_RCR_MDEC | FMFP_RCR_IDEC);
}
static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi)
{
int blk, i, port_id;
u32 val;
size_t offset;
void *base;
/* alloc free buffer pool in MURAM */
base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN);
if (!base) {
printf("%s: no muram for free buffer pool\n", __func__);
return -ENOMEM;
}
offset = base - fm_muram_base(fm_idx);
/* Need 128KB total free buffer pool size */
val = offset / 256;
blk = FM_FREE_POOL_SIZE / 256;
/* in IM, we must not begin from offset 0 in MURAM */
val |= ((blk - 1) << FMBM_CFG1_FBPS_SHIFT);
out_be32(&bmi->fmbm_cfg1, val);
/* disable all BMI interrupt */
out_be32(&bmi->fmbm_ier, FMBM_IER_DISABLE_ALL);
/* clear all events */
out_be32(&bmi->fmbm_ievr, FMBM_IEVR_CLEAR_ALL);
/*
* set port parameters - FMBM_PP_x
* max tasks 10G Rx/Tx=12, 1G Rx/Tx 4, others is 1
* max dma 10G Rx/Tx=3, others is 1
* set port FIFO size - FMBM_PFS_x
* 4KB for all Rx and Tx ports
*/
/* offline/parser port */
for (i = 0; i < MAX_NUM_OH_PORT; i++) {
port_id = OH_PORT_ID_BASE + i - 1;
/* max tasks=1, max dma=1, no extra */
out_be32(&bmi->fmbm_pp[port_id], 0);
/* port FIFO size - 256 bytes, no extra */
out_be32(&bmi->fmbm_pfs[port_id], 0);
}
/* Rx 1G port */
for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
port_id = RX_PORT_1G_BASE + i - 1;
/* max tasks=4, max dma=1, no extra */
out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
/* FIFO size - 4KB, no extra */
out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
}
/* Tx 1G port FIFO size - 4KB, no extra */
for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
port_id = TX_PORT_1G_BASE + i - 1;
/* max tasks=4, max dma=1, no extra */
out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
/* FIFO size - 4KB, no extra */
out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
}
/* Rx 10G port */
port_id = RX_PORT_10G_BASE - 1;
/* max tasks=12, max dma=3, no extra */
out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
/* FIFO size - 4KB, no extra */
out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
/* Tx 10G port */
port_id = TX_PORT_10G_BASE - 1;
/* max tasks=12, max dma=3, no extra */
out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
/* FIFO size - 4KB, no extra */
out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
/* initialize internal buffers data base (linked list) */
out_be32(&bmi->fmbm_init, FMBM_INIT_START);
return 0;
}
static void fm_init_qmi(struct fm_qmi_common *qmi)
{
/* disable all error interrupts */
out_be32(&qmi->fmqm_eien, FMQM_EIEN_DISABLE_ALL);
/* clear all error events */
out_be32(&qmi->fmqm_eie, FMQM_EIE_CLEAR_ALL);
/* disable all interrupts */
out_be32(&qmi->fmqm_ien, FMQM_IEN_DISABLE_ALL);
/* clear all interrupts */
out_be32(&qmi->fmqm_ie, FMQM_IE_CLEAR_ALL);
}
/* Init common part of FM, index is fm num# like fm as above */
#ifdef CONFIG_TFABOOT
int fm_init_common(int index, struct ccsr_fman *reg)
{
int rc;
void *addr = NULL;
enum boot_src src = get_boot_src();
if (src == BOOT_SOURCE_IFC_NOR) {
addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR +
CONFIG_SYS_FSL_IFC_BASE);
} else if (src == BOOT_SOURCE_IFC_NAND) {
size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
rc = nand_read(get_nand_dev_by_index(0),
(loff_t)CONFIG_SYS_FMAN_FW_ADDR,
&fw_length, (u_char *)addr);
if (rc == -EUCLEAN) {
printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
CONFIG_SYS_FMAN_FW_ADDR, rc);
}
} else if (src == BOOT_SOURCE_QSPI_NOR) {
struct spi_flash *ucode_flash;
addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
int ret = 0;
#ifdef CONFIG_DM_SPI_FLASH
struct udevice *new;
/* speed and mode will be read from DT */
ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
CONFIG_ENV_SPI_CS, 0, 0, &new);
ucode_flash = dev_get_uclass_priv(new);
#else
ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
CONFIG_ENV_SPI_CS,
CONFIG_ENV_SPI_MAX_HZ,
CONFIG_ENV_SPI_MODE);
#endif
if (!ucode_flash) {
printf("SF: probe for ucode failed\n");
} else {
ret = spi_flash_read(ucode_flash,
CONFIG_SYS_FMAN_FW_ADDR +
CONFIG_SYS_FSL_QSPI_BASE,
CONFIG_SYS_QE_FMAN_FW_LENGTH,
addr);
if (ret)
printf("SF: read for ucode failed\n");
spi_flash_free(ucode_flash);
}
} else if (src == BOOT_SOURCE_SD_MMC) {
int dev = CONFIG_SYS_MMC_ENV_DEV;
addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
if (!mmc) {
printf("\nMMC cannot find device for ucode\n");
} else {
printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
(void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
addr);
}
} else {
addr = NULL;
}
/* Upload the Fman microcode if it's present */
rc = fman_upload_firmware(index, &reg->fm_imem, addr);
if (rc)
return rc;
env_set_addr("fman_ucode", addr);
fm_init_muram(index, &reg->muram);
fm_init_qmi(&reg->fm_qmi_common);
fm_init_fpm(&reg->fm_fpm);
/* clear DMA status */
setbits_be32(&reg->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
/* set DMA mode */
setbits_be32(&reg->fm_dma.fmdmmr, FMDMMR_SBER);
return fm_init_bmi(index, &reg->fm_bmi_common);
}
#else
int fm_init_common(int index, struct ccsr_fman *reg)
{
int rc;
#if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
rc = nand_read(get_nand_dev_by_index(0),
(loff_t)CONFIG_SYS_FMAN_FW_ADDR,
&fw_length, (u_char *)addr);
if (rc == -EUCLEAN) {
printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
CONFIG_SYS_FMAN_FW_ADDR, rc);
}
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH)
struct spi_flash *ucode_flash;
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
int ret = 0;
#ifdef CONFIG_DM_SPI_FLASH
struct udevice *new;
/* speed and mode will be read from DT */
ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
0, 0, &new);
ucode_flash = dev_get_uclass_priv(new);
#else
ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
#endif
if (!ucode_flash)
printf("SF: probe for ucode failed\n");
else {
ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR,
CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
if (ret)
printf("SF: read for ucode failed\n");
spi_flash_free(ucode_flash);
}
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
int dev = CONFIG_SYS_MMC_ENV_DEV;
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
if (!mmc)
printf("\nMMC cannot find device for ucode\n");
else {
printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
(void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
addr);
}
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
#else
void *addr = NULL;
#endif
/* Upload the Fman microcode if it's present */
rc = fman_upload_firmware(index, &reg->fm_imem, addr);
if (rc)
return rc;
env_set_addr("fman_ucode", addr);
fm_init_muram(index, &reg->muram);
fm_init_qmi(&reg->fm_qmi_common);
fm_init_fpm(&reg->fm_fpm);
/* clear DMA status */
setbits_be32(&reg->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
/* set DMA mode */
setbits_be32(&reg->fm_dma.fmdmmr, FMDMMR_SBER);
return fm_init_bmi(index, &reg->fm_bmi_common);
}
#endif
source/bootloader/u-boot-2020.01/drivers/net/fm/fm.h
+148
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@@ -0,0 +1,148 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*/
#ifndef __FM_H__
#define __FM_H__
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <fsl_fman.h>
/* Port ID */
#define OH_PORT_ID_BASE 0x01
#define MAX_NUM_OH_PORT 7
#define RX_PORT_1G_BASE 0x08
#define MAX_NUM_RX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC
#define RX_PORT_10G_BASE 0x10
#define RX_PORT_10G_BASE2 0x08
#define TX_PORT_1G_BASE 0x28
#define MAX_NUM_TX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC
#define TX_PORT_10G_BASE 0x30
#define TX_PORT_10G_BASE2 0x28
#define MIIM_TIMEOUT 0xFFFF
struct fm_muram {
void *base;
void *top;
size_t size;
void *alloc;
};
#define FM_MURAM_RES_SIZE 0x01000
/* Rx/Tx buffer descriptor */
struct fm_port_bd {
u16 status;
u16 len;
u32 res0;
u16 res1;
u16 buf_ptr_hi;
u32 buf_ptr_lo;
};
/* Common BD flags */
#define BD_LAST 0x0800
/* Rx BD status flags */
#define RxBD_EMPTY 0x8000
#define RxBD_LAST BD_LAST
#define RxBD_FIRST 0x0400
#define RxBD_PHYS_ERR 0x0008
#define RxBD_SIZE_ERR 0x0004
#define RxBD_ERROR (RxBD_PHYS_ERR | RxBD_SIZE_ERR)
/* Tx BD status flags */
#define TxBD_READY 0x8000
#define TxBD_LAST BD_LAST
/* Rx/Tx queue descriptor */
struct fm_port_qd {
u16 gen;
u16 bd_ring_base_hi;
u32 bd_ring_base_lo;
u16 bd_ring_size;
u16 offset_in;
u16 offset_out;
u16 res0;
u32 res1[0x4];
};
/* IM global parameter RAM */
struct fm_port_global_pram {
u32 mode; /* independent mode register */
u32 rxqd_ptr; /* Rx queue descriptor pointer */
u32 txqd_ptr; /* Tx queue descriptor pointer */
u16 mrblr; /* max Rx buffer length */
u16 rxqd_bsy_cnt; /* RxQD busy counter, should be cleared */
u32 res0[0x4];
struct fm_port_qd rxqd; /* Rx queue descriptor */
struct fm_port_qd txqd; /* Tx queue descriptor */
u32 res1[0x28];
};
#define FM_PRAM_SIZE sizeof(struct fm_port_global_pram)
#define FM_PRAM_ALIGN 256
#define PRAM_MODE_GLOBAL 0x20000000
#define PRAM_MODE_GRACEFUL_STOP 0x00800000
#if defined(CONFIG_ARCH_P1023)
#define FM_FREE_POOL_SIZE 0x2000 /* 8K bytes */
#else
#define FM_FREE_POOL_SIZE 0x20000 /* 128K bytes */
#endif
#define FM_FREE_POOL_ALIGN 256
void *fm_muram_alloc(int fm_idx, size_t size, ulong align);
void *fm_muram_base(int fm_idx);
int fm_init_common(int index, struct ccsr_fman *reg);
int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info);
phy_interface_t fman_port_enet_if(enum fm_port port);
void fman_disable_port(enum fm_port port);
void fman_enable_port(enum fm_port port);
struct fsl_enet_mac {
void *base; /* MAC controller registers base address */
void *phyregs;
int max_rx_len;
void (*init_mac)(struct fsl_enet_mac *mac);
void (*enable_mac)(struct fsl_enet_mac *mac);
void (*disable_mac)(struct fsl_enet_mac *mac);
void (*set_mac_addr)(struct fsl_enet_mac *mac, u8 *mac_addr);
void (*set_if_mode)(struct fsl_enet_mac *mac, phy_interface_t type,
int speed);
};
/* Fman ethernet private struct */
struct fm_eth {
int fm_index; /* Fman index */
u32 num; /* 0..n-1 for give type */
struct fm_bmi_tx_port *tx_port;
struct fm_bmi_rx_port *rx_port;
enum fm_eth_type type; /* 1G or 10G ethernet */
phy_interface_t enet_if;
struct fsl_enet_mac *mac; /* MAC controller */
struct mii_dev *bus;
struct phy_device *phydev;
int phyaddr;
struct eth_device *dev;
int max_rx_len;
struct fm_port_global_pram *rx_pram; /* Rx parameter table */
struct fm_port_global_pram *tx_pram; /* Tx parameter table */
void *rx_bd_ring; /* Rx BD ring base */
void *cur_rxbd; /* current Rx BD */
void *rx_buf; /* Rx buffer base */
void *tx_bd_ring; /* Tx BD ring base */
void *cur_txbd; /* current Tx BD */
};
#define RX_BD_RING_SIZE 8
#define TX_BD_RING_SIZE 8
#define MAX_RXBUF_LOG2 11
#define MAX_RXBUF_LEN (1 << MAX_RXBUF_LOG2)
#define PORT_IS_ENABLED(port) (fm_port_to_index(port) == -1 ? \
0 : fm_info[fm_port_to_index(port)].enabled)
#endif /* __FM_H__ */
source/bootloader/u-boot-2020.01/drivers/net/fm/init.c
+382
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@@ -0,0 +1,382 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011-2015 Freescale Semiconductor, Inc.
*/
#include <errno.h>
#include <common.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#ifdef CONFIG_FSL_LAYERSCAPE
#include <asm/arch/fsl_serdes.h>
#else
#include <asm/fsl_serdes.h>
#endif
#include "fm.h"
struct fm_eth_info fm_info[] = {
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 1)
FM_DTSEC_INFO_INITIALIZER(1, 1),
#endif
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 2)
FM_DTSEC_INFO_INITIALIZER(1, 2),
#endif
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 3)
FM_DTSEC_INFO_INITIALIZER(1, 3),
#endif
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 4)
FM_DTSEC_INFO_INITIALIZER(1, 4),
#endif
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 5)
FM_DTSEC_INFO_INITIALIZER(1, 5),
#endif
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 6)
FM_DTSEC_INFO_INITIALIZER(1, 6),
#endif
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 7)
FM_DTSEC_INFO_INITIALIZER(1, 9),
#endif
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 8)
FM_DTSEC_INFO_INITIALIZER(1, 10),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 1)
FM_DTSEC_INFO_INITIALIZER(2, 1),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 2)
FM_DTSEC_INFO_INITIALIZER(2, 2),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 3)
FM_DTSEC_INFO_INITIALIZER(2, 3),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 4)
FM_DTSEC_INFO_INITIALIZER(2, 4),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5)
FM_DTSEC_INFO_INITIALIZER(2, 5),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 6)
FM_DTSEC_INFO_INITIALIZER(2, 6),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 7)
FM_DTSEC_INFO_INITIALIZER(2, 9),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 8)
FM_DTSEC_INFO_INITIALIZER(2, 10),
#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
FM_TGEC_INFO_INITIALIZER(1, 1),
#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 2)
FM_TGEC_INFO_INITIALIZER(1, 2),
#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
FM_TGEC_INFO_INITIALIZER2(1, 3),
#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 4)
FM_TGEC_INFO_INITIALIZER2(1, 4),
#endif
#if (CONFIG_SYS_NUM_FM2_10GEC >= 1)
FM_TGEC_INFO_INITIALIZER(2, 1),
#endif
#if (CONFIG_SYS_NUM_FM2_10GEC >= 2)
FM_TGEC_INFO_INITIALIZER(2, 2),
#endif
};
int fm_standard_init(bd_t *bis)
{
int i;
struct ccsr_fman *reg;
reg = (void *)CONFIG_SYS_FSL_FM1_ADDR;
if (fm_init_common(0, reg))
return 0;
for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
if ((fm_info[i].enabled) && (fm_info[i].index == 1))
fm_eth_initialize(reg, &fm_info[i]);
}
#if (CONFIG_SYS_NUM_FMAN == 2)
reg = (void *)CONFIG_SYS_FSL_FM2_ADDR;
if (fm_init_common(1, reg))
return 0;
for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
if ((fm_info[i].enabled) && (fm_info[i].index == 2))
fm_eth_initialize(reg, &fm_info[i]);
}
#endif
return 1;
}
/* simple linear search to map from port to array index */
static int fm_port_to_index(enum fm_port port)
{
int i;
for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
if (fm_info[i].port == port)
return i;
}
return -1;
}
/*
* Determine if an interface is actually active based on HW config
* we expect fman_port_enet_if() to report PHY_INTERFACE_MODE_NONE if
* the interface is not active based on HW cfg of the SoC
*/
void fman_enet_init(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
phy_interface_t enet_if;
enet_if = fman_port_enet_if(fm_info[i].port);
if (enet_if != PHY_INTERFACE_MODE_NONE) {
fm_info[i].enabled = 1;
fm_info[i].enet_if = enet_if;
} else {
fm_info[i].enabled = 0;
}
}
return ;
}
void fm_disable_port(enum fm_port port)
{
int i = fm_port_to_index(port);
if (i == -1)
return;
fm_info[i].enabled = 0;
#ifndef CONFIG_SYS_FMAN_V3
fman_disable_port(port);
#endif
}
void fm_enable_port(enum fm_port port)
{
int i = fm_port_to_index(port);
if (i == -1)
return;
fm_info[i].enabled = 1;
fman_enable_port(port);
}
void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus)
{
int i = fm_port_to_index(port);
if (i == -1)
return;
fm_info[i].bus = bus;
}
void fm_info_set_phy_address(enum fm_port port, int address)
{
int i = fm_port_to_index(port);
if (i == -1)
return;
fm_info[i].phy_addr = address;
}
/*
* Returns the PHY address for a given Fman port
*
* The port must be set via a prior call to fm_info_set_phy_address().
* A negative error code is returned if the port is invalid.
*/
int fm_info_get_phy_address(enum fm_port port)
{
int i = fm_port_to_index(port);
if (i == -1)
return -1;
return fm_info[i].phy_addr;
}
/*
* Returns the type of the data interface between the given MAC and its PHY.
* This is typically determined by the RCW.
*/
phy_interface_t fm_info_get_enet_if(enum fm_port port)
{
int i = fm_port_to_index(port);
if (i == -1)
return PHY_INTERFACE_MODE_NONE;
if (fm_info[i].enabled)
return fm_info[i].enet_if;
return PHY_INTERFACE_MODE_NONE;
}
static void
__def_board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
enum fm_port port, int offset)
{
return ;
}
void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
enum fm_port port, int offset)
__attribute__((weak, alias("__def_board_ft_fman_fixup_port")));
int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
{
int off;
uint32_t ph;
phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset;
#ifndef CONFIG_SYS_FMAN_V3
u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS +
CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET;
#endif
off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
if (off == -FDT_ERR_NOTFOUND)
return -EINVAL;
if (info->enabled) {
fdt_fixup_phy_connection(blob, off, info->enet_if);
board_ft_fman_fixup_port(blob, prop, paddr, info->port, off);
return 0;
}
#ifdef CONFIG_SYS_FMAN_V3
#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
/*
* On T2/T4 SoCs, physically FM1_DTSEC9 and FM1_10GEC1 use the same
* dual-role MAC, when FM1_10GEC1 is enabled and FM1_DTSEC9
* is disabled, ensure that the dual-role MAC is not disabled,
* ditto for other dual-role MACs.
*/
if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) ||
((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC3))) ||
((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC4))) ||
((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) ||
((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) ||
((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) ||
((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC2)))
#if (CONFIG_SYS_NUM_FMAN == 2)
||
((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1))) ||
((info->port == FM2_DTSEC10) && (PORT_IS_ENABLED(FM2_10GEC2))) ||
((info->port == FM2_10GEC1) && (PORT_IS_ENABLED(FM2_DTSEC9))) ||
((info->port == FM2_10GEC2) && (PORT_IS_ENABLED(FM2_DTSEC10)))
#endif
#else
/* FM1_DTSECx and FM1_10GECx use the same dual-role MAC */
if (((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC2))) ||
((info->port == FM1_DTSEC3) && (PORT_IS_ENABLED(FM1_10GEC3))) ||
((info->port == FM1_DTSEC4) && (PORT_IS_ENABLED(FM1_10GEC4))) ||
((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC1))) ||
((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC2))) ||
((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC3))) ||
((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC4)))
#endif
)
return 0;
#endif
/* board code might have caused offset to change */
off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
#ifndef CONFIG_SYS_FMAN_V3
/* Don't disable FM1-DTSEC1 MAC as its used for MDIO */
if (paddr != dtsec1_addr)
#endif
fdt_status_disabled(blob, off); /* disable the MAC node */
/* disable the fsl,dpa-ethernet node that points to the MAC */
ph = fdt_get_phandle(blob, off);
do_fixup_by_prop(blob, "fsl,fman-mac", &ph, sizeof(ph),
"status", "disabled", strlen("disabled") + 1, 1);
return 0;
}
void fdt_fixup_fman_ethernet(void *blob)
{
int i;
#ifdef CONFIG_SYS_FMAN_V3
for (i = 0; i < ARRAY_SIZE(fm_info); i++)
ft_fixup_port(blob, &fm_info[i], "fsl,fman-memac");
#else
for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
/* Try the new compatible first.
* If the node is missing, try the old.
*/
if (fm_info[i].type == FM_ETH_1G_E) {
if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-dtsec"))
ft_fixup_port(blob, &fm_info[i],
"fsl,fman-1g-mac");
} else {
if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-xgec") &&
ft_fixup_port(blob, &fm_info[i], "fsl,fman-tgec"))
ft_fixup_port(blob, &fm_info[i],
"fsl,fman-10g-mac");
}
}
#endif
}
/*QSGMII Riser Card can work in SGMII mode, but the PHY address is different.
*This function scans which Riser Card being used(QSGMII or SGMII Riser Card),
*then set the correct PHY address
*/
void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
unsigned int port_num, int phy_base_addr)
{
unsigned int regnum = 0;
int qsgmii;
int i;
int phy_real_addr;
qsgmii = is_qsgmii_riser_card(bus, phy_base_addr, port_num, regnum);
if (!qsgmii)
return;
for (i = base_port; i < base_port + port_num; i++) {
if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_SGMII) {
phy_real_addr = phy_base_addr + i - base_port;
fm_info_set_phy_address(i, phy_real_addr);
}
}
}
/*to check whether qsgmii riser card is used*/
int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
unsigned int port_num, unsigned regnum)
{
int i;
int val;
if (!bus)
return 0;
for (i = phy_base_addr; i < phy_base_addr + port_num; i++) {
val = bus->read(bus, i, MDIO_DEVAD_NONE, regnum);
if (val != MIIM_TIMEOUT)
return 1;
}
return 0;
}
source/bootloader/u-boot-2020.01/drivers/net/fm/ls1043.c
+111
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */
#define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
#define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000
#define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000
#define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */
#define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
#define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000
#define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000
#define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000
u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
[FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
[FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
[FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
[FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
[FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
[FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
[FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
[FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
[FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
};
static int is_device_disabled(enum fm_port port)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
}
void fman_disable_port(enum fm_port port)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
return PHY_INTERFACE_MODE_NONE;
if (port == FM1_DTSEC3)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) {
return PHY_INTERFACE_MODE_RGMII_TXID;
}
if (port == FM1_DTSEC4)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) {
return PHY_INTERFACE_MODE_RGMII_TXID;
}
/* handle SGMII */
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
if ((port == FM1_DTSEC2) &&
is_serdes_configured(SGMII_2500_FM1_DTSEC2))
return PHY_INTERFACE_MODE_SGMII_2500;
case FM1_DTSEC5:
case FM1_DTSEC6:
case FM1_DTSEC9:
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
else if ((port == FM1_DTSEC9) &&
is_serdes_configured(SGMII_2500_FM1_DTSEC9))
return PHY_INTERFACE_MODE_SGMII_2500;
break;
default:
break;
}
/* handle QSGMII */
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC5:
case FM1_DTSEC6:
/* only MAC 1,2,5,6 available for QSGMII */
if (is_serdes_configured(QSGMII_FM1_A))
return PHY_INTERFACE_MODE_QSGMII;
break;
default:
break;
}
return PHY_INTERFACE_MODE_NONE;
}
source/bootloader/u-boot-2020.01/drivers/net/fm/ls1046.c
+122
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */
#define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
#define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000
#define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000
#define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */
#define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
#define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000
#define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000
#define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000
u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
[FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
[FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
[FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
[FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
[FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
[FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
[FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
[FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
[FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
};
static int is_device_disabled(enum fm_port port)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
}
void fman_disable_port(enum fm_port port)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
return PHY_INTERFACE_MODE_NONE;
if ((port == FM1_10GEC2) && (is_serdes_configured(XFI_FM1_MAC10)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_DTSEC10) && (is_serdes_configured(XFI_FM1_MAC10)))
return PHY_INTERFACE_MODE_NONE;
if (port == FM1_DTSEC3)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII)
return PHY_INTERFACE_MODE_RGMII_TXID;
if (port == FM1_DTSEC4)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII)
return PHY_INTERFACE_MODE_RGMII_TXID;
/* handle SGMII, only MAC 2/5/6/9/10 available */
switch (port) {
case FM1_DTSEC2:
case FM1_DTSEC5:
case FM1_DTSEC6:
case FM1_DTSEC9:
case FM1_DTSEC10:
if (is_serdes_configured(SGMII_FM1_DTSEC2 + port - FM1_DTSEC2))
return PHY_INTERFACE_MODE_SGMII;
break;
default:
break;
}
/* handle 2.5G SGMII, only MAC 5/9/10 available */
switch (port) {
case FM1_DTSEC5:
case FM1_DTSEC9:
case FM1_DTSEC10:
if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 +
port - FM1_DTSEC5))
return PHY_INTERFACE_MODE_SGMII_2500;
break;
default:
break;
}
/* handle QSGMII, only MAC 1/5/6/10 available */
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC5:
case FM1_DTSEC6:
case FM1_DTSEC10:
if (is_serdes_configured(QSGMII_FM1_A))
return PHY_INTERFACE_MODE_QSGMII;
break;
default:
break;
}
return PHY_INTERFACE_MODE_NONE;
}
source/bootloader/u-boot-2020.01/drivers/net/fm/memac.c
+144
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2012 Freescale Semiconductor, Inc.
* Roy Zang <tie-fei.zang@freescale.com>
*/
/* MAXFRM - maximum frame length */
#define MAXFRM_MASK 0x0000ffff
#include <common.h>
#include <phy.h>
#include <asm/types.h>
#include <asm/io.h>
#include <fsl_memac.h>
#include "fm.h"
static void memac_init_mac(struct fsl_enet_mac *mac)
{
struct memac *regs = mac->base;
/* mask all interrupt */
out_be32(&regs->imask, IMASK_MASK_ALL);
/* clear all events */
out_be32(&regs->ievent, IEVENT_CLEAR_ALL);
/* set the max receive length */
out_be32(&regs->maxfrm, mac->max_rx_len & MAXFRM_MASK);
/* multicast frame reception for the hash entry disable */
out_be32(&regs->hashtable_ctrl, 0);
}
static void memac_enable_mac(struct fsl_enet_mac *mac)
{
struct memac *regs = mac->base;
setbits_be32(&regs->command_config,
MEMAC_CMD_CFG_RXTX_EN | MEMAC_CMD_CFG_NO_LEN_CHK);
}
static void memac_disable_mac(struct fsl_enet_mac *mac)
{
struct memac *regs = mac->base;
clrbits_be32(&regs->command_config, MEMAC_CMD_CFG_RXTX_EN);
}
static void memac_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr)
{
struct memac *regs = mac->base;
u32 mac_addr0, mac_addr1;
/*
* if a station address of 0x12345678ABCD, perform a write to
* MAC_ADDR0 of 0x78563412, MAC_ADDR1 of 0x0000CDAB
*/
mac_addr0 = (mac_addr[3] << 24) | (mac_addr[2] << 16) | \
(mac_addr[1] << 8) | (mac_addr[0]);
out_be32(&regs->mac_addr_0, mac_addr0);
mac_addr1 = ((mac_addr[5] << 8) | mac_addr[4]) & 0x0000ffff;
out_be32(&regs->mac_addr_1, mac_addr1);
}
static void memac_set_interface_mode(struct fsl_enet_mac *mac,
phy_interface_t type, int speed)
{
/* Roy need more work here */
struct memac *regs = mac->base;
u32 if_mode, if_status;
/* clear all bits relative with interface mode */
if_mode = in_be32(&regs->if_mode);
if_status = in_be32(&regs->if_status);
/* set interface mode */
switch (type) {
case PHY_INTERFACE_MODE_GMII:
if_mode &= ~IF_MODE_MASK;
if_mode |= IF_MODE_GMII;
break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
if_mode |= (IF_MODE_GMII | IF_MODE_RG);
break;
case PHY_INTERFACE_MODE_RMII:
if_mode |= (IF_MODE_GMII | IF_MODE_RM);
break;
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_QSGMII:
if_mode &= ~IF_MODE_MASK;
if_mode |= (IF_MODE_GMII);
break;
case PHY_INTERFACE_MODE_XGMII:
if_mode &= ~IF_MODE_MASK;
if_mode |= IF_MODE_XGMII;
break;
default:
break;
}
/* Enable automatic speed selection for Non-XGMII */
if (type != PHY_INTERFACE_MODE_XGMII)
if_mode |= IF_MODE_EN_AUTO;
if (type == PHY_INTERFACE_MODE_RGMII ||
type == PHY_INTERFACE_MODE_RGMII_TXID) {
if_mode &= ~IF_MODE_EN_AUTO;
if_mode &= ~IF_MODE_SETSP_MASK;
switch (speed) {
case SPEED_1000:
if_mode |= IF_MODE_SETSP_1000M;
break;
case SPEED_100:
if_mode |= IF_MODE_SETSP_100M;
break;
case SPEED_10:
if_mode |= IF_MODE_SETSP_10M;
default:
break;
}
}
debug(" %s, if_mode = %x\n", __func__, if_mode);
debug(" %s, if_status = %x\n", __func__, if_status);
out_be32(&regs->if_mode, if_mode);
return;
}
void init_memac(struct fsl_enet_mac *mac, void *base,
void *phyregs, int max_rx_len)
{
mac->base = base;
mac->phyregs = phyregs;
mac->max_rx_len = max_rx_len;
mac->init_mac = memac_init_mac;
mac->enable_mac = memac_enable_mac;
mac->disable_mac = memac_disable_mac;
mac->set_mac_addr = memac_set_mac_addr;
mac->set_if_mode = memac_set_interface_mode;
}
source/bootloader/u-boot-2020.01/drivers/net/fm/memac_phy.c
+169
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2012 Freescale Semiconductor, Inc.
* Andy Fleming <afleming@gmail.com>
* Roy Zang <tie-fei.zang@freescale.com>
* Some part is taken from tsec.c
*/
#include <common.h>
#include <miiphy.h>
#include <phy.h>
#include <asm/io.h>
#include <fsl_memac.h>
#include <fm_eth.h>
#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
#define memac_out_32(a, v) out_le32(a, v)
#define memac_clrbits_32(a, v) clrbits_le32(a, v)
#define memac_setbits_32(a, v) setbits_le32(a, v)
#else
#define memac_out_32(a, v) out_be32(a, v)
#define memac_clrbits_32(a, v) clrbits_be32(a, v)
#define memac_setbits_32(a, v) setbits_be32(a, v)
#endif
static u32 memac_in_32(u32 *reg)
{
#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
return in_le32(reg);
#else
return in_be32(reg);
#endif
}
/*
* Write value to the PHY for this device to the register at regnum, waiting
* until the write is done before it returns. All PHY configuration has to be
* done through the TSEC1 MIIM regs
*/
int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
int regnum, u16 value)
{
u32 mdio_ctl;
struct memac_mdio_controller *regs = bus->priv;
u32 c45 = 1; /* Default to 10G interface */
if (dev_addr == MDIO_DEVAD_NONE) {
c45 = 0; /* clause 22 */
dev_addr = regnum & 0x1f;
memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
} else
memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
/* Wait till the bus is free */
while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
;
/* Set the port and dev addr */
mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
memac_out_32(&regs->mdio_ctl, mdio_ctl);
/* Set the register address */
if (c45)
memac_out_32(&regs->mdio_addr, regnum & 0xffff);
/* Wait till the bus is free */
while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
;
/* Write the value to the register */
memac_out_32(&regs->mdio_data, MDIO_DATA(value));
/* Wait till the MDIO write is complete */
while ((memac_in_32(&regs->mdio_data)) & MDIO_DATA_BSY)
;
return 0;
}
/*
* Reads from register regnum in the PHY for device dev, returning the value.
* Clears miimcom first. All PHY configuration has to be done through the
* TSEC1 MIIM regs
*/
int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
int regnum)
{
u32 mdio_ctl;
struct memac_mdio_controller *regs = bus->priv;
u32 c45 = 1;
if (dev_addr == MDIO_DEVAD_NONE) {
if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME))
return 0xffff;
c45 = 0; /* clause 22 */
dev_addr = regnum & 0x1f;
memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
} else
memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
/* Wait till the bus is free */
while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
;
/* Set the Port and Device Addrs */
mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
memac_out_32(&regs->mdio_ctl, mdio_ctl);
/* Set the register address */
if (c45)
memac_out_32(&regs->mdio_addr, regnum & 0xffff);
/* Wait till the bus is free */
while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
;
/* Initiate the read */
mdio_ctl |= MDIO_CTL_READ;
memac_out_32(&regs->mdio_ctl, mdio_ctl);
/* Wait till the MDIO write is complete */
while ((memac_in_32(&regs->mdio_data)) & MDIO_DATA_BSY)
;
/* Return all Fs if nothing was there */
if (memac_in_32(&regs->mdio_stat) & MDIO_STAT_RD_ER)
return 0xffff;
return memac_in_32(&regs->mdio_data) & 0xffff;
}
int memac_mdio_reset(struct mii_dev *bus)
{
return 0;
}
int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
{
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate FM TGEC MDIO bus\n");
return -1;
}
bus->read = memac_mdio_read;
bus->write = memac_mdio_write;
bus->reset = memac_mdio_reset;
strcpy(bus->name, info->name);
bus->priv = info->regs;
/*
* On some platforms like B4860, default value of MDIO_CLK_DIV bits
* in mdio_stat(mdio_cfg) register generates MDIO clock too high
* (much higher than 2.5MHz), violating the IEEE specs.
* On other platforms like T1040, default value of MDIO_CLK_DIV bits
* is zero, so MDIO clock is disabled.
* So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
* be properly initialized.
* NEG bit default should be '1' as per FMAN-v3 RM, but on platform
* like T2080QDS, this bit default is '0', which leads to MDIO failure
* on XAUI PHY, so set this bit definitely.
*/
memac_setbits_32(
&((struct memac_mdio_controller *)info->regs)->mdio_stat,
MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
return mdio_register(bus);
}
source/bootloader/u-boot-2020.01/drivers/net/fm/p1023.c
+72
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
static u32 port_to_devdisr[] = {
[FM1_DTSEC1] = MPC85xx_DEVDISR_TSEC1,
[FM1_DTSEC2] = MPC85xx_DEVDISR_TSEC2,
};
static int is_device_disabled(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr = in_be32(&gur->devdisr);
return port_to_devdisr[port] & devdisr;
}
void fman_disable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */
if (port == FM1_DTSEC1)
return;
setbits_be32(&gur->devdisr, port_to_devdisr[port]);
}
void fman_enable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
/* DTSEC1 can be SGMII, RGMII or RMII */
if (port == FM1_DTSEC1) {
if (is_serdes_configured(SGMII_FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS) {
if (pordevsr & MPC85xx_PORDEVSR_TSEC1_PRTC)
return PHY_INTERFACE_MODE_RGMII;
else
return PHY_INTERFACE_MODE_RMII;
}
}
/* DTSEC2 only supports SGMII or RGMII */
if (port == FM1_DTSEC2) {
if (is_serdes_configured(SGMII_FM1_DTSEC2))
return PHY_INTERFACE_MODE_SGMII;
if (pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)
return PHY_INTERFACE_MODE_RGMII;
}
return PHY_INTERFACE_MODE_NONE;
}
source/bootloader/u-boot-2020.01/drivers/net/fm/p4080.c
+98
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
static u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
[FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
[FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
[FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
[FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
[FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2,
};
static int is_device_disabled(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
}
void fman_disable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */
if (port == FM1_DTSEC1)
return;
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
void fman_enable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2)))
return PHY_INTERFACE_MODE_XGMII;
/* handle RGMII first */
if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))
return PHY_INTERFACE_MODE_RGMII;
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC3:
case FM1_DTSEC4:
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
case FM2_DTSEC1:
case FM2_DTSEC2:
case FM2_DTSEC3:
case FM2_DTSEC4:
if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
default:
return PHY_INTERFACE_MODE_NONE;
}
return PHY_INTERFACE_MODE_NONE;
}
source/bootloader/u-boot-2020.01/drivers/net/fm/p5020.c
+89
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@@ -0,0 +1,89 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
static u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
};
static int is_device_disabled(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
}
void fman_disable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */
if (port == FM1_DTSEC1)
return;
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
void fman_enable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
return PHY_INTERFACE_MODE_XGMII;
/* handle RGMII first */
if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII))
return PHY_INTERFACE_MODE_MII;
if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII))
return PHY_INTERFACE_MODE_MII;
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC3:
case FM1_DTSEC4:
case FM1_DTSEC5:
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
default:
return PHY_INTERFACE_MODE_NONE;
}
return PHY_INTERFACE_MODE_NONE;
}
source/bootloader/u-boot-2020.01/drivers/net/fm/p5040.c
+106
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
[FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
[FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
[FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
[FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
[FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
[FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2,
};
static int is_device_disabled(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
}
void fman_disable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */
if (port == FM1_DTSEC1)
return;
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
void fman_enable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2)))
return PHY_INTERFACE_MODE_XGMII;
/* handle RGMII first */
if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII))
return PHY_INTERFACE_MODE_MII;
if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII))
return PHY_INTERFACE_MODE_MII;
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC3:
case FM1_DTSEC4:
case FM1_DTSEC5:
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
case FM2_DTSEC1:
case FM2_DTSEC2:
case FM2_DTSEC3:
case FM2_DTSEC4:
case FM2_DTSEC5:
if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
default:
return PHY_INTERFACE_MODE_NONE;
}
return PHY_INTERFACE_MODE_NONE;
}
source/bootloader/u-boot-2020.01/drivers/net/fm/t1024.c
+87
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@@ -0,0 +1,87 @@
// SPDX-License-Identifier: GPL-2.0+
/* Copyright 2014 Freescale Semiconductor, Inc.
*
* Shengzhou Liu <Shengzhou.Liu@freescale.com>
*/
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, /* MAC1 */
};
static int is_device_disabled(enum fm_port port)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
}
void fman_disable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
FSL_CORENET_RCWSR13_EC2_RGMII) &&
(!is_serdes_configured(QSGMII_FM1_A)))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
FSL_CORENET_RCWSR13_EC1_RGMII) &&
(!is_serdes_configured(QSGMII_FM1_A)))
return PHY_INTERFACE_MODE_RGMII;
/* handle SGMII */
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC3:
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1
+ port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII_2500;
break;
default:
break;
}
/* handle QSGMII */
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC3:
case FM1_DTSEC4:
/* check lane A on SerDes1 */
if (is_serdes_configured(QSGMII_FM1_A))
return PHY_INTERFACE_MODE_QSGMII;
break;
default:
break;
}
return PHY_INTERFACE_MODE_NONE;
}
source/bootloader/u-boot-2020.01/drivers/net/fm/t1040.c
+63
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
phy_interface_t fman_port_enet_if(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
/* handle RGMII first */
if ((port == FM1_DTSEC2) &&
((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) ==
FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) {
if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII)
return PHY_INTERFACE_MODE_RGMII;
else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
return PHY_INTERFACE_MODE_MII;
}
if ((port == FM1_DTSEC4) &&
((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) ==
FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) {
if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII)
return PHY_INTERFACE_MODE_RGMII;
else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
return PHY_INTERFACE_MODE_MII;
}
if (port == FM1_DTSEC5) {
if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII)
return PHY_INTERFACE_MODE_RGMII;
}
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1) ||
is_serdes_configured(SGMII_SW1_MAC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_QSGMII;
case FM1_DTSEC3:
case FM1_DTSEC4:
case FM1_DTSEC5:
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
default:
return PHY_INTERFACE_MODE_NONE;
}
return PHY_INTERFACE_MODE_NONE;
}
source/bootloader/u-boot-2020.01/drivers/net/fm/t2080.c
+92
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* Shengzhou Liu <Shengzhou.Liu@freescale.com>
*/
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
[FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
[FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
[FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
[FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
[FM1_10GEC3] = FSL_CORENET_DEVDISR2_10GEC1_3,
[FM1_10GEC4] = FSL_CORENET_DEVDISR2_10GEC1_4,
};
static int is_device_disabled(enum fm_port port)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
}
void fman_disable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
((is_serdes_configured(XAUI_FM1_MAC9)) ||
(is_serdes_configured(XFI_FM1_MAC9)) ||
(is_serdes_configured(XFI_FM1_MAC10))))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_10GEC3 || port == FM1_10GEC4) &&
((is_serdes_configured(XFI_FM1_MAC1)) ||
(is_serdes_configured(XFI_FM1_MAC2))))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM1_DTSEC10) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII))
return PHY_INTERFACE_MODE_RGMII;
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC3:
case FM1_DTSEC4:
case FM1_DTSEC5:
case FM1_DTSEC6:
case FM1_DTSEC9:
case FM1_DTSEC10:
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
default:
return PHY_INTERFACE_MODE_NONE;
}
return PHY_INTERFACE_MODE_NONE;
}
source/bootloader/u-boot-2020.01/drivers/net/fm/t4240.c
+170
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2012 Freescale Semiconductor, Inc.
* Roy Zang <tie-fei.zang@freescale.com>
*/
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
[FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
[FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
[FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
[FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
[FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
[FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
[FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
[FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
[FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
[FM2_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC2_6,
[FM2_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC2_9,
[FM2_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC2_10,
[FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2_1,
[FM2_10GEC2] = FSL_CORENET_DEVDISR2_10GEC2_2,
};
static int is_device_disabled(enum fm_port port)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
}
void fman_disable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
void fman_enable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
((is_serdes_configured(XAUI_FM1_MAC9)) ||
(is_serdes_configured(XAUI_FM1_MAC10)) ||
(is_serdes_configured(XFI_FM1_MAC9)) ||
(is_serdes_configured(XFI_FM1_MAC10))))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_DTSEC9 || port == FM1_DTSEC10) &&
((is_serdes_configured(XFI_FM1_MAC9)) ||
(is_serdes_configured(XFI_FM1_MAC10))))
return PHY_INTERFACE_MODE_NONE;
if ((port == FM2_10GEC1 || port == FM2_10GEC2) &&
((is_serdes_configured(XAUI_FM2_MAC9)) ||
(is_serdes_configured(XAUI_FM2_MAC10)) ||
(is_serdes_configured(XFI_FM2_MAC9)) ||
(is_serdes_configured(XFI_FM2_MAC10))))
return PHY_INTERFACE_MODE_XGMII;
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII 0x08000000
#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
/* handle RGMII first */
if ((port == FM2_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM1_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM2_DTSEC6) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII))
return PHY_INTERFACE_MODE_RGMII;
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC3:
case FM1_DTSEC4:
case FM1_DTSEC5:
case FM1_DTSEC6:
case FM1_DTSEC9:
case FM1_DTSEC10:
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
case FM2_DTSEC1:
case FM2_DTSEC2:
case FM2_DTSEC3:
case FM2_DTSEC4:
case FM2_DTSEC5:
case FM2_DTSEC6:
case FM2_DTSEC9:
case FM2_DTSEC10:
if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
default:
break;
}
/* handle QSGMII */
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC3:
case FM1_DTSEC4:
/* check lane G on SerDes1 */
if (is_serdes_configured(QSGMII_FM1_A))
return PHY_INTERFACE_MODE_QSGMII;
break;
case FM1_DTSEC5:
case FM1_DTSEC6:
case FM1_DTSEC9:
case FM1_DTSEC10:
/* check lane C on SerDes1 */
if (is_serdes_configured(QSGMII_FM1_B))
return PHY_INTERFACE_MODE_QSGMII;
break;
case FM2_DTSEC1:
case FM2_DTSEC2:
case FM2_DTSEC3:
case FM2_DTSEC4:
/* check lane G on SerDes2 */
if (is_serdes_configured(QSGMII_FM2_A))
return PHY_INTERFACE_MODE_QSGMII;
break;
case FM2_DTSEC5:
case FM2_DTSEC6:
case FM2_DTSEC9:
case FM2_DTSEC10:
/* check lane C on SerDes2 */
if (is_serdes_configured(QSGMII_FM2_B))
return PHY_INTERFACE_MODE_QSGMII;
break;
default:
break;
}
return PHY_INTERFACE_MODE_NONE;
}
source/bootloader/u-boot-2020.01/drivers/net/fm/tgec.c
+104
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@@ -0,0 +1,104 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*/
/* MAXFRM - maximum frame length */
#define MAXFRM_MASK 0x0000ffff
#include <common.h>
#include <phy.h>
#include <asm/types.h>
#include <asm/io.h>
#include <fsl_tgec.h>
#include "fm.h"
#define TGEC_CMD_CFG_INIT (TGEC_CMD_CFG_NO_LEN_CHK | \
TGEC_CMD_CFG_RX_ER_DISC | \
TGEC_CMD_CFG_STAT_CLR | \
TGEC_CMD_CFG_PAUSE_IGNORE | \
TGEC_CMD_CFG_CRC_FWD)
#define TGEC_CMD_CFG_FINAL (TGEC_CMD_CFG_NO_LEN_CHK | \
TGEC_CMD_CFG_RX_ER_DISC | \
TGEC_CMD_CFG_PAUSE_IGNORE | \
TGEC_CMD_CFG_CRC_FWD)
static void tgec_init_mac(struct fsl_enet_mac *mac)
{
struct tgec *regs = mac->base;
/* mask all interrupt */
out_be32(&regs->imask, IMASK_MASK_ALL);
/* clear all events */
out_be32(&regs->ievent, IEVENT_CLEAR_ALL);
/* set the max receive length */
out_be32(&regs->maxfrm, mac->max_rx_len & MAXFRM_MASK);
/*
* 1588 disable, insert second mac disable payload length check
* disable, normal operation, any rx error frame is discarded, clear
* counters, pause frame ignore, no promiscuous, LAN mode Rx CRC no
* strip, Tx CRC append, Rx disable and Tx disable
*/
out_be32(&regs->command_config, TGEC_CMD_CFG_INIT);
udelay(1000);
out_be32(&regs->command_config, TGEC_CMD_CFG_FINAL);
/* multicast frame reception for the hash entry disable */
out_be32(&regs->hashtable_ctrl, 0);
}
static void tgec_enable_mac(struct fsl_enet_mac *mac)
{
struct tgec *regs = mac->base;
setbits_be32(&regs->command_config, TGEC_CMD_CFG_RXTX_EN);
}
static void tgec_disable_mac(struct fsl_enet_mac *mac)
{
struct tgec *regs = mac->base;
clrbits_be32(&regs->command_config, TGEC_CMD_CFG_RXTX_EN);
}
static void tgec_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr)
{
struct tgec *regs = mac->base;
u32 mac_addr0, mac_addr1;
/*
* if a station address of 0x12345678ABCD, perform a write to
* MAC_ADDR0 of 0x78563412, MAC_ADDR1 of 0x0000CDAB
*/
mac_addr0 = (mac_addr[3] << 24) | (mac_addr[2] << 16) | \
(mac_addr[1] << 8) | (mac_addr[0]);
out_be32(&regs->mac_addr_0, mac_addr0);
mac_addr1 = ((mac_addr[5] << 8) | mac_addr[4]) & 0x0000ffff;
out_be32(&regs->mac_addr_1, mac_addr1);
}
static void tgec_set_interface_mode(struct fsl_enet_mac *mac,
phy_interface_t type, int speed)
{
/* nothing right now */
return;
}
void init_tgec(struct fsl_enet_mac *mac, void *base,
void *phyregs, int max_rx_len)
{
mac->base = base;
mac->phyregs = phyregs;
mac->max_rx_len = max_rx_len;
mac->init_mac = tgec_init_mac;
mac->enable_mac = tgec_enable_mac;
mac->disable_mac = tgec_disable_mac;
mac->set_mac_addr = tgec_set_mac_addr;
mac->set_if_mode = tgec_set_interface_mode;
}
source/bootloader/u-boot-2020.01/drivers/net/fm/tgec_phy.c
+125
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
* Andy Fleming <afleming@gmail.com>
* Some part is taken from tsec.c
*/
#include <common.h>
#include <miiphy.h>
#include <phy.h>
#include <asm/io.h>
#include <fsl_tgec.h>
#include <fm_eth.h>
/*
* Write value to the PHY for this device to the register at regnum, waiting
* until the write is done before it returns. All PHY configuration has to be
* done through the TSEC1 MIIM regs
*/
static int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
int regnum, u16 value)
{
u32 mdio_ctl;
u32 stat_val;
struct tgec_mdio_controller *regs = bus->priv;
if (dev_addr == MDIO_DEVAD_NONE)
return 0;
/* Wait till the bus is free */
stat_val = MDIO_STAT_CLKDIV(100);
out_be32(&regs->mdio_stat, stat_val);
while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
;
/* Set the port and dev addr */
mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
out_be32(&regs->mdio_ctl, mdio_ctl);
/* Set the register address */
out_be32(&regs->mdio_addr, regnum & 0xffff);
/* Wait till the bus is free */
while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
;
/* Write the value to the register */
out_be32(&regs->mdio_data, MDIO_DATA(value));
/* Wait till the MDIO write is complete */
while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY)
;
return 0;
}
/*
* Reads from register regnum in the PHY for device dev, returning the value.
* Clears miimcom first. All PHY configuration has to be done through the
* TSEC1 MIIM regs
*/
static int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
int regnum)
{
u32 mdio_ctl;
u32 stat_val;
struct tgec_mdio_controller *regs = bus->priv;
if (dev_addr == MDIO_DEVAD_NONE)
return 0xffff;
stat_val = MDIO_STAT_CLKDIV(100);
out_be32(&regs->mdio_stat, stat_val);
/* Wait till the bus is free */
while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
;
/* Set the Port and Device Addrs */
mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
out_be32(&regs->mdio_ctl, mdio_ctl);
/* Set the register address */
out_be32(&regs->mdio_addr, regnum & 0xffff);
/* Wait till the bus is free */
while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
;
/* Initiate the read */
mdio_ctl |= MDIO_CTL_READ;
out_be32(&regs->mdio_ctl, mdio_ctl);
/* Wait till the MDIO write is complete */
while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY)
;
/* Return all Fs if nothing was there */
if (in_be32(&regs->mdio_stat) & MDIO_STAT_RD_ER)
return 0xffff;
return in_be32(&regs->mdio_data) & 0xffff;
}
static int tgec_mdio_reset(struct mii_dev *bus)
{
return 0;
}
int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info)
{
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate FM TGEC MDIO bus\n");
return -1;
}
bus->read = tgec_mdio_read;
bus->write = tgec_mdio_write;
bus->reset = tgec_mdio_reset;
strcpy(bus->name, info->name);
bus->priv = info->regs;
return mdio_register(bus);
}