GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,34 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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# PCI Endpoint Support
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#
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menu "PCI Endpoint"
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config PCI_ENDPOINT
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bool "PCI Endpoint Support"
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depends on DM
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help
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Enable this configuration option to support configurable PCI
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endpoints. This should be enabled if the platform has a PCI
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controllers that can operate in endpoint mode (as a device
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connected to PCI host or bridge).
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config PCIE_CADENCE_EP
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bool "Cadence PCIe endpoint controller"
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depends on PCI_ENDPOINT
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help
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Say Y here if you want to support the Cadence PCIe controller in
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endpoint mode. This PCIe controller may be embedded into many
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different vendors SoCs.
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config PCI_SANDBOX_EP
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bool "Sandbox PCIe endpoint controller"
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depends on PCI_ENDPOINT
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help
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Say Y here if you want to support the Sandbox PCIe controller in
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endpoint mode.
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The sandbox driver act as a dummy driver which stores and
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retrieves PCIe endpoint configuration as is.
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endmenu
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@@ -0,0 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2019
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# Ramon Fried <ramon.fried@gmail.com>
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obj-y += pci_ep-uclass.o
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obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o
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obj-$(CONFIG_PCI_SANDBOX_EP) += sandbox-pci_ep.o
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@@ -0,0 +1,211 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* PCI Endpoint uclass
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*
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* Based on Linux PCI-EP driver written by
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* Kishon Vijay Abraham I <kishon@ti.com>
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*
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* Copyright (c) 2019
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* Written by Ramon Fried <ramon.fried@gmail.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <linux/log2.h>
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#include <pci_ep.h>
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DECLARE_GLOBAL_DATA_PTR;
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int pci_ep_write_header(struct udevice *dev, uint fn, struct pci_ep_header *hdr)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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if (!ops->write_header)
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return -ENOSYS;
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return ops->write_header(dev, fn, hdr);
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}
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int pci_ep_read_header(struct udevice *dev, uint fn, struct pci_ep_header *hdr)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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if (!ops->read_header)
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return -ENOSYS;
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return ops->read_header(dev, fn, hdr);
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}
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int pci_ep_set_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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int flags = ep_bar->flags;
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/* Some basic bar validity checks */
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if (ep_bar->barno > BAR_5 || ep_bar->barno < BAR_0)
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return -EINVAL;
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if ((ep_bar->barno == BAR_5 &&
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(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)) ||
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((flags & PCI_BASE_ADDRESS_SPACE_IO) &&
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(flags & PCI_BASE_ADDRESS_IO_MASK)) ||
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(upper_32_bits(ep_bar->size) &&
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!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)))
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return -EINVAL;
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if (!ops->set_bar)
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return -ENOSYS;
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return ops->set_bar(dev, func_no, ep_bar);
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}
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int pci_ep_read_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar,
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enum pci_barno barno)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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/* Some basic bar validity checks */
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if (barno > BAR_5 || barno < BAR_0)
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return -EINVAL;
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if (!ops->read_bar)
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return -ENOSYS;
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return ops->read_bar(dev, func_no, ep_bar, barno);
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}
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int pci_ep_clear_bar(struct udevice *dev, uint func_num, enum pci_barno bar)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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if (!ops->clear_bar)
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return -ENOSYS;
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return ops->clear_bar(dev, func_num, bar);
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}
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int pci_ep_map_addr(struct udevice *dev, uint func_no, phys_addr_t addr,
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u64 pci_addr, size_t size)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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if (!ops->map_addr)
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return -ENOSYS;
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return ops->map_addr(dev, func_no, addr, pci_addr, size);
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}
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int pci_ep_unmap_addr(struct udevice *dev, uint func_no, phys_addr_t addr)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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if (!ops->unmap_addr)
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return -ENOSYS;
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return ops->unmap_addr(dev, func_no, addr);
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}
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int pci_ep_set_msi(struct udevice *dev, uint func_no, uint interrupts)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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uint encode_int;
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if (interrupts > 32)
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return -EINVAL;
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if (!ops->set_msi)
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return -ENOSYS;
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/* MSI spec permits allocation of
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* only 1, 2, 4, 8, 16, 32 interrupts
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*/
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encode_int = order_base_2(interrupts);
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return ops->set_msi(dev, func_no, encode_int);
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}
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int pci_ep_get_msi(struct udevice *dev, uint func_no)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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int interrupt;
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if (!ops->get_msi)
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return -ENOSYS;
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interrupt = ops->get_msi(dev, func_no);
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if (interrupt < 0)
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return 0;
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/* Translate back from order base 2*/
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interrupt = 1 << interrupt;
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return interrupt;
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}
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int pci_ep_set_msix(struct udevice *dev, uint func_no, uint interrupts)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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if (interrupts < 1 || interrupts > 2048)
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return -EINVAL;
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if (!ops->set_msix)
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return -ENOSYS;
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return ops->set_msix(dev, func_no, interrupts - 1);
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}
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int pci_ep_get_msix(struct udevice *dev, uint func_no)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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int interrupt;
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if (!ops->get_msix)
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return -ENOSYS;
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interrupt = ops->get_msix(dev, func_no);
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if (interrupt < 0)
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return 0;
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return interrupt + 1;
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}
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int pci_ep_raise_irq(struct udevice *dev, uint func_no,
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enum pci_ep_irq_type type, uint interrupt_num)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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if (!ops->raise_irq)
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return -ENOSYS;
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return ops->raise_irq(dev, func_no, type, interrupt_num);
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}
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int pci_ep_start(struct udevice *dev)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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if (!ops->start)
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return -ENOSYS;
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return ops->start(dev);
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}
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int pci_ep_stop(struct udevice *dev)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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if (!ops->stop)
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return -ENOSYS;
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return ops->stop(dev);
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}
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UCLASS_DRIVER(pci_ep) = {
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.id = UCLASS_PCI_EP,
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.name = "pci_ep",
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.flags = DM_UC_FLAG_SEQ_ALIAS,
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};
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@@ -0,0 +1,177 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019
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* Written by Ramon Fried <ramon.fried@gmail.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <pci_ep.h>
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#include <linux/sizes.h>
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#include <linux/log2.h>
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#include "pcie-cadence.h"
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DECLARE_GLOBAL_DATA_PTR;
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static int cdns_write_header(struct udevice *dev, uint fn,
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struct pci_ep_header *hdr)
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{
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struct cdns_pcie *pcie = dev_get_priv(dev);
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cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
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cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
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cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG,
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hdr->progif_code);
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cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
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hdr->subclass_code |
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hdr->baseclass_code << 8);
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cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
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hdr->cache_line_size);
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cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID,
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hdr->subsys_id);
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cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN,
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hdr->interrupt_pin);
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/*
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* Vendor ID can only be modified from function 0, all other functions
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* use the same vendor ID as function 0.
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*/
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if (fn == 0) {
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/* Update the vendor IDs. */
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u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
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CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
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cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
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}
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return 0;
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}
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static int cdns_set_bar(struct udevice *dev, uint fn, struct pci_bar *ep_bar)
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{
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struct cdns_pcie *pcie = dev_get_priv(dev);
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dma_addr_t bar_phys = ep_bar->phys_addr;
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enum pci_barno bar = ep_bar->barno;
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int flags = ep_bar->flags;
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u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
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u64 sz;
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/* BAR size is 2^(aperture + 7) */
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sz = max_t(size_t, ep_bar->size, CDNS_PCIE_EP_MIN_APERTURE);
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/*
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* roundup_pow_of_two() returns an unsigned long, which is not suited
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* for 64bit values.
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*/
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sz = 1ULL << fls64(sz - 1);
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aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
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if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
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ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
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} else {
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bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
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bool is_64bits = (sz > SZ_2G) |
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!!(ep_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64);
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if (is_64bits && (bar & 1))
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return -EINVAL;
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if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
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ep_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
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if (is_64bits && is_prefetch)
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ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
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else if (is_prefetch)
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ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
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else if (is_64bits)
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ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
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else
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ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
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}
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addr0 = lower_32_bits(bar_phys);
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addr1 = upper_32_bits(bar_phys);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
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addr0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
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addr1);
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if (bar < BAR_4) {
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reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
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b = bar;
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} else {
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reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
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b = bar - BAR_4;
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}
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cfg = cdns_pcie_readl(pcie, reg);
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cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
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CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
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cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
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CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
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cdns_pcie_writel(pcie, reg, cfg);
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return 0;
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}
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static int cdns_set_msi(struct udevice *dev, uint fn, uint mmc)
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{
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struct cdns_pcie *pcie = dev_get_priv(dev);
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u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
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/*
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* Set the Multiple Message Capable bitfield into the Message Control
|
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* register.
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*/
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u16 flags;
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flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
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flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1);
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flags |= PCI_MSI_FLAGS_64BIT;
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flags &= ~PCI_MSI_FLAGS_MASKBIT;
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cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags);
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return 0;
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}
|
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static struct pci_ep_ops cdns_pci_ep_ops = {
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.write_header = cdns_write_header,
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.set_bar = cdns_set_bar,
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.set_msi = cdns_set_msi,
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};
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static int cdns_pci_ep_probe(struct udevice *dev)
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{
|
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struct cdns_pcie *pdata = dev_get_priv(dev);
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pdata->reg_base = (void __iomem *)devfdt_get_addr(dev);
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if (!pdata->reg_base)
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return -ENOMEM;
|
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pdata->max_functions = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"max-functions", 1);
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pdata->max_regions = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"cdns,max-outbound-regions", 8);
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return 0;
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}
|
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|
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static int cdns_pci_ep_remove(struct udevice *dev)
|
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{
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return 0;
|
||||
}
|
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|
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const struct udevice_id cadence_pci_ep_of_match[] = {
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{ .compatible = "cdns,cdns-pcie-ep" },
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{ }
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||||
};
|
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U_BOOT_DRIVER(cdns_pcie) = {
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.name = "cdns,pcie-ep",
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.id = UCLASS_PCI_EP,
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.of_match = cadence_pci_ep_of_match,
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.ops = &cdns_pci_ep_ops,
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.probe = cdns_pci_ep_probe,
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.remove = cdns_pci_ep_remove,
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.priv_auto_alloc_size = sizeof(struct cdns_pcie),
|
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};
|
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@@ -0,0 +1,309 @@
|
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/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Cadence PCIe controlloer definitions
|
||||
* Adapted from linux kernel driver.
|
||||
* Copyright (c) 2017 Cadence
|
||||
*
|
||||
* Copyright (c) 2019
|
||||
* Written by Ramon Fried <ramon.fried@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef PCIE_CADENCE_H
|
||||
#define PCIE_CADENCE_H
|
||||
|
||||
#include <common.h>
|
||||
#include <pci_ep.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
/*
|
||||
* Local Management Registers
|
||||
*/
|
||||
#define CDNS_PCIE_LM_BASE 0x00100000
|
||||
|
||||
/* Vendor ID Register */
|
||||
#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044)
|
||||
#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0)
|
||||
#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0
|
||||
#define CDNS_PCIE_LM_ID_VENDOR(vid) \
|
||||
(((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK)
|
||||
#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16)
|
||||
#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16
|
||||
#define CDNS_PCIE_LM_ID_SUBSYS(sub) \
|
||||
(((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK)
|
||||
|
||||
/* Root Port Requestor ID Register */
|
||||
#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228)
|
||||
#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0)
|
||||
#define CDNS_PCIE_LM_RP_RID_SHIFT 0
|
||||
#define CDNS_PCIE_LM_RP_RID_(rid) \
|
||||
(((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK)
|
||||
|
||||
/* Endpoint Bus and Device Number Register */
|
||||
#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c)
|
||||
#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0)
|
||||
#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0
|
||||
#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8)
|
||||
#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8
|
||||
|
||||
/* Endpoint Function f BAR b Configuration Registers */
|
||||
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \
|
||||
(CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008)
|
||||
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \
|
||||
(CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008)
|
||||
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \
|
||||
(GENMASK(4, 0) << ((b) * 8))
|
||||
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \
|
||||
(((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b))
|
||||
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \
|
||||
(GENMASK(7, 5) << ((b) * 8))
|
||||
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \
|
||||
(((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))
|
||||
|
||||
/* Endpoint Function Configuration Register */
|
||||
#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0)
|
||||
|
||||
/* Root Complex BAR Configuration Register */
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \
|
||||
(((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \
|
||||
(((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \
|
||||
(((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \
|
||||
(((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20)
|
||||
#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31)
|
||||
|
||||
/* BAR control values applicable to both Endpoint Function and Root Complex */
|
||||
#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0
|
||||
#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1
|
||||
#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4
|
||||
#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5
|
||||
#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6
|
||||
#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7
|
||||
|
||||
/*
|
||||
* Endpoint Function Registers (PCI configuration space for endpoint functions)
|
||||
*/
|
||||
#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12))
|
||||
|
||||
#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90
|
||||
|
||||
/*
|
||||
* Root Port Registers (PCI configuration space for the root port function)
|
||||
*/
|
||||
#define CDNS_PCIE_RP_BASE 0x00200000
|
||||
|
||||
/*
|
||||
* Address Translation Registers
|
||||
*/
|
||||
#define CDNS_PCIE_AT_BASE 0x00400000
|
||||
|
||||
/* Region r Outbound AXI to PCIe Address Translation Register 0 */
|
||||
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \
|
||||
(CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020)
|
||||
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)
|
||||
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \
|
||||
(((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
|
||||
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12)
|
||||
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
|
||||
(((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK)
|
||||
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20)
|
||||
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
|
||||
(((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)
|
||||
|
||||
/* Region r Outbound AXI to PCIe Address Translation Register 1 */
|
||||
#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \
|
||||
(CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020)
|
||||
|
||||
/* Region r Outbound PCIe Descriptor Register 0 */
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \
|
||||
(CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020)
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0)
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd
|
||||
/* Bit 23 MUST be set in RC mode. */
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23)
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24)
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \
|
||||
(((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK)
|
||||
|
||||
/* Region r Outbound PCIe Descriptor Register 1 */
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \
|
||||
(CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020)
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0)
|
||||
#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \
|
||||
((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK)
|
||||
|
||||
/* Region r AXI Region Base Address Register 0 */
|
||||
#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \
|
||||
(CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020)
|
||||
#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0)
|
||||
#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \
|
||||
(((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
|
||||
|
||||
/* Region r AXI Region Base Address Register 1 */
|
||||
#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \
|
||||
(CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020)
|
||||
|
||||
/* Root Port BAR Inbound PCIe to AXI Address Translation Register */
|
||||
#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \
|
||||
(CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008)
|
||||
#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0)
|
||||
#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \
|
||||
(((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
|
||||
#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
|
||||
(CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
|
||||
|
||||
/* AXI link down register */
|
||||
#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824)
|
||||
|
||||
enum cdns_pcie_rp_bar {
|
||||
RP_BAR0,
|
||||
RP_BAR1,
|
||||
RP_NO_BAR
|
||||
};
|
||||
|
||||
/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
|
||||
#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \
|
||||
(CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008)
|
||||
#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \
|
||||
(CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008)
|
||||
|
||||
/* Normal/Vendor specific message access: offset inside some outbound region */
|
||||
#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5)
|
||||
#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \
|
||||
(((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK)
|
||||
#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8)
|
||||
#define CDNS_PCIE_NORMAL_MSG_CODE(code) \
|
||||
(((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK)
|
||||
#define CDNS_PCIE_MSG_NO_DATA BIT(16)
|
||||
|
||||
#define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */
|
||||
|
||||
enum cdns_pcie_msg_code {
|
||||
MSG_CODE_ASSERT_INTA = 0x20,
|
||||
MSG_CODE_ASSERT_INTB = 0x21,
|
||||
MSG_CODE_ASSERT_INTC = 0x22,
|
||||
MSG_CODE_ASSERT_INTD = 0x23,
|
||||
MSG_CODE_DEASSERT_INTA = 0x24,
|
||||
MSG_CODE_DEASSERT_INTB = 0x25,
|
||||
MSG_CODE_DEASSERT_INTC = 0x26,
|
||||
MSG_CODE_DEASSERT_INTD = 0x27,
|
||||
};
|
||||
|
||||
enum cdns_pcie_msg_routing {
|
||||
/* Route to Root Complex */
|
||||
MSG_ROUTING_TO_RC,
|
||||
|
||||
/* Use Address Routing */
|
||||
MSG_ROUTING_BY_ADDR,
|
||||
|
||||
/* Use ID Routing */
|
||||
MSG_ROUTING_BY_ID,
|
||||
|
||||
/* Route as Broadcast Message from Root Complex */
|
||||
MSG_ROUTING_BCAST,
|
||||
|
||||
/* Local message; terminate at receiver (INTx messages) */
|
||||
MSG_ROUTING_LOCAL,
|
||||
|
||||
/* Gather & route to Root Complex (PME_TO_Ack message) */
|
||||
MSG_ROUTING_GATHER,
|
||||
};
|
||||
|
||||
struct cdns_pcie {
|
||||
void __iomem *reg_base;
|
||||
u32 max_functions;
|
||||
u32 max_regions;
|
||||
};
|
||||
|
||||
/* Register access */
|
||||
static inline void cdns_pcie_writeb(struct cdns_pcie *pcie, u32 reg, u8 value)
|
||||
{
|
||||
writeb(value, pcie->reg_base + reg);
|
||||
}
|
||||
|
||||
static inline void cdns_pcie_writew(struct cdns_pcie *pcie, u32 reg, u16 value)
|
||||
{
|
||||
writew(value, pcie->reg_base + reg);
|
||||
}
|
||||
|
||||
static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value)
|
||||
{
|
||||
writel(value, pcie->reg_base + reg);
|
||||
}
|
||||
|
||||
static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg)
|
||||
{
|
||||
return readl(pcie->reg_base + reg);
|
||||
}
|
||||
|
||||
/* Root Port register access */
|
||||
static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie,
|
||||
u32 reg, u8 value)
|
||||
{
|
||||
writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
|
||||
}
|
||||
|
||||
static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie,
|
||||
u32 reg, u16 value)
|
||||
{
|
||||
writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
|
||||
}
|
||||
|
||||
static inline void cdns_pcie_rp_writel(struct cdns_pcie *pcie,
|
||||
u32 reg, u32 value)
|
||||
{
|
||||
writel(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
|
||||
}
|
||||
|
||||
/* Endpoint Function register access */
|
||||
static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn,
|
||||
u32 reg, u8 value)
|
||||
{
|
||||
writeb(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
|
||||
}
|
||||
|
||||
static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn,
|
||||
u32 reg, u16 value)
|
||||
{
|
||||
writew(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
|
||||
}
|
||||
|
||||
static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn,
|
||||
u32 reg, u32 value)
|
||||
{
|
||||
writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
|
||||
}
|
||||
|
||||
static inline u8 cdns_pcie_ep_fn_readb(struct cdns_pcie *pcie, u8 fn, u32 reg)
|
||||
{
|
||||
return readb(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
|
||||
}
|
||||
|
||||
static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg)
|
||||
{
|
||||
return readw(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
|
||||
}
|
||||
|
||||
static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg)
|
||||
{
|
||||
return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
|
||||
}
|
||||
|
||||
#endif /* end of include guard: PCIE_CADENCE_H */
|
||||
@@ -0,0 +1,179 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2019 Ramon Fried <ramon.fried@gmail.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
#include <pci.h>
|
||||
#include <pci_ep.h>
|
||||
#include <asm/test.h>
|
||||
|
||||
/**
|
||||
* struct sandbox_pci_ep_priv - private data for driver
|
||||
* @hdr: Stores the EP device header
|
||||
* @msix: required MSIx count;
|
||||
* @msi: required MSI count;
|
||||
*/
|
||||
struct sandbox_pci_ep_priv {
|
||||
struct pci_ep_header hdr;
|
||||
struct pci_bar bars[6];
|
||||
int msix;
|
||||
int msi;
|
||||
int irq_count;
|
||||
};
|
||||
|
||||
/* Method exported for testing purposes */
|
||||
int sandbox_get_pci_ep_irq_count(struct udevice *dev)
|
||||
{
|
||||
struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
|
||||
|
||||
return priv->irq_count;
|
||||
}
|
||||
|
||||
static const struct udevice_id sandbox_pci_ep_ids[] = {
|
||||
{ .compatible = "sandbox,pci_ep" },
|
||||
{ }
|
||||
};
|
||||
|
||||
static int sandbox_write_header(struct udevice *dev, uint fn,
|
||||
struct pci_ep_header *hdr)
|
||||
{
|
||||
struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
|
||||
|
||||
if (fn > 0)
|
||||
return -ENODEV;
|
||||
|
||||
memcpy(&priv->hdr, hdr, sizeof(*hdr));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sandbox_read_header(struct udevice *dev, uint fn,
|
||||
struct pci_ep_header *hdr)
|
||||
{
|
||||
struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
|
||||
|
||||
if (fn > 0)
|
||||
return -ENODEV;
|
||||
|
||||
memcpy(hdr, &priv->hdr, sizeof(*hdr));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sandbox_set_bar(struct udevice *dev, uint fn,
|
||||
struct pci_bar *ep_bar)
|
||||
{
|
||||
struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
|
||||
int bar_idx;
|
||||
|
||||
if (fn > 0)
|
||||
return -ENODEV;
|
||||
|
||||
bar_idx = ep_bar->barno;
|
||||
|
||||
memcpy(&priv->bars[bar_idx], ep_bar, sizeof(*ep_bar));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sandbox_read_bar(struct udevice *dev, uint fn,
|
||||
struct pci_bar *ep_bar, enum pci_barno barno)
|
||||
{
|
||||
struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
|
||||
|
||||
if (fn > 0)
|
||||
return -ENODEV;
|
||||
|
||||
memcpy(ep_bar, &priv->bars[barno], sizeof(*ep_bar));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sandbox_set_msi(struct udevice *dev, uint fn, uint interrupts)
|
||||
{
|
||||
struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
|
||||
|
||||
if (fn > 0)
|
||||
return -ENODEV;
|
||||
|
||||
priv->msi = interrupts;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sandbox_get_msi(struct udevice *dev, uint fn)
|
||||
{
|
||||
struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
|
||||
|
||||
if (fn > 0)
|
||||
return -ENODEV;
|
||||
|
||||
return priv->msi;
|
||||
}
|
||||
|
||||
static int sandbox_set_msix(struct udevice *dev, uint fn, uint interrupts)
|
||||
{
|
||||
struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
|
||||
|
||||
if (fn > 0)
|
||||
return -ENODEV;
|
||||
|
||||
priv->msix = interrupts;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sandbox_get_msix(struct udevice *dev, uint fn)
|
||||
{
|
||||
struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
|
||||
|
||||
if (fn > 0)
|
||||
return -ENODEV;
|
||||
|
||||
return priv->msix;
|
||||
}
|
||||
|
||||
static int sandbox_raise_irq(struct udevice *dev, uint fn,
|
||||
enum pci_ep_irq_type type, uint interrupt_num)
|
||||
{
|
||||
struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
|
||||
|
||||
if (fn > 0)
|
||||
return -ENODEV;
|
||||
|
||||
priv->irq_count++;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sandbox_pci_ep_probe(struct udevice *dev)
|
||||
{
|
||||
struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
|
||||
|
||||
memset(priv, 0, sizeof(*priv));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct pci_ep_ops sandbox_pci_ep_ops = {
|
||||
.write_header = sandbox_write_header,
|
||||
.read_header = sandbox_read_header,
|
||||
.set_bar = sandbox_set_bar,
|
||||
.read_bar = sandbox_read_bar,
|
||||
.set_msi = sandbox_set_msi,
|
||||
.get_msi = sandbox_get_msi,
|
||||
.set_msix = sandbox_set_msix,
|
||||
.get_msix = sandbox_get_msix,
|
||||
.raise_irq = sandbox_raise_irq,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(pci_ep_sandbox) = {
|
||||
.name = "pci_ep_sandbox",
|
||||
.id = UCLASS_PCI_EP,
|
||||
.of_match = sandbox_pci_ep_ids,
|
||||
.probe = sandbox_pci_ep_probe,
|
||||
.ops = &sandbox_pci_ep_ops,
|
||||
.priv_auto_alloc_size = sizeof(struct sandbox_pci_ep_priv),
|
||||
};
|
||||
Reference in New Issue
Block a user