GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/drivers/pinctrl/broadcom/Kconfig

@@ -0,0 +1,15 @@
+config PINCTRL_BCM283X
+	depends on ARCH_BCM283X && PINCTRL_FULL && OF_CONTROL
+	default y
+	bool "Broadcom 283x family pin control driver"
+	help
+	   Support pin multiplexing and pin configuration control on
+	   Broadcom's 283x family of SoCs.
+
+config PINCTRL_BCM6838
+	depends on ARCH_BMIPS && PINCTRL_FULL && OF_CONTROL
+	default y
+	bool "Broadcom 6838 family pin control driver"
+	help
+	   Support pin multiplexing and pin configuration control on
+	   Broadcom's 6838 family of SoCs.

source/bootloader/u-boot-2020.01/drivers/pinctrl/broadcom/Makefile

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2018 Alexander Graf <agraf@suse.de>
+#
+# https://spdx.org/licenses
+
+obj-$(CONFIG_PINCTRL_BCM283X) += pinctrl-bcm283x.o
+obj-$(CONFIG_PINCTRL_BCM6838) += pinctrl-bcm6838.o

source/bootloader/u-boot-2020.01/drivers/pinctrl/broadcom/pinctrl-bcm283x.c

@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Alexander Graf <agraf@suse.de>
+ *
+ * Based on drivers/pinctrl/mvebu/pinctrl-mvebu.c and
+ *          drivers/gpio/bcm2835_gpio.c
+ *
+ * This driver gets instantiated by the GPIO driver, because both devices
+ * share the same device node.
+ * https://spdx.org/licenses
+ */
+
+#include <common.h>
+#include <config.h>
+#include <errno.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+struct bcm283x_pinctrl_priv {
+	u32 *base_reg;
+};
+
+#define MAX_PINS_PER_BANK 16
+
+static void bcm2835_gpio_set_func_id(struct udevice *dev, unsigned int gpio,
+				     int func)
+{
+	struct bcm283x_pinctrl_priv *priv = dev_get_priv(dev);
+	int reg_offset;
+	int field_offset;
+
+	reg_offset = BCM2835_GPIO_FSEL_BANK(gpio);
+	field_offset = BCM2835_GPIO_FSEL_SHIFT(gpio);
+
+	clrsetbits_le32(&priv->base_reg[reg_offset],
+			BCM2835_GPIO_FSEL_MASK << field_offset,
+			(func & BCM2835_GPIO_FSEL_MASK) << field_offset);
+}
+
+static int bcm2835_gpio_get_func_id(struct udevice *dev, unsigned int gpio)
+{
+	struct bcm283x_pinctrl_priv *priv = dev_get_priv(dev);
+	u32 val;
+
+	val = readl(&priv->base_reg[BCM2835_GPIO_FSEL_BANK(gpio)]);
+
+	return (val >> BCM2835_GPIO_FSEL_SHIFT(gpio) & BCM2835_GPIO_FSEL_MASK);
+}
+
+/*
+ * bcm283x_pinctrl_set_state: configure pin functions.
+ * @dev: the pinctrl device to be configured.
+ * @config: the state to be configured.
+ * @return: 0 in success
+ */
+int bcm283x_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+{
+	u32 pin_arr[MAX_PINS_PER_BANK];
+	u32 function;
+	int i, len, pin_count = 0;
+
+	if (!dev_read_prop(config, "brcm,pins", &len) || !len ||
+	    len & 0x3 || dev_read_u32_array(config, "brcm,pins", pin_arr,
+						  len / sizeof(u32))) {
+		debug("Failed reading pins array for pinconfig %s (%d)\n",
+		      config->name, len);
+		return -EINVAL;
+	}
+
+	pin_count = len / sizeof(u32);
+
+	function = dev_read_u32_default(config, "brcm,function", -1);
+	if (function < 0) {
+		debug("Failed reading function for pinconfig %s (%d)\n",
+		      config->name, function);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < pin_count; i++)
+		bcm2835_gpio_set_func_id(dev, pin_arr[i], function);
+
+	return 0;
+}
+
+static int bcm283x_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
+					int index)
+{
+	if (banknum != 0)
+		return -EINVAL;
+
+	return bcm2835_gpio_get_func_id(dev, index);
+}
+
+static const struct udevice_id bcm2835_pinctrl_id[] = {
+	{.compatible = "brcm,bcm2835-gpio"},
+	{.compatible = "brcm,bcm2711-gpio"},
+	{}
+};
+
+int bcm283x_pinctl_probe(struct udevice *dev)
+{
+	struct bcm283x_pinctrl_priv *priv;
+	int ret;
+	struct udevice *pdev;
+
+	priv = dev_get_priv(dev);
+	if (!priv) {
+		debug("%s: Failed to get private\n", __func__);
+		return -EINVAL;
+	}
+
+	priv->base_reg = dev_read_addr_ptr(dev);
+	if (priv->base_reg == (void *)FDT_ADDR_T_NONE) {
+		debug("%s: Failed to get base address\n", __func__);
+		return -EINVAL;
+	}
+
+	/* Create GPIO device as well */
+	ret = device_bind(dev, lists_driver_lookup_name("gpio_bcm2835"),
+			  "gpio_bcm2835", NULL, dev_of_offset(dev), &pdev);
+	if (ret) {
+		/*
+		 * While we really want the pinctrl driver to work to make
+		 * devices go where they should go, the GPIO controller is
+		 * not quite as crucial as it's only rarely used, so don't
+		 * fail here.
+		 */
+		printf("Failed to bind GPIO driver\n");
+	}
+
+	return 0;
+}
+
+static struct pinctrl_ops bcm283x_pinctrl_ops = {
+	.set_state	= bcm283x_pinctrl_set_state,
+	.get_gpio_mux	= bcm283x_pinctrl_get_gpio_mux,
+};
+
+U_BOOT_DRIVER(pinctrl_bcm283x) = {
+	.name		= "bcm283x_pinctrl",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= of_match_ptr(bcm2835_pinctrl_id),
+	.priv_auto_alloc_size = sizeof(struct bcm283x_pinctrl_priv),
+	.ops		= &bcm283x_pinctrl_ops,
+	.probe		= bcm283x_pinctl_probe,
+#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD)
+	.flags		= DM_FLAG_PRE_RELOC,
+#endif
+};

source/bootloader/u-boot-2020.01/drivers/pinctrl/broadcom/pinctrl-bcm6838.c

@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <dm/pinctrl.h>
+
+#define BCM6838_CMD_LOAD_MUX            0x21
+
+#define BCM6838_FUNC_OFFS               12
+#define BCM6838_FUNC_MASK               (0x37 << BCM6838_FUNC_OFFS)
+#define BCM6838_PIN_OFFS                 0
+#define BCM6838_PIN_MASK                (0xfff << BCM6838_PIN_OFFS)
+
+#define BCM6838_MAX_PIN_NAME_LEN         8
+static char bcm6838_pin_name[BCM6838_MAX_PIN_NAME_LEN];
+
+#define BCM6838_MAX_FUNC_NAME_LEN        8
+static char bcm6838_func_name[BCM6838_MAX_FUNC_NAME_LEN];
+
+struct bcm6838_test_port_hw {
+	unsigned long port_blk_data1;
+	unsigned long port_blk_data2;
+	unsigned long port_command;
+};
+
+static const struct bcm6838_test_port_hw bcm6838_hw = {
+	.port_blk_data1 = 0x10,
+	.port_blk_data2 = 0x14,
+	.port_command   = 0x18
+};
+
+struct bcm6838_pinctrl_priv {
+	const struct bcm6838_test_port_hw *hw;
+	struct regmap *regmap;
+	u32 pins_count;
+	u32 functions_count;
+};
+
+int bcm6838_pinctrl_get_pins_count(struct udevice *dev)
+{
+	struct bcm6838_pinctrl_priv *priv = dev_get_priv(dev);
+
+	return priv->pins_count;
+}
+
+const char *bcm6838_pinctrl_get_pin_name(struct udevice *dev,
+					 unsigned int selector)
+{
+	snprintf(bcm6838_pin_name, BCM6838_MAX_PIN_NAME_LEN, "%u", selector);
+	return bcm6838_pin_name;
+}
+
+int bcm6838_pinctrl_get_functions_count(struct udevice *dev)
+{
+	struct bcm6838_pinctrl_priv *priv = dev_get_priv(dev);
+
+	return priv->functions_count;
+}
+
+const char *bcm6838_pinctrl_get_function_name(struct udevice *dev,
+					      unsigned int selector)
+{
+	snprintf(bcm6838_func_name, BCM6838_MAX_FUNC_NAME_LEN, "%u", selector);
+	return bcm6838_func_name;
+}
+
+int bcm6838_pinctrl_pinmux_set(struct udevice *dev,
+			       unsigned int pin_selector,
+			       unsigned int func_selector)
+{
+	struct bcm6838_pinctrl_priv *priv = dev_get_priv(dev);
+	const struct bcm6838_test_port_hw *hw = priv->hw;
+	unsigned int data;
+
+	regmap_write(priv->regmap, hw->port_blk_data1, 0);
+	data = (func_selector << BCM6838_FUNC_OFFS) & BCM6838_FUNC_MASK;
+	data |= (pin_selector << BCM6838_PIN_OFFS) & BCM6838_PIN_MASK;
+	regmap_write(priv->regmap, hw->port_blk_data2, data);
+	regmap_write(priv->regmap, hw->port_command, BCM6838_CMD_LOAD_MUX);
+
+	return 0;
+}
+
+int bcm6838_pinctrl_probe(struct udevice *dev)
+{
+	struct bcm6838_pinctrl_priv *priv = dev_get_priv(dev);
+	const struct bcm6838_test_port_hw *hw =
+		(const struct bcm6838_test_port_hw *)dev_get_driver_data(dev);
+	int err;
+	u32 phandle;
+	ofnode node;
+
+	err = ofnode_read_u32(dev_ofnode(dev), "regmap", &phandle);
+	if (err) {
+		dev_err(dev, "%s: unable to read regmap\n", __func__);
+		goto out;
+	}
+
+	node = ofnode_get_by_phandle(phandle);
+	if (!ofnode_valid(node)) {
+		dev_err(dev, "%s: unable to find node\n", __func__);
+		err = -EINVAL;
+		goto out;
+	}
+
+	priv->regmap = syscon_node_to_regmap(node);
+	if (!priv->regmap) {
+		dev_err(dev, "%s: unable to find regmap\n", __func__);
+		err = -ENODEV;
+		goto out;
+	}
+
+	err = ofnode_read_u32(dev_ofnode(dev), "brcm,pins-count",
+			      &priv->pins_count);
+	if (err) {
+		dev_err(dev, "%s: unable to read brcm,pins-count\n",
+			__func__);
+		goto out;
+	}
+
+	err = ofnode_read_u32(dev_ofnode(dev), "brcm,functions-count",
+			      &priv->functions_count);
+	if (err) {
+		dev_err(dev, "%s: unable to read brcm,functions-count\n",
+			__func__);
+		goto out;
+	}
+
+	priv->hw = hw;
+
+ out:
+	return err;
+}
+
+const struct pinctrl_ops bcm6838_pinctrl_ops = {
+	.set_state = pinctrl_generic_set_state,
+	.get_pins_count = bcm6838_pinctrl_get_pins_count,
+	.get_pin_name = bcm6838_pinctrl_get_pin_name,
+	.get_functions_count = bcm6838_pinctrl_get_functions_count,
+	.get_function_name = bcm6838_pinctrl_get_function_name,
+	.pinmux_set = bcm6838_pinctrl_pinmux_set,
+};
+
+static const struct udevice_id bcm6838_pinctrl_match[] = {
+	{
+		.compatible = "brcm,bcm6838-pinctrl",
+		.data = (ulong)&bcm6838_hw,
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(bcm6838_pinctrl) = {
+	.name = "bcm6838_pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = bcm6838_pinctrl_match,
+	.ops = &bcm6838_pinctrl_ops,
+	.priv_auto_alloc_size = sizeof(struct bcm6838_pinctrl_priv),
+	.probe = bcm6838_pinctrl_probe,
+};