GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,50 @@
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# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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config PINCTRL_MSCC
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bool
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config PINCTRL_MSCC_OCELOT
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depends on SOC_OCELOT && PINCTRL_FULL && OF_CONTROL
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select PINCTRL_MSCC
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default y
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bool "Microsemi ocelot family pin control driver"
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help
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Support pin multiplexing and pin configuration control on
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Microsemi ocelot SoCs.
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config PINCTRL_MSCC_LUTON
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depends on SOC_LUTON && PINCTRL_FULL && OF_CONTROL
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select PINCTRL_MSCC
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default y
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bool "Microsemi luton family pin control driver"
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help
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Support pin multiplexing and pin configuration control on
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Microsemi luton SoCs.
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config PINCTRL_MSCC_JR2
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depends on SOC_JR2 && PINCTRL_FULL && OF_CONTROL
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select PINCTRL_MSCC
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default y
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bool "Microsemi jr2 family pin control driver"
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help
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Support pin multiplexing and pin configuration control on
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Microsemi jr2 SoCs.
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config PINCTRL_MSCC_SERVALT
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depends on SOC_SERVALT && PINCTRL_FULL && OF_CONTROL
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select PINCTRL_MSCC
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default y
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bool "Microsemi servalt family pin control driver"
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help
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Support pin multiplexing and pin configuration control on
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Microsemi servalt SoCs.
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config PINCTRL_MSCC_SERVAL
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depends on SOC_SERVAL && PINCTRL_FULL && OF_CONTROL
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select PINCTRL_MSCC
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default y
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bool "Microsemi serval family pin control driver"
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help
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Support pin multiplexing and pin configuration control on
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Microsemi serval SoCs.
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@@ -0,0 +1,8 @@
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# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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obj-y += mscc-common.o
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obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o
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obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o
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obj-$(CONFIG_PINCTRL_MSCC_JR2) += pinctrl-jr2.o
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obj-$(CONFIG_PINCTRL_MSCC_SERVALT) += pinctrl-servalt.o
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obj-$(CONFIG_PINCTRL_MSCC_SERVAL) += pinctrl-serval.o
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@@ -0,0 +1,274 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Microsemi SoCs pinctrl driver
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*
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* Author: <alexandre.belloni@free-electrons.com>
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* Author: <gregory.clement@bootlin.com>
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* License: Dual MIT/GPL
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* Copyright (c) 2017 Microsemi Corporation
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*/
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#include <asm/gpio.h>
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#include <asm/system.h>
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#include <common.h>
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#include <config.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/pinctrl.h>
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#include <dm/root.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <linux/io.h>
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#include "mscc-common.h"
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static void mscc_writel(unsigned int offset, void *addr)
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{
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if (offset < 32)
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writel(BIT(offset), addr);
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else
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writel(BIT(offset % 32), addr + 4);
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}
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static unsigned int mscc_readl(unsigned int offset, void *addr)
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{
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if (offset < 32)
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return readl(addr);
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else
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return readl(addr + 4);
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}
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static void mscc_setbits(unsigned int offset, void *addr)
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{
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if (offset < 32)
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writel(readl(addr) | BIT(offset), addr);
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else
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writel(readl(addr + 4) | BIT(offset % 32), addr + 4);
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}
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static void mscc_clrbits(unsigned int offset, void *addr)
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{
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if (offset < 32)
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writel(readl(addr) & ~BIT(offset), addr);
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else
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writel(readl(addr + 4) & ~BIT(offset % 32), addr + 4);
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}
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static int mscc_get_functions_count(struct udevice *dev)
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{
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struct mscc_pinctrl *info = dev_get_priv(dev);
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return info->num_func;
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}
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static const char *mscc_get_function_name(struct udevice *dev,
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unsigned int function)
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{
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struct mscc_pinctrl *info = dev_get_priv(dev);
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return info->function_names[function];
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}
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static int mscc_pin_function_idx(unsigned int pin, unsigned int function,
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const struct mscc_pin_data *mscc_pins)
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{
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struct mscc_pin_caps *p = mscc_pins[pin].drv_data;
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int i;
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for (i = 0; i < MSCC_FUNC_PER_PIN; i++) {
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if (function == p->functions[i])
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return i;
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}
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return -1;
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}
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static int mscc_pinmux_set_mux(struct udevice *dev,
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unsigned int pin_selector, unsigned int selector)
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{
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struct mscc_pinctrl *info = dev_get_priv(dev);
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struct mscc_pin_caps *pin = info->mscc_pins[pin_selector].drv_data;
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int f, offset, regoff;
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f = mscc_pin_function_idx(pin_selector, selector, info->mscc_pins);
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if (f < 0)
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return -EINVAL;
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/*
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* f is encoded on two bits.
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* bit 0 of f goes in BIT(pin) of ALT0, bit 1 of f goes in BIT(pin) of
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* ALT1
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* This is racy because both registers can't be updated at the same time
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* but it doesn't matter much for now.
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*/
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offset = pin->pin;
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regoff = info->mscc_gpios[MSCC_GPIO_ALT0];
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if (offset >= 32) {
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offset = offset % 32;
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regoff = info->mscc_gpios[MSCC_GPIO_ALT1];
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}
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if (f & BIT(0))
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mscc_setbits(offset, info->regs + regoff);
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else
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mscc_clrbits(offset, info->regs + regoff);
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if (f & BIT(1))
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mscc_setbits(offset, info->regs + regoff + 4);
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else
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mscc_clrbits(offset, info->regs + regoff + 4);
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return 0;
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}
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static int mscc_pctl_get_groups_count(struct udevice *dev)
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{
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struct mscc_pinctrl *info = dev_get_priv(dev);
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return info->num_pins;
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}
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static const char *mscc_pctl_get_group_name(struct udevice *dev,
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unsigned int group)
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{
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struct mscc_pinctrl *info = dev_get_priv(dev);
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return info->mscc_pins[group].name;
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}
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static int mscc_create_group_func_map(struct udevice *dev,
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struct mscc_pinctrl *info)
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{
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u16 pins[info->num_pins];
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int f, npins, i;
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for (f = 0; f < info->num_func; f++) {
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for (npins = 0, i = 0; i < info->num_pins; i++) {
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if (mscc_pin_function_idx(i, f, info->mscc_pins) >= 0)
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pins[npins++] = i;
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}
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info->func[f].ngroups = npins;
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info->func[f].groups = devm_kzalloc(dev, npins * sizeof(char *),
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GFP_KERNEL);
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if (!info->func[f].groups)
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return -ENOMEM;
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for (i = 0; i < npins; i++)
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info->func[f].groups[i] = info->mscc_pins[pins[i]].name;
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}
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return 0;
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}
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static int mscc_pinctrl_register(struct udevice *dev, struct mscc_pinctrl *info)
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{
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int ret;
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ret = mscc_create_group_func_map(dev, info);
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if (ret) {
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dev_err(dev, "Unable to create group func map.\n");
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return ret;
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}
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return 0;
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}
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static int mscc_gpio_get(struct udevice *dev, unsigned int offset)
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{
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struct mscc_pinctrl *info = dev_get_priv(dev->parent);
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unsigned int val;
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if (mscc_readl(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]) &
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BIT(offset % 32))
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val = mscc_readl(offset,
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info->regs + info->mscc_gpios[MSCC_GPIO_OUT]);
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else
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val = mscc_readl(offset,
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info->regs + info->mscc_gpios[MSCC_GPIO_IN]);
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return !!(val & BIT(offset % 32));
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}
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static int mscc_gpio_set(struct udevice *dev, unsigned int offset, int value)
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{
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struct mscc_pinctrl *info = dev_get_priv(dev->parent);
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if (value)
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mscc_writel(offset,
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info->regs + info->mscc_gpios[MSCC_GPIO_OUT_SET]);
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else
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mscc_writel(offset,
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info->regs + info->mscc_gpios[MSCC_GPIO_OUT_CLR]);
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return 0;
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}
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static int mscc_gpio_get_direction(struct udevice *dev, unsigned int offset)
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{
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struct mscc_pinctrl *info = dev_get_priv(dev->parent);
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unsigned int val;
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val = mscc_readl(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
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return (val & BIT(offset % 32)) ? GPIOF_OUTPUT : GPIOF_INPUT;
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}
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static int mscc_gpio_direction_input(struct udevice *dev, unsigned int offset)
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{
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struct mscc_pinctrl *info = dev_get_priv(dev->parent);
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mscc_clrbits(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
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return 0;
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}
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static int mscc_gpio_direction_output(struct udevice *dev,
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unsigned int offset, int value)
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{
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struct mscc_pinctrl *info = dev_get_priv(dev->parent);
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mscc_setbits(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
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return mscc_gpio_set(dev, offset, value);
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}
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const struct dm_gpio_ops mscc_gpio_ops = {
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.set_value = mscc_gpio_set,
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.get_value = mscc_gpio_get,
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.get_function = mscc_gpio_get_direction,
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.direction_input = mscc_gpio_direction_input,
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.direction_output = mscc_gpio_direction_output,
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};
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const struct pinctrl_ops mscc_pinctrl_ops = {
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.get_pins_count = mscc_pctl_get_groups_count,
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.get_pin_name = mscc_pctl_get_group_name,
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.get_functions_count = mscc_get_functions_count,
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.get_function_name = mscc_get_function_name,
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.pinmux_set = mscc_pinmux_set_mux,
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.set_state = pinctrl_generic_set_state,
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};
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int mscc_pinctrl_probe(struct udevice *dev, int num_func,
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const struct mscc_pin_data *mscc_pins, int num_pins,
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char * const *function_names,
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const unsigned long *mscc_gpios)
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{
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struct mscc_pinctrl *priv = dev_get_priv(dev);
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int ret;
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priv->regs = dev_remap_addr(dev);
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if (!priv->regs)
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return -EINVAL;
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priv->func = devm_kzalloc(dev, num_func * sizeof(struct mscc_pmx_func),
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GFP_KERNEL);
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priv->num_func = num_func;
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priv->mscc_pins = mscc_pins;
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priv->num_pins = num_pins;
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priv->function_names = function_names;
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priv->mscc_gpios = mscc_gpios;
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ret = mscc_pinctrl_register(dev, priv);
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return ret;
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}
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@@ -0,0 +1,66 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Microsemi SoCs pinctrl driver
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*
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* Author: <alexandre.belloni@free-electrons.com>
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* License: Dual MIT/GPL
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* Copyright (c) 2017 Microsemi Corporation
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*/
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#define MSCC_FUNC_PER_PIN 4
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enum mscc_regs_gpio {
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MSCC_GPIO_OUT_SET,
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MSCC_GPIO_OUT_CLR,
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MSCC_GPIO_OUT,
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MSCC_GPIO_IN,
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MSCC_GPIO_OE,
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MSCC_GPIO_INTR,
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MSCC_GPIO_INTR_ENA,
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MSCC_GPIO_INTR_IDENT,
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MSCC_GPIO_ALT0,
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MSCC_GPIO_ALT1,
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};
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struct mscc_pin_caps {
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unsigned int pin;
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unsigned char functions[MSCC_FUNC_PER_PIN];
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};
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struct mscc_pin_data {
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const char *name;
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struct mscc_pin_caps *drv_data;
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};
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#define MSCC_P(p, f0, f1, f2) \
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static struct mscc_pin_caps mscc_pin_##p = { \
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.pin = p, \
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.functions = { \
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FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
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}, \
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}
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struct mscc_pmx_func {
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const char **groups;
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unsigned int ngroups;
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};
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struct mscc_pinctrl {
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struct udevice *dev;
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struct pinctrl_dev *pctl;
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void __iomem *regs;
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struct mscc_pmx_func *func;
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int num_func;
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const struct mscc_pin_data *mscc_pins;
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int num_pins;
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char * const *function_names;
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const unsigned long *mscc_gpios;
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};
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int mscc_pinctrl_probe(struct udevice *dev, int num_func,
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const struct mscc_pin_data *mscc_pins, int num_pins,
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char * const *function_names,
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const unsigned long *mscc_gpios);
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const struct pinctrl_ops mscc_pinctrl_ops;
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const struct dm_gpio_ops mscc_gpio_ops;
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@@ -0,0 +1,323 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
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/*
|
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* Microsemi SoCs pinctrl driver
|
||||
*
|
||||
* Author: <horatiu.vultur@microchip.com>
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
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*/
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|
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#include <common.h>
|
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#include <config.h>
|
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#include <dm.h>
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#include <dm/device-internal.h>
|
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#include <dm/lists.h>
|
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#include <dm/pinctrl.h>
|
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#include <dm/root.h>
|
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#include <errno.h>
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#include <fdtdec.h>
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#include <linux/io.h>
|
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#include <asm/gpio.h>
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#include <asm/system.h>
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#include "mscc-common.h"
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enum {
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FUNC_NONE,
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FUNC_GPIO,
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FUNC_IRQ0_IN,
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FUNC_IRQ0_OUT,
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FUNC_IRQ1_IN,
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FUNC_IRQ1_OUT,
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FUNC_MIIM1,
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FUNC_MIIM2,
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FUNC_PCI_WAKE,
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FUNC_PTP0,
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FUNC_PTP1,
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FUNC_PTP2,
|
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FUNC_PTP3,
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FUNC_PWM,
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FUNC_RECO_CLK0,
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FUNC_RECO_CLK1,
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FUNC_SFP0,
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FUNC_SFP1,
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FUNC_SFP2,
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FUNC_SFP3,
|
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FUNC_SFP4,
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FUNC_SFP5,
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FUNC_SFP6,
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FUNC_SFP7,
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FUNC_SFP8,
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FUNC_SFP9,
|
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FUNC_SFP10,
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FUNC_SFP11,
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FUNC_SFP12,
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FUNC_SFP13,
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FUNC_SFP14,
|
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FUNC_SFP15,
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FUNC_SG0,
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FUNC_SG1,
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FUNC_SG2,
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FUNC_SI,
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FUNC_TACHO,
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FUNC_TWI,
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FUNC_TWI2,
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FUNC_TWI_SCL_M,
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FUNC_UART,
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FUNC_UART2,
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FUNC_MAX
|
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};
|
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static char * const jr2_function_names[] = {
|
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[FUNC_NONE] = "none",
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[FUNC_GPIO] = "gpio",
|
||||
[FUNC_IRQ0_IN] = "irq0_in",
|
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[FUNC_IRQ0_OUT] = "irq0_out",
|
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[FUNC_IRQ1_IN] = "irq1_in",
|
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[FUNC_IRQ1_OUT] = "irq1_out",
|
||||
[FUNC_MIIM1] = "miim1",
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||||
[FUNC_MIIM2] = "miim2",
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[FUNC_PCI_WAKE] = "pci_wake",
|
||||
[FUNC_PTP0] = "ptp0",
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||||
[FUNC_PTP1] = "ptp1",
|
||||
[FUNC_PTP2] = "ptp2",
|
||||
[FUNC_PTP3] = "ptp3",
|
||||
[FUNC_PWM] = "pwm",
|
||||
[FUNC_RECO_CLK0] = "reco_clk0",
|
||||
[FUNC_RECO_CLK1] = "reco_clk1",
|
||||
[FUNC_SFP0] = "sfp0",
|
||||
[FUNC_SFP1] = "sfp1",
|
||||
[FUNC_SFP2] = "sfp2",
|
||||
[FUNC_SFP3] = "sfp3",
|
||||
[FUNC_SFP4] = "sfp4",
|
||||
[FUNC_SFP5] = "sfp5",
|
||||
[FUNC_SFP6] = "sfp6",
|
||||
[FUNC_SFP7] = "sfp7",
|
||||
[FUNC_SFP8] = "sfp8",
|
||||
[FUNC_SFP9] = "sfp9",
|
||||
[FUNC_SFP10] = "sfp10",
|
||||
[FUNC_SFP11] = "sfp11",
|
||||
[FUNC_SFP12] = "sfp12",
|
||||
[FUNC_SFP13] = "sfp13",
|
||||
[FUNC_SFP14] = "sfp14",
|
||||
[FUNC_SFP15] = "sfp15",
|
||||
[FUNC_SG0] = "sg0",
|
||||
[FUNC_SG1] = "sg1",
|
||||
[FUNC_SG2] = "sg2",
|
||||
[FUNC_SI] = "si",
|
||||
[FUNC_TACHO] = "tacho",
|
||||
[FUNC_TWI] = "twi",
|
||||
[FUNC_TWI2] = "twi2",
|
||||
[FUNC_TWI_SCL_M] = "twi_scl_m",
|
||||
[FUNC_UART] = "uart",
|
||||
[FUNC_UART2] = "uart2",
|
||||
};
|
||||
|
||||
#define JR2_P(p, f0, f1) \
|
||||
static struct mscc_pin_caps jr2_pin_##p = { \
|
||||
.pin = p, \
|
||||
.functions = { \
|
||||
FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \
|
||||
}, \
|
||||
}
|
||||
|
||||
JR2_P(0, SG0, NONE);
|
||||
JR2_P(1, SG0, NONE);
|
||||
JR2_P(2, SG0, NONE);
|
||||
JR2_P(3, SG0, NONE);
|
||||
JR2_P(4, SG1, NONE);
|
||||
JR2_P(5, SG1, NONE);
|
||||
JR2_P(6, IRQ0_IN, IRQ0_OUT);
|
||||
JR2_P(7, IRQ1_IN, IRQ1_OUT);
|
||||
JR2_P(8, PTP0, NONE);
|
||||
JR2_P(9, PTP1, NONE);
|
||||
JR2_P(10, UART, NONE);
|
||||
JR2_P(11, UART, NONE);
|
||||
JR2_P(12, SG1, NONE);
|
||||
JR2_P(13, SG1, NONE);
|
||||
JR2_P(14, TWI, TWI_SCL_M);
|
||||
JR2_P(15, TWI, NONE);
|
||||
JR2_P(16, SI, TWI_SCL_M);
|
||||
JR2_P(17, SI, TWI_SCL_M);
|
||||
JR2_P(18, SI, TWI_SCL_M);
|
||||
JR2_P(19, PCI_WAKE, NONE);
|
||||
JR2_P(20, IRQ0_OUT, TWI_SCL_M);
|
||||
JR2_P(21, IRQ1_OUT, TWI_SCL_M);
|
||||
JR2_P(22, TACHO, NONE);
|
||||
JR2_P(23, PWM, NONE);
|
||||
JR2_P(24, UART2, NONE);
|
||||
JR2_P(25, UART2, SI);
|
||||
JR2_P(26, PTP2, SI);
|
||||
JR2_P(27, PTP3, SI);
|
||||
JR2_P(28, TWI2, SI);
|
||||
JR2_P(29, TWI, SI);
|
||||
JR2_P(30, SG2, SI);
|
||||
JR2_P(31, SG2, SI);
|
||||
JR2_P(32, SG2, SI);
|
||||
JR2_P(33, SG2, SI);
|
||||
JR2_P(34, NONE, TWI_SCL_M);
|
||||
JR2_P(35, NONE, TWI_SCL_M);
|
||||
JR2_P(36, NONE, TWI_SCL_M);
|
||||
JR2_P(37, NONE, TWI_SCL_M);
|
||||
JR2_P(38, NONE, TWI_SCL_M);
|
||||
JR2_P(39, NONE, TWI_SCL_M);
|
||||
JR2_P(40, NONE, TWI_SCL_M);
|
||||
JR2_P(41, NONE, TWI_SCL_M);
|
||||
JR2_P(42, NONE, TWI_SCL_M);
|
||||
JR2_P(43, NONE, TWI_SCL_M);
|
||||
JR2_P(44, NONE, SFP8);
|
||||
JR2_P(45, NONE, SFP9);
|
||||
JR2_P(46, NONE, SFP10);
|
||||
JR2_P(47, NONE, SFP11);
|
||||
JR2_P(48, SFP0, NONE);
|
||||
JR2_P(49, SFP1, SI);
|
||||
JR2_P(50, SFP2, SI);
|
||||
JR2_P(51, SFP3, SI);
|
||||
JR2_P(52, SFP4, NONE);
|
||||
JR2_P(53, SFP5, NONE);
|
||||
JR2_P(54, SFP6, NONE);
|
||||
JR2_P(55, SFP7, NONE);
|
||||
JR2_P(56, MIIM1, SFP12);
|
||||
JR2_P(57, MIIM1, SFP13);
|
||||
JR2_P(58, MIIM2, SFP14);
|
||||
JR2_P(59, MIIM2, SFP15);
|
||||
JR2_P(60, NONE, NONE);
|
||||
JR2_P(61, NONE, NONE);
|
||||
JR2_P(62, NONE, NONE);
|
||||
JR2_P(63, NONE, NONE);
|
||||
|
||||
#define JR2_PIN(n) { \
|
||||
.name = "GPIO_"#n, \
|
||||
.drv_data = &jr2_pin_##n \
|
||||
}
|
||||
|
||||
static const struct mscc_pin_data jr2_pins[] = {
|
||||
JR2_PIN(0),
|
||||
JR2_PIN(1),
|
||||
JR2_PIN(2),
|
||||
JR2_PIN(3),
|
||||
JR2_PIN(4),
|
||||
JR2_PIN(5),
|
||||
JR2_PIN(6),
|
||||
JR2_PIN(7),
|
||||
JR2_PIN(8),
|
||||
JR2_PIN(9),
|
||||
JR2_PIN(10),
|
||||
JR2_PIN(11),
|
||||
JR2_PIN(12),
|
||||
JR2_PIN(13),
|
||||
JR2_PIN(14),
|
||||
JR2_PIN(15),
|
||||
JR2_PIN(16),
|
||||
JR2_PIN(17),
|
||||
JR2_PIN(18),
|
||||
JR2_PIN(19),
|
||||
JR2_PIN(20),
|
||||
JR2_PIN(21),
|
||||
JR2_PIN(22),
|
||||
JR2_PIN(23),
|
||||
JR2_PIN(24),
|
||||
JR2_PIN(25),
|
||||
JR2_PIN(26),
|
||||
JR2_PIN(27),
|
||||
JR2_PIN(28),
|
||||
JR2_PIN(29),
|
||||
JR2_PIN(30),
|
||||
JR2_PIN(31),
|
||||
JR2_PIN(32),
|
||||
JR2_PIN(33),
|
||||
JR2_PIN(34),
|
||||
JR2_PIN(35),
|
||||
JR2_PIN(36),
|
||||
JR2_PIN(37),
|
||||
JR2_PIN(38),
|
||||
JR2_PIN(39),
|
||||
JR2_PIN(40),
|
||||
JR2_PIN(41),
|
||||
JR2_PIN(42),
|
||||
JR2_PIN(43),
|
||||
JR2_PIN(44),
|
||||
JR2_PIN(45),
|
||||
JR2_PIN(46),
|
||||
JR2_PIN(47),
|
||||
JR2_PIN(48),
|
||||
JR2_PIN(49),
|
||||
JR2_PIN(50),
|
||||
JR2_PIN(51),
|
||||
JR2_PIN(52),
|
||||
JR2_PIN(53),
|
||||
JR2_PIN(54),
|
||||
JR2_PIN(55),
|
||||
JR2_PIN(56),
|
||||
JR2_PIN(57),
|
||||
JR2_PIN(58),
|
||||
JR2_PIN(59),
|
||||
JR2_PIN(60),
|
||||
JR2_PIN(61),
|
||||
JR2_PIN(62),
|
||||
JR2_PIN(63),
|
||||
};
|
||||
|
||||
static const unsigned long jr2_gpios[] = {
|
||||
[MSCC_GPIO_OUT_SET] = 0x00,
|
||||
[MSCC_GPIO_OUT_CLR] = 0x08,
|
||||
[MSCC_GPIO_OUT] = 0x10,
|
||||
[MSCC_GPIO_IN] = 0x18,
|
||||
[MSCC_GPIO_OE] = 0x20,
|
||||
[MSCC_GPIO_INTR] = 0x28,
|
||||
[MSCC_GPIO_INTR_ENA] = 0x30,
|
||||
[MSCC_GPIO_INTR_IDENT] = 0x38,
|
||||
[MSCC_GPIO_ALT0] = 0x40,
|
||||
[MSCC_GPIO_ALT1] = 0x48,
|
||||
};
|
||||
|
||||
static int jr2_gpio_probe(struct udevice *dev)
|
||||
{
|
||||
struct gpio_dev_priv *uc_priv;
|
||||
|
||||
uc_priv = dev_get_uclass_priv(dev);
|
||||
uc_priv->bank_name = "jr2-gpio";
|
||||
uc_priv->gpio_count = ARRAY_SIZE(jr2_pins);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct driver jr2_gpio_driver = {
|
||||
.name = "jr2-gpio",
|
||||
.id = UCLASS_GPIO,
|
||||
.probe = jr2_gpio_probe,
|
||||
.ops = &mscc_gpio_ops,
|
||||
};
|
||||
|
||||
static int jr2_pinctrl_probe(struct udevice *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = mscc_pinctrl_probe(dev, FUNC_MAX, jr2_pins,
|
||||
ARRAY_SIZE(jr2_pins),
|
||||
jr2_function_names,
|
||||
jr2_gpios);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = device_bind(dev, &jr2_gpio_driver, "jr2-gpio", NULL,
|
||||
dev_of_offset(dev), NULL);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id jr2_pinctrl_of_match[] = {
|
||||
{ .compatible = "mscc,jaguar2-pinctrl" },
|
||||
{},
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(jr2_pinctrl) = {
|
||||
.name = "jr2-pinctrl",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = of_match_ptr(jr2_pinctrl_of_match),
|
||||
.probe = jr2_pinctrl_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
|
||||
.ops = &mscc_pinctrl_ops,
|
||||
};
|
||||
@@ -0,0 +1,186 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Microsemi SoCs pinctrl driver
|
||||
*
|
||||
* Author: <gregory.clement@bootlin.com>
|
||||
* License: Dual MIT/GPL
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <dm.h>
|
||||
#include <dm/device-internal.h>
|
||||
#include <dm/lists.h>
|
||||
#include <dm/pinctrl.h>
|
||||
#include <dm/root.h>
|
||||
#include <errno.h>
|
||||
#include <fdtdec.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/system.h>
|
||||
#include "mscc-common.h"
|
||||
|
||||
enum {
|
||||
FUNC_NONE,
|
||||
FUNC_GPIO,
|
||||
FUNC_SIO,
|
||||
FUNC_TACHO,
|
||||
FUNC_TWI,
|
||||
FUNC_PHY_LED,
|
||||
FUNC_EXT_IRQ,
|
||||
FUNC_SFP,
|
||||
FUNC_SI,
|
||||
FUNC_PWM,
|
||||
FUNC_UART,
|
||||
FUNC_MAX
|
||||
};
|
||||
|
||||
static char * const luton_function_names[] = {
|
||||
[FUNC_NONE] = "none",
|
||||
[FUNC_GPIO] = "gpio",
|
||||
[FUNC_SIO] = "sio",
|
||||
[FUNC_TACHO] = "tacho",
|
||||
[FUNC_TWI] = "twi",
|
||||
[FUNC_PHY_LED] = "phy_led",
|
||||
[FUNC_EXT_IRQ] = "ext_irq",
|
||||
[FUNC_SFP] = "sfp",
|
||||
[FUNC_SI] = "si",
|
||||
[FUNC_PWM] = "pwm",
|
||||
[FUNC_UART] = "uart",
|
||||
};
|
||||
|
||||
MSCC_P(0, SIO, NONE, NONE);
|
||||
MSCC_P(1, SIO, NONE, NONE);
|
||||
MSCC_P(2, SIO, NONE, NONE);
|
||||
MSCC_P(3, SIO, NONE, NONE);
|
||||
MSCC_P(4, TACHO, NONE, NONE);
|
||||
MSCC_P(5, TWI, PHY_LED, NONE);
|
||||
MSCC_P(6, TWI, PHY_LED, NONE);
|
||||
MSCC_P(7, NONE, PHY_LED, NONE);
|
||||
MSCC_P(8, EXT_IRQ, PHY_LED, NONE);
|
||||
MSCC_P(9, EXT_IRQ, PHY_LED, NONE);
|
||||
MSCC_P(10, SFP, PHY_LED, NONE);
|
||||
MSCC_P(11, SFP, PHY_LED, NONE);
|
||||
MSCC_P(12, SFP, PHY_LED, NONE);
|
||||
MSCC_P(13, SFP, PHY_LED, NONE);
|
||||
MSCC_P(14, SI, PHY_LED, NONE);
|
||||
MSCC_P(15, SI, PHY_LED, NONE);
|
||||
MSCC_P(16, SI, PHY_LED, NONE);
|
||||
MSCC_P(17, SFP, PHY_LED, NONE);
|
||||
MSCC_P(18, SFP, PHY_LED, NONE);
|
||||
MSCC_P(19, SFP, PHY_LED, NONE);
|
||||
MSCC_P(20, SFP, PHY_LED, NONE);
|
||||
MSCC_P(21, SFP, PHY_LED, NONE);
|
||||
MSCC_P(22, SFP, PHY_LED, NONE);
|
||||
MSCC_P(23, SFP, PHY_LED, NONE);
|
||||
MSCC_P(24, SFP, PHY_LED, NONE);
|
||||
MSCC_P(25, SFP, PHY_LED, NONE);
|
||||
MSCC_P(26, SFP, PHY_LED, NONE);
|
||||
MSCC_P(27, SFP, PHY_LED, NONE);
|
||||
MSCC_P(28, SFP, PHY_LED, NONE);
|
||||
MSCC_P(29, PWM, NONE, NONE);
|
||||
MSCC_P(30, UART, NONE, NONE);
|
||||
MSCC_P(31, UART, NONE, NONE);
|
||||
|
||||
#define LUTON_PIN(n) { \
|
||||
.name = "GPIO_"#n, \
|
||||
.drv_data = &mscc_pin_##n \
|
||||
}
|
||||
|
||||
static const struct mscc_pin_data luton_pins[] = {
|
||||
LUTON_PIN(0),
|
||||
LUTON_PIN(1),
|
||||
LUTON_PIN(2),
|
||||
LUTON_PIN(3),
|
||||
LUTON_PIN(4),
|
||||
LUTON_PIN(5),
|
||||
LUTON_PIN(6),
|
||||
LUTON_PIN(7),
|
||||
LUTON_PIN(8),
|
||||
LUTON_PIN(9),
|
||||
LUTON_PIN(10),
|
||||
LUTON_PIN(11),
|
||||
LUTON_PIN(12),
|
||||
LUTON_PIN(13),
|
||||
LUTON_PIN(14),
|
||||
LUTON_PIN(15),
|
||||
LUTON_PIN(16),
|
||||
LUTON_PIN(17),
|
||||
LUTON_PIN(18),
|
||||
LUTON_PIN(19),
|
||||
LUTON_PIN(20),
|
||||
LUTON_PIN(21),
|
||||
LUTON_PIN(22),
|
||||
LUTON_PIN(23),
|
||||
LUTON_PIN(24),
|
||||
LUTON_PIN(25),
|
||||
LUTON_PIN(26),
|
||||
LUTON_PIN(27),
|
||||
LUTON_PIN(28),
|
||||
LUTON_PIN(29),
|
||||
LUTON_PIN(30),
|
||||
LUTON_PIN(31),
|
||||
};
|
||||
|
||||
static const unsigned long luton_gpios[] = {
|
||||
[MSCC_GPIO_OUT_SET] = 0x00,
|
||||
[MSCC_GPIO_OUT_CLR] = 0x04,
|
||||
[MSCC_GPIO_OUT] = 0x08,
|
||||
[MSCC_GPIO_IN] = 0x0c,
|
||||
[MSCC_GPIO_OE] = 0x10,
|
||||
[MSCC_GPIO_INTR] = 0x14,
|
||||
[MSCC_GPIO_INTR_ENA] = 0x18,
|
||||
[MSCC_GPIO_INTR_IDENT] = 0x1c,
|
||||
[MSCC_GPIO_ALT0] = 0x20,
|
||||
[MSCC_GPIO_ALT1] = 0x24,
|
||||
};
|
||||
|
||||
static int luton_gpio_probe(struct udevice *dev)
|
||||
{
|
||||
struct gpio_dev_priv *uc_priv;
|
||||
|
||||
uc_priv = dev_get_uclass_priv(dev);
|
||||
uc_priv->bank_name = "luton-gpio";
|
||||
uc_priv->gpio_count = ARRAY_SIZE(luton_pins);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct driver luton_gpio_driver = {
|
||||
.name = "luton-gpio",
|
||||
.id = UCLASS_GPIO,
|
||||
.probe = luton_gpio_probe,
|
||||
.ops = &mscc_gpio_ops,
|
||||
};
|
||||
|
||||
int luton_pinctrl_probe(struct udevice *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = mscc_pinctrl_probe(dev, FUNC_MAX, luton_pins,
|
||||
ARRAY_SIZE(luton_pins), luton_function_names,
|
||||
luton_gpios);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = device_bind(dev, &luton_gpio_driver, "luton-gpio", NULL,
|
||||
dev_of_offset(dev), NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id luton_pinctrl_of_match[] = {
|
||||
{.compatible = "mscc,luton-pinctrl"},
|
||||
{},
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(luton_pinctrl) = {
|
||||
.name = "luton-pinctrl",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = of_match_ptr(luton_pinctrl_of_match),
|
||||
.probe = luton_pinctrl_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
|
||||
.ops = &mscc_pinctrl_ops,
|
||||
};
|
||||
@@ -0,0 +1,202 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Microsemi SoCs pinctrl driver
|
||||
*
|
||||
* Author: <alexandre.belloni@free-electrons.com>
|
||||
* Author: <gregory.clement@bootlin.com>
|
||||
* License: Dual MIT/GPL
|
||||
* Copyright (c) 2017 Microsemi Corporation
|
||||
*/
|
||||
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/system.h>
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <dm.h>
|
||||
#include <dm/device-internal.h>
|
||||
#include <dm/lists.h>
|
||||
#include <dm/pinctrl.h>
|
||||
#include <dm/root.h>
|
||||
#include <errno.h>
|
||||
#include <fdtdec.h>
|
||||
#include <linux/io.h>
|
||||
#include "mscc-common.h"
|
||||
|
||||
enum {
|
||||
FUNC_NONE,
|
||||
FUNC_GPIO,
|
||||
FUNC_IRQ0_IN,
|
||||
FUNC_IRQ0_OUT,
|
||||
FUNC_IRQ1_IN,
|
||||
FUNC_IRQ1_OUT,
|
||||
FUNC_MIIM1,
|
||||
FUNC_PCI_WAKE,
|
||||
FUNC_PTP0,
|
||||
FUNC_PTP1,
|
||||
FUNC_PTP2,
|
||||
FUNC_PTP3,
|
||||
FUNC_PWM,
|
||||
FUNC_RECO_CLK0,
|
||||
FUNC_RECO_CLK1,
|
||||
FUNC_SFP0,
|
||||
FUNC_SFP1,
|
||||
FUNC_SFP2,
|
||||
FUNC_SFP3,
|
||||
FUNC_SFP4,
|
||||
FUNC_SFP5,
|
||||
FUNC_SG0,
|
||||
FUNC_SI,
|
||||
FUNC_TACHO,
|
||||
FUNC_TWI,
|
||||
FUNC_TWI_SCL_M,
|
||||
FUNC_UART,
|
||||
FUNC_UART2,
|
||||
FUNC_MAX
|
||||
};
|
||||
|
||||
static char * const ocelot_function_names[] = {
|
||||
[FUNC_NONE] = "none",
|
||||
[FUNC_GPIO] = "gpio",
|
||||
[FUNC_IRQ0_IN] = "irq0_in",
|
||||
[FUNC_IRQ0_OUT] = "irq0_out",
|
||||
[FUNC_IRQ1_IN] = "irq1_in",
|
||||
[FUNC_IRQ1_OUT] = "irq1_out",
|
||||
[FUNC_MIIM1] = "miim1",
|
||||
[FUNC_PCI_WAKE] = "pci_wake",
|
||||
[FUNC_PTP0] = "ptp0",
|
||||
[FUNC_PTP1] = "ptp1",
|
||||
[FUNC_PTP2] = "ptp2",
|
||||
[FUNC_PTP3] = "ptp3",
|
||||
[FUNC_PWM] = "pwm",
|
||||
[FUNC_RECO_CLK0] = "reco_clk0",
|
||||
[FUNC_RECO_CLK1] = "reco_clk1",
|
||||
[FUNC_SFP0] = "sfp0",
|
||||
[FUNC_SFP1] = "sfp1",
|
||||
[FUNC_SFP2] = "sfp2",
|
||||
[FUNC_SFP3] = "sfp3",
|
||||
[FUNC_SFP4] = "sfp4",
|
||||
[FUNC_SFP5] = "sfp5",
|
||||
[FUNC_SG0] = "sg0",
|
||||
[FUNC_SI] = "si",
|
||||
[FUNC_TACHO] = "tacho",
|
||||
[FUNC_TWI] = "twi",
|
||||
[FUNC_TWI_SCL_M] = "twi_scl_m",
|
||||
[FUNC_UART] = "uart",
|
||||
[FUNC_UART2] = "uart2",
|
||||
};
|
||||
|
||||
MSCC_P(0, SG0, NONE, NONE);
|
||||
MSCC_P(1, SG0, NONE, NONE);
|
||||
MSCC_P(2, SG0, NONE, NONE);
|
||||
MSCC_P(3, SG0, NONE, NONE);
|
||||
MSCC_P(4, IRQ0_IN, IRQ0_OUT, TWI);
|
||||
MSCC_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
|
||||
MSCC_P(6, UART, TWI_SCL_M, NONE);
|
||||
MSCC_P(7, UART, TWI_SCL_M, NONE);
|
||||
MSCC_P(8, SI, TWI_SCL_M, IRQ0_OUT);
|
||||
MSCC_P(9, SI, TWI_SCL_M, IRQ1_OUT);
|
||||
MSCC_P(10, PTP2, TWI_SCL_M, SFP0);
|
||||
MSCC_P(11, PTP3, TWI_SCL_M, SFP1);
|
||||
MSCC_P(12, UART2, TWI_SCL_M, SFP2);
|
||||
MSCC_P(13, UART2, TWI_SCL_M, SFP3);
|
||||
MSCC_P(14, MIIM1, TWI_SCL_M, SFP4);
|
||||
MSCC_P(15, MIIM1, TWI_SCL_M, SFP5);
|
||||
MSCC_P(16, TWI, NONE, SI);
|
||||
MSCC_P(17, TWI, TWI_SCL_M, SI);
|
||||
MSCC_P(18, PTP0, TWI_SCL_M, NONE);
|
||||
MSCC_P(19, PTP1, TWI_SCL_M, NONE);
|
||||
MSCC_P(20, RECO_CLK0, TACHO, NONE);
|
||||
MSCC_P(21, RECO_CLK1, PWM, NONE);
|
||||
|
||||
#define OCELOT_PIN(n) { \
|
||||
.name = "GPIO_"#n, \
|
||||
.drv_data = &mscc_pin_##n \
|
||||
}
|
||||
|
||||
static const struct mscc_pin_data ocelot_pins[] = {
|
||||
OCELOT_PIN(0),
|
||||
OCELOT_PIN(1),
|
||||
OCELOT_PIN(2),
|
||||
OCELOT_PIN(3),
|
||||
OCELOT_PIN(4),
|
||||
OCELOT_PIN(5),
|
||||
OCELOT_PIN(6),
|
||||
OCELOT_PIN(7),
|
||||
OCELOT_PIN(8),
|
||||
OCELOT_PIN(9),
|
||||
OCELOT_PIN(10),
|
||||
OCELOT_PIN(11),
|
||||
OCELOT_PIN(12),
|
||||
OCELOT_PIN(13),
|
||||
OCELOT_PIN(14),
|
||||
OCELOT_PIN(15),
|
||||
OCELOT_PIN(16),
|
||||
OCELOT_PIN(17),
|
||||
OCELOT_PIN(18),
|
||||
OCELOT_PIN(19),
|
||||
OCELOT_PIN(20),
|
||||
OCELOT_PIN(21),
|
||||
};
|
||||
|
||||
static const unsigned long ocelot_gpios[] = {
|
||||
[MSCC_GPIO_OUT_SET] = 0x00,
|
||||
[MSCC_GPIO_OUT_CLR] = 0x04,
|
||||
[MSCC_GPIO_OUT] = 0x08,
|
||||
[MSCC_GPIO_IN] = 0x0c,
|
||||
[MSCC_GPIO_OE] = 0x10,
|
||||
[MSCC_GPIO_INTR] = 0x14,
|
||||
[MSCC_GPIO_INTR_ENA] = 0x18,
|
||||
[MSCC_GPIO_INTR_IDENT] = 0x1c,
|
||||
[MSCC_GPIO_ALT0] = 0x20,
|
||||
[MSCC_GPIO_ALT1] = 0x24,
|
||||
};
|
||||
|
||||
static int ocelot_gpio_probe(struct udevice *dev)
|
||||
{
|
||||
struct gpio_dev_priv *uc_priv;
|
||||
|
||||
uc_priv = dev_get_uclass_priv(dev);
|
||||
uc_priv->bank_name = "ocelot-gpio";
|
||||
uc_priv->gpio_count = ARRAY_SIZE(ocelot_pins);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct driver ocelot_gpio_driver = {
|
||||
.name = "ocelot-gpio",
|
||||
.id = UCLASS_GPIO,
|
||||
.probe = ocelot_gpio_probe,
|
||||
.ops = &mscc_gpio_ops,
|
||||
};
|
||||
|
||||
int ocelot_pinctrl_probe(struct udevice *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = mscc_pinctrl_probe(dev, FUNC_MAX, ocelot_pins,
|
||||
ARRAY_SIZE(ocelot_pins),
|
||||
ocelot_function_names,
|
||||
ocelot_gpios);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = device_bind(dev, &ocelot_gpio_driver, "ocelot-gpio", NULL,
|
||||
dev_of_offset(dev), NULL);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct udevice_id ocelot_pinctrl_of_match[] = {
|
||||
{.compatible = "mscc,ocelot-pinctrl"},
|
||||
{},
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(ocelot_pinctrl) = {
|
||||
.name = "ocelot-pinctrl",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = of_match_ptr(ocelot_pinctrl_of_match),
|
||||
.probe = ocelot_pinctrl_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
|
||||
.ops = &mscc_pinctrl_ops,
|
||||
};
|
||||
@@ -0,0 +1,233 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Microsemi SoCs pinctrl driver
|
||||
*
|
||||
* Author: <horatiu.vultur@microchip.com>
|
||||
* Copyright (c) 2019 Microsemi Corporation
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <dm.h>
|
||||
#include <dm/device-internal.h>
|
||||
#include <dm/lists.h>
|
||||
#include <dm/pinctrl.h>
|
||||
#include <dm/root.h>
|
||||
#include <errno.h>
|
||||
#include <fdtdec.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/system.h>
|
||||
#include "mscc-common.h"
|
||||
|
||||
enum {
|
||||
FUNC_NONE,
|
||||
FUNC_GPIO,
|
||||
FUNC_IRQ0,
|
||||
FUNC_IRQ1,
|
||||
FUNC_MIIM1,
|
||||
FUNC_PCI_WAKE,
|
||||
FUNC_PTP0,
|
||||
FUNC_PTP1,
|
||||
FUNC_PTP2,
|
||||
FUNC_PTP3,
|
||||
FUNC_PWM,
|
||||
FUNC_RECO_CLK0,
|
||||
FUNC_RECO_CLK1,
|
||||
FUNC_SFP0,
|
||||
FUNC_SFP1,
|
||||
FUNC_SFP2,
|
||||
FUNC_SFP3,
|
||||
FUNC_SFP4,
|
||||
FUNC_SFP5,
|
||||
FUNC_SFP6,
|
||||
FUNC_SFP7,
|
||||
FUNC_SFP8,
|
||||
FUNC_SFP9,
|
||||
FUNC_SFP10,
|
||||
FUNC_SIO,
|
||||
FUNC_SI,
|
||||
FUNC_TACHO,
|
||||
FUNC_TWI,
|
||||
FUNC_TWI_SCL_M,
|
||||
FUNC_UART,
|
||||
FUNC_UART2,
|
||||
FUNC_MD,
|
||||
FUNC_PTP1588,
|
||||
FUNC_MAX
|
||||
};
|
||||
|
||||
static char * const serval_function_names[] = {
|
||||
[FUNC_NONE] = "none",
|
||||
[FUNC_GPIO] = "gpio",
|
||||
[FUNC_IRQ0] = "irq0",
|
||||
[FUNC_IRQ1] = "irq1",
|
||||
[FUNC_MIIM1] = "miim1",
|
||||
[FUNC_PCI_WAKE] = "pci_wake",
|
||||
[FUNC_PTP0] = "ptp0",
|
||||
[FUNC_PTP1] = "ptp1",
|
||||
[FUNC_PTP2] = "ptp2",
|
||||
[FUNC_PTP3] = "ptp3",
|
||||
[FUNC_PWM] = "pwm",
|
||||
[FUNC_RECO_CLK0] = "reco_clk0",
|
||||
[FUNC_RECO_CLK1] = "reco_clk1",
|
||||
[FUNC_SFP0] = "sfp0",
|
||||
[FUNC_SFP1] = "sfp1",
|
||||
[FUNC_SFP2] = "sfp2",
|
||||
[FUNC_SFP3] = "sfp3",
|
||||
[FUNC_SFP4] = "sfp4",
|
||||
[FUNC_SFP5] = "sfp5",
|
||||
[FUNC_SFP6] = "sfp6",
|
||||
[FUNC_SFP7] = "sfp7",
|
||||
[FUNC_SFP8] = "sfp8",
|
||||
[FUNC_SFP9] = "sfp9",
|
||||
[FUNC_SFP10] = "sfp10",
|
||||
[FUNC_SIO] = "sio",
|
||||
[FUNC_SI] = "si",
|
||||
[FUNC_TACHO] = "tacho",
|
||||
[FUNC_TWI] = "twi",
|
||||
[FUNC_TWI_SCL_M] = "twi_scl_m",
|
||||
[FUNC_UART] = "uart",
|
||||
[FUNC_UART2] = "uart2",
|
||||
[FUNC_MD] = "md",
|
||||
[FUNC_PTP1588] = "1588",
|
||||
};
|
||||
|
||||
MSCC_P(0, SIO, NONE, NONE);
|
||||
MSCC_P(1, SIO, NONE, NONE);
|
||||
MSCC_P(2, SIO, NONE, NONE);
|
||||
MSCC_P(3, SIO, NONE, NONE);
|
||||
MSCC_P(4, TACHO, NONE, NONE);
|
||||
MSCC_P(5, PWM, NONE, NONE);
|
||||
MSCC_P(6, TWI, NONE, NONE);
|
||||
MSCC_P(7, TWI, NONE, NONE);
|
||||
MSCC_P(8, SI, NONE, NONE);
|
||||
MSCC_P(9, SI, MD, NONE);
|
||||
MSCC_P(10, SI, MD, NONE);
|
||||
MSCC_P(11, SFP0, MD, TWI_SCL_M);
|
||||
MSCC_P(12, SFP1, MD, TWI_SCL_M);
|
||||
MSCC_P(13, SFP2, UART2, TWI_SCL_M);
|
||||
MSCC_P(14, SFP3, UART2, TWI_SCL_M);
|
||||
MSCC_P(15, SFP4, PTP1588, TWI_SCL_M);
|
||||
MSCC_P(16, SFP5, PTP1588, TWI_SCL_M);
|
||||
MSCC_P(17, SFP6, PCI_WAKE, TWI_SCL_M);
|
||||
MSCC_P(18, SFP7, NONE, TWI_SCL_M);
|
||||
MSCC_P(19, SFP8, NONE, TWI_SCL_M);
|
||||
MSCC_P(20, SFP9, NONE, TWI_SCL_M);
|
||||
MSCC_P(21, SFP10, NONE, TWI_SCL_M);
|
||||
MSCC_P(22, NONE, NONE, NONE);
|
||||
MSCC_P(23, NONE, NONE, NONE);
|
||||
MSCC_P(24, NONE, NONE, NONE);
|
||||
MSCC_P(25, NONE, NONE, NONE);
|
||||
MSCC_P(26, UART, NONE, NONE);
|
||||
MSCC_P(27, UART, NONE, NONE);
|
||||
MSCC_P(28, IRQ0, NONE, NONE);
|
||||
MSCC_P(29, IRQ1, NONE, NONE);
|
||||
MSCC_P(30, PTP1588, NONE, NONE);
|
||||
MSCC_P(31, PTP1588, NONE, NONE);
|
||||
|
||||
#define SERVAL_PIN(n) { \
|
||||
.name = "GPIO_"#n, \
|
||||
.drv_data = &mscc_pin_##n \
|
||||
}
|
||||
|
||||
static const struct mscc_pin_data serval_pins[] = {
|
||||
SERVAL_PIN(0),
|
||||
SERVAL_PIN(1),
|
||||
SERVAL_PIN(2),
|
||||
SERVAL_PIN(3),
|
||||
SERVAL_PIN(4),
|
||||
SERVAL_PIN(5),
|
||||
SERVAL_PIN(6),
|
||||
SERVAL_PIN(7),
|
||||
SERVAL_PIN(8),
|
||||
SERVAL_PIN(9),
|
||||
SERVAL_PIN(10),
|
||||
SERVAL_PIN(11),
|
||||
SERVAL_PIN(12),
|
||||
SERVAL_PIN(13),
|
||||
SERVAL_PIN(14),
|
||||
SERVAL_PIN(15),
|
||||
SERVAL_PIN(16),
|
||||
SERVAL_PIN(17),
|
||||
SERVAL_PIN(18),
|
||||
SERVAL_PIN(19),
|
||||
SERVAL_PIN(20),
|
||||
SERVAL_PIN(21),
|
||||
SERVAL_PIN(22),
|
||||
SERVAL_PIN(23),
|
||||
SERVAL_PIN(24),
|
||||
SERVAL_PIN(25),
|
||||
SERVAL_PIN(26),
|
||||
SERVAL_PIN(27),
|
||||
SERVAL_PIN(28),
|
||||
SERVAL_PIN(29),
|
||||
SERVAL_PIN(30),
|
||||
SERVAL_PIN(31),
|
||||
};
|
||||
|
||||
static const unsigned long serval_gpios[] = {
|
||||
[MSCC_GPIO_OUT_SET] = 0x00,
|
||||
[MSCC_GPIO_OUT_CLR] = 0x04,
|
||||
[MSCC_GPIO_OUT] = 0x08,
|
||||
[MSCC_GPIO_IN] = 0x0c,
|
||||
[MSCC_GPIO_OE] = 0x10,
|
||||
[MSCC_GPIO_INTR] = 0x14,
|
||||
[MSCC_GPIO_INTR_ENA] = 0x18,
|
||||
[MSCC_GPIO_INTR_IDENT] = 0x1c,
|
||||
[MSCC_GPIO_ALT0] = 0x20,
|
||||
[MSCC_GPIO_ALT1] = 0x24,
|
||||
};
|
||||
|
||||
static int serval_gpio_probe(struct udevice *dev)
|
||||
{
|
||||
struct gpio_dev_priv *uc_priv;
|
||||
|
||||
uc_priv = dev_get_uclass_priv(dev);
|
||||
uc_priv->bank_name = "serval-gpio";
|
||||
uc_priv->gpio_count = ARRAY_SIZE(serval_pins);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct driver serval_gpio_driver = {
|
||||
.name = "serval-gpio",
|
||||
.id = UCLASS_GPIO,
|
||||
.probe = serval_gpio_probe,
|
||||
.ops = &mscc_gpio_ops,
|
||||
};
|
||||
|
||||
static int serval_pinctrl_probe(struct udevice *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = mscc_pinctrl_probe(dev, FUNC_MAX, serval_pins,
|
||||
ARRAY_SIZE(serval_pins),
|
||||
serval_function_names,
|
||||
serval_gpios);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = device_bind(dev, &serval_gpio_driver, "serval-gpio", NULL,
|
||||
dev_of_offset(dev), NULL);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id serval_pinctrl_of_match[] = {
|
||||
{ .compatible = "mscc,serval-pinctrl" },
|
||||
{},
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(serval_pinctrl) = {
|
||||
.name = "serval-pinctrl",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = of_match_ptr(serval_pinctrl_of_match),
|
||||
.probe = serval_pinctrl_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
|
||||
.ops = &mscc_pinctrl_ops,
|
||||
};
|
||||
@@ -0,0 +1,269 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Microsemi SoCs pinctrl driver
|
||||
*
|
||||
* Author: <horatiu.vultur@microchip.com>
|
||||
* Copyright (c) 2019 Microsemi Corporation
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <dm.h>
|
||||
#include <dm/device-internal.h>
|
||||
#include <dm/lists.h>
|
||||
#include <dm/pinctrl.h>
|
||||
#include <dm/root.h>
|
||||
#include <errno.h>
|
||||
#include <fdtdec.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/system.h>
|
||||
#include "mscc-common.h"
|
||||
|
||||
enum {
|
||||
FUNC_NONE,
|
||||
FUNC_GPIO,
|
||||
FUNC_IRQ0_IN,
|
||||
FUNC_IRQ0_OUT,
|
||||
FUNC_IRQ1_IN,
|
||||
FUNC_IRQ1_OUT,
|
||||
FUNC_MIIM1,
|
||||
FUNC_MIIM2,
|
||||
FUNC_PCI_WAKE,
|
||||
FUNC_PTP0,
|
||||
FUNC_PTP1,
|
||||
FUNC_PTP2,
|
||||
FUNC_PTP3,
|
||||
FUNC_PWM,
|
||||
FUNC_RCVRD_CLK0,
|
||||
FUNC_RCVRD_CLK1,
|
||||
FUNC_RCVRD_CLK2,
|
||||
FUNC_RCVRD_CLK3,
|
||||
FUNC_REF_CLK0,
|
||||
FUNC_REF_CLK1,
|
||||
FUNC_REF_CLK2,
|
||||
FUNC_REF_CLK3,
|
||||
FUNC_SFP0,
|
||||
FUNC_SFP1,
|
||||
FUNC_SFP2,
|
||||
FUNC_SFP3,
|
||||
FUNC_SFP4,
|
||||
FUNC_SFP5,
|
||||
FUNC_SFP6,
|
||||
FUNC_SFP7,
|
||||
FUNC_SFP8,
|
||||
FUNC_SFP9,
|
||||
FUNC_SFP10,
|
||||
FUNC_SFP11,
|
||||
FUNC_SFP12,
|
||||
FUNC_SFP13,
|
||||
FUNC_SFP14,
|
||||
FUNC_SFP15,
|
||||
FUNC_SIO,
|
||||
FUNC_SPI,
|
||||
FUNC_TACHO,
|
||||
FUNC_TWI,
|
||||
FUNC_TWI2,
|
||||
FUNC_TWI_SCL_M,
|
||||
FUNC_UART,
|
||||
FUNC_UART2,
|
||||
FUNC_MAX
|
||||
};
|
||||
|
||||
static char * const servalt_function_names[] = {
|
||||
[FUNC_NONE] = "none",
|
||||
[FUNC_GPIO] = "gpio",
|
||||
[FUNC_IRQ0_IN] = "irq0_in",
|
||||
[FUNC_IRQ0_OUT] = "irq0_out",
|
||||
[FUNC_IRQ1_IN] = "irq1_in",
|
||||
[FUNC_IRQ1_OUT] = "irq1_out",
|
||||
[FUNC_MIIM1] = "miim1",
|
||||
[FUNC_MIIM2] = "miim2",
|
||||
[FUNC_PCI_WAKE] = "pci_wake",
|
||||
[FUNC_PTP0] = "ptp0",
|
||||
[FUNC_PTP1] = "ptp1",
|
||||
[FUNC_PTP2] = "ptp2",
|
||||
[FUNC_PTP3] = "ptp3",
|
||||
[FUNC_PWM] = "pwm",
|
||||
[FUNC_RCVRD_CLK0] = "rcvrd_clk0",
|
||||
[FUNC_RCVRD_CLK1] = "rcvrd_clk1",
|
||||
[FUNC_RCVRD_CLK2] = "rcvrd_clk2",
|
||||
[FUNC_RCVRD_CLK3] = "rcvrd_clk3",
|
||||
[FUNC_REF_CLK0] = "ref_clk0",
|
||||
[FUNC_REF_CLK1] = "ref_clk1",
|
||||
[FUNC_REF_CLK2] = "ref_clk2",
|
||||
[FUNC_REF_CLK3] = "ref_clk3",
|
||||
[FUNC_SFP0] = "sfp0",
|
||||
[FUNC_SFP1] = "sfp1",
|
||||
[FUNC_SFP2] = "sfp2",
|
||||
[FUNC_SFP3] = "sfp3",
|
||||
[FUNC_SFP4] = "sfp4",
|
||||
[FUNC_SFP5] = "sfp5",
|
||||
[FUNC_SFP6] = "sfp6",
|
||||
[FUNC_SFP7] = "sfp7",
|
||||
[FUNC_SFP8] = "sfp8",
|
||||
[FUNC_SFP9] = "sfp9",
|
||||
[FUNC_SFP10] = "sfp10",
|
||||
[FUNC_SFP11] = "sfp11",
|
||||
[FUNC_SFP12] = "sfp12",
|
||||
[FUNC_SFP13] = "sfp13",
|
||||
[FUNC_SFP14] = "sfp14",
|
||||
[FUNC_SFP15] = "sfp15",
|
||||
[FUNC_SIO] = "sio",
|
||||
[FUNC_SPI] = "spi",
|
||||
[FUNC_TACHO] = "tacho",
|
||||
[FUNC_TWI] = "twi",
|
||||
[FUNC_TWI2] = "twi2",
|
||||
[FUNC_TWI_SCL_M] = "twi_scl_m",
|
||||
[FUNC_UART] = "uart",
|
||||
[FUNC_UART2] = "uart2",
|
||||
};
|
||||
|
||||
MSCC_P(0, SIO, NONE, NONE);
|
||||
MSCC_P(1, SIO, NONE, NONE);
|
||||
MSCC_P(2, SIO, NONE, NONE);
|
||||
MSCC_P(3, SIO, NONE, NONE);
|
||||
MSCC_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
|
||||
MSCC_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M);
|
||||
MSCC_P(6, UART, NONE, NONE);
|
||||
MSCC_P(7, UART, NONE, NONE);
|
||||
MSCC_P(8, SPI, SFP0, TWI_SCL_M);
|
||||
MSCC_P(9, PCI_WAKE, SFP1, SPI);
|
||||
MSCC_P(10, PTP0, SFP2, TWI_SCL_M);
|
||||
MSCC_P(11, PTP1, SFP3, TWI_SCL_M);
|
||||
MSCC_P(12, REF_CLK0, SFP4, TWI_SCL_M);
|
||||
MSCC_P(13, REF_CLK1, SFP5, TWI_SCL_M);
|
||||
MSCC_P(14, REF_CLK2, IRQ0_OUT, SPI);
|
||||
MSCC_P(15, REF_CLK3, IRQ1_OUT, SPI);
|
||||
MSCC_P(16, TACHO, SFP6, SPI);
|
||||
MSCC_P(17, PWM, NONE, TWI_SCL_M);
|
||||
MSCC_P(18, PTP2, SFP7, SPI);
|
||||
MSCC_P(19, PTP3, SFP8, SPI);
|
||||
MSCC_P(20, UART2, SFP9, SPI);
|
||||
MSCC_P(21, UART2, NONE, NONE);
|
||||
MSCC_P(22, MIIM1, SFP10, TWI2);
|
||||
MSCC_P(23, MIIM1, SFP11, TWI2);
|
||||
MSCC_P(24, TWI, NONE, NONE);
|
||||
MSCC_P(25, TWI, SFP12, TWI_SCL_M);
|
||||
MSCC_P(26, TWI_SCL_M, SFP13, SPI);
|
||||
MSCC_P(27, TWI_SCL_M, SFP14, SPI);
|
||||
MSCC_P(28, TWI_SCL_M, SFP15, SPI);
|
||||
MSCC_P(29, TWI_SCL_M, NONE, NONE);
|
||||
MSCC_P(30, TWI_SCL_M, NONE, NONE);
|
||||
MSCC_P(31, TWI_SCL_M, NONE, NONE);
|
||||
MSCC_P(32, TWI_SCL_M, NONE, NONE);
|
||||
MSCC_P(33, RCVRD_CLK0, NONE, NONE);
|
||||
MSCC_P(34, RCVRD_CLK1, NONE, NONE);
|
||||
MSCC_P(35, RCVRD_CLK2, NONE, NONE);
|
||||
MSCC_P(36, RCVRD_CLK3, NONE, NONE);
|
||||
|
||||
#define SERVALT_PIN(n) { \
|
||||
.name = "GPIO_"#n, \
|
||||
.drv_data = &mscc_pin_##n \
|
||||
}
|
||||
|
||||
static const struct mscc_pin_data servalt_pins[] = {
|
||||
SERVALT_PIN(0),
|
||||
SERVALT_PIN(1),
|
||||
SERVALT_PIN(2),
|
||||
SERVALT_PIN(3),
|
||||
SERVALT_PIN(4),
|
||||
SERVALT_PIN(5),
|
||||
SERVALT_PIN(6),
|
||||
SERVALT_PIN(7),
|
||||
SERVALT_PIN(8),
|
||||
SERVALT_PIN(9),
|
||||
SERVALT_PIN(10),
|
||||
SERVALT_PIN(11),
|
||||
SERVALT_PIN(12),
|
||||
SERVALT_PIN(13),
|
||||
SERVALT_PIN(14),
|
||||
SERVALT_PIN(15),
|
||||
SERVALT_PIN(16),
|
||||
SERVALT_PIN(17),
|
||||
SERVALT_PIN(18),
|
||||
SERVALT_PIN(19),
|
||||
SERVALT_PIN(20),
|
||||
SERVALT_PIN(21),
|
||||
SERVALT_PIN(22),
|
||||
SERVALT_PIN(23),
|
||||
SERVALT_PIN(24),
|
||||
SERVALT_PIN(25),
|
||||
SERVALT_PIN(26),
|
||||
SERVALT_PIN(27),
|
||||
SERVALT_PIN(28),
|
||||
SERVALT_PIN(29),
|
||||
SERVALT_PIN(30),
|
||||
SERVALT_PIN(31),
|
||||
SERVALT_PIN(32),
|
||||
SERVALT_PIN(33),
|
||||
SERVALT_PIN(34),
|
||||
SERVALT_PIN(35),
|
||||
SERVALT_PIN(36),
|
||||
};
|
||||
|
||||
static const unsigned long servalt_gpios[] = {
|
||||
[MSCC_GPIO_OUT_SET] = 0x00,
|
||||
[MSCC_GPIO_OUT_CLR] = 0x08,
|
||||
[MSCC_GPIO_OUT] = 0x10,
|
||||
[MSCC_GPIO_IN] = 0x18,
|
||||
[MSCC_GPIO_OE] = 0x20,
|
||||
[MSCC_GPIO_INTR] = 0x28,
|
||||
[MSCC_GPIO_INTR_ENA] = 0x30,
|
||||
[MSCC_GPIO_INTR_IDENT] = 0x38,
|
||||
[MSCC_GPIO_ALT0] = 0x40,
|
||||
[MSCC_GPIO_ALT1] = 0x48,
|
||||
};
|
||||
|
||||
static int servalt_gpio_probe(struct udevice *dev)
|
||||
{
|
||||
struct gpio_dev_priv *uc_priv;
|
||||
|
||||
uc_priv = dev_get_uclass_priv(dev);
|
||||
uc_priv->bank_name = "servalt-gpio";
|
||||
uc_priv->gpio_count = ARRAY_SIZE(servalt_pins);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct driver servalt_gpio_driver = {
|
||||
.name = "servalt-gpio",
|
||||
.id = UCLASS_GPIO,
|
||||
.probe = servalt_gpio_probe,
|
||||
.ops = &mscc_gpio_ops,
|
||||
};
|
||||
|
||||
static int servalt_pinctrl_probe(struct udevice *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = mscc_pinctrl_probe(dev, FUNC_MAX, servalt_pins,
|
||||
ARRAY_SIZE(servalt_pins),
|
||||
servalt_function_names,
|
||||
servalt_gpios);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = device_bind(dev, &servalt_gpio_driver, "servalt-gpio", NULL,
|
||||
dev_of_offset(dev), NULL);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id servalt_pinctrl_of_match[] = {
|
||||
{ .compatible = "mscc,servalt-pinctrl" },
|
||||
{},
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(servalt_pinctrl) = {
|
||||
.name = "servalt-pinctrl",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = of_match_ptr(servalt_pinctrl_of_match),
|
||||
.probe = servalt_pinctrl_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
|
||||
.ops = &mscc_pinctrl_ops,
|
||||
};
|
||||
Reference in New Issue
Block a user