GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2018 Rockchip Electronics Co., Ltd.
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*/
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#include <common.h>
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#include <ram.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/sdram.h>
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#include <asm/arch-rockchip/sdram_common.h>
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#include <asm/arch-rockchip/sdram_phy_px30.h>
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static void sdram_phy_dll_bypass_set(void __iomem *phy_base, u32 freq)
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{
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u32 tmp;
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u32 i, j;
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u32 dqs_dll_freq;
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setbits_le32(PHY_REG(phy_base, 0x13), 1 << 4);
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clrbits_le32(PHY_REG(phy_base, 0x14), 1 << 3);
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for (i = 0; i < 4; i++) {
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j = 0x26 + i * 0x10;
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setbits_le32(PHY_REG(phy_base, j), 1 << 4);
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clrbits_le32(PHY_REG(phy_base, j + 0x1), 1 << 3);
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}
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if (freq <= 400)
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/* DLL bypass */
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setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f);
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else
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clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f);
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#ifdef CONFIG_ROCKCHIP_RK3328
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dqs_dll_freq = 680;
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#else
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dqs_dll_freq = 801;
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#endif
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if (freq <= dqs_dll_freq)
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tmp = 2;
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else
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tmp = 1;
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for (i = 0; i < 4; i++) {
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j = 0x28 + i * 0x10;
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writel(tmp, PHY_REG(phy_base, j));
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}
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}
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static void sdram_phy_set_ds_odt(void __iomem *phy_base,
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u32 dram_type)
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{
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u32 cmd_drv, clk_drv, dqs_drv, dqs_odt;
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u32 i, j;
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if (dram_type == DDR3) {
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cmd_drv = PHY_DDR3_RON_RTT_34ohm;
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clk_drv = PHY_DDR3_RON_RTT_45ohm;
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dqs_drv = PHY_DDR3_RON_RTT_34ohm;
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dqs_odt = PHY_DDR3_RON_RTT_225ohm;
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} else {
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cmd_drv = PHY_DDR4_LPDDR3_RON_RTT_34ohm;
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clk_drv = PHY_DDR4_LPDDR3_RON_RTT_43ohm;
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dqs_drv = PHY_DDR4_LPDDR3_RON_RTT_34ohm;
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if (dram_type == LPDDR2)
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dqs_odt = PHY_DDR4_LPDDR3_RON_RTT_DISABLE;
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else
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dqs_odt = PHY_DDR4_LPDDR3_RON_RTT_240ohm;
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}
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/* DS */
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writel(cmd_drv, PHY_REG(phy_base, 0x11));
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clrsetbits_le32(PHY_REG(phy_base, 0x12), 0x1f << 3, cmd_drv << 3);
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writel(clk_drv, PHY_REG(phy_base, 0x16));
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writel(clk_drv, PHY_REG(phy_base, 0x18));
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for (i = 0; i < 4; i++) {
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j = 0x20 + i * 0x10;
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writel(dqs_drv, PHY_REG(phy_base, j));
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writel(dqs_drv, PHY_REG(phy_base, j + 0xf));
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/* ODT */
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writel(dqs_odt, PHY_REG(phy_base, j + 0x1));
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writel(dqs_odt, PHY_REG(phy_base, j + 0xe));
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}
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}
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void phy_soft_reset(void __iomem *phy_base)
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{
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clrbits_le32(PHY_REG(phy_base, 0), 0x3 << 2);
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udelay(1);
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setbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET);
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udelay(5);
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setbits_le32(PHY_REG(phy_base, 0), DIGITAL_DERESET);
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udelay(1);
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}
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void phy_dram_set_bw(void __iomem *phy_base, u32 bw)
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{
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if (bw == 2) {
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clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 0xf << 4);
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setbits_le32(PHY_REG(phy_base, 0x46), 1 << 3);
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setbits_le32(PHY_REG(phy_base, 0x56), 1 << 3);
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} else if (bw == 1) {
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clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 3 << 4);
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clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3);
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clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3);
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} else if (bw == 0) {
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clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 1 << 4);
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clrbits_le32(PHY_REG(phy_base, 0x36), 1 << 3);
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clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3);
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clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3);
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}
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phy_soft_reset(phy_base);
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}
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int phy_data_training(void __iomem *phy_base, u32 cs, u32 dramtype)
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{
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u32 ret;
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u32 odt_val;
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u32 i, j;
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odt_val = readl(PHY_REG(phy_base, 0x2e));
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for (i = 0; i < 4; i++) {
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j = 0x20 + i * 0x10;
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writel(PHY_DDR3_RON_RTT_225ohm, PHY_REG(phy_base, j + 0x1));
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writel(0, PHY_REG(phy_base, j + 0xe));
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}
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if (dramtype == DDR4) {
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clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0);
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clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0);
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clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0);
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clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0);
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}
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/* choose training cs */
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clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs));
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/* enable gate training */
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clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 1);
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udelay(50);
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ret = readl(PHY_REG(phy_base, 0xff));
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/* disable gate training */
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clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 0);
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#ifndef CONFIG_ROCKCHIP_RK3328
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clrbits_le32(PHY_REG(phy_base, 2), 0x30);
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#endif
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if (dramtype == DDR4) {
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clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0x2);
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clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0x2);
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clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0x2);
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clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0x2);
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}
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if (ret & 0x10) {
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ret = -1;
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} else {
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ret = (ret & 0xf) ^ (readl(PHY_REG(phy_base, 0)) >> 4);
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ret = (ret == 0) ? 0 : -1;
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}
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for (i = 0; i < 4; i++) {
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j = 0x20 + i * 0x10;
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writel(odt_val, PHY_REG(phy_base, j + 0x1));
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writel(odt_val, PHY_REG(phy_base, j + 0xe));
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}
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return ret;
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}
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void phy_cfg(void __iomem *phy_base,
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struct ddr_phy_regs *phy_regs, struct ddr_phy_skew *skew,
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struct sdram_base_params *base, u32 bw)
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{
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u32 i;
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sdram_phy_dll_bypass_set(phy_base, base->ddr_freq);
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for (i = 0; phy_regs->phy[i][0] != 0xFFFFFFFF; i++) {
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writel(phy_regs->phy[i][1],
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phy_base + phy_regs->phy[i][0]);
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}
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if (bw == 2) {
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clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 0xf << 4);
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} else if (bw == 1) {
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clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 3 << 4);
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/* disable DQS2,DQS3 tx dll for saving power */
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clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3);
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clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3);
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} else {
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clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 1 << 4);
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/* disable DQS2,DQS3 tx dll for saving power */
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clrbits_le32(PHY_REG(phy_base, 0x36), 1 << 3);
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clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3);
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clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3);
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}
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sdram_phy_set_ds_odt(phy_base, base->dramtype);
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/* deskew */
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setbits_le32(PHY_REG(phy_base, 2), 8);
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sdram_copy_to_reg(PHY_REG(phy_base, 0xb0),
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&skew->a0_a1_skew[0], 15 * 4);
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sdram_copy_to_reg(PHY_REG(phy_base, 0x70),
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&skew->cs0_dm0_skew[0], 44 * 4);
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sdram_copy_to_reg(PHY_REG(phy_base, 0xc0),
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&skew->cs1_dm0_skew[0], 44 * 4);
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}
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