GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2012 SAMSUNG Electronics
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* Padmavathi Venna <padma.v@samsung.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <malloc.h>
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#include <spi.h>
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#include <fdtdec.h>
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#include <time.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/spi.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct exynos_spi_platdata {
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enum periph_id periph_id;
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s32 frequency; /* Default clock frequency, -1 for none */
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struct exynos_spi *regs;
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uint deactivate_delay_us; /* Delay to wait after deactivate */
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};
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struct exynos_spi_priv {
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struct exynos_spi *regs;
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unsigned int freq; /* Default frequency */
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unsigned int mode;
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enum periph_id periph_id; /* Peripheral ID for this device */
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unsigned int fifo_size;
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int skip_preamble;
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ulong last_transaction_us; /* Time of last transaction end */
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};
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/**
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* Flush spi tx, rx fifos and reset the SPI controller
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*
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* @param regs Pointer to SPI registers
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*/
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static void spi_flush_fifo(struct exynos_spi *regs)
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{
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clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
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clrbits_le32(®s->ch_cfg, SPI_CH_RST);
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setbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
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}
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static void spi_get_fifo_levels(struct exynos_spi *regs,
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int *rx_lvl, int *tx_lvl)
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{
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uint32_t spi_sts = readl(®s->spi_sts);
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*rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
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*tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
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}
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/**
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* If there's something to transfer, do a software reset and set a
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* transaction size.
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*
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* @param regs SPI peripheral registers
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* @param count Number of bytes to transfer
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* @param step Number of bytes to transfer in each packet (1 or 4)
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*/
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static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
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{
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debug("%s: regs=%p, count=%d, step=%d\n", __func__, regs, count, step);
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/* For word address we need to swap bytes */
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if (step == 4) {
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setbits_le32(®s->mode_cfg,
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SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
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count /= 4;
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setbits_le32(®s->swap_cfg, SPI_TX_SWAP_EN | SPI_RX_SWAP_EN |
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SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP |
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SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP);
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} else {
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/* Select byte access and clear the swap configuration */
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clrbits_le32(®s->mode_cfg,
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SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
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writel(0, ®s->swap_cfg);
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}
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assert(count && count < (1 << 16));
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setbits_le32(®s->ch_cfg, SPI_CH_RST);
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clrbits_le32(®s->ch_cfg, SPI_CH_RST);
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writel(count | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
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}
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static int spi_rx_tx(struct exynos_spi_priv *priv, int todo,
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void **dinp, void const **doutp, unsigned long flags)
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{
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struct exynos_spi *regs = priv->regs;
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uchar *rxp = *dinp;
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const uchar *txp = *doutp;
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int rx_lvl, tx_lvl;
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uint out_bytes, in_bytes;
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int toread;
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unsigned start = get_timer(0);
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int stopping;
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int step;
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out_bytes = in_bytes = todo;
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stopping = priv->skip_preamble && (flags & SPI_XFER_END) &&
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!(priv->mode & SPI_SLAVE);
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/*
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* Try to transfer words if we can. This helps read performance at
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* SPI clock speeds above about 20MHz.
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*/
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step = 1;
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if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) &&
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!priv->skip_preamble)
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step = 4;
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/*
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* If there's something to send, do a software reset and set a
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* transaction size.
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*/
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spi_request_bytes(regs, todo, step);
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/*
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* Bytes are transmitted/received in pairs. Wait to receive all the
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* data because then transmission will be done as well.
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*/
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toread = in_bytes;
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while (in_bytes) {
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int temp;
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/* Keep the fifos full/empty. */
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spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl);
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/*
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* Don't completely fill the txfifo, since we don't want our
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* rxfifo to overflow, and it may already contain data.
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*/
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while (tx_lvl < priv->fifo_size/2 && out_bytes) {
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if (!txp)
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temp = -1;
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else if (step == 4)
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temp = *(uint32_t *)txp;
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else
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temp = *txp;
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writel(temp, ®s->tx_data);
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out_bytes -= step;
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if (txp)
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txp += step;
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tx_lvl += step;
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}
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if (rx_lvl >= step) {
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while (rx_lvl >= step) {
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temp = readl(®s->rx_data);
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if (priv->skip_preamble) {
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if (temp == SPI_PREAMBLE_END_BYTE) {
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priv->skip_preamble = 0;
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stopping = 0;
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}
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} else {
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if (rxp || stopping) {
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if (step == 4)
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*(uint32_t *)rxp = temp;
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else
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*rxp = temp;
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rxp += step;
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}
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in_bytes -= step;
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}
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toread -= step;
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rx_lvl -= step;
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}
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} else if (!toread) {
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/*
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* We have run out of input data, but haven't read
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* enough bytes after the preamble yet. Read some more,
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* and make sure that we transmit dummy bytes too, to
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* keep things going.
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*/
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assert(!out_bytes);
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out_bytes = in_bytes;
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toread = in_bytes;
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txp = NULL;
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spi_request_bytes(regs, toread, step);
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}
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if (priv->skip_preamble && get_timer(start) > 100) {
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debug("SPI timeout: in_bytes=%d, out_bytes=%d, ",
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in_bytes, out_bytes);
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return -ETIMEDOUT;
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}
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}
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*dinp = rxp;
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*doutp = txp;
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return 0;
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}
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/**
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* Activate the CS by driving it LOW
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*
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* @param slave Pointer to spi_slave to which controller has to
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* communicate with
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*/
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static void spi_cs_activate(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
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struct exynos_spi_priv *priv = dev_get_priv(bus);
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/* If it's too soon to do another transaction, wait */
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if (pdata->deactivate_delay_us &&
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priv->last_transaction_us) {
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ulong delay_us; /* The delay completed so far */
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delay_us = timer_get_us() - priv->last_transaction_us;
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if (delay_us < pdata->deactivate_delay_us)
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udelay(pdata->deactivate_delay_us - delay_us);
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}
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clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
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debug("Activate CS, bus '%s'\n", bus->name);
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priv->skip_preamble = priv->mode & SPI_PREAMBLE;
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}
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/**
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* Deactivate the CS by driving it HIGH
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*
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* @param slave Pointer to spi_slave to which controller has to
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* communicate with
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*/
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static void spi_cs_deactivate(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
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struct exynos_spi_priv *priv = dev_get_priv(bus);
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setbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
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/* Remember time of this transaction so we can honour the bus delay */
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if (pdata->deactivate_delay_us)
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priv->last_transaction_us = timer_get_us();
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debug("Deactivate CS, bus '%s'\n", bus->name);
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}
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static int exynos_spi_ofdata_to_platdata(struct udevice *bus)
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{
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struct exynos_spi_platdata *plat = bus->platdata;
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const void *blob = gd->fdt_blob;
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int node = dev_of_offset(bus);
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plat->regs = (struct exynos_spi *)devfdt_get_addr(bus);
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plat->periph_id = pinmux_decode_periph_id(blob, node);
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if (plat->periph_id == PERIPH_ID_NONE) {
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debug("%s: Invalid peripheral ID %d\n", __func__,
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plat->periph_id);
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return -FDT_ERR_NOTFOUND;
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}
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/* Use 500KHz as a suitable default */
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plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
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500000);
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plat->deactivate_delay_us = fdtdec_get_int(blob, node,
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"spi-deactivate-delay", 0);
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debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
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__func__, plat->regs, plat->periph_id, plat->frequency,
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plat->deactivate_delay_us);
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return 0;
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}
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static int exynos_spi_probe(struct udevice *bus)
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{
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struct exynos_spi_platdata *plat = dev_get_platdata(bus);
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struct exynos_spi_priv *priv = dev_get_priv(bus);
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priv->regs = plat->regs;
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if (plat->periph_id == PERIPH_ID_SPI1 ||
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plat->periph_id == PERIPH_ID_SPI2)
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priv->fifo_size = 64;
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else
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priv->fifo_size = 256;
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priv->skip_preamble = 0;
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priv->last_transaction_us = timer_get_us();
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priv->freq = plat->frequency;
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priv->periph_id = plat->periph_id;
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return 0;
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}
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static int exynos_spi_claim_bus(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct exynos_spi_priv *priv = dev_get_priv(bus);
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exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE);
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spi_flush_fifo(priv->regs);
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writel(SPI_FB_DELAY_180, &priv->regs->fb_clk);
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return 0;
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}
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static int exynos_spi_release_bus(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct exynos_spi_priv *priv = dev_get_priv(bus);
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spi_flush_fifo(priv->regs);
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return 0;
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}
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static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct exynos_spi_priv *priv = dev_get_priv(bus);
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int upto, todo;
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int bytelen;
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int ret = 0;
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/* spi core configured to do 8 bit transfers */
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if (bitlen % 8) {
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debug("Non byte aligned SPI transfer.\n");
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return -1;
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}
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/* Start the transaction, if necessary. */
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if ((flags & SPI_XFER_BEGIN))
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spi_cs_activate(dev);
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/*
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* Exynos SPI limits each transfer to 65535 transfers. To keep
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* things simple, allow a maximum of 65532 bytes. We could allow
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* more in word mode, but the performance difference is small.
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*/
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bytelen = bitlen / 8;
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for (upto = 0; !ret && upto < bytelen; upto += todo) {
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todo = min(bytelen - upto, (1 << 16) - 4);
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ret = spi_rx_tx(priv, todo, &din, &dout, flags);
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if (ret)
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break;
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}
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/* Stop the transaction, if necessary. */
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if ((flags & SPI_XFER_END) && !(priv->mode & SPI_SLAVE)) {
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spi_cs_deactivate(dev);
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if (priv->skip_preamble) {
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assert(!priv->skip_preamble);
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debug("Failed to complete premable transaction\n");
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ret = -1;
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}
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}
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return ret;
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}
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static int exynos_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct exynos_spi_platdata *plat = bus->platdata;
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struct exynos_spi_priv *priv = dev_get_priv(bus);
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int ret;
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if (speed > plat->frequency)
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speed = plat->frequency;
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ret = set_spi_clk(priv->periph_id, speed);
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if (ret)
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return ret;
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priv->freq = speed;
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debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
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return 0;
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}
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static int exynos_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct exynos_spi_priv *priv = dev_get_priv(bus);
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uint32_t reg;
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reg = readl(&priv->regs->ch_cfg);
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reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
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if (mode & SPI_CPHA)
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reg |= SPI_CH_CPHA_B;
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if (mode & SPI_CPOL)
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reg |= SPI_CH_CPOL_L;
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writel(reg, &priv->regs->ch_cfg);
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priv->mode = mode;
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debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
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return 0;
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}
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static const struct dm_spi_ops exynos_spi_ops = {
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.claim_bus = exynos_spi_claim_bus,
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.release_bus = exynos_spi_release_bus,
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.xfer = exynos_spi_xfer,
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.set_speed = exynos_spi_set_speed,
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.set_mode = exynos_spi_set_mode,
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/*
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* cs_info is not needed, since we require all chip selects to be
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* in the device tree explicitly
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*/
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};
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static const struct udevice_id exynos_spi_ids[] = {
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{ .compatible = "samsung,exynos-spi" },
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{ }
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};
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U_BOOT_DRIVER(exynos_spi) = {
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.name = "exynos_spi",
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.id = UCLASS_SPI,
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.of_match = exynos_spi_ids,
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.ops = &exynos_spi_ops,
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.ofdata_to_platdata = exynos_spi_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata),
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.priv_auto_alloc_size = sizeof(struct exynos_spi_priv),
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.probe = exynos_spi_probe,
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};
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