GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/drivers/spmi/Kconfig

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+menu "SPMI support"
+
+config SPMI
+	bool "Enable SPMI bus support"
+	depends on DM
+	---help---
+	  Select this to enable to support SPMI bus.
+	  SPMI (System Power Management Interface) bus is used
+	  to connect PMIC devices on various SoCs.
+
+config SPMI_MSM
+	bool "Support Qualcomm SPMI bus"
+	depends on SPMI
+	---help---
+	  Support SPMI bus implementation found on Qualcomm Snapdragon SoCs.
+
+config SPMI_SANDBOX
+	bool "Support for Sandbox SPMI bus"
+	depends on SPMI
+	---help---
+	  Demo SPMI bus implementation. Emulates part of PM8916 as single
+          slave (0) on bus. It has 4 GPIO peripherals, pid 0xC0-0xC3.
+endmenu

source/bootloader/u-boot-2020.01/drivers/spmi/Makefile

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+
+obj-$(CONFIG_SPMI)  += spmi-uclass.o
+obj-$(CONFIG_SPMI_MSM) += spmi-msm.o
+obj-$(CONFIG_SPMI_SANDBOX) += spmi-sandbox.o

source/bootloader/u-boot-2020.01/drivers/spmi/spmi-msm.c

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+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Qualcomm SPMI bus driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * Loosely based on Little Kernel driver
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <spmi/spmi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* PMIC Arbiter configuration registers */
+#define PMIC_ARB_VERSION		0x0000
+#define PMIC_ARB_VERSION_V2_MIN		0x20010000
+
+#define ARB_CHANNEL_OFFSET(n)		(0x4 * (n))
+#define SPMI_CH_OFFSET(chnl)		((chnl) * 0x8000)
+
+#define SPMI_REG_CMD0			0x0
+#define SPMI_REG_CONFIG			0x4
+#define SPMI_REG_STATUS			0x8
+#define SPMI_REG_WDATA			0x10
+#define SPMI_REG_RDATA			0x18
+
+#define SPMI_CMD_OPCODE_SHIFT		27
+#define SPMI_CMD_SLAVE_ID_SHIFT		20
+#define SPMI_CMD_ADDR_SHIFT		12
+#define SPMI_CMD_ADDR_OFFSET_SHIFT	4
+#define SPMI_CMD_BYTE_CNT_SHIFT		0
+
+#define SPMI_CMD_EXT_REG_WRITE_LONG	0x00
+#define SPMI_CMD_EXT_REG_READ_LONG	0x01
+
+#define SPMI_STATUS_DONE		0x1
+
+#define SPMI_MAX_CHANNELS	128
+#define SPMI_MAX_SLAVES		16
+#define SPMI_MAX_PERIPH		256
+
+struct msm_spmi_priv {
+	phys_addr_t arb_chnl; /* ARB channel mapping base */
+	phys_addr_t spmi_core; /* SPMI core */
+	phys_addr_t spmi_obs; /* SPMI observer */
+	/* SPMI channel map */
+	uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
+};
+
+static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
+			  uint8_t val)
+{
+	struct msm_spmi_priv *priv = dev_get_priv(dev);
+	unsigned channel;
+	uint32_t reg = 0;
+
+	if (usid >= SPMI_MAX_SLAVES)
+		return -EIO;
+	if (pid >= SPMI_MAX_PERIPH)
+		return -EIO;
+
+	channel = priv->channel_map[usid][pid];
+
+	/* Disable IRQ mode for the current channel*/
+	writel(0x0, priv->spmi_core + SPMI_CH_OFFSET(channel) +
+	       SPMI_REG_CONFIG);
+
+	/* Write single byte */
+	writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
+
+	/* Prepare write command */
+	reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
+	reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
+	reg |= (pid << SPMI_CMD_ADDR_SHIFT);
+	reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
+	reg |= 1; /* byte count */
+
+	/* Send write command */
+	writel(reg, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
+
+	/* Wait till CMD DONE status */
+	reg = 0;
+	while (!reg) {
+		reg = readl(priv->spmi_core + SPMI_CH_OFFSET(channel) +
+			    SPMI_REG_STATUS);
+	}
+
+	if (reg ^ SPMI_STATUS_DONE) {
+		printf("SPMI write failure.\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int msm_spmi_read(struct udevice *dev, int usid, int pid, int off)
+{
+	struct msm_spmi_priv *priv = dev_get_priv(dev);
+	unsigned channel;
+	uint32_t reg = 0;
+
+	if (usid >= SPMI_MAX_SLAVES)
+		return -EIO;
+	if (pid >= SPMI_MAX_PERIPH)
+		return -EIO;
+
+	channel = priv->channel_map[usid][pid];
+
+	/* Disable IRQ mode for the current channel*/
+	writel(0x0, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
+
+	/* Prepare read command */
+	reg |= SPMI_CMD_EXT_REG_READ_LONG << SPMI_CMD_OPCODE_SHIFT;
+	reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
+	reg |= (pid << SPMI_CMD_ADDR_SHIFT);
+	reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
+	reg |= 1; /* byte count */
+
+	/* Request read */
+	writel(reg, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
+
+	/* Wait till CMD DONE status */
+	reg = 0;
+	while (!reg) {
+		reg = readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
+			    SPMI_REG_STATUS);
+	}
+
+	if (reg ^ SPMI_STATUS_DONE) {
+		printf("SPMI read failure.\n");
+		return -EIO;
+	}
+
+	/* Read the data */
+	return readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
+		     SPMI_REG_RDATA) & 0xFF;
+}
+
+static struct dm_spmi_ops msm_spmi_ops = {
+	.read = msm_spmi_read,
+	.write = msm_spmi_write,
+};
+
+static int msm_spmi_probe(struct udevice *dev)
+{
+	struct udevice *parent = dev->parent;
+	struct msm_spmi_priv *priv = dev_get_priv(dev);
+	int node = dev_of_offset(dev);
+	u32 hw_ver;
+	bool is_v1;
+	int i;
+
+	priv->arb_chnl = devfdt_get_addr(dev);
+	priv->spmi_core = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
+			dev_of_offset(parent), node, "reg", 1, NULL, false);
+	priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
+			dev_of_offset(parent), node, "reg", 2, NULL, false);
+
+	hw_ver = readl(priv->arb_chnl + PMIC_ARB_VERSION - 0x800);
+	is_v1  = (hw_ver < PMIC_ARB_VERSION_V2_MIN);
+
+	dev_dbg(dev, "PMIC Arb Version-%d (0x%x)\n", (is_v1 ? 1 : 2), hw_ver);
+
+	if (priv->arb_chnl == FDT_ADDR_T_NONE ||
+	    priv->spmi_core == FDT_ADDR_T_NONE ||
+	    priv->spmi_obs == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	/* Scan peripherals connected to each SPMI channel */
+	for (i = 0; i < SPMI_MAX_PERIPH ; i++) {
+		uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i));
+		uint8_t slave_id = (periph & 0xf0000) >> 16;
+		uint8_t pid = (periph & 0xff00) >> 8;
+
+		priv->channel_map[slave_id][pid] = i;
+	}
+	return 0;
+}
+
+static const struct udevice_id msm_spmi_ids[] = {
+	{ .compatible = "qcom,spmi-pmic-arb" },
+	{ }
+};
+
+U_BOOT_DRIVER(msm_spmi) = {
+	.name = "msm_spmi",
+	.id = UCLASS_SPMI,
+	.of_match = msm_spmi_ids,
+	.ops = &msm_spmi_ops,
+	.probe = msm_spmi_probe,
+	.priv_auto_alloc_size = sizeof(struct msm_spmi_priv),
+};

source/bootloader/u-boot-2020.01/drivers/spmi/spmi-sandbox.c

@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Sample SPMI bus driver
+ *
+ * It emulates bus with single pm8916-like pmic that has only GPIO reigsters.
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <spmi/spmi.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+#define EMUL_GPIO_PID_START 0xC0
+#define EMUL_GPIO_PID_END   0xC3
+
+#define EMUL_GPIO_COUNT 4
+
+#define EMUL_GPIO_REG_END 0x46 /* Last valid register */
+
+#define EMUL_PERM_R 0x1
+#define EMUL_PERM_W 0x2
+#define EMUL_PERM_RW (EMUL_PERM_R | EMUL_PERM_W)
+
+struct sandbox_emul_fake_regs {
+	u8 value;
+	u8 access_mask;
+	u8 perms; /* Access permissions */
+};
+
+struct sandbox_emul_gpio {
+	/* Fake registers - need one more entry as REG_END is valid address. */
+	struct sandbox_emul_fake_regs r[EMUL_GPIO_REG_END + 1];
+};
+
+struct sandbox_spmi_priv {
+	struct sandbox_emul_gpio gpios[EMUL_GPIO_COUNT];
+};
+
+/* Check if valid register was requested */
+static bool check_address_valid(int usid, int pid, int off)
+{
+	if (usid != 0)
+		return false;
+	if (pid < EMUL_GPIO_PID_START || pid > EMUL_GPIO_PID_END)
+		return false;
+	if (off > EMUL_GPIO_REG_END)
+		return false;
+	return true;
+}
+
+static int sandbox_spmi_write(struct udevice *dev, int usid, int pid, int off,
+			  uint8_t val)
+{
+	struct sandbox_spmi_priv *priv = dev_get_priv(dev);
+	struct sandbox_emul_fake_regs *regs;
+
+	if (!check_address_valid(usid, pid, off))
+		return -EIO;
+
+	regs = priv->gpios[pid & 0x3].r; /* Last 3 bits of pid are gpio # */
+
+	switch (off) {
+	case 0x40: /* Control */
+		val &= regs[off].access_mask;
+		if (((val & 0x30) == 0x10) || ((val & 0x30) == 0x20)) {
+			/* out/inout - set status register */
+			regs[0x8].value &= ~0x1;
+			regs[0x8].value |= val & 0x1;
+		}
+		break;
+	default:
+		if (regs[off].perms & EMUL_PERM_W)
+			regs[off].value = val & regs[off].access_mask;
+	}
+	return 0;
+}
+
+static int sandbox_spmi_read(struct udevice *dev, int usid, int pid, int off)
+{
+	struct sandbox_spmi_priv *priv = dev_get_priv(dev);
+	struct sandbox_emul_fake_regs *regs;
+
+	if (!check_address_valid(usid, pid, off))
+		return -EIO;
+
+	regs = priv->gpios[pid & 0x3].r; /* Last 3 bits of pid are gpio # */
+
+	if (regs[0x46].value == 0) /* Block disabled */
+		return 0;
+
+	switch (off) {
+	case 0x8: /* Status */
+		if (regs[0x46].value == 0) /* Block disabled */
+			return 0;
+		return regs[off].value;
+	default:
+		if (regs[off].perms & EMUL_PERM_R)
+			return regs[off].value;
+		else
+			return 0;
+	}
+}
+
+static struct dm_spmi_ops sandbox_spmi_ops = {
+	.read = sandbox_spmi_read,
+	.write = sandbox_spmi_write,
+};
+
+static int sandbox_spmi_probe(struct udevice *dev)
+{
+	struct sandbox_spmi_priv *priv = dev_get_priv(dev);
+	int i;
+
+	for (i = 0; i < EMUL_GPIO_COUNT; ++i) {
+		struct sandbox_emul_fake_regs *regs = priv->gpios[i].r;
+		regs[4].perms = EMUL_PERM_R;
+		regs[4].value = 0x10;
+		regs[5].perms = EMUL_PERM_R;
+		regs[5].value = 0x5;
+		regs[8].access_mask = 0x81;
+		regs[8].perms = EMUL_PERM_RW;
+		regs[0x40].access_mask = 0x7F;
+		regs[0x40].perms = EMUL_PERM_RW;
+		regs[0x41].access_mask = 7;
+		regs[0x41].perms = EMUL_PERM_RW;
+		regs[0x42].access_mask = 7;
+		regs[0x42].perms = EMUL_PERM_RW;
+		regs[0x42].value = 0x4;
+		regs[0x45].access_mask = 0x3F;
+		regs[0x45].perms = EMUL_PERM_RW;
+		regs[0x45].value = 0x1;
+		regs[0x46].access_mask = 0x80;
+		regs[0x46].perms = EMUL_PERM_RW;
+		regs[0x46].value = 0x80;
+	}
+	return 0;
+}
+
+static const struct udevice_id sandbox_spmi_ids[] = {
+	{ .compatible = "sandbox,spmi" },
+	{ }
+};
+
+U_BOOT_DRIVER(msm_spmi) = {
+	.name = "sandbox_spmi",
+	.id = UCLASS_SPMI,
+	.of_match = sandbox_spmi_ids,
+	.ops = &sandbox_spmi_ops,
+	.probe = sandbox_spmi_probe,
+	.priv_auto_alloc_size = sizeof(struct sandbox_spmi_priv),
+};

source/bootloader/u-boot-2020.01/drivers/spmi/spmi-uclass.c

@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SPMI bus uclass driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <spmi/spmi.h>
+#include <linux/ctype.h>
+
+int spmi_reg_read(struct udevice *dev, int usid, int pid, int reg)
+{
+	const struct dm_spmi_ops *ops = dev_get_driver_ops(dev);
+
+	if (!ops || !ops->read)
+		return -ENOSYS;
+
+	return ops->read(dev, usid, pid, reg);
+}
+
+int spmi_reg_write(struct udevice *dev, int usid, int pid, int reg,
+		   uint8_t value)
+{
+	const struct dm_spmi_ops *ops = dev_get_driver_ops(dev);
+
+	if (!ops || !ops->write)
+		return -ENOSYS;
+
+	return ops->write(dev, usid, pid, reg, value);
+}
+
+UCLASS_DRIVER(spmi) = {
+	.id		= UCLASS_SPMI,
+	.name		= "spmi",
+	.post_bind	= dm_scan_fdt_dev,
+};