GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009, 2011, 2016 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
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*
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* Author: Tor Krill tor@excito.com
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*/
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#include <common.h>
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#include <env.h>
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#include <pci.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <usb/ehci-ci.h>
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#include <hwconfig.h>
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#include <fsl_usb.h>
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#include <fdt_support.h>
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#include <dm.h>
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#include "ehci.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#endif
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#if CONFIG_IS_ENABLED(DM_USB)
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struct ehci_fsl_priv {
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struct ehci_ctrl ehci;
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fdt_addr_t hcd_base;
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char *phy_type;
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};
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#endif
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static void set_txfifothresh(struct usb_ehci *, u32);
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#if CONFIG_IS_ENABLED(DM_USB)
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static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
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struct ehci_hccr *hccr, struct ehci_hcor *hcor);
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#else
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static int ehci_fsl_init(int index, struct usb_ehci *ehci,
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struct ehci_hccr *hccr, struct ehci_hcor *hcor);
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#endif
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/* Check USB PHY clock valid */
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static int usb_phy_clk_valid(struct usb_ehci *ehci)
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{
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if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
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in_be32(&ehci->prictrl))) {
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printf("USB PHY clock invalid!\n");
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return 0;
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} else {
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return 1;
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}
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}
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#if CONFIG_IS_ENABLED(DM_USB)
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static int ehci_fsl_ofdata_to_platdata(struct udevice *dev)
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{
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struct ehci_fsl_priv *priv = dev_get_priv(dev);
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const void *prop;
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prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy_type",
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NULL);
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if (prop) {
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priv->phy_type = (char *)prop;
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debug("phy_type %s\n", priv->phy_type);
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}
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return 0;
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}
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static int ehci_fsl_init_after_reset(struct ehci_ctrl *ctrl)
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{
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struct usb_ehci *ehci = NULL;
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struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
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ehci);
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#ifdef CONFIG_PPC
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ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
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#else
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ehci = (struct usb_ehci *)priv->hcd_base;
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#endif
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if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
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return -ENXIO;
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return 0;
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}
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static const struct ehci_ops fsl_ehci_ops = {
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.init_after_reset = ehci_fsl_init_after_reset,
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};
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static int ehci_fsl_probe(struct udevice *dev)
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{
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struct ehci_fsl_priv *priv = dev_get_priv(dev);
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struct usb_ehci *ehci = NULL;
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struct ehci_hccr *hccr;
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struct ehci_hcor *hcor;
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struct ehci_ctrl *ehci_ctrl = &priv->ehci;
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/*
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* Get the base address for EHCI controller from the device node
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*/
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priv->hcd_base = devfdt_get_addr(dev);
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if (priv->hcd_base == FDT_ADDR_T_NONE) {
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debug("Can't get the EHCI register base address\n");
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return -ENXIO;
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}
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#ifdef CONFIG_PPC
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ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
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#else
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ehci = (struct usb_ehci *)priv->hcd_base;
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#endif
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hccr = (struct ehci_hccr *)(&ehci->caplength);
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hcor = (struct ehci_hcor *)
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((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
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if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
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return -ENXIO;
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debug("ehci-fsl: init hccr %p and hcor %p hc_length %d\n",
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(void *)hccr, (void *)hcor,
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HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
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}
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static const struct udevice_id ehci_usb_ids[] = {
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{ .compatible = "fsl-usb2-mph", },
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{ .compatible = "fsl-usb2-dr", },
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{ }
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};
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U_BOOT_DRIVER(ehci_fsl) = {
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.name = "ehci_fsl",
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.id = UCLASS_USB,
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.of_match = ehci_usb_ids,
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.ofdata_to_platdata = ehci_fsl_ofdata_to_platdata,
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.probe = ehci_fsl_probe,
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.remove = ehci_deregister,
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.ops = &ehci_usb_ops,
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.platdata_auto_alloc_size = sizeof(struct usb_platdata),
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.priv_auto_alloc_size = sizeof(struct ehci_fsl_priv),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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#else
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/*
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* Create the appropriate control structures to manage
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* a new EHCI host controller.
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*
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* Excerpts from linux ehci fsl driver.
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*/
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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struct ehci_ctrl *ehci_ctrl = container_of(hccr,
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struct ehci_ctrl, hccr);
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struct usb_ehci *ehci = NULL;
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switch (index) {
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case 0:
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ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
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break;
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case 1:
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ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
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break;
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default:
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printf("ERROR: wrong controller index!!\n");
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return -EINVAL;
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};
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*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
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*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
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HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
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return ehci_fsl_init(index, ehci, *hccr, *hcor);
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}
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/*
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* Destroy the appropriate control structures corresponding
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* the the EHCI host controller.
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*/
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int ehci_hcd_stop(int index)
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{
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return 0;
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}
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#endif
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#if CONFIG_IS_ENABLED(DM_USB)
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static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
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struct ehci_hccr *hccr, struct ehci_hcor *hcor)
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#else
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static int ehci_fsl_init(int index, struct usb_ehci *ehci,
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struct ehci_hccr *hccr, struct ehci_hcor *hcor)
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#endif
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{
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const char *phy_type = NULL;
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#if !CONFIG_IS_ENABLED(DM_USB)
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size_t len;
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char current_usb_controller[5];
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#endif
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#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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char usb_phy[5];
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usb_phy[0] = '\0';
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#endif
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if (has_erratum_a007075()) {
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/*
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* A 5ms delay is needed after applying soft-reset to the
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* controller to let external ULPI phy come out of reset.
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* This delay needs to be added before re-initializing
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* the controller after soft-resetting completes
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*/
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mdelay(5);
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}
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/* Set to Host mode */
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setbits_le32(&ehci->usbmode, CM_HOST);
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out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
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out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
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/* Init phy */
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#if CONFIG_IS_ENABLED(DM_USB)
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if (priv->phy_type)
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phy_type = priv->phy_type;
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#else
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memset(current_usb_controller, '\0', 5);
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snprintf(current_usb_controller, sizeof(current_usb_controller),
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"usb%d", index+1);
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if (hwconfig_sub(current_usb_controller, "phy_type"))
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phy_type = hwconfig_subarg(current_usb_controller,
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"phy_type", &len);
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#endif
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else
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phy_type = env_get("usb_phy_type");
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if (!phy_type) {
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#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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/* if none specified assume internal UTMI */
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strcpy(usb_phy, "utmi");
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phy_type = usb_phy;
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#else
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printf("WARNING: USB phy type not defined !!\n");
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return -1;
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#endif
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}
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if (!strncmp(phy_type, "utmi", 4)) {
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#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
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clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
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PHY_CLK_SEL_UTMI);
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clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
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UTMI_PHY_EN);
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udelay(1000); /* delay required for PHY Clk to appear */
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#endif
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out_le32(&(hcor)->or_portsc[0], PORT_PTS_UTMI);
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clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
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USB_EN);
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} else {
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clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
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PHY_CLK_SEL_ULPI);
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clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
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CONTROL_REGISTER_W1C_MASK, USB_EN);
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udelay(1000); /* delay required for PHY Clk to appear */
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if (!usb_phy_clk_valid(ehci))
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return -EINVAL;
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out_le32(&(hcor)->or_portsc[0], PORT_PTS_ULPI);
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}
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out_be32(&ehci->prictrl, 0x0000000c);
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out_be32(&ehci->age_cnt_limit, 0x00000040);
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out_be32(&ehci->sictrl, 0x00000001);
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in_le32(&ehci->usbmode);
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if (has_erratum_a007798())
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set_txfifothresh(ehci, TXFIFOTHRESH);
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if (has_erratum_a004477()) {
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/*
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* When reset is issued while any ULPI transaction is ongoing
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* then it may result to corruption of ULPI Function Control
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* Register which eventually causes phy clock to enter low
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* power mode which stops the clock. Thus delay is required
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* before reset to let ongoing ULPI transaction complete.
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*/
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udelay(1);
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}
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return 0;
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}
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/*
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* Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
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* to counter DDR latencies in writing data into Tx buffer.
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* This prevents Tx buffer from getting underrun
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*/
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static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
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{
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u32 cmd;
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cmd = ehci_readl(&ehci->txfilltuning);
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cmd &= ~TXFIFO_THRESH_MASK;
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cmd |= TXFIFO_THRESH(txfifo_thresh);
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ehci_writel(&ehci->txfilltuning, cmd);
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}
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