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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
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source/bootloader/u-boot-2020.01/drivers/usb/musb/Kconfig
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# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2017
# Adam Ford, Logic PD, aford173@gmail.com
comment "Legacy MUSB Support"
config USB_MUSB_HCD
bool "Legacy MUSB Host Controller"
config USB_MUSB_UDC
bool "Legacy USB Device Controller"
config USB_OMAP3
bool "Legacy MUSB OMAP3 / OMAP4"
depends on ARCH_OMAP2PLUS
config USB_AM35X
bool"Legacy MUSB AM35x"
depends on ARCH_OMAP2PLUS && !USB_OMAP3
source/bootloader/u-boot-2020.01/drivers/usb/musb/Makefile
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# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-$(CONFIG_USB_MUSB_HCD) += musb_hcd.o musb_core.o
obj-$(CONFIG_USB_MUSB_UDC) += musb_udc.o musb_core.o
obj-$(CONFIG_USB_OMAP3) += omap3.o
obj-$(CONFIG_USB_AM35X) += am35x.o
source/bootloader/u-boot-2020.01/drivers/usb/musb/am35x.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* am35x.c - TI's AM35x platform specific usb wrapper functions.
*
* Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
*
* Based on drivers/usb/musb/da8xx.c
*
* Copyright (c) 2010 Texas Instruments Incorporated
*/
#include <common.h>
#include "am35x.h"
/* MUSB platform configuration */
struct musb_config musb_cfg = {
.regs = (struct musb_regs *)AM35X_USB_OTG_CORE_BASE,
.timeout = AM35X_USB_OTG_TIMEOUT,
.musb_speed = 0,
};
/*
* Enable the USB phy
*/
static u8 phy_on(void)
{
u32 devconf2;
u32 timeout;
devconf2 = readl(&am35x_scm_general_regs->devconf2);
devconf2 &= ~(DEVCONF2_RESET | DEVCONF2_PHYPWRDN | DEVCONF2_OTGPWRDN |
DEVCONF2_OTGMODE | DEVCONF2_REFFREQ |
DEVCONF2_PHY_GPIOMODE);
devconf2 |= DEVCONF2_SESENDEN | DEVCONF2_VBDTCTEN | DEVCONF2_PHY_PLLON |
DEVCONF2_REFFREQ_13MHZ | DEVCONF2_DATPOL;
writel(devconf2, &am35x_scm_general_regs->devconf2);
/* wait until the USB phy is turned on */
timeout = musb_cfg.timeout;
while (timeout--)
if (readl(&am35x_scm_general_regs->devconf2) & DEVCONF2_PHYCKGD)
return 1;
/* USB phy was not turned on */
return 0;
}
/*
* Disable the USB phy
*/
static void phy_off(void)
{
u32 devconf2;
/*
* Power down the on-chip PHY.
*/
devconf2 = readl(&am35x_scm_general_regs->devconf2);
devconf2 &= ~DEVCONF2_PHY_PLLON;
devconf2 |= DEVCONF2_PHYPWRDN | DEVCONF2_OTGPWRDN;
writel(devconf2, &am35x_scm_general_regs->devconf2);
}
/*
* This function performs platform specific initialization for usb0.
*/
int musb_platform_init(void)
{
u32 revision;
u32 sw_reset;
/* global usb reset */
sw_reset = readl(&am35x_scm_general_regs->ip_sw_reset);
sw_reset |= (1 << 0);
writel(sw_reset, &am35x_scm_general_regs->ip_sw_reset);
sw_reset &= ~(1 << 0);
writel(sw_reset, &am35x_scm_general_regs->ip_sw_reset);
/* reset the controller */
writel(0x1, &am35x_usb_regs->control);
udelay(5000);
/* start the on-chip usb phy and its pll */
if (phy_on() == 0)
return -1;
/* Returns zero if e.g. not clocked */
revision = readl(&am35x_usb_regs->revision);
if (revision == 0)
return -1;
return 0;
}
/*
* This function performs platform specific deinitialization for usb0.
*/
void musb_platform_deinit(void)
{
/* Turn off the phy */
phy_off();
}
/*
* This function reads data from endpoint fifo for AM35x
* which supports only 32bit read operation.
*
* ep - endpoint number
* length - number of bytes to read from FIFO
* fifo_data - pointer to data buffer into which data is read
*/
__attribute__((weak))
void read_fifo(u8 ep, u32 length, void *fifo_data)
{
u8 *data = (u8 *)fifo_data;
u32 val;
int i;
/* select the endpoint index */
writeb(ep, &musbr->index);
if (length > 4) {
for (i = 0; i < (length >> 2); i++) {
val = readl(&musbr->fifox[ep]);
memcpy(data, &val, 4);
data += 4;
}
length %= 4;
}
if (length > 0) {
val = readl(&musbr->fifox[ep]);
memcpy(data, &val, length);
}
}
source/bootloader/u-boot-2020.01/drivers/usb/musb/am35x.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* am35x.h - TI's AM35x platform specific usb wrapper definitions.
*
* Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
*
* Based on drivers/usb/musb/da8xx.h
*
* Copyright (c) 2010 Texas Instruments Incorporated
*/
#ifndef __AM35X_USB_H__
#define __AM35X_USB_H__
#include <asm/arch/am35x_def.h>
#include "musb_core.h"
/* Base address of musb wrapper */
#define AM35X_USB_OTG_BASE 0x5C040000
/* Base address of musb core */
#define AM35X_USB_OTG_CORE_BASE (AM35X_USB_OTG_BASE + 0x400)
/* Timeout for AM35x usb module */
#define AM35X_USB_OTG_TIMEOUT 0x3FFFFFF
/*
* AM35x platform USB wrapper register overlay.
*/
struct am35x_usb_regs {
u32 revision;
u32 control;
u32 status;
u32 emulation;
u32 reserved0[1];
u32 autoreq;
u32 srpfixtime;
u32 ep_intsrc;
u32 ep_intsrcset;
u32 ep_intsrcclr;
u32 ep_intmsk;
u32 ep_intmskset;
u32 ep_intmskclr;
u32 ep_intsrcmsked;
u32 reserved1[1];
u32 core_intsrc;
u32 core_intsrcset;
u32 core_intsrcclr;
u32 core_intmsk;
u32 core_intmskset;
u32 core_intmskclr;
u32 core_intsrcmsked;
u32 reserved2[1];
u32 eoi;
u32 mop_sop_en;
u32 reserved3[2];
u32 txmode;
u32 rxmode;
u32 epcount_mode;
};
#define am35x_usb_regs ((struct am35x_usb_regs *)AM35X_USB_OTG_BASE)
/* USB 2.0 PHY Control */
#define DEVCONF2_PHY_GPIOMODE (1 << 23)
#define DEVCONF2_OTGMODE (3 << 14)
#define DEVCONF2_SESENDEN (1 << 13) /* Vsess_end comparator */
#define DEVCONF2_VBDTCTEN (1 << 12) /* Vbus comparator */
#define DEVCONF2_REFFREQ_24MHZ (2 << 8)
#define DEVCONF2_REFFREQ_26MHZ (7 << 8)
#define DEVCONF2_REFFREQ_13MHZ (6 << 8)
#define DEVCONF2_REFFREQ (0xf << 8)
#define DEVCONF2_PHYCKGD (1 << 7)
#define DEVCONF2_VBUSSENSE (1 << 6)
#define DEVCONF2_PHY_PLLON (1 << 5) /* override PLL suspend */
#define DEVCONF2_RESET (1 << 4)
#define DEVCONF2_PHYPWRDN (1 << 3)
#define DEVCONF2_OTGPWRDN (1 << 2)
#define DEVCONF2_DATPOL (1 << 1)
#endif /* __AM35X_USB_H__ */
source/bootloader/u-boot-2020.01/drivers/usb/musb/musb_core.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Mentor USB OTG Core functionality common for both Host and Device
* functionality.
*
* Copyright (c) 2008 Texas Instruments
*
* Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
*/
#include <common.h>
#include "musb_core.h"
struct musb_regs *musbr;
/*
* program the mentor core to start (enable interrupts, dma, etc.)
*/
void musb_start(void)
{
#if defined(CONFIG_USB_MUSB_HCD)
u8 devctl;
u8 busctl;
#endif
/* disable all interrupts */
writew(0, &musbr->intrtxe);
writew(0, &musbr->intrrxe);
writeb(0, &musbr->intrusbe);
writeb(0, &musbr->testmode);
/* put into basic highspeed mode and start session */
writeb(MUSB_POWER_HSENAB, &musbr->power);
#if defined(CONFIG_USB_MUSB_HCD)
/* Program PHY to use EXT VBUS if required */
if (musb_cfg.extvbus == 1) {
busctl = musb_read_ulpi_buscontrol(musbr);
musb_write_ulpi_buscontrol(musbr, busctl | ULPI_USE_EXTVBUS);
}
devctl = readb(&musbr->devctl);
writeb(devctl | MUSB_DEVCTL_SESSION, &musbr->devctl);
#endif
}
#ifdef MUSB_NO_DYNAMIC_FIFO
# define config_fifo(dir, idx, addr)
#else
# define config_fifo(dir, idx, addr) \
do { \
writeb(idx, &musbr->dir##fifosz); \
writew(fifoaddr >> 3, &musbr->dir##fifoadd); \
} while (0)
#endif
/*
* This function configures the endpoint configuration. The musb hcd or musb
* device implementation can use this function to configure the endpoints
* and set the FIFO sizes. Note: The summation of FIFO sizes of all endpoints
* should not be more than the available FIFO size.
*
* epinfo - Pointer to EP configuration table
* cnt - Number of entries in the EP conf table.
*/
void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt)
{
u16 csr;
u16 fifoaddr = 64; /* First 64 bytes of FIFO reserved for EP0 */
u32 fifosize;
u8 idx;
while (cnt--) {
/* prepare fifosize to write to register */
fifosize = epinfo->epsize >> 3;
idx = ffs(fifosize) - 1;
writeb(epinfo->epnum, &musbr->index);
if (epinfo->epdir) {
/* Configure fifo size and fifo base address */
config_fifo(tx, idx, fifoaddr);
csr = readw(&musbr->txcsr);
#if defined(CONFIG_USB_MUSB_HCD)
/* clear the data toggle bit */
writew(csr | MUSB_TXCSR_CLRDATATOG, &musbr->txcsr);
#endif
/* Flush fifo if required */
if (csr & MUSB_TXCSR_TXPKTRDY)
writew(csr | MUSB_TXCSR_FLUSHFIFO,
&musbr->txcsr);
} else {
/* Configure fifo size and fifo base address */
config_fifo(rx, idx, fifoaddr);
csr = readw(&musbr->rxcsr);
#if defined(CONFIG_USB_MUSB_HCD)
/* clear the data toggle bit */
writew(csr | MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr);
#endif
/* Flush fifo if required */
if (csr & MUSB_RXCSR_RXPKTRDY)
writew(csr | MUSB_RXCSR_FLUSHFIFO,
&musbr->rxcsr);
}
fifoaddr += epinfo->epsize;
epinfo++;
}
}
/*
* This function writes data to endpoint fifo
*
* ep - endpoint number
* length - number of bytes to write to FIFO
* fifo_data - Pointer to data buffer that contains the data to write
*/
__attribute__((weak))
void write_fifo(u8 ep, u32 length, void *fifo_data)
{
u8 *data = (u8 *)fifo_data;
/* select the endpoint index */
writeb(ep, &musbr->index);
/* write the data to the fifo */
while (length--)
writeb(*data++, &musbr->fifox[ep]);
}
/*
* AM35x supports only 32bit read operations so
* use seperate read_fifo() function for it.
*/
#ifndef CONFIG_USB_AM35X
/*
* This function reads data from endpoint fifo
*
* ep - endpoint number
* length - number of bytes to read from FIFO
* fifo_data - pointer to data buffer into which data is read
*/
__attribute__((weak))
void read_fifo(u8 ep, u32 length, void *fifo_data)
{
u8 *data = (u8 *)fifo_data;
/* select the endpoint index */
writeb(ep, &musbr->index);
/* read the data to the fifo */
while (length--)
*data++ = readb(&musbr->fifox[ep]);
}
#endif /* CONFIG_USB_AM35X */
source/bootloader/u-boot-2020.01/drivers/usb/musb/musb_core.h
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/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************
* Copyright 2008 Mentor Graphics Corporation
* Copyright (C) 2008 by Texas Instruments
*
* This file is part of the Inventra Controller Driver for Linux.
******************************************************************/
#ifndef __MUSB_HDRC_DEFS_H__
#define __MUSB_HDRC_DEFS_H__
#include <usb_defs.h>
#include <asm/io.h>
#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
/* EP0 */
struct musb_ep0_regs {
u16 reserved4;
u16 csr0;
u16 reserved5;
u16 reserved6;
u16 count0;
u8 host_type0;
u8 host_naklimit0;
u8 reserved7;
u8 reserved8;
u8 reserved9;
u8 configdata;
};
/* EP 1-15 */
struct musb_epN_regs {
u16 txmaxp;
u16 txcsr;
u16 rxmaxp;
u16 rxcsr;
u16 rxcount;
u8 txtype;
u8 txinterval;
u8 rxtype;
u8 rxinterval;
u8 reserved0;
u8 fifosize;
};
/* Mentor USB core register overlay structure */
#ifndef musb_regs
struct musb_regs {
/* common registers */
u8 faddr;
u8 power;
u16 intrtx;
u16 intrrx;
u16 intrtxe;
u16 intrrxe;
u8 intrusb;
u8 intrusbe;
u16 frame;
u8 index;
u8 testmode;
/* indexed registers */
u16 txmaxp;
u16 txcsr;
u16 rxmaxp;
u16 rxcsr;
u16 rxcount;
u8 txtype;
u8 txinterval;
u8 rxtype;
u8 rxinterval;
u8 reserved0;
u8 fifosize;
/* fifo */
u32 fifox[16];
/* OTG, dynamic FIFO, version & vendor registers */
u8 devctl;
u8 reserved1;
u8 txfifosz;
u8 rxfifosz;
u16 txfifoadd;
u16 rxfifoadd;
u32 vcontrol;
u16 hwvers;
u16 reserved2a[1];
u8 ulpi_busctl;
u8 reserved2b[1];
u16 reserved2[3];
u8 epinfo;
u8 raminfo;
u8 linkinfo;
u8 vplen;
u8 hseof1;
u8 fseof1;
u8 lseof1;
u8 reserved3;
/* target address registers */
struct musb_tar_regs {
u8 txfuncaddr;
u8 reserved0;
u8 txhubaddr;
u8 txhubport;
u8 rxfuncaddr;
u8 reserved1;
u8 rxhubaddr;
u8 rxhubport;
} tar[16];
/*
* endpoint registers
* ep0 elements are valid when array index is 0
* otherwise epN is valid
*/
union musb_ep_regs {
struct musb_ep0_regs ep0;
struct musb_epN_regs epN;
} ep[16];
} __attribute__((packed));
#endif
/*
* MUSB Register bits
*/
/* POWER */
#define MUSB_POWER_ISOUPDATE 0x80
#define MUSB_POWER_SOFTCONN 0x40
#define MUSB_POWER_HSENAB 0x20
#define MUSB_POWER_HSMODE 0x10
#define MUSB_POWER_RESET 0x08
#define MUSB_POWER_RESUME 0x04
#define MUSB_POWER_SUSPENDM 0x02
#define MUSB_POWER_ENSUSPEND 0x01
#define MUSB_POWER_HSMODE_SHIFT 4
/* INTRUSB */
#define MUSB_INTR_SUSPEND 0x01
#define MUSB_INTR_RESUME 0x02
#define MUSB_INTR_RESET 0x04
#define MUSB_INTR_BABBLE 0x04
#define MUSB_INTR_SOF 0x08
#define MUSB_INTR_CONNECT 0x10
#define MUSB_INTR_DISCONNECT 0x20
#define MUSB_INTR_SESSREQ 0x40
#define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */
/* DEVCTL */
#define MUSB_DEVCTL_BDEVICE 0x80
#define MUSB_DEVCTL_FSDEV 0x40
#define MUSB_DEVCTL_LSDEV 0x20
#define MUSB_DEVCTL_VBUS 0x18
#define MUSB_DEVCTL_VBUS_SHIFT 3
#define MUSB_DEVCTL_HM 0x04
#define MUSB_DEVCTL_HR 0x02
#define MUSB_DEVCTL_SESSION 0x01
/* ULPI VBUSCONTROL */
#define ULPI_USE_EXTVBUS 0x01
#define ULPI_USE_EXTVBUSIND 0x02
/* TESTMODE */
#define MUSB_TEST_FORCE_HOST 0x80
#define MUSB_TEST_FIFO_ACCESS 0x40
#define MUSB_TEST_FORCE_FS 0x20
#define MUSB_TEST_FORCE_HS 0x10
#define MUSB_TEST_PACKET 0x08
#define MUSB_TEST_K 0x04
#define MUSB_TEST_J 0x02
#define MUSB_TEST_SE0_NAK 0x01
/* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
#define MUSB_FIFOSZ_DPB 0x10
/* Allocation size (8, 16, 32, ... 4096) */
#define MUSB_FIFOSZ_SIZE 0x0f
/* CSR0 */
#define MUSB_CSR0_FLUSHFIFO 0x0100
#define MUSB_CSR0_TXPKTRDY 0x0002
#define MUSB_CSR0_RXPKTRDY 0x0001
/* CSR0 in Peripheral mode */
#define MUSB_CSR0_P_SVDSETUPEND 0x0080
#define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
#define MUSB_CSR0_P_SENDSTALL 0x0020
#define MUSB_CSR0_P_SETUPEND 0x0010
#define MUSB_CSR0_P_DATAEND 0x0008
#define MUSB_CSR0_P_SENTSTALL 0x0004
/* CSR0 in Host mode */
#define MUSB_CSR0_H_DIS_PING 0x0800
#define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */
#define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */
#define MUSB_CSR0_H_NAKTIMEOUT 0x0080
#define MUSB_CSR0_H_STATUSPKT 0x0040
#define MUSB_CSR0_H_REQPKT 0x0020
#define MUSB_CSR0_H_ERROR 0x0010
#define MUSB_CSR0_H_SETUPPKT 0x0008
#define MUSB_CSR0_H_RXSTALL 0x0004
/* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
#define MUSB_CSR0_P_WZC_BITS \
(MUSB_CSR0_P_SENTSTALL)
#define MUSB_CSR0_H_WZC_BITS \
(MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
| MUSB_CSR0_RXPKTRDY)
/* TxType/RxType */
#define MUSB_TYPE_SPEED 0xc0
#define MUSB_TYPE_SPEED_SHIFT 6
#define MUSB_TYPE_SPEED_HIGH 1
#define MUSB_TYPE_SPEED_FULL 2
#define MUSB_TYPE_SPEED_LOW 3
#define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */
#define MUSB_TYPE_PROTO_SHIFT 4
#define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */
#define MUSB_TYPE_PROTO_BULK 2
#define MUSB_TYPE_PROTO_INTR 3
/* CONFIGDATA */
#define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */
#define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */
#define MUSB_CONFIGDATA_BIGENDIAN 0x20
#define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
#define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
#define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */
#define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
#define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */
/* TXCSR in Peripheral and Host mode */
#define MUSB_TXCSR_AUTOSET 0x8000
#define MUSB_TXCSR_MODE 0x2000
#define MUSB_TXCSR_DMAENAB 0x1000
#define MUSB_TXCSR_FRCDATATOG 0x0800
#define MUSB_TXCSR_DMAMODE 0x0400
#define MUSB_TXCSR_CLRDATATOG 0x0040
#define MUSB_TXCSR_FLUSHFIFO 0x0008
#define MUSB_TXCSR_FIFONOTEMPTY 0x0002
#define MUSB_TXCSR_TXPKTRDY 0x0001
/* TXCSR in Peripheral mode */
#define MUSB_TXCSR_P_ISO 0x4000
#define MUSB_TXCSR_P_INCOMPTX 0x0080
#define MUSB_TXCSR_P_SENTSTALL 0x0020
#define MUSB_TXCSR_P_SENDSTALL 0x0010
#define MUSB_TXCSR_P_UNDERRUN 0x0004
/* TXCSR in Host mode */
#define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200
#define MUSB_TXCSR_H_DATATOGGLE 0x0100
#define MUSB_TXCSR_H_NAKTIMEOUT 0x0080
#define MUSB_TXCSR_H_RXSTALL 0x0020
#define MUSB_TXCSR_H_ERROR 0x0004
#define MUSB_TXCSR_H_DATATOGGLE_SHIFT 8
/* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
#define MUSB_TXCSR_P_WZC_BITS \
(MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
| MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
#define MUSB_TXCSR_H_WZC_BITS \
(MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
| MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
/* RXCSR in Peripheral and Host mode */
#define MUSB_RXCSR_AUTOCLEAR 0x8000
#define MUSB_RXCSR_DMAENAB 0x2000
#define MUSB_RXCSR_DISNYET 0x1000
#define MUSB_RXCSR_PID_ERR 0x1000
#define MUSB_RXCSR_DMAMODE 0x0800
#define MUSB_RXCSR_INCOMPRX 0x0100
#define MUSB_RXCSR_CLRDATATOG 0x0080
#define MUSB_RXCSR_FLUSHFIFO 0x0010
#define MUSB_RXCSR_DATAERROR 0x0008
#define MUSB_RXCSR_FIFOFULL 0x0002
#define MUSB_RXCSR_RXPKTRDY 0x0001
/* RXCSR in Peripheral mode */
#define MUSB_RXCSR_P_ISO 0x4000
#define MUSB_RXCSR_P_SENTSTALL 0x0040
#define MUSB_RXCSR_P_SENDSTALL 0x0020
#define MUSB_RXCSR_P_OVERRUN 0x0004
/* RXCSR in Host mode */
#define MUSB_RXCSR_H_AUTOREQ 0x4000
#define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400
#define MUSB_RXCSR_H_DATATOGGLE 0x0200
#define MUSB_RXCSR_H_RXSTALL 0x0040
#define MUSB_RXCSR_H_REQPKT 0x0020
#define MUSB_RXCSR_H_ERROR 0x0004
#define MUSB_S_RXCSR_H_DATATOGGLE 9
/* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
#define MUSB_RXCSR_P_WZC_BITS \
(MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
| MUSB_RXCSR_RXPKTRDY)
#define MUSB_RXCSR_H_WZC_BITS \
(MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
| MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
/* HUBADDR */
#define MUSB_HUBADDR_MULTI_TT 0x80
/* Endpoint configuration information. Note: The value of endpoint fifo size
* element should be either 8,16,32,64,128,256,512,1024,2048 or 4096. Other
* values are not supported
*/
struct musb_epinfo {
u8 epnum; /* endpoint number */
u8 epdir; /* endpoint direction */
u16 epsize; /* endpoint FIFO size */
};
/*
* Platform specific MUSB configuration. Any platform using the musb
* functionality should create one instance of this structure in the
* platform specific file.
*/
struct musb_config {
struct musb_regs *regs;
u32 timeout;
u8 musb_speed;
u8 extvbus;
};
/* externally defined data */
extern struct musb_config musb_cfg;
extern struct musb_regs *musbr;
/* exported functions */
extern void musb_start(void);
extern void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt);
extern void write_fifo(u8 ep, u32 length, void *fifo_data);
extern void read_fifo(u8 ep, u32 length, void *fifo_data);
static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr)
{
return readb(&musbr->ulpi_busctl);
}
static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val)
{
writeb(val, &musbr->ulpi_busctl);
}
#endif /* __MUSB_HDRC_DEFS_H__ */
source/bootloader/u-boot-2020.01/drivers/usb/musb/musb_debug.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2009 Wind River Systems, Inc.
* Tom Rix <Tom.Rix@windriver.com>
*/
/* Define MUSB_DEBUG before including this file to get debug macros */
#ifdef MUSB_DEBUG
#define MUSB_FLAGS_PRINT(v, x, y) \
if (((v) & MUSB_##x##_##y)) \
serial_printf("\t\t"#y"\n")
static inline void musb_print_pwr(u8 b)
{
serial_printf("\tpower 0x%2.2x\n", b);
MUSB_FLAGS_PRINT(b, POWER, ISOUPDATE);
MUSB_FLAGS_PRINT(b, POWER, SOFTCONN);
MUSB_FLAGS_PRINT(b, POWER, HSENAB);
MUSB_FLAGS_PRINT(b, POWER, HSMODE);
MUSB_FLAGS_PRINT(b, POWER, RESET);
MUSB_FLAGS_PRINT(b, POWER, RESUME);
MUSB_FLAGS_PRINT(b, POWER, SUSPENDM);
MUSB_FLAGS_PRINT(b, POWER, ENSUSPEND);
}
static inline void musb_print_csr0(u16 w)
{
serial_printf("\tcsr0 0x%4.4x\n", w);
MUSB_FLAGS_PRINT(w, CSR0, FLUSHFIFO);
MUSB_FLAGS_PRINT(w, CSR0_P, SVDSETUPEND);
MUSB_FLAGS_PRINT(w, CSR0_P, SVDRXPKTRDY);
MUSB_FLAGS_PRINT(w, CSR0_P, SENDSTALL);
MUSB_FLAGS_PRINT(w, CSR0_P, SETUPEND);
MUSB_FLAGS_PRINT(w, CSR0_P, DATAEND);
MUSB_FLAGS_PRINT(w, CSR0_P, SENTSTALL);
MUSB_FLAGS_PRINT(w, CSR0, TXPKTRDY);
MUSB_FLAGS_PRINT(w, CSR0, RXPKTRDY);
}
static inline void musb_print_intrusb(u8 b)
{
serial_printf("\tintrusb 0x%2.2x\n", b);
MUSB_FLAGS_PRINT(b, INTR, VBUSERROR);
MUSB_FLAGS_PRINT(b, INTR, SESSREQ);
MUSB_FLAGS_PRINT(b, INTR, DISCONNECT);
MUSB_FLAGS_PRINT(b, INTR, CONNECT);
MUSB_FLAGS_PRINT(b, INTR, SOF);
MUSB_FLAGS_PRINT(b, INTR, RESUME);
MUSB_FLAGS_PRINT(b, INTR, SUSPEND);
if (b & MUSB_INTR_BABBLE)
serial_printf("\t\tMUSB_INTR_RESET or MUSB_INTR_BABBLE\n");
}
static inline void musb_print_intrtx(u16 w)
{
serial_printf("\tintrtx 0x%4.4x\n", w);
}
static inline void musb_print_intrrx(u16 w)
{
serial_printf("\tintrx 0x%4.4x\n", w);
}
static inline void musb_print_devctl(u8 b)
{
serial_printf("\tdevctl 0x%2.2x\n", b);
if (b & MUSB_DEVCTL_BDEVICE)
serial_printf("\t\tB device\n");
else
serial_printf("\t\tA device\n");
if (b & MUSB_DEVCTL_FSDEV)
serial_printf("\t\tFast Device -(host mode)\n");
if (b & MUSB_DEVCTL_LSDEV)
serial_printf("\t\tSlow Device -(host mode)\n");
if (b & MUSB_DEVCTL_HM)
serial_printf("\t\tHost mode\n");
else
serial_printf("\t\tPeripherial mode\n");
if (b & MUSB_DEVCTL_HR)
serial_printf("\t\tHost request started(B device)\n");
else
serial_printf("\t\tHost request finished(B device)\n");
if (b & MUSB_DEVCTL_BDEVICE) {
if (b & MUSB_DEVCTL_SESSION)
serial_printf("\t\tStart of session(B device)\n");
else
serial_printf("\t\tEnd of session(B device)\n");
} else {
if (b & MUSB_DEVCTL_SESSION)
serial_printf("\t\tStart of session(A device)\n");
else
serial_printf("\t\tEnd of session(A device)\n");
}
}
static inline void musb_print_config(u8 b)
{
serial_printf("\tconfig 0x%2.2x\n", b);
if (b & MUSB_CONFIGDATA_MPRXE)
serial_printf("\t\tAuto combine rx bulk packets\n");
if (b & MUSB_CONFIGDATA_MPTXE)
serial_printf("\t\tAuto split tx bulk packets\n");
if (b & MUSB_CONFIGDATA_BIGENDIAN)
serial_printf("\t\tBig Endian ordering\n");
else
serial_printf("\t\tLittle Endian ordering\n");
if (b & MUSB_CONFIGDATA_HBRXE)
serial_printf("\t\tHigh speed rx iso endpoint\n");
if (b & MUSB_CONFIGDATA_HBTXE)
serial_printf("\t\tHigh speed tx iso endpoint\n");
if (b & MUSB_CONFIGDATA_DYNFIFO)
serial_printf("\t\tDynamic fifo sizing\n");
if (b & MUSB_CONFIGDATA_SOFTCONE)
serial_printf("\t\tSoft Connect\n");
if (b & MUSB_CONFIGDATA_UTMIDW)
serial_printf("\t\t16 bit data width\n");
else
serial_printf("\t\t8 bit data width\n");
}
static inline void musb_print_rxmaxp(u16 w)
{
serial_printf("\trxmaxp 0x%4.4x\n", w);
}
static inline void musb_print_rxcsr(u16 w)
{
serial_printf("\trxcsr 0x%4.4x\n", w);
MUSB_FLAGS_PRINT(w, RXCSR, AUTOCLEAR);
MUSB_FLAGS_PRINT(w, RXCSR, DMAENAB);
MUSB_FLAGS_PRINT(w, RXCSR, DISNYET);
MUSB_FLAGS_PRINT(w, RXCSR, PID_ERR);
MUSB_FLAGS_PRINT(w, RXCSR, DMAMODE);
MUSB_FLAGS_PRINT(w, RXCSR, CLRDATATOG);
MUSB_FLAGS_PRINT(w, RXCSR, FLUSHFIFO);
MUSB_FLAGS_PRINT(w, RXCSR, DATAERROR);
MUSB_FLAGS_PRINT(w, RXCSR, FIFOFULL);
MUSB_FLAGS_PRINT(w, RXCSR, RXPKTRDY);
MUSB_FLAGS_PRINT(w, RXCSR_P, SENTSTALL);
MUSB_FLAGS_PRINT(w, RXCSR_P, SENDSTALL);
MUSB_FLAGS_PRINT(w, RXCSR_P, OVERRUN);
if (w & MUSB_RXCSR_P_ISO)
serial_printf("\t\tiso mode\n");
else
serial_printf("\t\tbulk mode\n");
}
static inline void musb_print_txmaxp(u16 w)
{
serial_printf("\ttxmaxp 0x%4.4x\n", w);
}
static inline void musb_print_txcsr(u16 w)
{
serial_printf("\ttxcsr 0x%4.4x\n", w);
MUSB_FLAGS_PRINT(w, TXCSR, TXPKTRDY);
MUSB_FLAGS_PRINT(w, TXCSR, FIFONOTEMPTY);
MUSB_FLAGS_PRINT(w, TXCSR, FLUSHFIFO);
MUSB_FLAGS_PRINT(w, TXCSR, CLRDATATOG);
MUSB_FLAGS_PRINT(w, TXCSR_P, UNDERRUN);
MUSB_FLAGS_PRINT(w, TXCSR_P, SENTSTALL);
MUSB_FLAGS_PRINT(w, TXCSR_P, SENDSTALL);
if (w & MUSB_TXCSR_MODE)
serial_printf("\t\tTX mode\n");
else
serial_printf("\t\tRX mode\n");
}
#else
/* stubs */
#define musb_print_pwr(b)
#define musb_print_csr0(w)
#define musb_print_intrusb(b)
#define musb_print_intrtx(w)
#define musb_print_intrrx(w)
#define musb_print_devctl(b)
#define musb_print_config(b)
#define musb_print_rxmaxp(w)
#define musb_print_rxcsr(w)
#define musb_print_txmaxp(w)
#define musb_print_txcsr(w)
#endif /* MUSB_DEBUG */
source/bootloader/u-boot-2020.01/drivers/usb/musb/musb_hcd.c
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source/bootloader/u-boot-2020.01/drivers/usb/musb/musb_hcd.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Mentor USB OTG Core host controller driver.
*
* Copyright (c) 2008 Texas Instruments
*
* Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
*/
#ifndef __MUSB_HCD_H__
#define __MUSB_HCD_H__
#include "musb_core.h"
#ifdef CONFIG_USB_KEYBOARD
#include <stdio_dev.h>
extern unsigned char new[];
#endif
#ifndef CONFIG_USB_MUSB_TIMEOUT
# define CONFIG_USB_MUSB_TIMEOUT 100000
#endif
/* This defines the endpoint number used for control transfers */
#define MUSB_CONTROL_EP 0
/* This defines the endpoint number used for bulk transfer */
#ifndef MUSB_BULK_EP
# define MUSB_BULK_EP 1
#endif
/* This defines the endpoint number used for interrupt transfer */
#define MUSB_INTR_EP 2
/* Determine the operating speed of MUSB core */
#define musb_ishighspeed() \
((readb(&musbr->power) & MUSB_POWER_HSMODE) \
>> MUSB_POWER_HSMODE_SHIFT)
/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
/* destination of request */
#define RH_INTERFACE 0x01
#define RH_ENDPOINT 0x02
#define RH_OTHER 0x03
#define RH_CLASS 0x20
#define RH_VENDOR 0x40
/* Requests: bRequest << 8 | bmRequestType */
#define RH_GET_STATUS 0x0080
#define RH_CLEAR_FEATURE 0x0100
#define RH_SET_FEATURE 0x0300
#define RH_SET_ADDRESS 0x0500
#define RH_GET_DESCRIPTOR 0x0680
#define RH_SET_DESCRIPTOR 0x0700
#define RH_GET_CONFIGURATION 0x0880
#define RH_SET_CONFIGURATION 0x0900
#define RH_GET_STATE 0x0280
#define RH_GET_INTERFACE 0x0A80
#define RH_SET_INTERFACE 0x0B00
#define RH_SYNC_FRAME 0x0C80
/* Our Vendor Specific Request */
#define RH_SET_EP 0x2000
/* Hub port features */
#define RH_PORT_CONNECTION 0x00
#define RH_PORT_ENABLE 0x01
#define RH_PORT_SUSPEND 0x02
#define RH_PORT_OVER_CURRENT 0x03
#define RH_PORT_RESET 0x04
#define RH_PORT_POWER 0x08
#define RH_PORT_LOW_SPEED 0x09
#define RH_C_PORT_CONNECTION 0x10
#define RH_C_PORT_ENABLE 0x11
#define RH_C_PORT_SUSPEND 0x12
#define RH_C_PORT_OVER_CURRENT 0x13
#define RH_C_PORT_RESET 0x14
/* Hub features */
#define RH_C_HUB_LOCAL_POWER 0x00
#define RH_C_HUB_OVER_CURRENT 0x01
#define RH_DEVICE_REMOTE_WAKEUP 0x00
#define RH_ENDPOINT_STALL 0x01
#define RH_ACK 0x01
#define RH_REQ_ERR -1
#define RH_NACK 0x00
/* extern functions */
extern int musb_platform_init(void);
extern void musb_platform_deinit(void);
#endif /* __MUSB_HCD_H__ */
source/bootloader/u-boot-2020.01/drivers/usb/musb/musb_udc.c
+957
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2009 Wind River Systems, Inc.
* Tom Rix <Tom.Rix@windriver.com>
*
* This file is a rewrite of the usb device part of
* repository git.omapzoom.org/repo/u-boot.git, branch master,
* file cpu/omap3/fastboot.c
*
* This is the unique part of its copyright :
*
* -------------------------------------------------------------------------
*
* (C) Copyright 2008 - 2009
* Windriver, <www.windriver.com>
* Tom Rix <Tom.Rix@windriver.com>
*
* -------------------------------------------------------------------------
*
* The details of connecting the device to the uboot usb device subsystem
* came from the old omap3 repository www.sakoman.net/u-boot-omap3.git,
* branch omap3-dev-usb, file drivers/usb/usbdcore_musb.c
*
* This is the unique part of its copyright :
*
* -------------------------------------------------------------------------
*
* (C) Copyright 2008 Texas Instruments Incorporated.
*
* Based on
* u-boot OMAP1510 USB drivers (drivers/usbdcore_omap1510.c)
* twl4030 init based on linux (drivers/i2c/chips/twl4030_usb.c)
*
* Author: Diego Dompe (diego.dompe@ridgerun.com)
* Atin Malaviya (atin.malaviya@gmail.com)
*
* -------------------------------------------------------------------------
*/
#include <common.h>
#include <serial.h>
#include <usbdevice.h>
#include <usb/udc.h>
#include "../gadget/ep0.h"
#include "musb_core.h"
#if defined(CONFIG_USB_OMAP3)
#include "omap3.h"
#elif defined(CONFIG_USB_AM35X)
#include "am35x.h"
#endif
/* Define MUSB_DEBUG for debugging */
/* #define MUSB_DEBUG */
#include "musb_debug.h"
#define MAX_ENDPOINT 15
#define GET_ENDPOINT(dev,ep) \
(((struct usb_device_instance *)(dev))->bus->endpoint_array + ep)
#define SET_EP0_STATE(s) \
do { \
if ((0 <= (s)) && (SET_ADDRESS >= (s))) { \
if ((s) != ep0_state) { \
if ((debug_setup) && (debug_level > 1)) \
serial_printf("INFO : Changing state " \
"from %s to %s in %s at " \
"line %d\n", \
ep0_state_strings[ep0_state],\
ep0_state_strings[s], \
__PRETTY_FUNCTION__, \
__LINE__); \
ep0_state = s; \
} \
} else { \
if (debug_level > 0) \
serial_printf("Error at %s %d with setting " \
"state %d is invalid\n", \
__PRETTY_FUNCTION__, __LINE__, s); \
} \
} while (0)
/* static implies these initialized to 0 or NULL */
static int debug_setup;
static int debug_level;
static struct musb_epinfo epinfo[MAX_ENDPOINT * 2 + 2];
static enum ep0_state_enum {
IDLE = 0,
TX,
RX,
SET_ADDRESS
} ep0_state = IDLE;
static char *ep0_state_strings[4] = {
"IDLE",
"TX",
"RX",
"SET_ADDRESS",
};
static struct urb *ep0_urb;
struct usb_endpoint_instance *ep0_endpoint;
static struct usb_device_instance *udc_device;
static int enabled;
#ifdef MUSB_DEBUG
static void musb_db_regs(void)
{
u8 b;
u16 w;
b = readb(&musbr->faddr);
serial_printf("\tfaddr 0x%2.2x\n", b);
b = readb(&musbr->power);
musb_print_pwr(b);
w = readw(&musbr->ep[0].ep0.csr0);
musb_print_csr0(w);
b = readb(&musbr->devctl);
musb_print_devctl(b);
b = readb(&musbr->ep[0].ep0.configdata);
musb_print_config(b);
w = readw(&musbr->frame);
serial_printf("\tframe 0x%4.4x\n", w);
b = readb(&musbr->index);
serial_printf("\tindex 0x%2.2x\n", b);
w = readw(&musbr->ep[1].epN.rxmaxp);
musb_print_rxmaxp(w);
w = readw(&musbr->ep[1].epN.rxcsr);
musb_print_rxcsr(w);
w = readw(&musbr->ep[1].epN.txmaxp);
musb_print_txmaxp(w);
w = readw(&musbr->ep[1].epN.txcsr);
musb_print_txcsr(w);
}
#else
#define musb_db_regs()
#endif /* DEBUG_MUSB */
static void musb_peri_softconnect(void)
{
u8 power, devctl;
/* Power off MUSB */
power = readb(&musbr->power);
power &= ~MUSB_POWER_SOFTCONN;
writeb(power, &musbr->power);
/* Read intr to clear */
readb(&musbr->intrusb);
readw(&musbr->intrrx);
readw(&musbr->intrtx);
udelay(1000 * 1000); /* 1 sec */
/* Power on MUSB */
power = readb(&musbr->power);
power |= MUSB_POWER_SOFTCONN;
/*
* The usb device interface is usb 1.1
* Disable 2.0 high speed by clearring the hsenable bit.
*/
power &= ~MUSB_POWER_HSENAB;
writeb(power, &musbr->power);
/* Check if device is in b-peripheral mode */
devctl = readb(&musbr->devctl);
if (!(devctl & MUSB_DEVCTL_BDEVICE) ||
(devctl & MUSB_DEVCTL_HM)) {
serial_printf("ERROR : Unsupport USB mode\n");
serial_printf("Check that mini-B USB cable is attached "
"to the device\n");
}
if (debug_setup && (debug_level > 1))
musb_db_regs();
}
static void musb_peri_reset(void)
{
if ((debug_setup) && (debug_level > 1))
serial_printf("INFO : %s reset\n", __PRETTY_FUNCTION__);
if (ep0_endpoint)
ep0_endpoint->endpoint_address = 0xff;
/* Sync sw and hw addresses */
writeb(udc_device->address, &musbr->faddr);
SET_EP0_STATE(IDLE);
}
static void musb_peri_resume(void)
{
/* noop */
}
static void musb_peri_ep0_stall(void)
{
u16 csr0;
csr0 = readw(&musbr->ep[0].ep0.csr0);
csr0 |= MUSB_CSR0_P_SENDSTALL;
writew(csr0, &musbr->ep[0].ep0.csr0);
if ((debug_setup) && (debug_level > 1))
serial_printf("INFO : %s stall\n", __PRETTY_FUNCTION__);
}
static void musb_peri_ep0_ack_req(void)
{
u16 csr0;
csr0 = readw(&musbr->ep[0].ep0.csr0);
csr0 |= MUSB_CSR0_P_SVDRXPKTRDY;
writew(csr0, &musbr->ep[0].ep0.csr0);
}
static void musb_ep0_tx_ready(void)
{
u16 csr0;
csr0 = readw(&musbr->ep[0].ep0.csr0);
csr0 |= MUSB_CSR0_TXPKTRDY;
writew(csr0, &musbr->ep[0].ep0.csr0);
}
static void musb_ep0_tx_ready_and_last(void)
{
u16 csr0;
csr0 = readw(&musbr->ep[0].ep0.csr0);
csr0 |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_P_DATAEND);
writew(csr0, &musbr->ep[0].ep0.csr0);
}
static void musb_peri_ep0_last(void)
{
u16 csr0;
csr0 = readw(&musbr->ep[0].ep0.csr0);
csr0 |= MUSB_CSR0_P_DATAEND;
writew(csr0, &musbr->ep[0].ep0.csr0);
}
static void musb_peri_ep0_set_address(void)
{
u8 faddr;
writeb(udc_device->address, &musbr->faddr);
/* Verify */
faddr = readb(&musbr->faddr);
if (udc_device->address == faddr) {
SET_EP0_STATE(IDLE);
usbd_device_event_irq(udc_device, DEVICE_ADDRESS_ASSIGNED, 0);
if ((debug_setup) && (debug_level > 1))
serial_printf("INFO : %s Address set to %d\n",
__PRETTY_FUNCTION__, udc_device->address);
} else {
if (debug_level > 0)
serial_printf("ERROR : %s Address missmatch "
"sw %d vs hw %d\n",
__PRETTY_FUNCTION__,
udc_device->address, faddr);
}
}
static void musb_peri_rx_ack(unsigned int ep)
{
u16 peri_rxcsr;
peri_rxcsr = readw(&musbr->ep[ep].epN.rxcsr);
peri_rxcsr &= ~MUSB_RXCSR_RXPKTRDY;
writew(peri_rxcsr, &musbr->ep[ep].epN.rxcsr);
}
static void musb_peri_tx_ready(unsigned int ep)
{
u16 peri_txcsr;
peri_txcsr = readw(&musbr->ep[ep].epN.txcsr);
peri_txcsr |= MUSB_TXCSR_TXPKTRDY;
writew(peri_txcsr, &musbr->ep[ep].epN.txcsr);
}
static void musb_peri_ep0_zero_data_request(int err)
{
musb_peri_ep0_ack_req();
if (err) {
musb_peri_ep0_stall();
SET_EP0_STATE(IDLE);
} else {
musb_peri_ep0_last();
/* USBD state */
switch (ep0_urb->device_request.bRequest) {
case USB_REQ_SET_ADDRESS:
if ((debug_setup) && (debug_level > 1))
serial_printf("INFO : %s received set "
"address\n", __PRETTY_FUNCTION__);
break;
case USB_REQ_SET_CONFIGURATION:
if ((debug_setup) && (debug_level > 1))
serial_printf("INFO : %s Configured\n",
__PRETTY_FUNCTION__);
usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0);
break;
}
/* EP0 state */
if (USB_REQ_SET_ADDRESS == ep0_urb->device_request.bRequest) {
SET_EP0_STATE(SET_ADDRESS);
} else {
SET_EP0_STATE(IDLE);
}
}
}
static void musb_peri_ep0_rx_data_request(void)
{
/*
* This is the completion of the data OUT / RX
*
* Host is sending data to ep0 that is not
* part of setup. This comes from the cdc_recv_setup
* op that is device specific.
*
*/
musb_peri_ep0_ack_req();
ep0_endpoint->rcv_urb = ep0_urb;
ep0_urb->actual_length = 0;
SET_EP0_STATE(RX);
}
static void musb_peri_ep0_tx_data_request(int err)
{
if (err) {
musb_peri_ep0_stall();
SET_EP0_STATE(IDLE);
} else {
musb_peri_ep0_ack_req();
ep0_endpoint->tx_urb = ep0_urb;
ep0_endpoint->sent = 0;
SET_EP0_STATE(TX);
}
}
static void musb_peri_ep0_idle(void)
{
u16 count0;
int err;
u16 csr0;
/*
* Verify addresses
* A lot of confusion can be caused if the address
* in software, udc layer, does not agree with the
* hardware. Since the setting of the hardware address
* must be set after the set address request, the
* usb state machine is out of sync for a few frame.
* It is a good idea to run this check when changes
* are made to the state machine.
*/
if ((debug_level > 0) &&
(ep0_state != SET_ADDRESS)) {
u8 faddr;
faddr = readb(&musbr->faddr);
if (udc_device->address != faddr) {
serial_printf("ERROR : %s addresses do not"
"match sw %d vs hw %d\n",
__PRETTY_FUNCTION__,
udc_device->address, faddr);
udelay(1000 * 1000);
hang();
}
}
csr0 = readw(&musbr->ep[0].ep0.csr0);
if (!(MUSB_CSR0_RXPKTRDY & csr0))
goto end;
count0 = readw(&musbr->ep[0].ep0.count0);
if (count0 == 0)
goto end;
if (count0 != 8) {
if ((debug_setup) && (debug_level > 1))
serial_printf("WARN : %s SETUP incorrect size %d\n",
__PRETTY_FUNCTION__, count0);
musb_peri_ep0_stall();
goto end;
}
read_fifo(0, count0, &ep0_urb->device_request);
if (debug_level > 2)
print_usb_device_request(&ep0_urb->device_request);
if (ep0_urb->device_request.wLength == 0) {
err = ep0_recv_setup(ep0_urb);
/* Zero data request */
musb_peri_ep0_zero_data_request(err);
} else {
/* Is data coming or going ? */
u8 reqType = ep0_urb->device_request.bmRequestType;
if (USB_REQ_DEVICE2HOST == (reqType & USB_REQ_DIRECTION_MASK)) {
err = ep0_recv_setup(ep0_urb);
/* Device to host */
musb_peri_ep0_tx_data_request(err);
} else {
/*
* Host to device
*
* The RX routine will call ep0_recv_setup
* when the data packet has arrived.
*/
musb_peri_ep0_rx_data_request();
}
}
end:
return;
}
static void musb_peri_ep0_rx(void)
{
/*
* This is the completion of the data OUT / RX
*
* Host is sending data to ep0 that is not
* part of setup. This comes from the cdc_recv_setup
* op that is device specific.
*
* Pass the data back to driver ep0_recv_setup which
* should give the cdc_recv_setup the chance to handle
* the rx
*/
u16 csr0;
u16 count0;
if (debug_level > 3) {
if (0 != ep0_urb->actual_length) {
serial_printf("%s finished ? %d of %d\n",
__PRETTY_FUNCTION__,
ep0_urb->actual_length,
ep0_urb->device_request.wLength);
}
}
if (ep0_urb->device_request.wLength == ep0_urb->actual_length) {
musb_peri_ep0_last();
SET_EP0_STATE(IDLE);
ep0_recv_setup(ep0_urb);
return;
}
csr0 = readw(&musbr->ep[0].ep0.csr0);
if (!(MUSB_CSR0_RXPKTRDY & csr0))
return;
count0 = readw(&musbr->ep[0].ep0.count0);
if (count0) {
struct usb_endpoint_instance *endpoint;
u32 length;
u8 *data;
endpoint = ep0_endpoint;
if (endpoint && endpoint->rcv_urb) {
struct urb *urb = endpoint->rcv_urb;
unsigned int remaining_space = urb->buffer_length -
urb->actual_length;
if (remaining_space) {
int urb_bad = 0; /* urb is good */
if (count0 > remaining_space)
length = remaining_space;
else
length = count0;
data = (u8 *) urb->buffer_data;
data += urb->actual_length;
/* The common musb fifo reader */
read_fifo(0, length, data);
musb_peri_ep0_ack_req();
/*
* urb's actual_length is updated in
* usbd_rcv_complete
*/
usbd_rcv_complete(endpoint, length, urb_bad);
} else {
if (debug_level > 0)
serial_printf("ERROR : %s no space in "
"rcv buffer\n",
__PRETTY_FUNCTION__);
}
} else {
if (debug_level > 0)
serial_printf("ERROR : %s problem with "
"endpoint\n",
__PRETTY_FUNCTION__);
}
} else {
if (debug_level > 0)
serial_printf("ERROR : %s with nothing to do\n",
__PRETTY_FUNCTION__);
}
}
static void musb_peri_ep0_tx(void)
{
u16 csr0;
int transfer_size = 0;
unsigned int p, pm;
csr0 = readw(&musbr->ep[0].ep0.csr0);
/* Check for pending tx */
if (csr0 & MUSB_CSR0_TXPKTRDY)
goto end;
/* Check if this is the last packet sent */
if (ep0_endpoint->sent >= ep0_urb->actual_length) {
SET_EP0_STATE(IDLE);
goto end;
}
transfer_size = ep0_urb->actual_length - ep0_endpoint->sent;
/* Is the transfer size negative ? */
if (transfer_size <= 0) {
if (debug_level > 0)
serial_printf("ERROR : %s problem with the"
" transfer size %d\n",
__PRETTY_FUNCTION__,
transfer_size);
SET_EP0_STATE(IDLE);
goto end;
}
/* Truncate large transfers to the fifo size */
if (transfer_size > ep0_endpoint->tx_packetSize)
transfer_size = ep0_endpoint->tx_packetSize;
write_fifo(0, transfer_size, &ep0_urb->buffer[ep0_endpoint->sent]);
ep0_endpoint->sent += transfer_size;
/* Done or more to send ? */
if (ep0_endpoint->sent >= ep0_urb->actual_length)
musb_ep0_tx_ready_and_last();
else
musb_ep0_tx_ready();
/* Wait a bit */
pm = 10;
for (p = 0; p < pm; p++) {
csr0 = readw(&musbr->ep[0].ep0.csr0);
if (!(csr0 & MUSB_CSR0_TXPKTRDY))
break;
/* Double the delay. */
udelay(1 << pm);
}
if ((ep0_endpoint->sent >= ep0_urb->actual_length) && (p < pm))
SET_EP0_STATE(IDLE);
end:
return;
}
static void musb_peri_ep0(void)
{
u16 csr0;
if (SET_ADDRESS == ep0_state)
return;
csr0 = readw(&musbr->ep[0].ep0.csr0);
/* Error conditions */
if (MUSB_CSR0_P_SENTSTALL & csr0) {
csr0 &= ~MUSB_CSR0_P_SENTSTALL;
writew(csr0, &musbr->ep[0].ep0.csr0);
SET_EP0_STATE(IDLE);
}
if (MUSB_CSR0_P_SETUPEND & csr0) {
csr0 |= MUSB_CSR0_P_SVDSETUPEND;
writew(csr0, &musbr->ep[0].ep0.csr0);
SET_EP0_STATE(IDLE);
if ((debug_setup) && (debug_level > 1))
serial_printf("WARN: %s SETUPEND\n",
__PRETTY_FUNCTION__);
}
/* Normal states */
if (IDLE == ep0_state)
musb_peri_ep0_idle();
if (TX == ep0_state)
musb_peri_ep0_tx();
if (RX == ep0_state)
musb_peri_ep0_rx();
}
static void musb_peri_rx_ep(unsigned int ep)
{
u16 peri_rxcount;
u8 peri_rxcsr = readw(&musbr->ep[ep].epN.rxcsr);
if (!(peri_rxcsr & MUSB_RXCSR_RXPKTRDY)) {
if (debug_level > 0)
serial_printf("ERROR : %s %d without MUSB_RXCSR_RXPKTRDY set\n",
__PRETTY_FUNCTION__, ep);
return;
}
peri_rxcount = readw(&musbr->ep[ep].epN.rxcount);
if (peri_rxcount) {
struct usb_endpoint_instance *endpoint;
u32 length;
u8 *data;
endpoint = GET_ENDPOINT(udc_device, ep);
if (endpoint && endpoint->rcv_urb) {
struct urb *urb = endpoint->rcv_urb;
unsigned int remaining_space = urb->buffer_length -
urb->actual_length;
if (remaining_space) {
int urb_bad = 0; /* urb is good */
if (peri_rxcount > remaining_space)
length = remaining_space;
else
length = peri_rxcount;
data = (u8 *) urb->buffer_data;
data += urb->actual_length;
/* The common musb fifo reader */
read_fifo(ep, length, data);
musb_peri_rx_ack(ep);
/*
* urb's actual_length is updated in
* usbd_rcv_complete
*/
usbd_rcv_complete(endpoint, length, urb_bad);
} else {
if (debug_level > 0)
serial_printf("ERROR : %s %d no space "
"in rcv buffer\n",
__PRETTY_FUNCTION__, ep);
}
} else {
if (debug_level > 0)
serial_printf("ERROR : %s %d problem with "
"endpoint\n",
__PRETTY_FUNCTION__, ep);
}
} else {
if (debug_level > 0)
serial_printf("ERROR : %s %d with nothing to do\n",
__PRETTY_FUNCTION__, ep);
}
}
static void musb_peri_rx(u16 intr)
{
unsigned int ep;
/* Check for EP0 */
if (0x01 & intr)
musb_peri_ep0();
for (ep = 1; ep < 16; ep++) {
if ((1 << ep) & intr)
musb_peri_rx_ep(ep);
}
}
static void musb_peri_tx(u16 intr)
{
/* Check for EP0 */
if (0x01 & intr)
musb_peri_ep0_tx();
/*
* Use this in the future when handling epN tx
*
* u8 ep;
*
* for (ep = 1; ep < 16; ep++) {
* if ((1 << ep) & intr) {
* / * handle tx for this endpoint * /
* }
* }
*/
}
void udc_irq(void)
{
/* This is a high freq called function */
if (enabled) {
u8 intrusb;
intrusb = readb(&musbr->intrusb);
/*
* See drivers/usb/gadget/mpc8xx_udc.c for
* state diagram going from detached through
* configuration.
*/
if (MUSB_INTR_RESUME & intrusb) {
usbd_device_event_irq(udc_device,
DEVICE_BUS_ACTIVITY, 0);
musb_peri_resume();
}
musb_peri_ep0();
if (MUSB_INTR_RESET & intrusb) {
usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
musb_peri_reset();
}
if (MUSB_INTR_DISCONNECT & intrusb) {
/* cable unplugged from hub/host */
usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
musb_peri_reset();
usbd_device_event_irq(udc_device, DEVICE_HUB_RESET, 0);
}
if (MUSB_INTR_SOF & intrusb) {
usbd_device_event_irq(udc_device,
DEVICE_BUS_ACTIVITY, 0);
musb_peri_resume();
}
if (MUSB_INTR_SUSPEND & intrusb) {
usbd_device_event_irq(udc_device,
DEVICE_BUS_INACTIVE, 0);
}
if (ep0_state != SET_ADDRESS) {
u16 intrrx, intrtx;
intrrx = readw(&musbr->intrrx);
intrtx = readw(&musbr->intrtx);
if (intrrx)
musb_peri_rx(intrrx);
if (intrtx)
musb_peri_tx(intrtx);
} else {
if (MUSB_INTR_SOF & intrusb) {
u8 faddr;
faddr = readb(&musbr->faddr);
/*
* Setting of the address can fail.
* Normally it succeeds the second time.
*/
if (udc_device->address != faddr)
musb_peri_ep0_set_address();
}
}
}
}
void udc_set_nak(int ep_num)
{
/* noop */
}
void udc_unset_nak(int ep_num)
{
/* noop */
}
int udc_endpoint_write(struct usb_endpoint_instance *endpoint)
{
int ret = 0;
/* Transmit only if the hardware is available */
if (endpoint->tx_urb && endpoint->state == 0) {
unsigned int ep = endpoint->endpoint_address &
USB_ENDPOINT_NUMBER_MASK;
u16 peri_txcsr = readw(&musbr->ep[ep].epN.txcsr);
/* Error conditions */
if (peri_txcsr & MUSB_TXCSR_P_UNDERRUN) {
peri_txcsr &= ~MUSB_TXCSR_P_UNDERRUN;
writew(peri_txcsr, &musbr->ep[ep].epN.txcsr);
}
if (debug_level > 1)
musb_print_txcsr(peri_txcsr);
/* Check if a packet is waiting to be sent */
if (!(peri_txcsr & MUSB_TXCSR_TXPKTRDY)) {
u32 length;
u8 *data;
struct urb *urb = endpoint->tx_urb;
unsigned int remaining_packet = urb->actual_length -
endpoint->sent;
if (endpoint->tx_packetSize < remaining_packet)
length = endpoint->tx_packetSize;
else
length = remaining_packet;
data = (u8 *) urb->buffer;
data += endpoint->sent;
/* common musb fifo function */
write_fifo(ep, length, data);
musb_peri_tx_ready(ep);
endpoint->last = length;
/* usbd_tx_complete will take care of updating 'sent' */
usbd_tx_complete(endpoint);
}
} else {
if (debug_level > 0)
serial_printf("ERROR : %s Problem with urb %p "
"or ep state %d\n",
__PRETTY_FUNCTION__,
endpoint->tx_urb, endpoint->state);
}
return ret;
}
void udc_setup_ep(struct usb_device_instance *device, unsigned int id,
struct usb_endpoint_instance *endpoint)
{
if (0 == id) {
/* EP0 */
ep0_endpoint = endpoint;
ep0_endpoint->endpoint_address = 0xff;
ep0_urb = usbd_alloc_urb(device, endpoint);
} else if (MAX_ENDPOINT >= id) {
int ep_addr;
/* Check the direction */
ep_addr = endpoint->endpoint_address;
if (USB_DIR_IN == (ep_addr & USB_ENDPOINT_DIR_MASK)) {
/* IN */
epinfo[(id * 2) + 1].epsize = endpoint->tx_packetSize;
} else {
/* OUT */
epinfo[id * 2].epsize = endpoint->rcv_packetSize;
}
musb_configure_ep(&epinfo[0], ARRAY_SIZE(epinfo));
} else {
if (debug_level > 0)
serial_printf("ERROR : %s endpoint request %d "
"exceeds maximum %d\n",
__PRETTY_FUNCTION__, id, MAX_ENDPOINT);
}
}
void udc_connect(void)
{
/* noop */
}
void udc_disconnect(void)
{
/* noop */
}
void udc_enable(struct usb_device_instance *device)
{
/* Save the device structure pointer */
udc_device = device;
enabled = 1;
}
void udc_disable(void)
{
enabled = 0;
}
void udc_startup_events(struct usb_device_instance *device)
{
/* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */
usbd_device_event_irq(device, DEVICE_INIT, 0);
/*
* The DEVICE_CREATE event puts the USB device in the state
* STATE_ATTACHED.
*/
usbd_device_event_irq(device, DEVICE_CREATE, 0);
/* Resets the address to 0 */
usbd_device_event_irq(device, DEVICE_RESET, 0);
udc_enable(device);
}
int udc_init(void)
{
int ret;
int ep_loop;
ret = musb_platform_init();
if (ret < 0)
goto end;
/* Configure all the endpoint FIFO's and start usb controller */
musbr = musb_cfg.regs;
/* Initialize the endpoints */
for (ep_loop = 0; ep_loop <= MAX_ENDPOINT * 2; ep_loop++) {
epinfo[ep_loop].epnum = (ep_loop / 2) + 1;
epinfo[ep_loop].epdir = ep_loop % 2; /* OUT, IN */
epinfo[ep_loop].epsize = 0;
}
musb_peri_softconnect();
ret = 0;
end:
return ret;
}
source/bootloader/u-boot-2020.01/drivers/usb/musb/omap3.c
+145
View File
@@ -0,0 +1,145 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2009 Wind River Systems, Inc.
* Tom Rix <Tom.Rix@windriver.com>
*
* This is file is based on
* repository git.gitorious.org/u-boot-omap3/mainline.git,
* branch omap3-dev-usb, file drivers/usb/host/omap3530_usb.c
*
* This is the unique part of its copyright :
*
* ------------------------------------------------------------------------
*
* Copyright (c) 2009 Texas Instruments
*
* ------------------------------------------------------------------------
*/
#include <serial.h>
#include <asm/omap_common.h>
#include <twl4030.h>
#include <twl6030.h>
#include "omap3.h"
static int platform_needs_initialization = 1;
struct musb_config musb_cfg = {
.regs = (struct musb_regs *)MENTOR_USB0_BASE,
.timeout = OMAP3_USB_TIMEOUT,
.musb_speed = 0,
};
/*
* OMAP3 USB OTG registers.
*/
struct omap3_otg_regs {
u32 revision;
u32 sysconfig;
u32 sysstatus;
u32 interfsel;
u32 simenable;
u32 forcestdby;
};
static struct omap3_otg_regs *otg;
#define OMAP3_OTG_SYSCONFIG_SMART_STANDBY_MODE 0x2000
#define OMAP3_OTG_SYSCONFIG_NO_STANDBY_MODE 0x1000
#define OMAP3_OTG_SYSCONFIG_SMART_IDLE_MODE 0x0010
#define OMAP3_OTG_SYSCONFIG_NO_IDLE_MODE 0x0008
#define OMAP3_OTG_SYSCONFIG_ENABLEWAKEUP 0x0004
#define OMAP3_OTG_SYSCONFIG_SOFTRESET 0x0002
#define OMAP3_OTG_SYSCONFIG_AUTOIDLE 0x0001
#define OMAP3_OTG_SYSSTATUS_RESETDONE 0x0001
/* OMAP4430 has an internal PHY, use it */
#ifdef CONFIG_OMAP44XX
#define OMAP3_OTG_INTERFSEL_OMAP 0x0000
#else
#define OMAP3_OTG_INTERFSEL_OMAP 0x0001
#endif
#define OMAP3_OTG_FORCESTDBY_STANDBY 0x0001
#ifdef DEBUG_MUSB_OMAP3
static void musb_db_otg_regs(void)
{
u32 l;
l = readl(&otg->revision);
serial_printf("OTG_REVISION 0x%x\n", l);
l = readl(&otg->sysconfig);
serial_printf("OTG_SYSCONFIG 0x%x\n", l);
l = readl(&otg->sysstatus);
serial_printf("OTG_SYSSTATUS 0x%x\n", l);
l = readl(&otg->interfsel);
serial_printf("OTG_INTERFSEL 0x%x\n", l);
l = readl(&otg->forcestdby);
serial_printf("OTG_FORCESTDBY 0x%x\n", l);
}
#endif
int musb_platform_init(void)
{
int ret = -1;
if (platform_needs_initialization) {
u32 stdby;
/*
* OMAP3EVM uses ISP1504 phy and so
* twl4030 related init is not required.
*/
#ifdef CONFIG_TWL4030_USB
if (twl4030_usb_ulpi_init()) {
serial_printf("ERROR: %s Could not initialize PHY\n",
__PRETTY_FUNCTION__);
goto end;
}
#endif
#ifdef CONFIG_TWL6030_POWER
twl6030_usb_device_settings();
#endif
otg = (struct omap3_otg_regs *)OMAP3_OTG_BASE;
/* Set OTG to always be on */
writel(OMAP3_OTG_SYSCONFIG_NO_STANDBY_MODE |
OMAP3_OTG_SYSCONFIG_NO_IDLE_MODE, &otg->sysconfig);
/* Set the interface */
writel(OMAP3_OTG_INTERFSEL_OMAP, &otg->interfsel);
/* Clear force standby */
stdby = readl(&otg->forcestdby);
stdby &= ~OMAP3_OTG_FORCESTDBY_STANDBY;
writel(stdby, &otg->forcestdby);
#ifdef CONFIG_TARGET_OMAP3_EVM
musb_cfg.extvbus = omap3_evm_need_extvbus();
#endif
#ifdef CONFIG_OMAP44XX
u32 *usbotghs_control =
(u32 *)((*ctrl)->control_usbotghs_ctrl);
*usbotghs_control = 0x15;
#endif
platform_needs_initialization = 0;
}
ret = platform_needs_initialization;
#ifdef CONFIG_TWL4030_USB
end:
#endif
return ret;
}
void musb_platform_deinit(void)
{
/* noop */
}
source/bootloader/u-boot-2020.01/drivers/usb/musb/omap3.h
+38
View File
@@ -0,0 +1,38 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2009 Wind River Systems, Inc.
* Tom Rix <Tom.Rix@windriver.com>
*
* This file is based on the file drivers/usb/musb/davinci.h
*
* This is the unique part of its copyright:
*
* --------------------------------------------------------------------
*
* Copyright (c) 2008 Texas Instruments
* Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
*
* --------------------------------------------------------------------
*/
#ifndef _MUSB_OMAP3_H_
#define _MUSB_OMAP3_H_
#include <asm/arch/cpu.h>
#include "musb_core.h"
/* Base address of MUSB registers */
#define MENTOR_USB0_BASE MUSB_BASE
/* Base address of OTG registers */
#define OMAP3_OTG_BASE (MENTOR_USB0_BASE + 0x400)
/* Timeout for USB module */
#define OMAP3_USB_TIMEOUT 0x3FFFFFF
int musb_platform_init(void);
#ifdef CONFIG_TARGET_OMAP3_EVM
extern u8 omap3_evm_need_extvbus(void);
#endif
#endif /* _MUSB_OMAP3_H */