GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 BayLibre, SAS
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* Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
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*/
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#include <common.h>
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#include <display.h>
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#include <dm.h>
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#include <edid.h>
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#include <asm/io.h>
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#include <dw_hdmi.h>
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#include <dm/device-internal.h>
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#include <dm/uclass-internal.h>
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#include <power/regulator.h>
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#include <clk.h>
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#include <linux/delay.h>
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#include <reset.h>
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#include <media_bus_format.h>
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#include "meson_dw_hdmi.h"
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#include "meson_vpu.h"
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/* TOP Block Communication Channel */
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#define HDMITX_TOP_ADDR_REG 0x0
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#define HDMITX_TOP_DATA_REG 0x4
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#define HDMITX_TOP_CTRL_REG 0x8
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#define HDMITX_TOP_G12A_OFFSET 0x8000
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/* Controller Communication Channel */
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#define HDMITX_DWC_ADDR_REG 0x10
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#define HDMITX_DWC_DATA_REG 0x14
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#define HDMITX_DWC_CTRL_REG 0x18
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/* HHI Registers */
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#define HHI_MEM_PD_REG0 0x100 /* 0x40 */
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#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */
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#define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */
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#define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */
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#define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */
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#define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */
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#define HHI_HDMI_PHY_CNTL4 0x3b0 /* 0xec */
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#define HHI_HDMI_PHY_CNTL5 0x3b4 /* 0xed */
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struct meson_dw_hdmi {
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struct udevice *dev;
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struct dw_hdmi hdmi;
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void __iomem *hhi_base;
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};
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enum hdmi_compatible {
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HDMI_COMPATIBLE_GXBB = 0,
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HDMI_COMPATIBLE_GXL = 1,
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HDMI_COMPATIBLE_GXM = 2,
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HDMI_COMPATIBLE_G12A = 3,
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};
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static inline bool meson_hdmi_is_compatible(struct meson_dw_hdmi *priv,
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enum hdmi_compatible family)
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{
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enum hdmi_compatible compat = dev_get_driver_data(priv->dev);
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return compat == family;
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}
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static unsigned int dw_hdmi_top_read(struct dw_hdmi *hdmi, unsigned int addr)
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{
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struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi,
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hdmi);
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unsigned int data;
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if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A))
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return readl(hdmi->ioaddr +
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HDMITX_TOP_G12A_OFFSET + (addr << 2));
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/* ADDR must be written twice */
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writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
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writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
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/* Read needs a second DATA read */
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data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG);
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data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG);
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return data;
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}
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static inline void dw_hdmi_top_write(struct dw_hdmi *hdmi,
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unsigned int addr, unsigned int data)
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{
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struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi,
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hdmi);
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if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A)) {
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writel(data, hdmi->ioaddr +
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HDMITX_TOP_G12A_OFFSET + (addr << 2));
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return;
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}
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/* ADDR must be written twice */
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writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
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writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
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/* Write needs single DATA write */
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writel(data, hdmi->ioaddr + HDMITX_TOP_DATA_REG);
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}
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static inline void dw_hdmi_top_write_bits(struct dw_hdmi *hdmi,
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unsigned int addr,
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unsigned int mask,
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unsigned int val)
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{
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unsigned int data = dw_hdmi_top_read(hdmi, addr);
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data &= ~mask;
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data |= val;
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dw_hdmi_top_write(hdmi, addr, data);
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}
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static u8 dw_hdmi_dwc_read(struct dw_hdmi *hdmi, int addr)
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{
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unsigned int data;
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/* ADDR must be written twice */
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writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
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writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
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/* Read needs a second DATA read */
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data = readl(hdmi->ioaddr + HDMITX_DWC_DATA_REG);
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data = readl(hdmi->ioaddr + HDMITX_DWC_DATA_REG);
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return data;
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}
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static inline void dw_hdmi_dwc_write(struct dw_hdmi *hdmi, u8 data, int addr)
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{
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/* ADDR must be written twice */
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writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
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writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
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/* Write needs single DATA write */
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writel(data, hdmi->ioaddr + HDMITX_DWC_DATA_REG);
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}
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static inline void dw_hdmi_dwc_write_bits(struct dw_hdmi *hdmi,
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unsigned int addr,
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unsigned int mask,
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unsigned int val)
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{
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u8 data = dw_hdmi_dwc_read(hdmi, addr);
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data &= ~mask;
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data |= val;
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dw_hdmi_dwc_write(hdmi, data, addr);
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}
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static inline void dw_hdmi_hhi_write(struct meson_dw_hdmi *priv,
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unsigned int addr, unsigned int data)
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{
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hhi_write(addr, data);
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}
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__attribute__((unused))
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static unsigned int dw_hdmi_hhi_read(struct meson_dw_hdmi *priv,
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unsigned int addr)
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{
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return hhi_read(addr);
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}
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static inline void dw_hdmi_hhi_update_bits(struct meson_dw_hdmi *priv,
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unsigned int addr,
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unsigned int mask,
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unsigned int val)
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{
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hhi_update_bits(addr, mask, val);
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}
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static int meson_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
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{
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#if defined DEBUG
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struct display_timing timing;
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int panel_bits_per_colour;
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#endif
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struct meson_dw_hdmi *priv = dev_get_priv(dev);
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int ret;
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ret = dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
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#if defined DEBUG
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if (!ret)
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return ret;
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edid_print_info((struct edid1_info *)buf);
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edid_get_timing(buf, ret, &timing, &panel_bits_per_colour);
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debug("Display timing:\n");
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debug(" hactive %04d, hfrontp %04d, hbackp %04d hsync %04d\n"
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" vactive %04d, vfrontp %04d, vbackp %04d vsync %04d\n",
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timing.hactive.typ, timing.hfront_porch.typ,
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timing.hback_porch.typ, timing.hsync_len.typ,
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timing.vactive.typ, timing.vfront_porch.typ,
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timing.vback_porch.typ, timing.vsync_len.typ);
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debug(" flags: ");
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if (timing.flags & DISPLAY_FLAGS_INTERLACED)
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debug("interlaced ");
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if (timing.flags & DISPLAY_FLAGS_DOUBLESCAN)
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debug("doublescan ");
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if (timing.flags & DISPLAY_FLAGS_DOUBLECLK)
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debug("doubleclk ");
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if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW)
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debug("hsync_low ");
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if (timing.flags & DISPLAY_FLAGS_HSYNC_HIGH)
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debug("hsync_high ");
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if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW)
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debug("vsync_low ");
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if (timing.flags & DISPLAY_FLAGS_VSYNC_HIGH)
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debug("vsync_high ");
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debug("\n");
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#endif
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return ret;
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}
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static inline void meson_dw_hdmi_phy_reset(struct meson_dw_hdmi *priv)
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{
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/* Enable and software reset */
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dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, 0xf, 0xf);
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mdelay(2);
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/* Enable and unreset */
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dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, 0xf, 0xe);
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mdelay(2);
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}
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static void meson_dw_hdmi_phy_setup_mode(struct meson_dw_hdmi *priv,
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uint pixel_clock)
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{
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pixel_clock = pixel_clock / 1000;
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if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXL) ||
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meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXM)) {
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if (pixel_clock >= 371250) {
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/* 5.94Gbps, 3.7125Gbps */
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hhi_write(HHI_HDMI_PHY_CNTL0, 0x333d3282);
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hhi_write(HHI_HDMI_PHY_CNTL3, 0x2136315b);
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} else if (pixel_clock >= 297000) {
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/* 2.97Gbps */
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hhi_write(HHI_HDMI_PHY_CNTL0, 0x33303382);
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hhi_write(HHI_HDMI_PHY_CNTL3, 0x2036315b);
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} else if (pixel_clock >= 148500) {
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/* 1.485Gbps */
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hhi_write(HHI_HDMI_PHY_CNTL0, 0x33303362);
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hhi_write(HHI_HDMI_PHY_CNTL3, 0x2016315b);
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} else {
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/* 742.5Mbps, and below */
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hhi_write(HHI_HDMI_PHY_CNTL0, 0x33604142);
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hhi_write(HHI_HDMI_PHY_CNTL3, 0x0016315b);
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}
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} else if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXBB)) {
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if (pixel_clock >= 371250) {
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/* 5.94Gbps, 3.7125Gbps */
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hhi_write(HHI_HDMI_PHY_CNTL0, 0x33353245);
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hhi_write(HHI_HDMI_PHY_CNTL3, 0x2100115b);
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} else if (pixel_clock >= 297000) {
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/* 2.97Gbps */
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hhi_write(HHI_HDMI_PHY_CNTL0, 0x33634283);
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hhi_write(HHI_HDMI_PHY_CNTL3, 0xb000115b);
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} else {
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/* 1.485Gbps, and below */
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hhi_write(HHI_HDMI_PHY_CNTL0, 0x33632122);
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hhi_write(HHI_HDMI_PHY_CNTL3, 0x2000115b);
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}
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} else if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A)) {
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if (pixel_clock >= 371250) {
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/* 5.94Gbps, 3.7125Gbps */
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hhi_write(HHI_HDMI_PHY_CNTL0, 0x37eb65c4);
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hhi_write(HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
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hhi_write(HHI_HDMI_PHY_CNTL5, 0x0000080b);
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} else if (pixel_clock >= 297000) {
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/* 2.97Gbps */
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hhi_write(HHI_HDMI_PHY_CNTL0, 0x33eb6262);
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hhi_write(HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
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hhi_write(HHI_HDMI_PHY_CNTL5, 0x00000003);
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} else {
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/* 1.485Gbps, and below */
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hhi_write(HHI_HDMI_PHY_CNTL0, 0x33eb4242);
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hhi_write(HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
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hhi_write(HHI_HDMI_PHY_CNTL5, 0x00000003);
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}
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}
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}
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static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi, uint pixel_clock)
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{
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struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi,
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hdmi);
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/* Enable clocks */
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dw_hdmi_hhi_update_bits(priv, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
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/* Bring HDMITX MEM output of power down */
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dw_hdmi_hhi_update_bits(priv, HHI_MEM_PD_REG0, 0xff << 8, 0);
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/* Bring out of reset */
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dw_hdmi_top_write(hdmi, HDMITX_TOP_SW_RESET, 0);
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/* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */
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dw_hdmi_top_write_bits(hdmi, HDMITX_TOP_CLK_CNTL, 0x3, 0x3);
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dw_hdmi_top_write_bits(hdmi, HDMITX_TOP_CLK_CNTL, 0x3 << 4, 0x3 << 4);
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/* Enable normal output to PHY */
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dw_hdmi_top_write(hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
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/* TMDS pattern setup (TOFIX pattern for 4k2k scrambling) */
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dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0x001f001f);
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dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, 0x001f001f);
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/* Load TMDS pattern */
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dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1);
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mdelay(20);
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dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2);
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/* Setup PHY parameters */
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meson_dw_hdmi_phy_setup_mode(priv, pixel_clock);
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/* Setup PHY */
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dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1,
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0xffff << 16, 0x0390 << 16);
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/* BIT_INVERT */
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if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXL) ||
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meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXM) ||
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meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A))
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dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, BIT(17), 0);
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else
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dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1,
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BIT(17), BIT(17));
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/* Disable clock, fifo, fifo_wr */
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dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, 0xf, 0);
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mdelay(100);
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/* Reset PHY 3 times in a row */
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meson_dw_hdmi_phy_reset(priv);
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meson_dw_hdmi_phy_reset(priv);
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meson_dw_hdmi_phy_reset(priv);
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return 0;
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}
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static int meson_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
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const struct display_timing *edid)
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{
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struct meson_dw_hdmi *priv = dev_get_priv(dev);
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/* will back into meson_dw_hdmi_phy_init */
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return dw_hdmi_enable(&priv->hdmi, edid);
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}
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static int meson_dw_hdmi_wait_hpd(struct dw_hdmi *hdmi)
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{
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int i;
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/* Poll 1 second for HPD signal */
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for (i = 0; i < 10; ++i) {
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if (dw_hdmi_top_read(hdmi, HDMITX_TOP_STAT0))
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return 0;
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mdelay(100);
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}
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return -ETIMEDOUT;
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}
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static int meson_dw_hdmi_probe(struct udevice *dev)
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{
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struct meson_dw_hdmi *priv = dev_get_priv(dev);
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struct reset_ctl_bulk resets;
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struct clk_bulk clocks;
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struct udevice *supply;
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int ret;
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priv->dev = dev;
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priv->hdmi.ioaddr = (ulong)dev_remap_addr_index(dev, 0);
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if (!priv->hdmi.ioaddr)
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return -EINVAL;
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priv->hhi_base = dev_remap_addr_index(dev, 1);
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if (!priv->hhi_base)
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return -EINVAL;
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priv->hdmi.hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
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priv->hdmi.hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
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priv->hdmi.phy_set = meson_dw_hdmi_phy_init;
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if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A))
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priv->hdmi.reg_io_width = 1;
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else {
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priv->hdmi.write_reg = dw_hdmi_dwc_write;
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priv->hdmi.read_reg = dw_hdmi_dwc_read;
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}
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priv->hdmi.i2c_clk_high = 0x67;
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priv->hdmi.i2c_clk_low = 0x78;
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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ret = device_get_supply_regulator(dev, "hdmi-supply", &supply);
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if (ret && ret != -ENOENT) {
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pr_err("Failed to get HDMI regulator\n");
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return ret;
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}
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if (!ret) {
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ret = regulator_set_enable(supply, true);
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if (ret)
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
|
||||
&priv->hdmi.ddc_bus);
|
||||
|
||||
ret = reset_get_bulk(dev, &resets);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_get_bulk(dev, &clocks);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_enable_bulk(&clocks);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Enable clocks */
|
||||
dw_hdmi_hhi_update_bits(priv, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
|
||||
|
||||
/* Bring HDMITX MEM output of power down */
|
||||
dw_hdmi_hhi_update_bits(priv, HHI_MEM_PD_REG0, 0xff << 8, 0);
|
||||
|
||||
/* Reset HDMITX APB & TX & PHY: cycle needed for EDID */
|
||||
ret = reset_deassert_bulk(&resets);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = reset_assert_bulk(&resets);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = reset_deassert_bulk(&resets);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (!meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A)) {
|
||||
/* Enable APB3 fail on error */
|
||||
writel_bits(BIT(15), BIT(15),
|
||||
priv->hdmi.ioaddr + HDMITX_TOP_CTRL_REG);
|
||||
writel_bits(BIT(15), BIT(15),
|
||||
priv->hdmi.ioaddr + HDMITX_DWC_CTRL_REG);
|
||||
}
|
||||
|
||||
/* Bring out of reset */
|
||||
dw_hdmi_top_write(&priv->hdmi, HDMITX_TOP_SW_RESET, 0);
|
||||
mdelay(20);
|
||||
dw_hdmi_top_write(&priv->hdmi, HDMITX_TOP_CLK_CNTL, 0xff);
|
||||
|
||||
dw_hdmi_init(&priv->hdmi);
|
||||
dw_hdmi_phy_init(&priv->hdmi);
|
||||
|
||||
/* wait for connector */
|
||||
ret = meson_dw_hdmi_wait_hpd(&priv->hdmi);
|
||||
if (ret)
|
||||
debug("hdmi can not get hpd signal\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static bool meson_dw_hdmi_mode_valid(struct udevice *dev,
|
||||
const struct display_timing *timing)
|
||||
{
|
||||
return meson_venc_hdmi_supported_mode(timing);
|
||||
}
|
||||
|
||||
static const struct dm_display_ops meson_dw_hdmi_ops = {
|
||||
.read_edid = meson_dw_hdmi_read_edid,
|
||||
.enable = meson_dw_hdmi_enable,
|
||||
.mode_valid = meson_dw_hdmi_mode_valid,
|
||||
};
|
||||
|
||||
static const struct udevice_id meson_dw_hdmi_ids[] = {
|
||||
{ .compatible = "amlogic,meson-gxbb-dw-hdmi",
|
||||
.data = HDMI_COMPATIBLE_GXBB },
|
||||
{ .compatible = "amlogic,meson-gxl-dw-hdmi",
|
||||
.data = HDMI_COMPATIBLE_GXL },
|
||||
{ .compatible = "amlogic,meson-gxm-dw-hdmi",
|
||||
.data = HDMI_COMPATIBLE_GXM },
|
||||
{ .compatible = "amlogic,meson-g12a-dw-hdmi",
|
||||
.data = HDMI_COMPATIBLE_G12A },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(meson_dw_hdmi) = {
|
||||
.name = "meson_dw_hdmi",
|
||||
.id = UCLASS_DISPLAY,
|
||||
.of_match = meson_dw_hdmi_ids,
|
||||
.ops = &meson_dw_hdmi_ops,
|
||||
.probe = meson_dw_hdmi_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct meson_dw_hdmi),
|
||||
};
|
||||
Reference in New Issue
Block a user