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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
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source/bootloader/u-boot-2020.01/drivers/video/sunxi/Makefile
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# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o simplefb_common.o lcdc.o tve_common.o ../videomodes.o
obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o simplefb_common.o lcdc.o ../dw_hdmi.o sunxi_lcd.o
source/bootloader/u-boot-2020.01/drivers/video/sunxi/lcdc.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Timing controller driver for Allwinner SoCs.
*
* (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
* (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/lcdc.h>
#include <asm/io.h>
static int lcdc_get_clk_delay(const struct display_timing *mode, int tcon)
{
int delay;
delay = mode->vfront_porch.typ + mode->vsync_len.typ +
mode->vback_porch.typ;
if (mode->flags & DISPLAY_FLAGS_INTERLACED)
delay /= 2;
if (tcon == 1)
delay -= 2;
return (delay > 30) ? 30 : delay;
}
void lcdc_init(struct sunxi_lcdc_reg * const lcdc)
{
/* Init lcdc */
writel(0, &lcdc->ctrl); /* Disable tcon */
writel(0, &lcdc->int0); /* Disable all interrupts */
/* Disable tcon0 dot clock */
clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
/* Set all io lines to tristate */
writel(0xffffffff, &lcdc->tcon0_io_tristate);
writel(0xffffffff, &lcdc->tcon1_io_tristate);
}
void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth)
{
setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE);
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0);
#ifdef CONFIG_SUNXI_GEN_SUN6I
udelay(2); /* delay at least 1200 ns */
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB);
udelay(2); /* delay at least 1200 ns */
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC);
if (depth == 18)
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7));
else
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf));
#else
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
udelay(2); /* delay at least 1200 ns */
setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1);
udelay(1); /* delay at least 120 ns */
setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2);
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
#endif
#endif
}
void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
const struct display_timing *mode,
int clk_div, bool for_ext_vga_dac,
int depth, int dclk_phase)
{
int bp, clk_delay, total, val;
#ifndef CONFIG_SUNXI_DE2
/* Use tcon0 */
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
SUNXI_LCDC_CTRL_IO_MAP_TCON0);
#endif
clk_delay = lcdc_get_clk_delay(mode, 0);
writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
writel(SUNXI_LCDC_X(mode->hactive.typ) |
SUNXI_LCDC_Y(mode->vactive.typ), &lcdc->tcon0_timing_active);
bp = mode->hsync_len.typ + mode->hback_porch.typ;
total = mode->hactive.typ + mode->hfront_porch.typ + bp;
writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
bp = mode->vsync_len.typ + mode->vback_porch.typ;
total = mode->vactive.typ + mode->vfront_porch.typ + bp;
writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_VIDEO_DE2)
writel(SUNXI_LCDC_X(mode->hsync_len.typ) |
SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon0_timing_sync);
writel(0, &lcdc->tcon0_hv_intf);
writel(0, &lcdc->tcon0_cpu_intf);
#endif
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
val = (depth == 18) ? 1 : 0;
writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val) |
SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, &lcdc->tcon0_lvds_intf);
#endif
if (depth == 18 || depth == 16) {
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
writel(((depth == 18) ?
SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
&lcdc->tcon0_frm_ctrl);
}
val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(dclk_phase);
if (mode->flags & DISPLAY_FLAGS_HSYNC_LOW)
val |= SUNXI_LCDC_TCON_HSYNC_MASK;
if (mode->flags & DISPLAY_FLAGS_VSYNC_LOW)
val |= SUNXI_LCDC_TCON_VSYNC_MASK;
#ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
if (for_ext_vga_dac)
val = 0;
#endif
writel(val, &lcdc->tcon0_io_polarity);
writel(0, &lcdc->tcon0_io_tristate);
}
void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
const struct display_timing *mode,
bool ext_hvsync, bool is_composite)
{
int bp, clk_delay, total, val, yres;
#ifndef CONFIG_SUNXI_DE2
/* Use tcon1 */
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
SUNXI_LCDC_CTRL_IO_MAP_TCON1);
#endif
clk_delay = lcdc_get_clk_delay(mode, 1);
writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
((mode->flags & DISPLAY_FLAGS_INTERLACED) ?
SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) |
SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);
yres = mode->vactive.typ;
if (mode->flags & DISPLAY_FLAGS_INTERLACED)
yres /= 2;
writel(SUNXI_LCDC_X(mode->hactive.typ) | SUNXI_LCDC_Y(yres),
&lcdc->tcon1_timing_source);
writel(SUNXI_LCDC_X(mode->hactive.typ) | SUNXI_LCDC_Y(yres),
&lcdc->tcon1_timing_scale);
writel(SUNXI_LCDC_X(mode->hactive.typ) | SUNXI_LCDC_Y(yres),
&lcdc->tcon1_timing_out);
bp = mode->hsync_len.typ + mode->hback_porch.typ;
total = mode->hactive.typ + mode->hfront_porch.typ + bp;
writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
bp = mode->vsync_len.typ + mode->vback_porch.typ;
total = mode->vactive.typ + mode->vfront_porch.typ + bp;
if (!(mode->flags & DISPLAY_FLAGS_INTERLACED))
total *= 2;
writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
writel(SUNXI_LCDC_X(mode->hsync_len.typ) |
SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon1_timing_sync);
if (ext_hvsync) {
val = 0;
if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= SUNXI_LCDC_TCON_HSYNC_MASK;
if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
val |= SUNXI_LCDC_TCON_VSYNC_MASK;
writel(val, &lcdc->tcon1_io_polarity);
clrbits_le32(&lcdc->tcon1_io_tristate,
SUNXI_LCDC_TCON_VSYNC_MASK |
SUNXI_LCDC_TCON_HSYNC_MASK);
}
#ifdef CONFIG_MACH_SUN5I
if (is_composite)
clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK,
SUNXI_LCDC_MUX_CTRL_SRC0(1));
#endif
}
void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
int *clk_div, int *clk_double, bool is_composite)
{
int value, n, m, min_m, max_m, diff, step;
int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
int best_double = 0;
bool use_mipi_pll = false;
#ifdef CONFIG_SUNXI_DE2
step = 6000;
#else
step = 3000;
#endif
if (tcon == 0) {
#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_SUNXI_DE2)
min_m = 6;
max_m = 127;
#endif
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
min_m = 7;
max_m = 7;
#endif
} else {
min_m = 1;
max_m = 15;
}
/*
* Find the lowest divider resulting in a matching clock, if there
* is no match, pick the closest lower clock, as monitors tend to
* not sync to higher frequencies.
*/
for (m = min_m; m <= max_m; m++) {
#ifndef CONFIG_SUNXI_DE2
n = (m * dotclock) / step;
if ((n >= 9) && (n <= 127)) {
value = (step * n) / m;
diff = dotclock - value;
if (diff < best_diff) {
best_diff = diff;
best_m = m;
best_n = n;
best_double = 0;
}
}
/* These are just duplicates */
if (!(m & 1))
continue;
#endif
/* No double clock on DE2 */
n = (m * dotclock) / (step * 2);
if ((n >= 9) && (n <= 127)) {
value = (step * 2 * n) / m;
diff = dotclock - value;
if (diff < best_diff) {
best_diff = diff;
best_m = m;
best_n = n;
best_double = 1;
}
}
}
#ifdef CONFIG_MACH_SUN6I
/*
* Use the MIPI pll if we've been unable to find any matching setting
* for PLL3, this happens with high dotclocks because of min_m = 6.
*/
if (tcon == 0 && best_n == 0) {
use_mipi_pll = true;
best_m = 6; /* Minimum m for tcon0 */
}
if (use_mipi_pll) {
clock_set_pll3(297000000); /* Fix the video pll at 297 MHz */
clock_set_mipi_pll(best_m * dotclock * 1000);
debug("dotclock: %dkHz = %dkHz via mipi pll\n",
dotclock, clock_get_mipi_pll() / best_m / 1000);
} else
#endif
{
clock_set_pll3(best_n * step * 1000);
debug("dotclock: %dkHz = %dkHz: (%d * %dkHz * %d) / %d\n",
dotclock,
(best_double + 1) * clock_get_pll3() / best_m / 1000,
best_double + 1, step, best_n, best_m);
}
if (tcon == 0) {
u32 pll;
if (use_mipi_pll)
pll = CCM_LCD_CH0_CTRL_MIPI_PLL;
else if (best_double)
pll = CCM_LCD_CH0_CTRL_PLL3_2X;
else
pll = CCM_LCD_CH0_CTRL_PLL3;
#ifndef CONFIG_SUNXI_DE2
writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST | pll,
&ccm->lcd0_ch0_clk_cfg);
#else
writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST | pll,
&ccm->lcd0_clk_cfg);
#endif
}
#ifndef CONFIG_SUNXI_DE2
else {
writel(CCM_LCD_CH1_CTRL_GATE |
(best_double ? CCM_LCD_CH1_CTRL_PLL3_2X :
CCM_LCD_CH1_CTRL_PLL3) |
CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
if (is_composite)
setbits_le32(&ccm->lcd0_ch1_clk_cfg,
CCM_LCD_CH1_CTRL_HALF_SCLK1);
}
#endif
*clk_div = best_m;
*clk_double = best_double;
}
source/bootloader/u-boot-2020.01/drivers/video/sunxi/simplefb_common.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Common code for Allwinner SimpleFB with pipeline.
*
* (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
* (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
*/
#include <fdtdec.h>
int sunxi_simplefb_fdt_match(void *blob, const char *pipeline)
{
int offset, ret;
/* Find a prefilled simpefb node, matching out pipeline config */
offset = fdt_node_offset_by_compatible(blob, -1,
"allwinner,simple-framebuffer");
while (offset >= 0) {
ret = fdt_stringlist_search(blob, offset, "allwinner,pipeline",
pipeline);
if (ret == 0)
break;
offset = fdt_node_offset_by_compatible(blob, offset,
"allwinner,simple-framebuffer");
}
return offset;
}
source/bootloader/u-boot-2020.01/drivers/video/sunxi/simplefb_common.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
*/
#ifndef __SIMPLEFB_COMMON_H
#define __SIMPLEFB_COMMON_H
/**
* sunxi_simplefb_fdt_match() - match a sunxi simplefb node
*
* Match a sunxi simplefb device node with a specified pipeline, and
* return its offset.
*
* @blob: device tree blob
* @pipeline: display pipeline
* @return device node offset in blob, or negative values if failed
*/
int sunxi_simplefb_fdt_match(void *blob, const char *pipeline);
#endif
source/bootloader/u-boot-2020.01/drivers/video/sunxi/sunxi_de2.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Allwinner DE2 display driver
*
* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
*/
#include <common.h>
#include <display.h>
#include <dm.h>
#include <edid.h>
#include <efi_loader.h>
#include <fdtdec.h>
#include <fdt_support.h>
#include <video.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/display2.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include "simplefb_common.h"
DECLARE_GLOBAL_DATA_PTR;
enum {
/* Maximum LCD size we support */
LCD_MAX_WIDTH = 3840,
LCD_MAX_HEIGHT = 2160,
LCD_MAX_LOG2_BPP = VIDEO_BPP32,
};
static void sunxi_de2_composer_init(void)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
#ifdef CONFIG_MACH_SUN50I
u32 reg_value;
/* set SRAM for video use (A64 only) */
reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
reg_value &= ~(0x01 << 24);
writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
#endif
clock_set_pll10(432000000);
/* Set DE parent to pll10 */
clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK,
CCM_DE2_CTRL_PLL10);
/* Set ahb gating to pass */
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE);
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE);
/* Clock on */
setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE);
}
static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
int bpp, ulong address, bool is_composite)
{
ulong de_mux_base = (mux == 0) ?
SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE;
struct de_clk * const de_clk_regs =
(struct de_clk *)(SUNXI_DE2_BASE);
struct de_glb * const de_glb_regs =
(struct de_glb *)(de_mux_base +
SUNXI_DE2_MUX_GLB_REGS);
struct de_bld * const de_bld_regs =
(struct de_bld *)(de_mux_base +
SUNXI_DE2_MUX_BLD_REGS);
struct de_ui * const de_ui_regs =
(struct de_ui *)(de_mux_base +
SUNXI_DE2_MUX_CHAN_REGS +
SUNXI_DE2_MUX_CHAN_SZ * 1);
struct de_csc * const de_csc_regs =
(struct de_csc *)(de_mux_base +
SUNXI_DE2_MUX_DCSC_REGS);
u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ);
int channel;
u32 format;
/* enable clock */
#ifdef CONFIG_MACH_SUN8I_H3
setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4);
#else
setbits_le32(&de_clk_regs->rst_cfg, BIT(mux));
#endif
setbits_le32(&de_clk_regs->gate_cfg, BIT(mux));
setbits_le32(&de_clk_regs->bus_cfg, BIT(mux));
clrbits_le32(&de_clk_regs->sel_cfg, 1);
writel(SUNXI_DE2_MUX_GLB_CTL_EN, &de_glb_regs->ctl);
writel(0, &de_glb_regs->status);
writel(1, &de_glb_regs->dbuff);
writel(size, &de_glb_regs->size);
for (channel = 0; channel < 4; channel++) {
void *ch = (void *)(de_mux_base + SUNXI_DE2_MUX_CHAN_REGS +
SUNXI_DE2_MUX_CHAN_SZ * channel);
memset(ch, 0, (channel == 0) ?
sizeof(struct de_vi) : sizeof(struct de_ui));
}
memset(de_bld_regs, 0, sizeof(struct de_bld));
writel(0x00000101, &de_bld_regs->fcolor_ctl);
writel(1, &de_bld_regs->route);
writel(0, &de_bld_regs->premultiply);
writel(0xff000000, &de_bld_regs->bkcolor);
writel(0x03010301, &de_bld_regs->bld_mode[0]);
writel(size, &de_bld_regs->output_size);
writel(mode->flags & DISPLAY_FLAGS_INTERLACED ? 2 : 0,
&de_bld_regs->out_ctl);
writel(0, &de_bld_regs->ck_ctl);
writel(0xff000000, &de_bld_regs->attr[0].fcolor);
writel(size, &de_bld_regs->attr[0].insize);
/* Disable all other units */
writel(0, de_mux_base + SUNXI_DE2_MUX_VSU_REGS);
writel(0, de_mux_base + SUNXI_DE2_MUX_GSU1_REGS);
writel(0, de_mux_base + SUNXI_DE2_MUX_GSU2_REGS);
writel(0, de_mux_base + SUNXI_DE2_MUX_GSU3_REGS);
writel(0, de_mux_base + SUNXI_DE2_MUX_FCE_REGS);
writel(0, de_mux_base + SUNXI_DE2_MUX_BWS_REGS);
writel(0, de_mux_base + SUNXI_DE2_MUX_LTI_REGS);
writel(0, de_mux_base + SUNXI_DE2_MUX_PEAK_REGS);
writel(0, de_mux_base + SUNXI_DE2_MUX_ASE_REGS);
writel(0, de_mux_base + SUNXI_DE2_MUX_FCC_REGS);
if (is_composite) {
/* set CSC coefficients */
writel(0x107, &de_csc_regs->coef11);
writel(0x204, &de_csc_regs->coef12);
writel(0x64, &de_csc_regs->coef13);
writel(0x4200, &de_csc_regs->coef14);
writel(0x1f68, &de_csc_regs->coef21);
writel(0x1ed6, &de_csc_regs->coef22);
writel(0x1c2, &de_csc_regs->coef23);
writel(0x20200, &de_csc_regs->coef24);
writel(0x1c2, &de_csc_regs->coef31);
writel(0x1e87, &de_csc_regs->coef32);
writel(0x1fb7, &de_csc_regs->coef33);
writel(0x20200, &de_csc_regs->coef34);
/* enable CSC unit */
writel(1, &de_csc_regs->csc_ctl);
} else {
writel(0, &de_csc_regs->csc_ctl);
}
switch (bpp) {
case 16:
format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_RGB_565);
break;
case 32:
default:
format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_XRGB_8888);
break;
}
writel(SUNXI_DE2_UI_CFG_ATTR_EN | format, &de_ui_regs->cfg[0].attr);
writel(size, &de_ui_regs->cfg[0].size);
writel(0, &de_ui_regs->cfg[0].coord);
writel((bpp / 8) * mode->hactive.typ, &de_ui_regs->cfg[0].pitch);
writel(address, &de_ui_regs->cfg[0].top_laddr);
writel(size, &de_ui_regs->ovl_size);
/* apply settings */
writel(1, &de_glb_regs->dbuff);
}
static int sunxi_de2_init(struct udevice *dev, ulong fbbase,
enum video_log2_bpp l2bpp,
struct udevice *disp, int mux, bool is_composite)
{
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct display_timing timing;
struct display_plat *disp_uc_plat;
int ret;
disp_uc_plat = dev_get_uclass_platdata(disp);
debug("Using device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
if (display_in_use(disp)) {
debug(" - device in use\n");
return -EBUSY;
}
disp_uc_plat->source_id = mux;
ret = device_probe(disp);
if (ret) {
debug("%s: device '%s' display won't probe (ret=%d)\n",
__func__, dev->name, ret);
return ret;
}
ret = display_read_timing(disp, &timing);
if (ret) {
debug("%s: Failed to read timings\n", __func__);
return ret;
}
sunxi_de2_composer_init();
sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite);
ret = display_enable(disp, 1 << l2bpp, &timing);
if (ret) {
debug("%s: Failed to enable display\n", __func__);
return ret;
}
uc_priv->xsize = timing.hactive.typ;
uc_priv->ysize = timing.vactive.typ;
uc_priv->bpix = l2bpp;
debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
#ifdef CONFIG_EFI_LOADER
efi_add_memory_map(fbbase,
ALIGN(timing.hactive.typ * timing.vactive.typ *
(1 << l2bpp) / 8, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT,
EFI_RESERVED_MEMORY_TYPE, false);
#endif
return 0;
}
static int sunxi_de2_probe(struct udevice *dev)
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct udevice *disp;
int ret;
/* Before relocation we don't need to do anything */
if (!(gd->flags & GD_FLG_RELOC))
return 0;
ret = uclass_find_device_by_name(UCLASS_DISPLAY,
"sunxi_lcd", &disp);
if (!ret) {
int mux;
mux = 0;
ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
false);
if (!ret) {
video_set_flush_dcache(dev, 1);
return 0;
}
}
debug("%s: lcd display not found (ret=%d)\n", __func__, ret);
ret = uclass_find_device_by_name(UCLASS_DISPLAY,
"sunxi_dw_hdmi", &disp);
if (!ret) {
int mux;
if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
mux = 0;
else
mux = 1;
ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
false);
if (!ret) {
video_set_flush_dcache(dev, 1);
return 0;
}
}
debug("%s: hdmi display not found (ret=%d)\n", __func__, ret);
ret = uclass_find_device_by_name(UCLASS_DISPLAY,
"sunxi_tve", &disp);
if (ret) {
debug("%s: tv not found (ret=%d)\n", __func__, ret);
return ret;
}
ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, 1, true);
if (ret)
return ret;
video_set_flush_dcache(dev, 1);
return 0;
}
static int sunxi_de2_bind(struct udevice *dev)
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << LCD_MAX_LOG2_BPP) / 8;
return 0;
}
static const struct video_ops sunxi_de2_ops = {
};
U_BOOT_DRIVER(sunxi_de2) = {
.name = "sunxi_de2",
.id = UCLASS_VIDEO,
.ops = &sunxi_de2_ops,
.bind = sunxi_de2_bind,
.probe = sunxi_de2_probe,
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DEVICE(sunxi_de2) = {
.name = "sunxi_de2"
};
/*
* Simplefb support.
*/
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
int sunxi_simplefb_setup(void *blob)
{
struct udevice *de2, *hdmi, *lcd;
struct video_priv *de2_priv;
struct video_uc_platdata *de2_plat;
int mux;
int offset, ret;
u64 start, size;
const char *pipeline = NULL;
debug("Setting up simplefb\n");
if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
mux = 0;
else
mux = 1;
/* Skip simplefb setting if DE2 / HDMI is not present */
ret = uclass_find_device_by_name(UCLASS_VIDEO,
"sunxi_de2", &de2);
if (ret) {
debug("DE2 not present\n");
return 0;
} else if (!device_active(de2)) {
debug("DE2 present but not probed\n");
return 0;
}
ret = uclass_find_device_by_name(UCLASS_DISPLAY,
"sunxi_dw_hdmi", &hdmi);
if (ret) {
debug("HDMI not present\n");
} else if (device_active(hdmi)) {
if (mux == 0)
pipeline = "mixer0-lcd0-hdmi";
else
pipeline = "mixer1-lcd1-hdmi";
} else {
debug("HDMI present but not probed\n");
}
ret = uclass_find_device_by_name(UCLASS_DISPLAY,
"sunxi_lcd", &lcd);
if (ret)
debug("LCD not present\n");
else if (device_active(lcd))
pipeline = "mixer0-lcd0";
else
debug("LCD present but not probed\n");
if (!pipeline) {
debug("No active display present\n");
return 0;
}
de2_priv = dev_get_uclass_priv(de2);
de2_plat = dev_get_uclass_platdata(de2);
offset = sunxi_simplefb_fdt_match(blob, pipeline);
if (offset < 0) {
eprintf("Cannot setup simplefb: node not found\n");
return 0; /* Keep older kernels working */
}
start = gd->bd->bi_dram[0].start;
size = de2_plat->base - start;
ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
if (ret) {
eprintf("Cannot setup simplefb: Error reserving memory\n");
return ret;
}
ret = fdt_setup_simplefb_node(blob, offset, de2_plat->base,
de2_priv->xsize, de2_priv->ysize,
VNBYTES(de2_priv->bpix) * de2_priv->xsize,
"x8r8g8b8");
if (ret)
eprintf("Cannot setup simplefb: Error setting properties\n");
return ret;
}
#endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */
source/bootloader/u-boot-2020.01/drivers/video/sunxi/sunxi_display.c
+1328
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File diff suppressed because it is too large Load Diff
source/bootloader/u-boot-2020.01/drivers/video/sunxi/sunxi_dw_hdmi.c
+400
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@@ -0,0 +1,400 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Allwinner DW HDMI bridge
*
* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
*/
#include <common.h>
#include <display.h>
#include <dm.h>
#include <dw_hdmi.h>
#include <edid.h>
#include <time.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/lcdc.h>
struct sunxi_dw_hdmi_priv {
struct dw_hdmi hdmi;
int mux;
};
struct sunxi_hdmi_phy {
u32 pol;
u32 res1[3];
u32 read_en;
u32 unscramble;
u32 res2[2];
u32 ctrl;
u32 unk1;
u32 unk2;
u32 pll;
u32 clk;
u32 unk3;
u32 status;
};
#define HDMI_PHY_OFFS 0x10000
static int sunxi_dw_hdmi_get_divider(uint clock)
{
/*
* Due to missing documentaion of HDMI PHY, we know correct
* settings only for following four PHY dividers. Select one
* based on clock speed.
*/
if (clock <= 27000000)
return 11;
else if (clock <= 74250000)
return 4;
else if (clock <= 148500000)
return 2;
else
return 1;
}
static void sunxi_dw_hdmi_phy_init(void)
{
struct sunxi_hdmi_phy * const phy =
(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
unsigned long tmo;
u32 tmp;
/*
* HDMI PHY settings are taken as-is from Allwinner BSP code.
* There is no documentation.
*/
writel(0, &phy->ctrl);
setbits_le32(&phy->ctrl, BIT(0));
udelay(5);
setbits_le32(&phy->ctrl, BIT(16));
setbits_le32(&phy->ctrl, BIT(1));
udelay(10);
setbits_le32(&phy->ctrl, BIT(2));
udelay(5);
setbits_le32(&phy->ctrl, BIT(3));
udelay(40);
setbits_le32(&phy->ctrl, BIT(19));
udelay(100);
setbits_le32(&phy->ctrl, BIT(18));
setbits_le32(&phy->ctrl, 7 << 4);
/* Note that Allwinner code doesn't fail in case of timeout */
tmo = timer_get_us() + 2000;
while ((readl(&phy->status) & 0x80) == 0) {
if (timer_get_us() > tmo) {
printf("Warning: HDMI PHY init timeout!\n");
break;
}
}
setbits_le32(&phy->ctrl, 0xf << 8);
setbits_le32(&phy->ctrl, BIT(7));
writel(0x39dc5040, &phy->pll);
writel(0x80084343, &phy->clk);
udelay(10000);
writel(1, &phy->unk3);
setbits_le32(&phy->pll, BIT(25));
udelay(100000);
tmp = (readl(&phy->status) & 0x1f800) >> 11;
setbits_le32(&phy->pll, BIT(31) | BIT(30));
setbits_le32(&phy->pll, tmp);
writel(0x01FF0F7F, &phy->ctrl);
writel(0x80639000, &phy->unk1);
writel(0x0F81C405, &phy->unk2);
/* enable read access to HDMI controller */
writel(0x54524545, &phy->read_en);
/* descramble register offsets */
writel(0x42494E47, &phy->unscramble);
}
static int sunxi_dw_hdmi_get_plug_in_status(void)
{
struct sunxi_hdmi_phy * const phy =
(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
return !!(readl(&phy->status) & (1 << 19));
}
static int sunxi_dw_hdmi_wait_for_hpd(void)
{
ulong start;
start = get_timer(0);
do {
if (sunxi_dw_hdmi_get_plug_in_status())
return 0;
udelay(100);
} while (get_timer(start) < 300);
return -1;
}
static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div)
{
struct sunxi_hdmi_phy * const phy =
(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
int div = sunxi_dw_hdmi_get_divider(clock);
u32 tmp;
/*
* Unfortunately, we don't know much about those magic
* numbers. They are taken from Allwinner BSP driver.
*/
switch (div) {
case 1:
writel(0x30dc5fc0, &phy->pll);
writel(0x800863C0 | (phy_div - 1), &phy->clk);
mdelay(10);
writel(0x00000001, &phy->unk3);
setbits_le32(&phy->pll, BIT(25));
mdelay(200);
tmp = (readl(&phy->status) & 0x1f800) >> 11;
setbits_le32(&phy->pll, BIT(31) | BIT(30));
if (tmp < 0x3d)
setbits_le32(&phy->pll, tmp + 2);
else
setbits_le32(&phy->pll, 0x3f);
mdelay(100);
writel(0x01FFFF7F, &phy->ctrl);
writel(0x8063b000, &phy->unk1);
writel(0x0F8246B5, &phy->unk2);
break;
case 2:
writel(0x39dc5040, &phy->pll);
writel(0x80084380 | (phy_div - 1), &phy->clk);
mdelay(10);
writel(0x00000001, &phy->unk3);
setbits_le32(&phy->pll, BIT(25));
mdelay(100);
tmp = (readl(&phy->status) & 0x1f800) >> 11;
setbits_le32(&phy->pll, BIT(31) | BIT(30));
setbits_le32(&phy->pll, tmp);
writel(0x01FFFF7F, &phy->ctrl);
writel(0x8063a800, &phy->unk1);
writel(0x0F81C485, &phy->unk2);
break;
case 4:
writel(0x39dc5040, &phy->pll);
writel(0x80084340 | (phy_div - 1), &phy->clk);
mdelay(10);
writel(0x00000001, &phy->unk3);
setbits_le32(&phy->pll, BIT(25));
mdelay(100);
tmp = (readl(&phy->status) & 0x1f800) >> 11;
setbits_le32(&phy->pll, BIT(31) | BIT(30));
setbits_le32(&phy->pll, tmp);
writel(0x01FFFF7F, &phy->ctrl);
writel(0x8063b000, &phy->unk1);
writel(0x0F81C405, &phy->unk2);
break;
case 11:
writel(0x39dc5040, &phy->pll);
writel(0x80084300 | (phy_div - 1), &phy->clk);
mdelay(10);
writel(0x00000001, &phy->unk3);
setbits_le32(&phy->pll, BIT(25));
mdelay(100);
tmp = (readl(&phy->status) & 0x1f800) >> 11;
setbits_le32(&phy->pll, BIT(31) | BIT(30));
setbits_le32(&phy->pll, tmp);
writel(0x01FFFF7F, &phy->ctrl);
writel(0x8063b000, &phy->unk1);
writel(0x0F81C405, &phy->unk2);
break;
}
}
static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div)
{
int value, n, m, div, diff;
int best_n = 0, best_m = 0, best_div = 0, best_diff = 0x0FFFFFFF;
/*
* Find the lowest divider resulting in a matching clock. If there
* is no match, pick the closest lower clock, as monitors tend to
* not sync to higher frequencies.
*/
for (div = 1; div <= 16; div++) {
int target = clk_khz * div;
if (target < 192000)
continue;
if (target > 912000)
continue;
for (m = 1; m <= 16; m++) {
n = (m * target) / 24000;
if (n >= 1 && n <= 128) {
value = (24000 * n) / m / div;
diff = clk_khz - value;
if (diff < best_diff) {
best_diff = diff;
best_m = m;
best_n = n;
best_div = div;
}
}
}
}
*phy_div = best_div;
clock_set_pll3_factors(best_m, best_n);
debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
clk_khz, (clock_get_pll3() / 1000) / best_div,
best_n, best_m, best_div);
}
static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
int bpp)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
int div = DIV_ROUND_UP(clock_get_pll3(), edid->pixelclock.typ);
struct sunxi_lcdc_reg *lcdc;
if (mux == 0) {
lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
/* Reset off */
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
/* Clock on */
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
writel(CCM_LCD0_CTRL_GATE | CCM_LCD0_CTRL_M(div),
&ccm->lcd0_clk_cfg);
} else {
lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD1_BASE;
/* Reset off */
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1);
/* Clock on */
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1);
writel(CCM_LCD1_CTRL_GATE | CCM_LCD1_CTRL_M(div),
&ccm->lcd1_clk_cfg);
}
lcdc_init(lcdc);
lcdc_tcon1_mode_set(lcdc, edid, false, false);
lcdc_enable(lcdc, bpp);
}
static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
{
int phy_div;
sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
sunxi_dw_hdmi_phy_set(mpixelclock, phy_div);
return 0;
}
static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
{
struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
}
static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
const struct display_timing *edid)
{
struct sunxi_hdmi_phy * const phy =
(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
int ret;
ret = dw_hdmi_enable(&priv->hdmi, edid);
if (ret)
return ret;
sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp);
if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
setbits_le32(&phy->pol, 0x200);
if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
setbits_le32(&phy->pol, 0x100);
setbits_le32(&phy->ctrl, 0xf << 12);
/*
* This is last hdmi access before boot, so scramble addresses
* again or othwerwise BSP driver won't work. Dummy read is
* needed or otherwise last write doesn't get written correctly.
*/
(void)readb(SUNXI_HDMI_BASE);
writel(0, &phy->unscramble);
return 0;
}
static int sunxi_dw_hdmi_probe(struct udevice *dev)
{
struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
int ret;
/* Set pll3 to 297 MHz */
clock_set_pll3(297000000);
/* Set hdmi parent to pll3 */
clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
CCM_HDMI_CTRL_PLL3);
/* Set ahb gating to pass */
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
/* Clock on */
setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
sunxi_dw_hdmi_phy_init();
ret = sunxi_dw_hdmi_wait_for_hpd();
if (ret < 0) {
debug("hdmi can not get hpd signal\n");
return -1;
}
priv->hdmi.ioaddr = SUNXI_HDMI_BASE;
priv->hdmi.i2c_clk_high = 0xd8;
priv->hdmi.i2c_clk_low = 0xfe;
priv->hdmi.reg_io_width = 1;
priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
priv->mux = uc_plat->source_id;
uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
&priv->hdmi.ddc_bus);
dw_hdmi_init(&priv->hdmi);
return 0;
}
static const struct dm_display_ops sunxi_dw_hdmi_ops = {
.read_edid = sunxi_dw_hdmi_read_edid,
.enable = sunxi_dw_hdmi_enable,
};
U_BOOT_DRIVER(sunxi_dw_hdmi) = {
.name = "sunxi_dw_hdmi",
.id = UCLASS_DISPLAY,
.ops = &sunxi_dw_hdmi_ops,
.probe = sunxi_dw_hdmi_probe,
.priv_auto_alloc_size = sizeof(struct sunxi_dw_hdmi_priv),
};
U_BOOT_DEVICE(sunxi_dw_hdmi) = {
.name = "sunxi_dw_hdmi"
};
source/bootloader/u-boot-2020.01/drivers/video/sunxi/sunxi_lcd.c
+151
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@@ -0,0 +1,151 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Allwinner LCD driver
*
* (C) Copyright 2017 Vasily Khoruzhick <anarsoul@gmail.com>
*/
#include <common.h>
#include <display.h>
#include <video_bridge.h>
#include <backlight.h>
#include <dm.h>
#include <edid.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/lcdc.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
struct sunxi_lcd_priv {
struct display_timing timing;
int panel_bpp;
};
static void sunxi_lcdc_config_pinmux(void)
{
#ifdef CONFIG_MACH_SUN50I
int pin;
for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(21); pin++) {
sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
sunxi_gpio_set_drv(pin, 3);
}
#endif
}
static int sunxi_lcd_enable(struct udevice *dev, int bpp,
const struct display_timing *edid)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_lcdc_reg * const lcdc =
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
struct sunxi_lcd_priv *priv = dev_get_priv(dev);
struct udevice *backlight;
int clk_div, clk_double, ret;
/* Reset off */
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
/* Clock on */
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
lcdc_init(lcdc);
sunxi_lcdc_config_pinmux();
lcdc_pll_set(ccm, 0, edid->pixelclock.typ / 1000,
&clk_div, &clk_double, false);
lcdc_tcon0_mode_set(lcdc, edid, clk_div, false,
priv->panel_bpp, CONFIG_VIDEO_LCD_DCLK_PHASE);
lcdc_enable(lcdc, priv->panel_bpp);
ret = uclass_get_device(UCLASS_PANEL_BACKLIGHT, 0, &backlight);
if (!ret)
backlight_enable(backlight);
return 0;
}
static int sunxi_lcd_read_timing(struct udevice *dev,
struct display_timing *timing)
{
struct sunxi_lcd_priv *priv = dev_get_priv(dev);
memcpy(timing, &priv->timing, sizeof(struct display_timing));
return 0;
}
static int sunxi_lcd_probe(struct udevice *dev)
{
struct udevice *cdev;
struct sunxi_lcd_priv *priv = dev_get_priv(dev);
int ret;
int node, timing_node, val;
#ifdef CONFIG_VIDEO_BRIDGE
/* Try to get timings from bridge first */
ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &cdev);
if (!ret) {
u8 edid[EDID_SIZE];
int channel_bpp;
ret = video_bridge_attach(cdev);
if (ret) {
debug("video bridge attach failed: %d\n", ret);
return ret;
}
ret = video_bridge_read_edid(cdev, edid, EDID_SIZE);
if (ret > 0) {
ret = edid_get_timing(edid, ret,
&priv->timing, &channel_bpp);
priv->panel_bpp = channel_bpp * 3;
if (!ret)
return ret;
}
}
#endif
/* Fallback to timings from DT if there's no bridge or
* if reading EDID failed
*/
ret = uclass_get_device(UCLASS_PANEL, 0, &cdev);
if (ret) {
debug("video panel not found: %d\n", ret);
return ret;
}
if (fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(cdev),
0, &priv->timing)) {
debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL;
}
timing_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(cdev),
"display-timings");
node = fdt_first_subnode(gd->fdt_blob, timing_node);
val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1);
if (val != -1)
priv->panel_bpp = val;
else
priv->panel_bpp = 18;
return 0;
}
static const struct dm_display_ops sunxi_lcd_ops = {
.read_timing = sunxi_lcd_read_timing,
.enable = sunxi_lcd_enable,
};
U_BOOT_DRIVER(sunxi_lcd) = {
.name = "sunxi_lcd",
.id = UCLASS_DISPLAY,
.ops = &sunxi_lcd_ops,
.probe = sunxi_lcd_probe,
.priv_auto_alloc_size = sizeof(struct sunxi_lcd_priv),
};
#ifdef CONFIG_MACH_SUN50I
U_BOOT_DEVICE(sunxi_lcd) = {
.name = "sunxi_lcd"
};
#endif
source/bootloader/u-boot-2020.01/drivers/video/sunxi/tve_common.c
+85
View File
@@ -0,0 +1,85 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* TV encoder driver for Allwinner SoCs.
*
* (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
* (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
*/
#include <common.h>
#include <asm/arch/tve.h>
#include <asm/io.h>
void tvencoder_mode_set(struct sunxi_tve_reg * const tve, enum tve_mode mode)
{
switch (mode) {
case tve_mode_vga:
writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
SUNXI_TVE_GCTRL_DAC_INPUT(2, 3), &tve->gctrl);
writel(SUNXI_TVE_CFG0_VGA, &tve->cfg0);
writel(SUNXI_TVE_DAC_CFG0_VGA, &tve->dac_cfg0);
writel(SUNXI_TVE_UNKNOWN1_VGA, &tve->unknown1);
break;
case tve_mode_composite_pal_nc:
writel(SUNXI_TVE_CHROMA_FREQ_PAL_NC, &tve->chroma_freq);
/* Fall through */
case tve_mode_composite_pal:
writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
SUNXI_TVE_GCTRL_DAC_INPUT(2, 3) |
SUNXI_TVE_GCTRL_DAC_INPUT(3, 4), &tve->gctrl);
writel(SUNXI_TVE_CFG0_PAL, &tve->cfg0);
writel(SUNXI_TVE_DAC_CFG0_COMPOSITE, &tve->dac_cfg0);
writel(SUNXI_TVE_FILTER_COMPOSITE, &tve->filter);
writel(SUNXI_TVE_PORCH_NUM_PAL, &tve->porch_num);
writel(SUNXI_TVE_LINE_NUM_PAL, &tve->line_num);
writel(SUNXI_TVE_BLANK_BLACK_LEVEL_PAL,
&tve->blank_black_level);
writel(SUNXI_TVE_UNKNOWN1_COMPOSITE, &tve->unknown1);
writel(SUNXI_TVE_CBR_LEVEL_PAL, &tve->cbr_level);
writel(SUNXI_TVE_BURST_WIDTH_COMPOSITE, &tve->burst_width);
writel(SUNXI_TVE_UNKNOWN2_PAL, &tve->unknown2);
writel(SUNXI_TVE_ACTIVE_NUM_COMPOSITE, &tve->active_num);
writel(SUNXI_TVE_CHROMA_BW_GAIN_COMP, &tve->chroma_bw_gain);
writel(SUNXI_TVE_NOTCH_WIDTH_COMPOSITE, &tve->notch_width);
writel(SUNXI_TVE_RESYNC_NUM_PAL, &tve->resync_num);
writel(SUNXI_TVE_SLAVE_PARA_COMPOSITE, &tve->slave_para);
break;
case tve_mode_composite_pal_m:
writel(SUNXI_TVE_CHROMA_FREQ_PAL_M, &tve->chroma_freq);
writel(SUNXI_TVE_COLOR_BURST_PAL_M, &tve->color_burst);
/* Fall through */
case tve_mode_composite_ntsc:
writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
SUNXI_TVE_GCTRL_DAC_INPUT(2, 3) |
SUNXI_TVE_GCTRL_DAC_INPUT(3, 4), &tve->gctrl);
writel(SUNXI_TVE_CFG0_NTSC, &tve->cfg0);
writel(SUNXI_TVE_DAC_CFG0_COMPOSITE, &tve->dac_cfg0);
writel(SUNXI_TVE_FILTER_COMPOSITE, &tve->filter);
writel(SUNXI_TVE_PORCH_NUM_NTSC, &tve->porch_num);
writel(SUNXI_TVE_LINE_NUM_NTSC, &tve->line_num);
writel(SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC,
&tve->blank_black_level);
writel(SUNXI_TVE_UNKNOWN1_COMPOSITE, &tve->unknown1);
writel(SUNXI_TVE_CBR_LEVEL_NTSC, &tve->cbr_level);
writel(SUNXI_TVE_BURST_PHASE_NTSC, &tve->burst_phase);
writel(SUNXI_TVE_BURST_WIDTH_COMPOSITE, &tve->burst_width);
writel(SUNXI_TVE_UNKNOWN2_NTSC, &tve->unknown2);
writel(SUNXI_TVE_SYNC_VBI_LEVEL_NTSC, &tve->sync_vbi_level);
writel(SUNXI_TVE_ACTIVE_NUM_COMPOSITE, &tve->active_num);
writel(SUNXI_TVE_CHROMA_BW_GAIN_COMP, &tve->chroma_bw_gain);
writel(SUNXI_TVE_NOTCH_WIDTH_COMPOSITE, &tve->notch_width);
writel(SUNXI_TVE_RESYNC_NUM_NTSC, &tve->resync_num);
writel(SUNXI_TVE_SLAVE_PARA_COMPOSITE, &tve->slave_para);
break;
}
}
void tvencoder_enable(struct sunxi_tve_reg * const tve)
{
setbits_le32(&tve->gctrl, SUNXI_TVE_GCTRL_ENABLE);
}