GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (c) 2014 Google, Inc
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#
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obj-y += display.o
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obj-y += dp.o
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obj-y += sor.o
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@@ -0,0 +1,501 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014 Google Inc.
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*
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* Extracted from Chromium coreboot commit 3f59b13d
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*/
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#include <common.h>
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#include <dm.h>
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#include <edid.h>
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#include <errno.h>
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#include <display.h>
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#include <edid.h>
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#include <lcd.h>
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#include <video.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/pwm.h>
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#include <asm/arch-tegra/dc.h>
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#include <dm/uclass-internal.h>
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#include "displayport.h"
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/* return in 1000ths of a Hertz */
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static int tegra_dc_calc_refresh(const struct display_timing *timing)
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{
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int h_total, v_total, refresh;
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int pclk = timing->pixelclock.typ;
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h_total = timing->hactive.typ + timing->hfront_porch.typ +
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timing->hback_porch.typ + timing->hsync_len.typ;
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v_total = timing->vactive.typ + timing->vfront_porch.typ +
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timing->vback_porch.typ + timing->vsync_len.typ;
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if (!pclk || !h_total || !v_total)
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return 0;
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refresh = pclk / h_total;
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refresh *= 1000;
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refresh /= v_total;
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return refresh;
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}
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static void print_mode(const struct display_timing *timing)
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{
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int refresh = tegra_dc_calc_refresh(timing);
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debug("MODE:%dx%d@%d.%03uHz pclk=%d\n",
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timing->hactive.typ, timing->vactive.typ, refresh / 1000,
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refresh % 1000, timing->pixelclock.typ);
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}
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static int update_display_mode(struct dc_ctlr *disp_ctrl,
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const struct display_timing *timing,
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int href_to_sync, int vref_to_sync)
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{
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print_mode(timing);
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writel(0x1, &disp_ctrl->disp.disp_timing_opt);
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writel(vref_to_sync << 16 | href_to_sync,
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&disp_ctrl->disp.ref_to_sync);
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writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ,
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&disp_ctrl->disp.sync_width);
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writel(((timing->vback_porch.typ - vref_to_sync) << 16) |
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timing->hback_porch.typ, &disp_ctrl->disp.back_porch);
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writel(((timing->vfront_porch.typ + vref_to_sync) << 16) |
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timing->hfront_porch.typ, &disp_ctrl->disp.front_porch);
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writel(timing->hactive.typ | (timing->vactive.typ << 16),
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&disp_ctrl->disp.disp_active);
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/**
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* We want to use PLLD_out0, which is PLLD / 2:
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* PixelClock = (PLLD / 2) / ShiftClockDiv / PixelClockDiv.
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*
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* Currently most panels work inside clock range 50MHz~100MHz, and PLLD
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* has some requirements to have VCO in range 500MHz~1000MHz (see
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* clock.c for more detail). To simplify calculation, we set
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* PixelClockDiv to 1 and ShiftClockDiv to 1. In future these values
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* may be calculated by clock_display, to allow wider frequency range.
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*
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* Note ShiftClockDiv is a 7.1 format value.
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*/
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const u32 shift_clock_div = 1;
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writel((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) |
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((shift_clock_div - 1) * 2) << SHIFT_CLK_DIVIDER_SHIFT,
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&disp_ctrl->disp.disp_clk_ctrl);
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debug("%s: PixelClock=%u, ShiftClockDiv=%u\n", __func__,
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timing->pixelclock.typ, shift_clock_div);
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return 0;
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}
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static u32 tegra_dc_poll_register(void *reg,
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u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_us)
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{
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u32 temp = timeout_us;
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u32 reg_val = 0;
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do {
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udelay(poll_interval_us);
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reg_val = readl(reg);
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if (timeout_us > poll_interval_us)
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timeout_us -= poll_interval_us;
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else
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break;
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} while ((reg_val & mask) != exp_val);
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if ((reg_val & mask) == exp_val)
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return 0; /* success */
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return temp;
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}
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int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl)
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{
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writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
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if (tegra_dc_poll_register(&disp_ctrl->cmd.state_ctrl,
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GENERAL_ACT_REQ, 0, 100,
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DC_POLL_TIMEOUT_MS * 1000)) {
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debug("dc timeout waiting for DC to stop\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static struct display_timing min_mode = {
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.hsync_len = { .typ = 1 },
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.vsync_len = { .typ = 1 },
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.hback_porch = { .typ = 20 },
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.vback_porch = { .typ = 0 },
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.hactive = { .typ = 16 },
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.vactive = { .typ = 16 },
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.hfront_porch = { .typ = 1 },
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.vfront_porch = { .typ = 2 },
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};
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/* Disable windows and set minimum raster timings */
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void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl,
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int *dc_reg_ctx)
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{
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const int href_to_sync = 0, vref_to_sync = 1;
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int selected_windows, i;
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selected_windows = readl(&disp_ctrl->cmd.disp_win_header);
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/* Store and clear window options */
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for (i = 0; i < DC_N_WINDOWS; ++i) {
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writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);
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dc_reg_ctx[i] = readl(&disp_ctrl->win.win_opt);
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writel(0, &disp_ctrl->win.win_opt);
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writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);
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}
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writel(selected_windows, &disp_ctrl->cmd.disp_win_header);
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/* Store current raster timings and set minimum timings */
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dc_reg_ctx[i++] = readl(&disp_ctrl->disp.ref_to_sync);
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writel(href_to_sync | (vref_to_sync << 16),
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&disp_ctrl->disp.ref_to_sync);
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dc_reg_ctx[i++] = readl(&disp_ctrl->disp.sync_width);
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writel(min_mode.hsync_len.typ | (min_mode.vsync_len.typ << 16),
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&disp_ctrl->disp.sync_width);
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dc_reg_ctx[i++] = readl(&disp_ctrl->disp.back_porch);
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writel(min_mode.hback_porch.typ | (min_mode.vback_porch.typ << 16),
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&disp_ctrl->disp.back_porch);
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dc_reg_ctx[i++] = readl(&disp_ctrl->disp.front_porch);
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writel(min_mode.hfront_porch.typ | (min_mode.vfront_porch.typ << 16),
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&disp_ctrl->disp.front_porch);
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dc_reg_ctx[i++] = readl(&disp_ctrl->disp.disp_active);
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writel(min_mode.hactive.typ | (min_mode.vactive.typ << 16),
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&disp_ctrl->disp.disp_active);
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writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
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}
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/* Restore previous windows status and raster timings */
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void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl,
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int *dc_reg_ctx)
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{
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int selected_windows, i;
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selected_windows = readl(&disp_ctrl->cmd.disp_win_header);
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for (i = 0; i < DC_N_WINDOWS; ++i) {
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writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);
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writel(dc_reg_ctx[i], &disp_ctrl->win.win_opt);
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writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);
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}
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writel(selected_windows, &disp_ctrl->cmd.disp_win_header);
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writel(dc_reg_ctx[i++], &disp_ctrl->disp.ref_to_sync);
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writel(dc_reg_ctx[i++], &disp_ctrl->disp.sync_width);
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writel(dc_reg_ctx[i++], &disp_ctrl->disp.back_porch);
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writel(dc_reg_ctx[i++], &disp_ctrl->disp.front_porch);
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writel(dc_reg_ctx[i++], &disp_ctrl->disp.disp_active);
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writel(GENERAL_UPDATE, &disp_ctrl->cmd.state_ctrl);
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}
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static int tegra_depth_for_bpp(int bpp)
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{
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switch (bpp) {
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case 32:
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return COLOR_DEPTH_R8G8B8A8;
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case 16:
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return COLOR_DEPTH_B5G6R5;
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default:
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debug("Unsupported LCD bit depth");
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return -1;
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}
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}
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static int update_window(struct dc_ctlr *disp_ctrl,
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u32 frame_buffer, int fb_bits_per_pixel,
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const struct display_timing *timing)
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{
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const u32 colour_white = 0xffffff;
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int colour_depth;
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u32 val;
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writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
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writel(((timing->vactive.typ << 16) | timing->hactive.typ),
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&disp_ctrl->win.size);
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writel(((timing->vactive.typ << 16) |
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(timing->hactive.typ * fb_bits_per_pixel / 8)),
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&disp_ctrl->win.prescaled_size);
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writel(((timing->hactive.typ * fb_bits_per_pixel / 8 + 31) /
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32 * 32), &disp_ctrl->win.line_stride);
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colour_depth = tegra_depth_for_bpp(fb_bits_per_pixel);
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if (colour_depth == -1)
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return -EINVAL;
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writel(colour_depth, &disp_ctrl->win.color_depth);
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writel(frame_buffer, &disp_ctrl->winbuf.start_addr);
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writel(0x1000 << V_DDA_INC_SHIFT | 0x1000 << H_DDA_INC_SHIFT,
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&disp_ctrl->win.dda_increment);
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writel(colour_white, &disp_ctrl->disp.blend_background_color);
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writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
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&disp_ctrl->cmd.disp_cmd);
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writel(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
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val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
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val |= GENERAL_UPDATE | WIN_A_UPDATE;
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writel(val, &disp_ctrl->cmd.state_ctrl);
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/* Enable win_a */
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val = readl(&disp_ctrl->win.win_opt);
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writel(val | WIN_ENABLE, &disp_ctrl->win.win_opt);
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return 0;
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}
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static int tegra_dc_init(struct dc_ctlr *disp_ctrl)
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{
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/* do not accept interrupts during initialization */
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writel(0x00000000, &disp_ctrl->cmd.int_mask);
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writel(WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY,
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&disp_ctrl->cmd.state_access);
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writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
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writel(0x00000000, &disp_ctrl->win.win_opt);
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writel(0x00000000, &disp_ctrl->win.byte_swap);
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writel(0x00000000, &disp_ctrl->win.buffer_ctrl);
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writel(0x00000000, &disp_ctrl->win.pos);
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writel(0x00000000, &disp_ctrl->win.h_initial_dda);
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writel(0x00000000, &disp_ctrl->win.v_initial_dda);
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writel(0x00000000, &disp_ctrl->win.dda_increment);
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writel(0x00000000, &disp_ctrl->win.dv_ctrl);
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writel(0x01000000, &disp_ctrl->win.blend_layer_ctrl);
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writel(0x00000000, &disp_ctrl->win.blend_match_select);
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writel(0x00000000, &disp_ctrl->win.blend_nomatch_select);
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writel(0x00000000, &disp_ctrl->win.blend_alpha_1bit);
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writel(0x00000000, &disp_ctrl->winbuf.start_addr_hi);
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writel(0x00000000, &disp_ctrl->winbuf.addr_h_offset);
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writel(0x00000000, &disp_ctrl->winbuf.addr_v_offset);
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writel(0x00000000, &disp_ctrl->com.crc_checksum);
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writel(0x00000000, &disp_ctrl->com.pin_output_enb[0]);
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writel(0x00000000, &disp_ctrl->com.pin_output_enb[1]);
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writel(0x00000000, &disp_ctrl->com.pin_output_enb[2]);
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writel(0x00000000, &disp_ctrl->com.pin_output_enb[3]);
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writel(0x00000000, &disp_ctrl->disp.disp_signal_opt0);
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return 0;
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}
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static void dump_config(int panel_bpp, struct display_timing *timing)
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{
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printf("timing->hactive.typ = %d\n", timing->hactive.typ);
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printf("timing->vactive.typ = %d\n", timing->vactive.typ);
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printf("timing->pixelclock.typ = %d\n", timing->pixelclock.typ);
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printf("timing->hfront_porch.typ = %d\n", timing->hfront_porch.typ);
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printf("timing->hsync_len.typ = %d\n", timing->hsync_len.typ);
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printf("timing->hback_porch.typ = %d\n", timing->hback_porch.typ);
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printf("timing->vfront_porch.typ %d\n", timing->vfront_porch.typ);
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printf("timing->vsync_len.typ = %d\n", timing->vsync_len.typ);
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printf("timing->vback_porch.typ = %d\n", timing->vback_porch.typ);
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printf("panel_bits_per_pixel = %d\n", panel_bpp);
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}
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static int display_update_config_from_edid(struct udevice *dp_dev,
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int *panel_bppp,
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struct display_timing *timing)
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{
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return display_read_timing(dp_dev, timing);
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}
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static int display_init(struct udevice *dev, void *lcdbase,
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int fb_bits_per_pixel, struct display_timing *timing)
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{
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struct display_plat *disp_uc_plat;
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struct dc_ctlr *dc_ctlr;
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struct udevice *dp_dev;
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const int href_to_sync = 1, vref_to_sync = 1;
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int panel_bpp = 18; /* default 18 bits per pixel */
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u32 plld_rate;
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int ret;
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/*
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* Before we probe the display device (eDP), tell it that this device
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* is the source of the display data.
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*/
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ret = uclass_find_first_device(UCLASS_DISPLAY, &dp_dev);
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if (ret) {
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debug("%s: device '%s' display not found (ret=%d)\n", __func__,
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dev->name, ret);
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return ret;
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}
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disp_uc_plat = dev_get_uclass_platdata(dp_dev);
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debug("Found device '%s', disp_uc_priv=%p\n", dp_dev->name,
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disp_uc_plat);
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disp_uc_plat->src_dev = dev;
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ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev);
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if (ret) {
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debug("%s: Failed to probe eDP, ret=%d\n", __func__, ret);
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return ret;
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}
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dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev);
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if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
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debug("%s: Failed to decode display timing\n", __func__);
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return -EINVAL;
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}
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ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing);
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if (ret) {
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debug("%s: Failed to decode EDID, using defaults\n", __func__);
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dump_config(panel_bpp, timing);
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}
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/*
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* The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
|
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* and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
|
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* update_display_mode() for detail.
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*/
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plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2);
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if (plld_rate == 0) {
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printf("dc: clock init failed\n");
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return -EIO;
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} else if (plld_rate != timing->pixelclock.typ * 2) {
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debug("dc: plld rounded to %u\n", plld_rate);
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timing->pixelclock.typ = plld_rate / 2;
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}
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/* Init dc */
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ret = tegra_dc_init(dc_ctlr);
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if (ret) {
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debug("dc: init failed\n");
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return ret;
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}
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/* Configure dc mode */
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ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync);
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if (ret) {
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debug("dc: failed to configure display mode\n");
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return ret;
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}
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||||
/* Enable dp */
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ret = display_enable(dp_dev, panel_bpp, timing);
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if (ret) {
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debug("dc: failed to enable display: ret=%d\n", ret);
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return ret;
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||||
}
|
||||
|
||||
ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing);
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||||
if (ret) {
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debug("dc: failed to update window\n");
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return ret;
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||||
}
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||||
debug("%s: ready\n", __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
enum {
|
||||
/* Maximum LCD size we support */
|
||||
LCD_MAX_WIDTH = 1920,
|
||||
LCD_MAX_HEIGHT = 1200,
|
||||
LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */
|
||||
};
|
||||
|
||||
static int tegra124_lcd_init(struct udevice *dev, void *lcdbase,
|
||||
enum video_log2_bpp l2bpp)
|
||||
{
|
||||
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
|
||||
struct display_timing timing;
|
||||
int ret;
|
||||
|
||||
clock_set_up_plldp();
|
||||
clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000);
|
||||
|
||||
clock_enable(PERIPH_ID_HOST1X);
|
||||
clock_enable(PERIPH_ID_DISP1);
|
||||
clock_enable(PERIPH_ID_PWM);
|
||||
clock_enable(PERIPH_ID_DPAUX);
|
||||
clock_enable(PERIPH_ID_SOR0);
|
||||
udelay(2);
|
||||
|
||||
reset_set_enable(PERIPH_ID_HOST1X, 0);
|
||||
reset_set_enable(PERIPH_ID_DISP1, 0);
|
||||
reset_set_enable(PERIPH_ID_PWM, 0);
|
||||
reset_set_enable(PERIPH_ID_DPAUX, 0);
|
||||
reset_set_enable(PERIPH_ID_SOR0, 0);
|
||||
|
||||
ret = display_init(dev, lcdbase, 1 << l2bpp, &timing);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
uc_priv->xsize = roundup(timing.hactive.typ, 16);
|
||||
uc_priv->ysize = timing.vactive.typ;
|
||||
uc_priv->bpix = l2bpp;
|
||||
|
||||
video_set_flush_dcache(dev, 1);
|
||||
debug("%s: done\n", __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra124_lcd_probe(struct udevice *dev)
|
||||
{
|
||||
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
|
||||
ulong start;
|
||||
int ret;
|
||||
|
||||
start = get_timer(0);
|
||||
bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "lcd");
|
||||
ret = tegra124_lcd_init(dev, (void *)plat->base, VIDEO_BPP16);
|
||||
bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
|
||||
debug("LCD init took %lu ms\n", get_timer(start));
|
||||
if (ret)
|
||||
printf("%s: Error %d\n", __func__, ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra124_lcd_bind(struct udevice *dev)
|
||||
{
|
||||
struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
|
||||
|
||||
uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
|
||||
(1 << VIDEO_BPP16) / 8;
|
||||
debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id tegra124_lcd_ids[] = {
|
||||
{ .compatible = "nvidia,tegra124-dc" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(tegra124_dc) = {
|
||||
.name = "tegra124-dc",
|
||||
.id = UCLASS_VIDEO,
|
||||
.of_match = tegra124_lcd_ids,
|
||||
.bind = tegra124_lcd_bind,
|
||||
.probe = tegra124_lcd_probe,
|
||||
};
|
||||
@@ -0,0 +1,411 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2014, NVIDIA Corporation.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA_DISPLAYPORT_H
|
||||
#define _TEGRA_DISPLAYPORT_H
|
||||
|
||||
#include <linux/drm_dp_helper.h>
|
||||
|
||||
struct dpaux_ctlr {
|
||||
u32 reserved0;
|
||||
u32 intr_en_aux;
|
||||
u32 reserved2_4;
|
||||
u32 intr_aux;
|
||||
};
|
||||
|
||||
#define DPAUX_INTR_EN_AUX 0x1
|
||||
#define DPAUX_INTR_AUX 0x5
|
||||
#define DPAUX_DP_AUXDATA_WRITE_W(i) (0x9 + 4 * (i))
|
||||
#define DPAUX_DP_AUXDATA_READ_W(i) (0x19 + 4 * (i))
|
||||
#define DPAUX_DP_AUXADDR 0x29
|
||||
#define DPAUX_DP_AUXCTL 0x2d
|
||||
#define DPAUX_DP_AUXCTL_CMDLEN_SHIFT 0
|
||||
#define DPAUX_DP_AUXCTL_CMDLEN_FIELD 0xff
|
||||
#define DPAUX_DP_AUXCTL_CMD_SHIFT 12
|
||||
#define DPAUX_DP_AUXCTL_CMD_MASK (0xf << 12)
|
||||
#define DPAUX_DP_AUXCTL_CMD_I2CWR (0 << 12)
|
||||
#define DPAUX_DP_AUXCTL_CMD_I2CRD (1 << 12)
|
||||
#define DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT (2 << 12)
|
||||
#define DPAUX_DP_AUXCTL_CMD_MOTWR (4 << 12)
|
||||
#define DPAUX_DP_AUXCTL_CMD_MOTRD (5 << 12)
|
||||
#define DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT (6 << 12)
|
||||
#define DPAUX_DP_AUXCTL_CMD_AUXWR (8 << 12)
|
||||
#define DPAUX_DP_AUXCTL_CMD_AUXRD (9 << 12)
|
||||
#define DPAUX_DP_AUXCTL_TRANSACTREQ_SHIFT 16
|
||||
#define DPAUX_DP_AUXCTL_TRANSACTREQ_MASK (0x1 << 16)
|
||||
#define DPAUX_DP_AUXCTL_TRANSACTREQ_DONE (0 << 16)
|
||||
#define DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING (1 << 16)
|
||||
#define DPAUX_DP_AUXCTL_RST_SHIFT 31
|
||||
#define DPAUX_DP_AUXCTL_RST_DEASSERT (0 << 31)
|
||||
#define DPAUX_DP_AUXCTL_RST_ASSERT (1 << 31)
|
||||
#define DPAUX_DP_AUXSTAT 0x31
|
||||
#define DPAUX_DP_AUXSTAT_HPD_STATUS_SHIFT 28
|
||||
#define DPAUX_DP_AUXSTAT_HPD_STATUS_UNPLUG (0 << 28)
|
||||
#define DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED (1 << 28)
|
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SHIFT 20
|
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_MASK (0xf << 20)
|
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_IDLE (0 << 20)
|
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SYNC (1 << 20)
|
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_START1 (2 << 20)
|
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_COMMAND (3 << 20)
|
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_ADDRESS (4 << 20)
|
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_LENGTH (5 << 20)
|
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_WRITE1 (6 << 20)
|
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_READ1 (7 << 20)
|
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_GET_M (8 << 20)
|
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP1 (9 << 20)
|
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP2 (10 << 20)
|
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_REPLY (11 << 20)
|
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_CLEANUP (12 << 20)
|
||||
#define DPAUX_DP_AUXSTAT_REPLYTYPE_SHIFT 16
|
||||
#define DPAUX_DP_AUXSTAT_REPLYTYPE_MASK (0xf << 16)
|
||||
#define DPAUX_DP_AUXSTAT_REPLYTYPE_ACK (0 << 16)
|
||||
#define DPAUX_DP_AUXSTAT_REPLYTYPE_NACK (1 << 16)
|
||||
#define DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER (2 << 16)
|
||||
#define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK (4 << 16)
|
||||
#define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER (8 << 16)
|
||||
#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SHIFT 11
|
||||
#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_NOT_PENDING (0 << 11)
|
||||
#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING (1 << 11)
|
||||
#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SHIFT 10
|
||||
#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_NOT_PENDING (0 << 10)
|
||||
#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING (1 << 10)
|
||||
#define DPAUX_DP_AUXSTAT_RX_ERROR_SHIFT 9
|
||||
#define DPAUX_DP_AUXSTAT_RX_ERROR_NOT_PENDING (0 << 9)
|
||||
#define DPAUX_DP_AUXSTAT_RX_ERROR_PENDING (1 << 9)
|
||||
#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_SHIFT 8
|
||||
#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_NOT_PENDING (0 << 8)
|
||||
#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING (1 << 8)
|
||||
#define DPAUX_DP_AUXSTAT_REPLY_M_SHIFT 0
|
||||
#define DPAUX_DP_AUXSTAT_REPLY_M_MASK (0xff << 0)
|
||||
#define DPAUX_HPD_CONFIG (0x3d)
|
||||
#define DPAUX_HPD_IRQ_CONFIG 0x41
|
||||
#define DPAUX_DP_AUX_CONFIG 0x45
|
||||
#define DPAUX_HYBRID_PADCTL 0x49
|
||||
#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_SHIFT 15
|
||||
#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_DISABLE (0 << 15)
|
||||
#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE (1 << 15)
|
||||
#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_SHIFT 14
|
||||
#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_DISABLE (0 << 14)
|
||||
#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE (1 << 14)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_CMH_SHIFT 12
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_CMH_DEFAULT_MASK (0x3 << 12)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_60 (0 << 12)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_64 (1 << 12)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 (2 << 12)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_56 (3 << 12)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_SHIFT 8
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_DEFAULT_MASK (0x7 << 8)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_78 (0 << 8)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_60 (1 << 8)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_54 (2 << 8)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_45 (3 << 8)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 (4 << 8)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_42 (5 << 8)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_39 (6 << 8)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_34 (7 << 8)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT 2
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVI_DEFAULT_MASK (0x3f << 2)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_SHIFT 1
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_DISABLE (0 << 1)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE (1 << 1)
|
||||
#define DPAUX_HYBRID_PADCTL_MODE_SHIFT 0
|
||||
#define DPAUX_HYBRID_PADCTL_MODE_AUX 0
|
||||
#define DPAUX_HYBRID_PADCTL_MODE_I2C 1
|
||||
#define DPAUX_HYBRID_SPARE 0x4d
|
||||
#define DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP 0
|
||||
#define DPAUX_HYBRID_SPARE_PAD_PWR_POWERDOWN 1
|
||||
|
||||
#define DP_AUX_DEFER_MAX_TRIES 7
|
||||
#define DP_AUX_TIMEOUT_MAX_TRIES 2
|
||||
#define DP_POWER_ON_MAX_TRIES 3
|
||||
|
||||
#define DP_AUX_MAX_BYTES 16
|
||||
|
||||
#define DP_AUX_TIMEOUT_MS 40
|
||||
#define DP_DPCP_RETRY_SLEEP_NS 400
|
||||
|
||||
static const u32 tegra_dp_vs_regs[][4][4] = {
|
||||
/* postcursor2 L0 */
|
||||
{
|
||||
/* pre-emphasis: L0, L1, L2, L3 */
|
||||
{0x13, 0x19, 0x1e, 0x28}, /* voltage swing: L0 */
|
||||
{0x1e, 0x25, 0x2d}, /* L1 */
|
||||
{0x28, 0x32}, /* L2 */
|
||||
{0x3c}, /* L3 */
|
||||
},
|
||||
|
||||
/* postcursor2 L1 */
|
||||
{
|
||||
{0x12, 0x17, 0x1b, 0x25},
|
||||
{0x1c, 0x23, 0x2a},
|
||||
{0x25, 0x2f},
|
||||
{0x39},
|
||||
},
|
||||
|
||||
/* postcursor2 L2 */
|
||||
{
|
||||
{0x12, 0x16, 0x1a, 0x22},
|
||||
{0x1b, 0x20, 0x27},
|
||||
{0x24, 0x2d},
|
||||
{0x36},
|
||||
},
|
||||
|
||||
/* postcursor2 L3 */
|
||||
{
|
||||
{0x11, 0x14, 0x17, 0x1f},
|
||||
{0x19, 0x1e, 0x24},
|
||||
{0x22, 0x2a},
|
||||
{0x32},
|
||||
},
|
||||
};
|
||||
|
||||
static const u32 tegra_dp_pe_regs[][4][4] = {
|
||||
/* postcursor2 L0 */
|
||||
{
|
||||
/* pre-emphasis: L0, L1, L2, L3 */
|
||||
{0x00, 0x09, 0x13, 0x25}, /* voltage swing: L0 */
|
||||
{0x00, 0x0f, 0x1e}, /* L1 */
|
||||
{0x00, 0x14}, /* L2 */
|
||||
{0x00}, /* L3 */
|
||||
},
|
||||
|
||||
/* postcursor2 L1 */
|
||||
{
|
||||
{0x00, 0x0a, 0x14, 0x28},
|
||||
{0x00, 0x0f, 0x1e},
|
||||
{0x00, 0x14},
|
||||
{0x00},
|
||||
},
|
||||
|
||||
/* postcursor2 L2 */
|
||||
{
|
||||
{0x00, 0x0a, 0x14, 0x28},
|
||||
{0x00, 0x0f, 0x1e},
|
||||
{0x00, 0x14},
|
||||
{0x00},
|
||||
},
|
||||
|
||||
/* postcursor2 L3 */
|
||||
{
|
||||
{0x00, 0x0a, 0x14, 0x28},
|
||||
{0x00, 0x0f, 0x1e},
|
||||
{0x00, 0x14},
|
||||
{0x00},
|
||||
},
|
||||
};
|
||||
|
||||
static const u32 tegra_dp_pc_regs[][4][4] = {
|
||||
/* postcursor2 L0 */
|
||||
{
|
||||
/* pre-emphasis: L0, L1, L2, L3 */
|
||||
{0x00, 0x00, 0x00, 0x00}, /* voltage swing: L0 */
|
||||
{0x00, 0x00, 0x00}, /* L1 */
|
||||
{0x00, 0x00}, /* L2 */
|
||||
{0x00}, /* L3 */
|
||||
},
|
||||
|
||||
/* postcursor2 L1 */
|
||||
{
|
||||
{0x02, 0x02, 0x04, 0x05},
|
||||
{0x02, 0x04, 0x05},
|
||||
{0x04, 0x05},
|
||||
{0x05},
|
||||
},
|
||||
|
||||
/* postcursor2 L2 */
|
||||
{
|
||||
{0x04, 0x05, 0x08, 0x0b},
|
||||
{0x05, 0x09, 0x0b},
|
||||
{0x08, 0x0a},
|
||||
{0x0b},
|
||||
},
|
||||
|
||||
/* postcursor2 L3 */
|
||||
{
|
||||
{0x05, 0x09, 0x0b, 0x12},
|
||||
{0x09, 0x0d, 0x12},
|
||||
{0x0b, 0x0f},
|
||||
{0x12},
|
||||
},
|
||||
};
|
||||
|
||||
static const u32 tegra_dp_tx_pu[][4][4] = {
|
||||
/* postcursor2 L0 */
|
||||
{
|
||||
/* pre-emphasis: L0, L1, L2, L3 */
|
||||
{0x20, 0x30, 0x40, 0x60}, /* voltage swing: L0 */
|
||||
{0x30, 0x40, 0x60}, /* L1 */
|
||||
{0x40, 0x60}, /* L2 */
|
||||
{0x60}, /* L3 */
|
||||
},
|
||||
|
||||
/* postcursor2 L1 */
|
||||
{
|
||||
{0x20, 0x20, 0x30, 0x50},
|
||||
{0x30, 0x40, 0x50},
|
||||
{0x40, 0x50},
|
||||
{0x60},
|
||||
},
|
||||
|
||||
/* postcursor2 L2 */
|
||||
{
|
||||
{0x20, 0x20, 0x30, 0x40},
|
||||
{0x30, 0x30, 0x40},
|
||||
{0x40, 0x50},
|
||||
{0x60},
|
||||
},
|
||||
|
||||
/* postcursor2 L3 */
|
||||
{
|
||||
{0x20, 0x20, 0x20, 0x40},
|
||||
{0x30, 0x30, 0x40},
|
||||
{0x40, 0x40},
|
||||
{0x60},
|
||||
},
|
||||
};
|
||||
|
||||
enum {
|
||||
DRIVECURRENT_LEVEL0 = 0,
|
||||
DRIVECURRENT_LEVEL1 = 1,
|
||||
DRIVECURRENT_LEVEL2 = 2,
|
||||
DRIVECURRENT_LEVEL3 = 3,
|
||||
};
|
||||
|
||||
enum {
|
||||
PREEMPHASIS_DISABLED = 0,
|
||||
PREEMPHASIS_LEVEL1 = 1,
|
||||
PREEMPHASIS_LEVEL2 = 2,
|
||||
PREEMPHASIS_LEVEL3 = 3,
|
||||
};
|
||||
|
||||
enum {
|
||||
POSTCURSOR2_LEVEL0 = 0,
|
||||
POSTCURSOR2_LEVEL1 = 1,
|
||||
POSTCURSOR2_LEVEL2 = 2,
|
||||
POSTCURSOR2_LEVEL3 = 3,
|
||||
POSTCURSOR2_SUPPORTED
|
||||
};
|
||||
|
||||
static inline int tegra_dp_is_max_vs(u32 pe, u32 vs)
|
||||
{
|
||||
return (vs < (DRIVECURRENT_LEVEL3 - pe)) ? 0 : 1;
|
||||
}
|
||||
|
||||
static inline int tegra_dp_is_max_pe(u32 pe, u32 vs)
|
||||
{
|
||||
return (pe < (PREEMPHASIS_LEVEL3 - vs)) ? 0 : 1;
|
||||
}
|
||||
|
||||
static inline int tegra_dp_is_max_pc(u32 pc)
|
||||
{
|
||||
return (pc < POSTCURSOR2_LEVEL3) ? 0 : 1;
|
||||
}
|
||||
|
||||
/* DPCD definitions which are not defined in drm_dp_helper.h */
|
||||
#define DP_DPCD_REV_MAJOR_SHIFT 4
|
||||
#define DP_DPCD_REV_MAJOR_MASK (0xf << 4)
|
||||
#define DP_DPCD_REV_MINOR_SHIFT 0
|
||||
#define DP_DPCD_REV_MINOR_MASK 0xf
|
||||
|
||||
#define DP_MAX_LINK_RATE_VAL_1_62_GPBS 0x6
|
||||
#define DP_MAX_LINK_RATE_VAL_2_70_GPBS 0xa
|
||||
#define DP_MAX_LINK_RATE_VAL_5_40_GPBS 0x4
|
||||
|
||||
#define DP_MAX_LANE_COUNT_LANE_1 0x1
|
||||
#define DP_MAX_LANE_COUNT_LANE_2 0x2
|
||||
#define DP_MAX_LANE_COUNT_LANE_4 0x4
|
||||
#define DP_MAX_LANE_COUNT_TPS3_SUPPORTED_YES (1 << 6)
|
||||
#define DP_MAX_LANE_COUNT_ENHANCED_FRAMING_YES (1 << 7)
|
||||
|
||||
#define NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT 0
|
||||
#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T (0x00000001 << 2)
|
||||
#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F (0x00000000 << 2)
|
||||
#define NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3
|
||||
#define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T (0x00000001 << 5)
|
||||
#define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F (0x00000000 << 5)
|
||||
|
||||
#define DP_MAX_DOWNSPREAD_VAL_NONE 0
|
||||
#define DP_MAX_DOWNSPREAD_VAL_0_5_PCT 1
|
||||
#define DP_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T (1 << 6)
|
||||
|
||||
#define DP_EDP_CONFIGURATION_CAP_ASC_RESET_YES 1
|
||||
#define DP_EDP_CONFIGURATION_CAP_FRAMING_CHANGE_YES (1 << 1)
|
||||
|
||||
#define DP_LANE_COUNT_SET_ENHANCEDFRAMING_T (1 << 7)
|
||||
|
||||
#define DP_TRAINING_PATTERN_SET_SC_DISABLED_T (1 << 5)
|
||||
#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F (0x00000000 << 5)
|
||||
#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T (0x00000001 << 5)
|
||||
|
||||
#define DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_DISABLE 0
|
||||
#define DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_ENABLE 1
|
||||
|
||||
#define NV_DPCD_TRAINING_LANE0_1_SET2 0x10f
|
||||
#define NV_DPCD_TRAINING_LANE2_3_SET2 0x110
|
||||
#define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T (1 << 2)
|
||||
#define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F (0 << 2)
|
||||
#define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T (1 << 6)
|
||||
#define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F (0 << 6)
|
||||
#define NV_DPCD_LANEX_SET2_PC2_SHIFT 0
|
||||
#define NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT 4
|
||||
|
||||
#define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT 0
|
||||
#define NV_DPCD_STATUS_LANEX_CR_DONE_NO (0x00000000)
|
||||
#define NV_DPCD_STATUS_LANEX_CR_DONE_YES (0x00000001)
|
||||
#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT 1
|
||||
#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000 << 1)
|
||||
#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001 << 1)
|
||||
#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT 2
|
||||
#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000 << 2)
|
||||
#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001 << 2)
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT 4
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000 << 4)
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001 << 4)
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5)
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5)
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT 6
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000 << 6)
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6)
|
||||
|
||||
#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED (0x00000204)
|
||||
#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_NO (0x00000000)
|
||||
#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES (0x00000001)
|
||||
|
||||
#define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT 0
|
||||
#define NV_DPCD_STATUS_LANEX_CR_DONE_NO (0x00000000)
|
||||
#define NV_DPCD_STATUS_LANEX_CR_DONE_YES (0x00000001)
|
||||
#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT 1
|
||||
#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000 << 1)
|
||||
#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001 << 1)
|
||||
#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT 2
|
||||
#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000 << 2)
|
||||
#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001 << 2)
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT 4
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000 << 4)
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001 << 4)
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5)
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5)
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT 6
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000 << 6)
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6)
|
||||
|
||||
#define NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT 0
|
||||
#define NV_DPCD_ADJUST_REQ_LANEX_DC_MASK 0x3
|
||||
#define NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT 2
|
||||
#define NV_DPCD_ADJUST_REQ_LANEX_PE_MASK (0x3 << 2)
|
||||
#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT 4
|
||||
#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK (0x3 << 4)
|
||||
#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT 6
|
||||
#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK (0x3 << 6)
|
||||
#define NV_DPCD_ADJUST_REQ_POST_CURSOR2 (0x0000020C)
|
||||
#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK 0x3
|
||||
#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(i) (i*2)
|
||||
|
||||
#define NV_DPCD_TRAINING_AUX_RD_INTERVAL (0x0000000E)
|
||||
#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F (0x00000000 << 2)
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,914 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2011-2013, NVIDIA Corporation.
|
||||
*/
|
||||
|
||||
#ifndef _VIDEO_TEGRA124_SOR_H
|
||||
#define _VIDEO_TEGRA124_SOR_H
|
||||
|
||||
#define SUPER_STATE0 0x1
|
||||
#define SUPER_STATE0_UPDATE_SHIFT 0
|
||||
#define SUPER_STATE0_UPDATE_DEFAULT_MASK 0x1
|
||||
#define SUPER_STATE1 0x2
|
||||
#define SUPER_STATE1_ATTACHED_SHIFT 3
|
||||
#define SUPER_STATE1_ATTACHED_NO (0 << 3)
|
||||
#define SUPER_STATE1_ATTACHED_YES (1 << 3)
|
||||
#define SUPER_STATE1_ASY_ORMODE_SHIFT 2
|
||||
#define SUPER_STATE1_ASY_ORMODE_SAFE (0 << 2)
|
||||
#define SUPER_STATE1_ASY_ORMODE_NORMAL (1 << 2)
|
||||
#define SUPER_STATE1_ASY_HEAD_OP_SHIFT 0
|
||||
#define SUPER_STATE1_ASY_HEAD_OP_DEFAULT_MASK 0x3
|
||||
#define SUPER_STATE1_ASY_HEAD_OP_SLEEP 0
|
||||
#define SUPER_STATE1_ASY_HEAD_OP_SNOOZE 1
|
||||
#define SUPER_STATE1_ASY_HEAD_OP_AWAKE 2
|
||||
#define STATE0 0x3
|
||||
#define STATE0_UPDATE_SHIFT 0
|
||||
#define STATE0_UPDATE_DEFAULT_MASK 0x1
|
||||
#define STATE1 0x4
|
||||
#define STATE1_ASY_PIXELDEPTH_SHIFT 17
|
||||
#define STATE1_ASY_PIXELDEPTH_DEFAULT_MASK (0xf << 17)
|
||||
#define STATE1_ASY_PIXELDEPTH_BPP_16_422 (1 << 17)
|
||||
#define STATE1_ASY_PIXELDEPTH_BPP_18_444 (2 << 17)
|
||||
#define STATE1_ASY_PIXELDEPTH_BPP_20_422 (3 << 17)
|
||||
#define STATE1_ASY_PIXELDEPTH_BPP_24_422 (4 << 17)
|
||||
#define STATE1_ASY_PIXELDEPTH_BPP_24_444 (5 << 17)
|
||||
#define STATE1_ASY_PIXELDEPTH_BPP_30_444 (6 << 17)
|
||||
#define STATE1_ASY_PIXELDEPTH_BPP_32_422 (7 << 17)
|
||||
#define STATE1_ASY_PIXELDEPTH_BPP_36_444 (8 << 17)
|
||||
#define STATE1_ASY_PIXELDEPTH_BPP_48_444 (9 << 17)
|
||||
#define STATE1_ASY_REPLICATE_SHIFT 15
|
||||
#define STATE1_ASY_REPLICATE_DEFAULT_MASK (3 << 15)
|
||||
#define STATE1_ASY_REPLICATE_OFF (0 << 15)
|
||||
#define STATE1_ASY_REPLICATE_X2 (1 << 15)
|
||||
#define STATE1_ASY_REPLICATE_X4 (2 << 15)
|
||||
#define STATE1_ASY_DEPOL_SHIFT 14
|
||||
#define STATE1_ASY_DEPOL_DEFAULT_MASK (1 << 14)
|
||||
#define STATE1_ASY_DEPOL_POSITIVE_TRUE (0 << 14)
|
||||
#define STATE1_ASY_DEPOL_NEGATIVE_TRUE (1 << 14)
|
||||
#define STATE1_ASY_VSYNCPOL_SHIFT 13
|
||||
#define STATE1_ASY_VSYNCPOL_DEFAULT_MASK (1 << 13)
|
||||
#define STATE1_ASY_VSYNCPOL_POSITIVE_TRUE (0 << 13)
|
||||
#define STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE (1 << 13)
|
||||
#define STATE1_ASY_HSYNCPOL_SHIFT 12
|
||||
#define STATE1_ASY_HSYNCPOL_DEFAULT_MASK (1 << 12)
|
||||
#define STATE1_ASY_HSYNCPOL_POSITIVE_TRUE (0 << 12)
|
||||
#define STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE (1 << 12)
|
||||
#define STATE1_ASY_PROTOCOL_SHIFT 8
|
||||
#define STATE1_ASY_PROTOCOL_DEFAULT_MASK (0xf << 8)
|
||||
#define STATE1_ASY_PROTOCOL_LVDS_CUSTOM (0 << 8)
|
||||
#define STATE1_ASY_PROTOCOL_DP_A (8 << 8)
|
||||
#define STATE1_ASY_PROTOCOL_DP_B (9 << 8)
|
||||
#define STATE1_ASY_PROTOCOL_CUSTOM (15 << 8)
|
||||
#define STATE1_ASY_CRCMODE_SHIFT 6
|
||||
#define STATE1_ASY_CRCMODE_DEFAULT_MASK (3 << 6)
|
||||
#define STATE1_ASY_CRCMODE_ACTIVE_RASTER (0 << 6)
|
||||
#define STATE1_ASY_CRCMODE_COMPLETE_RASTER (1 << 6)
|
||||
#define STATE1_ASY_CRCMODE_NON_ACTIVE_RASTER (2 << 6)
|
||||
#define STATE1_ASY_SUBOWNER_SHIFT 4
|
||||
#define STATE1_ASY_SUBOWNER_DEFAULT_MASK (3 << 4)
|
||||
#define STATE1_ASY_SUBOWNER_NONE (0 << 4)
|
||||
#define STATE1_ASY_SUBOWNER_SUBHEAD0 (1 << 4)
|
||||
#define STATE1_ASY_SUBOWNER_SUBHEAD1 (2 << 4)
|
||||
#define STATE1_ASY_SUBOWNER_BOTH (3 << 4)
|
||||
#define STATE1_ASY_OWNER_SHIFT 0
|
||||
#define STATE1_ASY_OWNER_DEFAULT_MASK 0xf
|
||||
#define STATE1_ASY_OWNER_NONE 0
|
||||
#define STATE1_ASY_OWNER_HEAD0 1
|
||||
#define STATE1_ASY_OWNER_HEAD1 2
|
||||
#define NV_HEAD_STATE0(i) 0x5
|
||||
#define NV_HEAD_STATE0_INTERLACED_SHIFT 4
|
||||
#define NV_HEAD_STATE0_INTERLACED_DEFAULT_MASK (3 << 4)
|
||||
#define NV_HEAD_STATE0_INTERLACED_PROGRESSIVE (0 << 4)
|
||||
#define NV_HEAD_STATE0_INTERLACED_INTERLACED (1 << 4)
|
||||
#define NV_HEAD_STATE0_RANGECOMPRESS_SHIFT 3
|
||||
#define NV_HEAD_STATE0_RANGECOMPRESS_DEFAULT_MASK (1 << 3)
|
||||
#define NV_HEAD_STATE0_RANGECOMPRESS_DISABLE (0 << 3)
|
||||
#define NV_HEAD_STATE0_RANGECOMPRESS_ENABLE (1 << 3)
|
||||
#define NV_HEAD_STATE0_DYNRANGE_SHIFT 2
|
||||
#define NV_HEAD_STATE0_DYNRANGE_DEFAULT_MASK (1 << 2)
|
||||
#define NV_HEAD_STATE0_DYNRANGE_VESA (0 << 2)
|
||||
#define NV_HEAD_STATE0_DYNRANGE_CEA (1 << 2)
|
||||
#define NV_HEAD_STATE0_COLORSPACE_SHIFT 0
|
||||
#define NV_HEAD_STATE0_COLORSPACE_DEFAULT_MASK 0x3
|
||||
#define NV_HEAD_STATE0_COLORSPACE_RGB 0
|
||||
#define NV_HEAD_STATE0_COLORSPACE_YUV_601 1
|
||||
#define NV_HEAD_STATE0_COLORSPACE_YUV_709 2
|
||||
#define NV_HEAD_STATE1(i) (7 + i)
|
||||
#define NV_HEAD_STATE1_VTOTAL_SHIFT 16
|
||||
#define NV_HEAD_STATE1_VTOTAL_DEFAULT_MASK (0x7fff << 16)
|
||||
#define NV_HEAD_STATE1_HTOTAL_SHIFT 0
|
||||
#define NV_HEAD_STATE1_HTOTAL_DEFAULT_MASK 0x7fff
|
||||
#define NV_HEAD_STATE2(i) (9 + i)
|
||||
#define NV_HEAD_STATE2_VSYNC_END_SHIFT 16
|
||||
#define NV_HEAD_STATE2_VSYNC_END_DEFAULT_MASK (0x7fff << 16)
|
||||
#define NV_HEAD_STATE2_HSYNC_END_SHIFT 0
|
||||
#define NV_HEAD_STATE2_HSYNC_END_DEFAULT_MASK 0x7fff
|
||||
#define NV_HEAD_STATE3(i) (0xb + i)
|
||||
#define NV_HEAD_STATE3_VBLANK_END_SHIFT 16
|
||||
#define NV_HEAD_STATE3_VBLANK_END_DEFAULT_MASK (0x7fff << 16)
|
||||
#define NV_HEAD_STATE3_HBLANK_END_SHIFT 0
|
||||
#define NV_HEAD_STATE3_HBLANK_END_DEFAULT_MASK 0x7fff
|
||||
#define NV_HEAD_STATE4(i) (0xd + i)
|
||||
#define NV_HEAD_STATE4_VBLANK_START_SHIFT 16
|
||||
#define NV_HEAD_STATE4_VBLANK_START_DEFAULT_MASK (0x7fff << 16)
|
||||
#define NV_HEAD_STATE4_HBLANK_START_SHIFT 0
|
||||
#define NV_HEAD_STATE4_HBLANK_START_DEFAULT_MASK 0x7fff
|
||||
#define NV_HEAD_STATE5(i) (0xf + i)
|
||||
#define CRC_CNTRL 0x11
|
||||
#define CRC_CNTRL_ARM_CRC_ENABLE_SHIFT 0
|
||||
#define CRC_CNTRL_ARM_CRC_ENABLE_NO 0
|
||||
#define CRC_CNTRL_ARM_CRC_ENABLE_YES 1
|
||||
#define CRC_CNTRL_ARM_CRC_ENABLE_DIS 0
|
||||
#define CRC_CNTRL_ARM_CRC_ENABLE_EN 1
|
||||
#define CLK_CNTRL 0x13
|
||||
#define CLK_CNTRL_DP_CLK_SEL_SHIFT 0
|
||||
#define CLK_CNTRL_DP_CLK_SEL_MASK 0x3
|
||||
#define CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK 0
|
||||
#define CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK 1
|
||||
#define CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK 2
|
||||
#define CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK 3
|
||||
#define CLK_CNTRL_DP_LINK_SPEED_SHIFT 2
|
||||
#define CLK_CNTRL_DP_LINK_SPEED_MASK (0x1f << 2)
|
||||
#define CLK_CNTRL_DP_LINK_SPEED_G1_62 (6 << 2)
|
||||
#define CLK_CNTRL_DP_LINK_SPEED_G2_7 (10 << 2)
|
||||
#define CLK_CNTRL_DP_LINK_SPEED_LVDS (7 << 2)
|
||||
#define CAP 0x14
|
||||
#define CAP_DP_A_SHIFT 24
|
||||
#define CAP_DP_A_DEFAULT_MASK (1 << 24)
|
||||
#define CAP_DP_A_FALSE (0 << 24)
|
||||
#define CAP_DP_A_TRUE (1 << 24)
|
||||
#define CAP_DP_B_SHIFT 25
|
||||
#define CAP_DP_B_DEFAULT_MASK (1 << 24)
|
||||
#define CAP_DP_B_FALSE (0 << 24)
|
||||
#define CAP_DP_B_TRUE (1 << 24)
|
||||
#define PWR 0x15
|
||||
#define PWR_SETTING_NEW_SHIFT 31
|
||||
#define PWR_SETTING_NEW_DEFAULT_MASK (1 << 31)
|
||||
#define PWR_SETTING_NEW_DONE (0 << 31)
|
||||
#define PWR_SETTING_NEW_PENDING (1 << 31)
|
||||
#define PWR_SETTING_NEW_TRIGGER (1 << 31)
|
||||
#define PWR_MODE_SHIFT 28
|
||||
#define PWR_MODE_DEFAULT_MASK (1 << 28)
|
||||
#define PWR_MODE_NORMAL (0 << 28)
|
||||
#define PWR_MODE_SAFE (1 << 28)
|
||||
#define PWR_HALT_DELAY_SHIFT 24
|
||||
#define PWR_HALT_DELAY_DEFAULT_MASK (1 << 24)
|
||||
#define PWR_HALT_DELAY_DONE (0 << 24)
|
||||
#define PWR_HALT_DELAY_ACTIVE (1 << 24)
|
||||
#define PWR_SAFE_START_SHIFT 17
|
||||
#define PWR_SAFE_START_DEFAULT_MASK (1 << 17)
|
||||
#define PWR_SAFE_START_NORMAL (0 << 17)
|
||||
#define PWR_SAFE_START_ALT (1 << 17)
|
||||
#define PWR_SAFE_STATE_SHIFT 16
|
||||
#define PWR_SAFE_STATE_DEFAULT_MASK (1 << 16)
|
||||
#define PWR_SAFE_STATE_PD (0 << 16)
|
||||
#define PWR_SAFE_STATE_PU (1 << 16)
|
||||
#define PWR_NORMAL_START_SHIFT 1
|
||||
#define PWR_NORMAL_START_DEFAULT_MASK (1 << 1)
|
||||
#define PWR_NORMAL_START_NORMAL (0 << 16)
|
||||
#define PWR_NORMAL_START_ALT (1 << 16)
|
||||
#define PWR_NORMAL_STATE_SHIFT 0
|
||||
#define PWR_NORMAL_STATE_DEFAULT_MASK 0x1
|
||||
#define PWR_NORMAL_STATE_PD 0
|
||||
#define PWR_NORMAL_STATE_PU 1
|
||||
#define TEST 0x16
|
||||
#define TEST_TESTMUX_SHIFT 24
|
||||
#define TEST_TESTMUX_DEFAULT_MASK (0xff << 24)
|
||||
#define TEST_TESTMUX_AVSS (0 << 24)
|
||||
#define TEST_TESTMUX_CLOCKIN (2 << 24)
|
||||
#define TEST_TESTMUX_PLL_VOL (4 << 24)
|
||||
#define TEST_TESTMUX_SLOWCLKINT (8 << 24)
|
||||
#define TEST_TESTMUX_AVDD (16 << 24)
|
||||
#define TEST_TESTMUX_VDDREG (32 << 24)
|
||||
#define TEST_TESTMUX_REGREF_VDDREG (64 << 24)
|
||||
#define TEST_TESTMUX_REGREF_AVDD (128 << 24)
|
||||
#define TEST_CRC_SHIFT 23
|
||||
#define TEST_CRC_PRE_SERIALIZE (0 << 23)
|
||||
#define TEST_CRC_POST_DESERIALIZE (1 << 23)
|
||||
#define TEST_TPAT_SHIFT 20
|
||||
#define TEST_TPAT_DEFAULT_MASK (7 << 20)
|
||||
#define TEST_TPAT_LO (0 << 20)
|
||||
#define TEST_TPAT_TDAT (1 << 20)
|
||||
#define TEST_TPAT_RAMP (2 << 20)
|
||||
#define TEST_TPAT_WALK (3 << 20)
|
||||
#define TEST_TPAT_MAXSTEP (4 << 20)
|
||||
#define TEST_TPAT_MINSTEP (5 << 20)
|
||||
#define TEST_DSRC_SHIFT 16
|
||||
#define TEST_DSRC_DEFAULT_MASK (3 << 16)
|
||||
#define TEST_DSRC_NORMAL (0 << 16)
|
||||
#define TEST_DSRC_DEBUG (1 << 16)
|
||||
#define TEST_DSRC_TGEN (2 << 16)
|
||||
#define TEST_HEAD_NUMBER_SHIFT 12
|
||||
#define TEST_HEAD_NUMBER_DEFAULT_MASK (3 << 12)
|
||||
#define TEST_HEAD_NUMBER_NONE (0 << 12)
|
||||
#define TEST_HEAD_NUMBER_HEAD0 (1 << 12)
|
||||
#define TEST_HEAD_NUMBER_HEAD1 (2 << 12)
|
||||
#define TEST_ATTACHED_SHIFT 10
|
||||
#define TEST_ATTACHED_DEFAULT_MASK (1 << 10)
|
||||
#define TEST_ATTACHED_FALSE (0 << 10)
|
||||
#define TEST_ATTACHED_TRUE (1 << 10)
|
||||
#define TEST_ACT_HEAD_OPMODE_SHIFT 8
|
||||
#define TEST_ACT_HEAD_OPMODE_DEFAULT_MASK (3 << 8)
|
||||
#define TEST_ACT_HEAD_OPMODE_SLEEP (0 << 8)
|
||||
#define TEST_ACT_HEAD_OPMODE_SNOOZE (1 << 8)
|
||||
#define TEST_ACT_HEAD_OPMODE_AWAKE (2 << 8)
|
||||
#define TEST_INVD_SHIFT 6
|
||||
#define TEST_INVD_DISABLE (0 << 6)
|
||||
#define TEST_INVD_ENABLE (1 << 6)
|
||||
#define TEST_TEST_ENABLE_SHIFT 1
|
||||
#define TEST_TEST_ENABLE_DISABLE (0 << 1)
|
||||
#define TEST_TEST_ENABLE_ENABLE (1 << 1)
|
||||
#define PLL0 0x17
|
||||
#define PLL0_ICHPMP_SHFIT 24
|
||||
#define PLL0_ICHPMP_DEFAULT_MASK (0xf << 24)
|
||||
#define PLL0_VCOCAP_SHIFT 8
|
||||
#define PLL0_VCOCAP_DEFAULT_MASK (0xf << 8)
|
||||
#define PLL0_PLLREG_LEVEL_SHIFT 6
|
||||
#define PLL0_PLLREG_LEVEL_DEFAULT_MASK (3 << 6)
|
||||
#define PLL0_PLLREG_LEVEL_V25 (0 << 6)
|
||||
#define PLL0_PLLREG_LEVEL_V15 (1 << 6)
|
||||
#define PLL0_PLLREG_LEVEL_V35 (2 << 6)
|
||||
#define PLL0_PLLREG_LEVEL_V45 (3 << 6)
|
||||
#define PLL0_PULLDOWN_SHIFT 5
|
||||
#define PLL0_PULLDOWN_DEFAULT_MASK (1 << 5)
|
||||
#define PLL0_PULLDOWN_DISABLE (0 << 5)
|
||||
#define PLL0_PULLDOWN_ENABLE (1 << 5)
|
||||
#define PLL0_RESISTORSEL_SHIFT 4
|
||||
#define PLL0_RESISTORSEL_DEFAULT_MASK (1 << 4)
|
||||
#define PLL0_RESISTORSEL_INT (0 << 4)
|
||||
#define PLL0_RESISTORSEL_EXT (1 << 4)
|
||||
#define PLL0_VCOPD_SHIFT 2
|
||||
#define PLL0_VCOPD_MASK (1 << 2)
|
||||
#define PLL0_VCOPD_RESCIND (0 << 2)
|
||||
#define PLL0_VCOPD_ASSERT (1 << 2)
|
||||
#define PLL0_PWR_SHIFT 0
|
||||
#define PLL0_PWR_MASK 1
|
||||
#define PLL0_PWR_ON 0
|
||||
#define PLL0_PWR_OFF 1
|
||||
#define PLL1_TMDS_TERM_SHIFT 8
|
||||
#define PLL1_TMDS_TERM_DISABLE (0 << 8)
|
||||
#define PLL1_TMDS_TERM_ENABLE (1 << 8)
|
||||
#define PLL1 0x18
|
||||
#define PLL1_TERM_COMPOUT_SHIFT 15
|
||||
#define PLL1_TERM_COMPOUT_LOW (0 << 15)
|
||||
#define PLL1_TERM_COMPOUT_HIGH (1 << 15)
|
||||
#define PLL2 0x19
|
||||
#define PLL2_DCIR_PLL_RESET_SHIFT 0
|
||||
#define PLL2_DCIR_PLL_RESET_OVERRIDE (0 << 0)
|
||||
#define PLL2_DCIR_PLL_RESET_ALLOW (1 << 0)
|
||||
#define PLL2_AUX1_SHIFT 17
|
||||
#define PLL2_AUX1_SEQ_MASK (1 << 17)
|
||||
#define PLL2_AUX1_SEQ_PLLCAPPD_ALLOW (0 << 17)
|
||||
#define PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE (1 << 17)
|
||||
#define PLL2_AUX2_SHIFT 18
|
||||
#define PLL2_AUX2_MASK (1 << 18)
|
||||
#define PLL2_AUX2_OVERRIDE_POWERDOWN (0 << 18)
|
||||
#define PLL2_AUX2_ALLOW_POWERDOWN (1 << 18)
|
||||
#define PLL2_AUX6_SHIFT 22
|
||||
#define PLL2_AUX6_BANDGAP_POWERDOWN_MASK (1 << 22)
|
||||
#define PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE (0 << 22)
|
||||
#define PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE (1 << 22)
|
||||
#define PLL2_AUX7_SHIFT 23
|
||||
#define PLL2_AUX7_PORT_POWERDOWN_MASK (1 << 23)
|
||||
#define PLL2_AUX7_PORT_POWERDOWN_DISABLE (0 << 23)
|
||||
#define PLL2_AUX7_PORT_POWERDOWN_ENABLE (1 << 23)
|
||||
#define PLL2_AUX8_SHIFT 24
|
||||
#define PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK (1 << 24)
|
||||
#define PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE (0 << 24)
|
||||
#define PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE (1 << 24)
|
||||
#define PLL2_AUX9_SHIFT 25
|
||||
#define PLL2_AUX9_LVDSEN_ALLOW (0 << 25)
|
||||
#define PLL2_AUX9_LVDSEN_OVERRIDE (1 << 25)
|
||||
#define PLL3 0x1a
|
||||
#define PLL3_PLLVDD_MODE_SHIFT 13
|
||||
#define PLL3_PLLVDD_MODE_MASK (1 << 13)
|
||||
#define PLL3_PLLVDD_MODE_V1_8 (0 << 13)
|
||||
#define PLL3_PLLVDD_MODE_V3_3 (1 << 13)
|
||||
#define CSTM 0x1b
|
||||
#define CSTM_ROTDAT_SHIFT 28
|
||||
#define CSTM_ROTDAT_DEFAULT_MASK (7 << 28)
|
||||
#define CSTM_ROTCLK_SHIFT 24
|
||||
#define CSTM_ROTCLK_DEFAULT_MASK (0xf << 24)
|
||||
#define CSTM_LVDS_EN_SHIFT 16
|
||||
#define CSTM_LVDS_EN_DISABLE (0 << 16)
|
||||
#define CSTM_LVDS_EN_ENABLE (1 << 16)
|
||||
#define CSTM_LINKACTB_SHIFT 15
|
||||
#define CSTM_LINKACTB_DISABLE (0 << 15)
|
||||
#define CSTM_LINKACTB_ENABLE (1 << 15)
|
||||
#define CSTM_LINKACTA_SHIFT 14
|
||||
#define CSTM_LINKACTA_DISABLE (0 << 14)
|
||||
#define CSTM_LINKACTA_ENABLE (1 << 14)
|
||||
#define LVDS 0x1c
|
||||
#define LVDS_ROTDAT_SHIFT 28
|
||||
#define LVDS_ROTDAT_DEFAULT_MASK (7 << 28)
|
||||
#define LVDS_ROTDAT_RST (0 << 28)
|
||||
#define LVDS_ROTCLK_SHIFT 24
|
||||
#define LVDS_ROTCLK_DEFAULT_MASK (0xf << 24)
|
||||
#define LVDS_ROTCLK_RST (0 << 24)
|
||||
#define LVDS_PLLDIV_SHIFT 21
|
||||
#define LVDS_PLLDIV_DEFAULT_MASK (1 << 21)
|
||||
#define LVDS_PLLDIV_BY_7 (0 << 21)
|
||||
#define LVDS_BALANCED_SHIFT 19
|
||||
#define LVDS_BALANCED_DEFAULT_MASK (1 << 19)
|
||||
#define LVDS_BALANCED_DISABLE (0 << 19)
|
||||
#define LVDS_BALANCED_ENABLE (1 << 19)
|
||||
#define LVDS_NEW_MODE_SHIFT 18
|
||||
#define LVDS_NEW_MODE_DEFAULT_MASK (1 << 18)
|
||||
#define LVDS_NEW_MODE_DISABLE (0 << 18)
|
||||
#define LVDS_NEW_MODE_ENABLE (1 << 18)
|
||||
#define LVDS_DUP_SYNC_SHIFT 17
|
||||
#define LVDS_DUP_SYNC_DEFAULT_MASK (1 << 17)
|
||||
#define LVDS_DUP_SYNC_DISABLE (0 << 17)
|
||||
#define LVDS_DUP_SYNC_ENABLE (1 << 17)
|
||||
#define LVDS_LVDS_EN_SHIFT 16
|
||||
#define LVDS_LVDS_EN_DEFAULT_MASK (1 << 16)
|
||||
#define LVDS_LVDS_EN_ENABLE (1 << 16)
|
||||
#define LVDS_LINKACTB_SHIFT 15
|
||||
#define LVDS_LINKACTB_DEFAULT_MASK (1 << 15)
|
||||
#define LVDS_LINKACTB_DISABLE (0 << 15)
|
||||
#define LVDS_LINKACTB_ENABLE (1 << 15)
|
||||
#define LVDS_LINKACTA_SHIFT 14
|
||||
#define LVDS_LINKACTA_DEFAULT_MASK (1 << 14)
|
||||
#define LVDS_LINKACTA_ENABLE (1 << 14)
|
||||
#define LVDS_MODE_SHIFT 12
|
||||
#define LVDS_MODE_DEFAULT_MASK (3 << 12)
|
||||
#define LVDS_MODE_LVDS (0 << 12)
|
||||
#define LVDS_UPPER_SHIFT 11
|
||||
#define LVDS_UPPER_DEFAULT_MASK (1 << 11)
|
||||
#define LVDS_UPPER_FALSE (0 << 11)
|
||||
#define LVDS_UPPER_TRUE (1 << 11)
|
||||
#define LVDS_PD_TXCB_SHIFT 9
|
||||
#define LVDS_PD_TXCB_DEFAULT_MASK (1 << 9)
|
||||
#define LVDS_PD_TXCB_ENABLE (0 << 9)
|
||||
#define LVDS_PD_TXCB_DISABLE (1 << 9)
|
||||
#define LVDS_PD_TXCA_SHIFT 8
|
||||
#define LVDS_PD_TXCA_DEFAULT_MASK (1 << 8)
|
||||
#define LVDS_PD_TXCA_ENABLE (0 << 8)
|
||||
#define LVDS_PD_TXDB_3_SHIFT 7
|
||||
#define LVDS_PD_TXDB_3_DEFAULT_MASK (1 << 7)
|
||||
#define LVDS_PD_TXDB_3_ENABLE (0 << 7)
|
||||
#define LVDS_PD_TXDB_3_DISABLE (1 << 7)
|
||||
#define LVDS_PD_TXDB_2_SHIFT 6
|
||||
#define LVDS_PD_TXDB_2_DEFAULT_MASK (1 << 6)
|
||||
#define LVDS_PD_TXDB_2_ENABLE (0 << 6)
|
||||
#define LVDS_PD_TXDB_2_DISABLE (1 << 6)
|
||||
#define LVDS_PD_TXDB_1_SHIFT 5
|
||||
#define LVDS_PD_TXDB_1_DEFAULT_MASK (1 << 5)
|
||||
#define LVDS_PD_TXDB_1_ENABLE (0 << 5)
|
||||
#define LVDS_PD_TXDB_1_DISABLE (1 << 5)
|
||||
#define LVDS_PD_TXDB_0_SHIFT 4
|
||||
#define LVDS_PD_TXDB_0_DEFAULT_MASK (1 << 4)
|
||||
#define LVDS_PD_TXDB_0_ENABLE (0 << 4)
|
||||
#define LVDS_PD_TXDB_0_DISABLE (1 << 4)
|
||||
#define LVDS_PD_TXDA_3_SHIFT 3
|
||||
#define LVDS_PD_TXDA_3_DEFAULT_MASK (1 << 3)
|
||||
#define LVDS_PD_TXDA_3_ENABLE (0 << 3)
|
||||
#define LVDS_PD_TXDA_3_DISABLE (1 << 3)
|
||||
#define LVDS_PD_TXDA_2_SHIFT 2
|
||||
#define LVDS_PD_TXDA_2_DEFAULT_MASK (1 << 2)
|
||||
#define LVDS_PD_TXDA_2_ENABLE (0 << 2)
|
||||
#define LVDS_PD_TXDA_1_SHIFT 1
|
||||
#define LVDS_PD_TXDA_1_DEFAULT_MASK (1 << 1)
|
||||
#define LVDS_PD_TXDA_1_ENABLE (0 << 1)
|
||||
#define LVDS_PD_TXDA_0_SHIFT 0
|
||||
#define LVDS_PD_TXDA_0_DEFAULT_MASK 0x1
|
||||
#define LVDS_PD_TXDA_0_ENABLE 0
|
||||
#define CRCA 0x1d
|
||||
#define CRCA_VALID_FALSE 0
|
||||
#define CRCA_VALID_TRUE 1
|
||||
#define CRCA_VALID_RST 1
|
||||
#define CRCB 0x1e
|
||||
#define CRCB_CRC_DEFAULT_MASK 0xffffffff
|
||||
#define SEQ_CTL 0x20
|
||||
#define SEQ_CTL_SWITCH_SHIFT 30
|
||||
#define SEQ_CTL_SWITCH_MASK (1 << 30)
|
||||
#define SEQ_CTL_SWITCH_WAIT (0 << 30)
|
||||
#define SEQ_CTL_SWITCH_FORCE (1 << 30)
|
||||
#define SEQ_CTL_STATUS_SHIFT 28
|
||||
#define SEQ_CTL_STATUS_MASK (1 << 28)
|
||||
#define SEQ_CTL_STATUS_STOPPED (0 << 28)
|
||||
#define SEQ_CTL_STATUS_RUNNING (1 << 28)
|
||||
#define SEQ_CTL_PC_SHIFT 16
|
||||
#define SEQ_CTL_PC_MASK (0xf << 16)
|
||||
#define SEQ_CTL_PD_PC_ALT_SHIFT 12
|
||||
#define SEQ_CTL_PD_PC_ALT_MASK (0xf << 12)
|
||||
#define SEQ_CTL_PD_PC_SHIFT 8
|
||||
#define SEQ_CTL_PD_PC_MASK (0xf << 8)
|
||||
#define SEQ_CTL_PU_PC_ALT_SHIFT 4
|
||||
#define SEQ_CTL_PU_PC_ALT_MASK (0xf << 4)
|
||||
#define SEQ_CTL_PU_PC_SHIFT 0
|
||||
#define SEQ_CTL_PU_PC_MASK 0xf
|
||||
#define LANE_SEQ_CTL 0x21
|
||||
#define LANE_SEQ_CTL_SETTING_NEW_SHIFT 31
|
||||
#define LANE_SEQ_CTL_SETTING_MASK (1 << 31)
|
||||
#define LANE_SEQ_CTL_SETTING_NEW_DONE (0 << 31)
|
||||
#define LANE_SEQ_CTL_SETTING_NEW_PENDING (1 << 31)
|
||||
#define LANE_SEQ_CTL_SETTING_NEW_TRIGGER (1 << 31)
|
||||
#define LANE_SEQ_CTL_SEQ_STATE_SHIFT 28
|
||||
#define LANE_SEQ_CTL_SEQ_STATE_IDLE (0 << 28)
|
||||
#define LANE_SEQ_CTL_SEQ_STATE_BUSY (1 << 28)
|
||||
#define LANE_SEQ_CTL_SEQUENCE_SHIFT 20
|
||||
#define LANE_SEQ_CTL_SEQUENCE_UP (0 << 20)
|
||||
#define LANE_SEQ_CTL_SEQUENCE_DOWN (1 << 20)
|
||||
#define LANE_SEQ_CTL_NEW_POWER_STATE_SHIFT 16
|
||||
#define LANE_SEQ_CTL_NEW_POWER_STATE_PU (0 << 16)
|
||||
#define LANE_SEQ_CTL_NEW_POWER_STATE_PD (1 << 16)
|
||||
#define LANE_SEQ_CTL_DELAY_SHIFT 12
|
||||
#define LANE_SEQ_CTL_DELAY_DEFAULT_MASK (0xf << 12)
|
||||
#define LANE_SEQ_CTL_LANE9_STATE_SHIFT 9
|
||||
#define LANE_SEQ_CTL_LANE9_STATE_POWERUP (0 << 9)
|
||||
#define LANE_SEQ_CTL_LANE9_STATE_POWERDOWN (1 << 9)
|
||||
#define LANE_SEQ_CTL_LANE8_STATE_SHIFT 8
|
||||
#define LANE_SEQ_CTL_LANE8_STATE_POWERUP (0 << 8)
|
||||
#define LANE_SEQ_CTL_LANE8_STATE_POWERDOWN (1 << 8)
|
||||
#define LANE_SEQ_CTL_LANE7_STATE_SHIFT 7
|
||||
#define LANE_SEQ_CTL_LANE7_STATE_POWERUP (0 << 7)
|
||||
#define LANE_SEQ_CTL_LANE7_STATE_POWERDOWN (1 << 7)
|
||||
#define LANE_SEQ_CTL_LANE6_STATE_SHIFT 6
|
||||
#define LANE_SEQ_CTL_LANE6_STATE_POWERUP (0 << 6)
|
||||
#define LANE_SEQ_CTL_LANE6_STATE_POWERDOWN (1 << 6)
|
||||
#define LANE_SEQ_CTL_LANE5_STATE_SHIFT 5
|
||||
#define LANE_SEQ_CTL_LANE5_STATE_POWERUP (0 << 5)
|
||||
#define LANE_SEQ_CTL_LANE5_STATE_POWERDOWN (1 << 5)
|
||||
#define LANE_SEQ_CTL_LANE4_STATE_SHIFT 4
|
||||
#define LANE_SEQ_CTL_LANE4_STATE_POWERUP (0 << 4)
|
||||
#define LANE_SEQ_CTL_LANE4_STATE_POWERDOWN (1 << 4)
|
||||
#define LANE_SEQ_CTL_LANE3_STATE_SHIFT 3
|
||||
#define LANE_SEQ_CTL_LANE3_STATE_POWERUP (0 << 3)
|
||||
#define LANE_SEQ_CTL_LANE3_STATE_POWERDOWN (1 << 3)
|
||||
#define LANE_SEQ_CTL_LANE2_STATE_SHIFT 2
|
||||
#define LANE_SEQ_CTL_LANE2_STATE_POWERUP (0 << 2)
|
||||
#define LANE_SEQ_CTL_LANE2_STATE_POWERDOWN (1 << 2)
|
||||
#define LANE_SEQ_CTL_LANE1_STATE_SHIFT 1
|
||||
#define LANE_SEQ_CTL_LANE1_STATE_POWERUP (0 << 1)
|
||||
#define LANE_SEQ_CTL_LANE1_STATE_POWERDOWN (1 << 1)
|
||||
#define LANE_SEQ_CTL_LANE0_STATE_SHIFT 0
|
||||
#define LANE_SEQ_CTL_LANE0_STATE_POWERUP 0
|
||||
#define LANE_SEQ_CTL_LANE0_STATE_POWERDOWN 1
|
||||
#define SEQ_INST(i) (0x22 + i)
|
||||
#define SEQ_INST_PLL_PULLDOWN_SHIFT 31
|
||||
#define SEQ_INST_PLL_PULLDOWN_DISABLE (0 << 31)
|
||||
#define SEQ_INST_PLL_PULLDOWN_ENABLE (1 << 31)
|
||||
#define SEQ_INST_POWERDOWN_MACRO_SHIFT 30
|
||||
#define SEQ_INST_POWERDOWN_MACRO_NORMAL (0 << 30)
|
||||
#define SEQ_INST_POWERDOWN_MACRO_POWERDOWN (1 << 30)
|
||||
#define SEQ_INST_ASSERT_PLL_RESET_SHIFT 29
|
||||
#define SEQ_INST_ASSERT_PLL_RESET_NORMAL (0 << 29)
|
||||
#define SEQ_INST_ASSERT_PLL_RESET_RST (1 << 29)
|
||||
#define SEQ_INST_BLANK_V_SHIFT 28
|
||||
#define SEQ_INST_BLANK_V_NORMAL (0 << 28)
|
||||
#define SEQ_INST_BLANK_V_INACTIVE (1 << 28)
|
||||
#define SEQ_INST_BLANK_H_SHIFT 27
|
||||
#define SEQ_INST_BLANK_H_NORMAL (0 << 27)
|
||||
#define SEQ_INST_BLANK_H_INACTIVE (1 << 27)
|
||||
#define SEQ_INST_BLANK_DE_SHIFT 26
|
||||
#define SEQ_INST_BLANK_DE_NORMAL (0 << 26)
|
||||
#define SEQ_INST_BLANK_DE_INACTIVE (1 << 26)
|
||||
#define SEQ_INST_BLACK_DATA_SHIFT 25
|
||||
#define SEQ_INST_BLACK_DATA_NORMAL (0 << 25)
|
||||
#define SEQ_INST_BLACK_DATA_BLACK (1 << 25)
|
||||
#define SEQ_INST_TRISTATE_IOS_SHIFT 24
|
||||
#define SEQ_INST_TRISTATE_IOS_ENABLE_PINS (0 << 24)
|
||||
#define SEQ_INST_TRISTATE_IOS_TRISTATE (1 << 24)
|
||||
#define SEQ_INST_DRIVE_PWM_OUT_LO_SHIFT 23
|
||||
#define SEQ_INST_DRIVE_PWM_OUT_LO_FALSE (0 << 23)
|
||||
#define SEQ_INST_DRIVE_PWM_OUT_LO_TRUE (1 << 23)
|
||||
#define SEQ_INST_PIN_B_SHIFT 22
|
||||
#define SEQ_INST_PIN_B_LOW (0 << 22)
|
||||
#define SEQ_INST_PIN_B_HIGH (1 << 22)
|
||||
#define SEQ_INST_PIN_A_SHIFT 21
|
||||
#define SEQ_INST_PIN_A_LOW (0 << 21)
|
||||
#define SEQ_INST_PIN_A_HIGH (1 << 21)
|
||||
#define SEQ_INST_SEQUENCE_SHIFT 19
|
||||
#define SEQ_INST_SEQUENCE_UP (0 << 19)
|
||||
#define SEQ_INST_SEQUENCE_DOWN (1 << 19)
|
||||
#define SEQ_INST_LANE_SEQ_SHIFT 18
|
||||
#define SEQ_INST_LANE_SEQ_STOP (0 << 18)
|
||||
#define SEQ_INST_LANE_SEQ_RUN (1 << 18)
|
||||
#define SEQ_INST_PDPORT_SHIFT 17
|
||||
#define SEQ_INST_PDPORT_NO (0 << 17)
|
||||
#define SEQ_INST_PDPORT_YES (1 << 17)
|
||||
#define SEQ_INST_PDPLL_SHIFT 16
|
||||
#define SEQ_INST_PDPLL_NO (0 << 16)
|
||||
#define SEQ_INST_PDPLL_YES (1 << 16)
|
||||
#define SEQ_INST_HALT_SHIFT 15
|
||||
#define SEQ_INST_HALT_FALSE (0 << 15)
|
||||
#define SEQ_INST_HALT_TRUE (1 << 15)
|
||||
#define SEQ_INST_WAIT_UNITS_SHIFT 12
|
||||
#define SEQ_INST_WAIT_UNITS_DEFAULT_MASK (3 << 12)
|
||||
#define SEQ_INST_WAIT_UNITS_US (0 << 12)
|
||||
#define SEQ_INST_WAIT_UNITS_MS (1 << 12)
|
||||
#define SEQ_INST_WAIT_UNITS_VSYNC (2 << 12)
|
||||
#define SEQ_INST_WAIT_TIME_SHIFT 0
|
||||
#define SEQ_INST_WAIT_TIME_DEFAULT_MASK 0x3ff
|
||||
#define PWM_DIV 0x32
|
||||
#define PWM_DIV_DIVIDE_DEFAULT_MASK 0xffffff
|
||||
#define PWM_CTL 0x33
|
||||
#define PWM_CTL_SETTING_NEW_SHIFT 31
|
||||
#define PWM_CTL_SETTING_NEW_DONE (0 << 31)
|
||||
#define PWM_CTL_SETTING_NEW_PENDING (1 << 31)
|
||||
#define PWM_CTL_SETTING_NEW_TRIGGER (1 << 31)
|
||||
#define PWM_CTL_CLKSEL_SHIFT 30
|
||||
#define PWM_CTL_CLKSEL_PCLK (0 << 30)
|
||||
#define PWM_CTL_CLKSEL_XTAL (1 << 30)
|
||||
#define PWM_CTL_DUTY_CYCLE_SHIFT 0
|
||||
#define PWM_CTL_DUTY_CYCLE_MASK 0xffffff
|
||||
#define MSCHECK 0x49
|
||||
#define MSCHECK_CTL_SHIFT 31
|
||||
#define MSCHECK_CTL_CLEAR (0 << 31)
|
||||
#define MSCHECK_CTL_RUN (1 << 31)
|
||||
#define XBAR_CTRL 0x4a
|
||||
#define DP_LINKCTL(i) (0x4c + (i))
|
||||
#define DP_LINKCTL_FORCE_IDLEPTTRN_SHIFT 31
|
||||
#define DP_LINKCTL_FORCE_IDLEPTTRN_NO (0 << 31)
|
||||
#define DP_LINKCTL_FORCE_IDLEPTTRN_YES (1 << 31)
|
||||
#define DP_LINKCTL_COMPLIANCEPTTRN_SHIFT 28
|
||||
#define DP_LINKCTL_COMPLIANCEPTTRN_NOPATTERN (0 << 28)
|
||||
#define DP_LINKCTL_COMPLIANCEPTTRN_COLORSQARE (1 << 28)
|
||||
#define DP_LINKCTL_LANECOUNT_SHIFT 16
|
||||
#define DP_LINKCTL_LANECOUNT_MASK (0x1f << 16)
|
||||
#define DP_LINKCTL_LANECOUNT_ZERO (0 << 16)
|
||||
#define DP_LINKCTL_LANECOUNT_ONE (1 << 16)
|
||||
#define DP_LINKCTL_LANECOUNT_TWO (3 << 16)
|
||||
#define DP_LINKCTL_LANECOUNT_FOUR (15 << 16)
|
||||
#define DP_LINKCTL_ENHANCEDFRAME_SHIFT 14
|
||||
#define DP_LINKCTL_ENHANCEDFRAME_DISABLE (0 << 14)
|
||||
#define DP_LINKCTL_ENHANCEDFRAME_ENABLE (1 << 14)
|
||||
#define DP_LINKCTL_SYNCMODE_SHIFT 10
|
||||
#define DP_LINKCTL_SYNCMODE_DISABLE (0 << 10)
|
||||
#define DP_LINKCTL_SYNCMODE_ENABLE (1 << 10)
|
||||
#define DP_LINKCTL_TUSIZE_SHIFT 2
|
||||
#define DP_LINKCTL_TUSIZE_MASK (0x7f << 2)
|
||||
#define DP_LINKCTL_ENABLE_SHIFT 0
|
||||
#define DP_LINKCTL_ENABLE_NO 0
|
||||
#define DP_LINKCTL_ENABLE_YES 1
|
||||
#define DC(i) (0x4e + (i))
|
||||
#define DC_LANE3_DP_LANE3_SHIFT 24
|
||||
#define DC_LANE3_DP_LANE3_MASK (0xff << 24)
|
||||
#define DC_LANE3_DP_LANE3_P0_LEVEL0 (17 << 24)
|
||||
#define DC_LANE3_DP_LANE3_P1_LEVEL0 (21 << 24)
|
||||
#define DC_LANE3_DP_LANE3_P2_LEVEL0 (26 << 24)
|
||||
#define DC_LANE3_DP_LANE3_P3_LEVEL0 (34 << 24)
|
||||
#define DC_LANE3_DP_LANE3_P0_LEVEL1 (26 << 24)
|
||||
#define DC_LANE3_DP_LANE3_P1_LEVEL1 (32 << 24)
|
||||
#define DC_LANE3_DP_LANE3_P2_LEVEL1 (39 << 24)
|
||||
#define DC_LANE3_DP_LANE3_P0_LEVEL2 (34 << 24)
|
||||
#define DC_LANE3_DP_LANE3_P1_LEVEL2 (43 << 24)
|
||||
#define DC_LANE3_DP_LANE3_P0_LEVEL3 (51 << 24)
|
||||
#define DC_LANE2_DP_LANE0_SHIFT 16
|
||||
#define DC_LANE2_DP_LANE0_MASK (0xff << 16)
|
||||
#define DC_LANE2_DP_LANE0_P0_LEVEL0 (17 << 16)
|
||||
#define DC_LANE2_DP_LANE0_P1_LEVEL0 (21 << 16)
|
||||
#define DC_LANE2_DP_LANE0_P2_LEVEL0 (26 << 16)
|
||||
#define DC_LANE2_DP_LANE0_P3_LEVEL0 (34 << 16)
|
||||
#define DC_LANE2_DP_LANE0_P0_LEVEL1 (26 << 16)
|
||||
#define DC_LANE2_DP_LANE0_P1_LEVEL1 (32 << 16)
|
||||
#define DC_LANE2_DP_LANE0_P2_LEVEL1 (39 << 16)
|
||||
#define DC_LANE2_DP_LANE0_P0_LEVEL2 (34 << 16)
|
||||
#define DC_LANE2_DP_LANE0_P1_LEVEL2 (43 << 16)
|
||||
#define DC_LANE2_DP_LANE0_P0_LEVEL3 (51 << 16)
|
||||
#define DC_LANE1_DP_LANE1_SHIFT 8
|
||||
#define DC_LANE1_DP_LANE1_MASK (0xff << 8)
|
||||
#define DC_LANE1_DP_LANE1_P0_LEVEL0 (17 << 8)
|
||||
#define DC_LANE1_DP_LANE1_P1_LEVEL0 (21 << 8)
|
||||
#define DC_LANE1_DP_LANE1_P2_LEVEL0 (26 << 8)
|
||||
#define DC_LANE1_DP_LANE1_P3_LEVEL0 (34 << 8)
|
||||
#define DC_LANE1_DP_LANE1_P0_LEVEL1 (26 << 8)
|
||||
#define DC_LANE1_DP_LANE1_P1_LEVEL1 (32 << 8)
|
||||
#define DC_LANE1_DP_LANE1_P2_LEVEL1 (39 << 8)
|
||||
#define DC_LANE1_DP_LANE1_P0_LEVEL2 (34 << 8)
|
||||
#define DC_LANE1_DP_LANE1_P1_LEVEL2 (43 << 8)
|
||||
#define DC_LANE1_DP_LANE1_P0_LEVEL3 (51 << 8)
|
||||
#define DC_LANE0_DP_LANE2_SHIFT 0
|
||||
#define DC_LANE0_DP_LANE2_MASK 0xff
|
||||
#define DC_LANE0_DP_LANE2_P0_LEVEL0 17
|
||||
#define DC_LANE0_DP_LANE2_P1_LEVEL0 21
|
||||
#define DC_LANE0_DP_LANE2_P2_LEVEL0 26
|
||||
#define DC_LANE0_DP_LANE2_P3_LEVEL0 34
|
||||
#define DC_LANE0_DP_LANE2_P0_LEVEL1 26
|
||||
#define DC_LANE0_DP_LANE2_P1_LEVEL1 32
|
||||
#define DC_LANE0_DP_LANE2_P2_LEVEL1 39
|
||||
#define DC_LANE0_DP_LANE2_P0_LEVEL2 34
|
||||
#define DC_LANE0_DP_LANE2_P1_LEVEL2 43
|
||||
#define DC_LANE0_DP_LANE2_P0_LEVEL3 51
|
||||
#define LANE_DRIVE_CURRENT(i) (0x4e + (i))
|
||||
#define PR(i) (0x52 + (i))
|
||||
#define PR_LANE3_DP_LANE3_SHIFT 24
|
||||
#define PR_LANE3_DP_LANE3_MASK (0xff << 24)
|
||||
#define PR_LANE3_DP_LANE3_D0_LEVEL0 (0 << 24)
|
||||
#define PR_LANE3_DP_LANE3_D1_LEVEL0 (0 << 24)
|
||||
#define PR_LANE3_DP_LANE3_D2_LEVEL0 (0 << 24)
|
||||
#define PR_LANE3_DP_LANE3_D3_LEVEL0 (0 << 24)
|
||||
#define PR_LANE3_DP_LANE3_D0_LEVEL1 (4 << 24)
|
||||
#define PR_LANE3_DP_LANE3_D1_LEVEL1 (6 << 24)
|
||||
#define PR_LANE3_DP_LANE3_D2_LEVEL1 (17 << 24)
|
||||
#define PR_LANE3_DP_LANE3_D0_LEVEL2 (8 << 24)
|
||||
#define PR_LANE3_DP_LANE3_D1_LEVEL2 (13 << 24)
|
||||
#define PR_LANE3_DP_LANE3_D0_LEVEL3 (17 << 24)
|
||||
#define PR_LANE2_DP_LANE0_SHIFT 16
|
||||
#define PR_LANE2_DP_LANE0_MASK (0xff << 16)
|
||||
#define PR_LANE2_DP_LANE0_D0_LEVEL0 (0 << 16)
|
||||
#define PR_LANE2_DP_LANE0_D1_LEVEL0 (0 << 16)
|
||||
#define PR_LANE2_DP_LANE0_D2_LEVEL0 (0 << 16)
|
||||
#define PR_LANE2_DP_LANE0_D3_LEVEL0 (0 << 16)
|
||||
#define PR_LANE2_DP_LANE0_D0_LEVEL1 (4 << 16)
|
||||
#define PR_LANE2_DP_LANE0_D1_LEVEL1 (6 << 16)
|
||||
#define PR_LANE2_DP_LANE0_D2_LEVEL1 (17 << 16)
|
||||
#define PR_LANE2_DP_LANE0_D0_LEVEL2 (8 << 16)
|
||||
#define PR_LANE2_DP_LANE0_D1_LEVEL2 (13 << 16)
|
||||
#define PR_LANE2_DP_LANE0_D0_LEVEL3 (17 << 16)
|
||||
#define PR_LANE1_DP_LANE1_SHIFT 8
|
||||
#define PR_LANE1_DP_LANE1_MASK (0xff >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D0_LEVEL0 (0 >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D1_LEVEL0 (0 >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D2_LEVEL0 (0 >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D3_LEVEL0 (0 >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D0_LEVEL1 (4 >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D1_LEVEL1 (6 >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D2_LEVEL1 (17 >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D0_LEVEL2 (8 >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D1_LEVEL2 (13 >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D0_LEVEL3 (17 >> 8)
|
||||
#define PR_LANE0_DP_LANE2_SHIFT 0
|
||||
#define PR_LANE0_DP_LANE2_MASK 0xff
|
||||
#define PR_LANE0_DP_LANE2_D0_LEVEL0 0
|
||||
#define PR_LANE0_DP_LANE2_D1_LEVEL0 0
|
||||
#define PR_LANE0_DP_LANE2_D2_LEVEL0 0
|
||||
#define PR_LANE0_DP_LANE2_D3_LEVEL0 0
|
||||
#define PR_LANE0_DP_LANE2_D0_LEVEL1 4
|
||||
#define PR_LANE0_DP_LANE2_D1_LEVEL1 6
|
||||
#define PR_LANE0_DP_LANE2_D2_LEVEL1 17
|
||||
#define PR_LANE0_DP_LANE2_D0_LEVEL2 8
|
||||
#define PR_LANE0_DP_LANE2_D1_LEVEL2 13
|
||||
#define PR_LANE0_DP_LANE2_D0_LEVEL3 17
|
||||
#define LANE4_PREEMPHASIS(i) (0x54 + (i))
|
||||
#define POSTCURSOR(i) (0x56 + (i))
|
||||
#define DP_CONFIG(i) (0x58 + (i))
|
||||
#define DP_CONFIG_RD_RESET_VAL_SHIFT 31
|
||||
#define DP_CONFIG_RD_RESET_VAL_POSITIVE (0 << 31)
|
||||
#define DP_CONFIG_RD_RESET_VAL_NEGATIVE (1 << 31)
|
||||
#define DP_CONFIG_IDLE_BEFORE_ATTACH_SHIFT 28
|
||||
#define DP_CONFIG_IDLE_BEFORE_ATTACH_DISABLE (0 << 28)
|
||||
#define DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE (1 << 28)
|
||||
#define DP_CONFIG_ACTIVESYM_CNTL_SHIFT 26
|
||||
#define DP_CONFIG_ACTIVESYM_CNTL_DISABLE (0 << 26)
|
||||
#define DP_CONFIG_ACTIVESYM_CNTL_ENABLE (1 << 26)
|
||||
#define DP_CONFIG_ACTIVESYM_POLARITY_SHIFT 24
|
||||
#define DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE (0 << 24)
|
||||
#define DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE (1 << 24)
|
||||
#define DP_CONFIG_ACTIVESYM_FRAC_SHIFT 16
|
||||
#define DP_CONFIG_ACTIVESYM_FRAC_MASK (0xf << 16)
|
||||
#define DP_CONFIG_ACTIVESYM_COUNT_SHIFT 8
|
||||
#define DP_CONFIG_ACTIVESYM_COUNT_MASK (0x7f << 8)
|
||||
#define DP_CONFIG_WATERMARK_SHIFT 0
|
||||
#define DP_CONFIG_WATERMARK_MASK 0x3f
|
||||
#define DP_MN(i) (0x5a + i)
|
||||
#define DP_MN_M_MOD_SHIFT 30
|
||||
#define DP_MN_M_MOD_DEFAULT_MASK (3 << 30)
|
||||
#define DP_MN_M_MOD_NONE (0 << 30)
|
||||
#define DP_MN_M_MOD_INC (1 << 30)
|
||||
#define DP_MN_M_MOD_DEC (2 << 30)
|
||||
#define DP_MN_M_DELTA_SHIFT 24
|
||||
#define DP_MN_M_DELTA_DEFAULT_MASK (0xf << 24)
|
||||
#define DP_MN_N_VAL_SHIFT 0
|
||||
#define DP_MN_N_VAL_DEFAULT_MASK 0xffffff
|
||||
#define DP_PADCTL(i) (0x5c + (i))
|
||||
#define DP_PADCTL_SPARE_SHIFT 25
|
||||
#define DP_PADCTL_SPARE_DEFAULT_MASK (0x7f << 25)
|
||||
#define DP_PADCTL_VCO_2X_SHIFT 24
|
||||
#define DP_PADCTL_VCO_2X_DISABLE (0 << 24)
|
||||
#define DP_PADCTL_VCO_2X_ENABLE (1 << 24)
|
||||
#define DP_PADCTL_PAD_CAL_PD_SHIFT 23
|
||||
#define DP_PADCTL_PAD_CAL_PD_POWERUP (0 << 23)
|
||||
#define DP_PADCTL_PAD_CAL_PD_POWERDOWN (1 << 23)
|
||||
#define DP_PADCTL_TX_PU_SHIFT 22
|
||||
#define DP_PADCTL_TX_PU_DISABLE (0 << 22)
|
||||
#define DP_PADCTL_TX_PU_ENABLE (1 << 22)
|
||||
#define DP_PADCTL_TX_PU_MASK (1 << 22)
|
||||
#define DP_PADCTL_REG_CTRL_SHIFT 20
|
||||
#define DP_PADCTL_REG_CTRL_DEFAULT_MASK (3 << 20)
|
||||
#define DP_PADCTL_VCMMODE_SHIFT 16
|
||||
#define DP_PADCTL_VCMMODE_DEFAULT_MASK (0xf << 16)
|
||||
#define DP_PADCTL_VCMMODE_TRISTATE (0 << 16)
|
||||
#define DP_PADCTL_VCMMODE_TEST_MUX (1 << 16)
|
||||
#define DP_PADCTL_VCMMODE_WEAK_PULLDOWN (2 << 16)
|
||||
#define DP_PADCTL_VCMMODE_STRONG_PULLDOWN (4 << 16)
|
||||
#define DP_PADCTL_TX_PU_VALUE_SHIFT 8
|
||||
#define DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK (0xff << 8)
|
||||
#define DP_PADCTL_COMODE_TXD_3_DP_TXD_3_SHIFT 7
|
||||
#define DP_PADCTL_COMODE_TXD_3_DP_TXD_3_DISABLE (0 << 7)
|
||||
#define DP_PADCTL_COMODE_TXD_3_DP_TXD_3_ENABLE (1 << 7)
|
||||
#define DP_PADCTL_COMODE_TXD_2_DP_TXD_0_SHIFT 6
|
||||
#define DP_PADCTL_COMODE_TXD_2_DP_TXD_0_DISABLE (0 << 6)
|
||||
#define DP_PADCTL_COMODE_TXD_2_DP_TXD_0_ENABLE (1 << 6)
|
||||
#define DP_PADCTL_COMODE_TXD_1_DP_TXD_1_SHIFT 5
|
||||
#define DP_PADCTL_COMODE_TXD_1_DP_TXD_1_DISABLE (0 << 5)
|
||||
#define DP_PADCTL_COMODE_TXD_1_DP_TXD_1_ENABLE (1 << 5)
|
||||
#define DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT 4
|
||||
#define DP_PADCTL_COMODE_TXD_0_DP_TXD_2_DISABLE (0 << 4)
|
||||
#define DP_PADCTL_COMODE_TXD_0_DP_TXD_2_ENABLE (1 << 4)
|
||||
#define DP_PADCTL_PD_TXD_3_SHIFT 3
|
||||
#define DP_PADCTL_PD_TXD_3_YES (0 << 3)
|
||||
#define DP_PADCTL_PD_TXD_3_NO (1 << 3)
|
||||
#define DP_PADCTL_PD_TXD_0_SHIFT 2
|
||||
#define DP_PADCTL_PD_TXD_0_YES (0 << 2)
|
||||
#define DP_PADCTL_PD_TXD_0_NO (1 << 2)
|
||||
#define DP_PADCTL_PD_TXD_1_SHIFT 1
|
||||
#define DP_PADCTL_PD_TXD_1_YES (0 << 1)
|
||||
#define DP_PADCTL_PD_TXD_1_NO (1 << 1)
|
||||
#define DP_PADCTL_PD_TXD_2_SHIFT 0
|
||||
#define DP_PADCTL_PD_TXD_2_YES 0
|
||||
#define DP_PADCTL_PD_TXD_2_NO 1
|
||||
#define DP_DEBUG(i) (0x5e + i)
|
||||
#define DP_SPARE(i) (0x60 + (i))
|
||||
#define DP_SPARE_REG_SHIFT 3
|
||||
#define DP_SPARE_REG_DEFAULT_MASK (0x1fffffff << 3)
|
||||
#define DP_SPARE_SOR_CLK_SEL_SHIFT 2
|
||||
#define DP_SPARE_SOR_CLK_SEL_DEFAULT_MASK (1 << 2)
|
||||
#define DP_SPARE_SOR_CLK_SEL_SAFE_SORCLK (0 << 2)
|
||||
#define DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK (1 << 2)
|
||||
#define DP_SPARE_PANEL_SHIFT 1
|
||||
#define DP_SPARE_PANEL_EXTERNAL (0 << 1)
|
||||
#define DP_SPARE_PANEL_INTERNAL (1 << 1)
|
||||
#define DP_SPARE_SEQ_ENABLE_SHIFT 0
|
||||
#define DP_SPARE_SEQ_ENABLE_NO 0
|
||||
#define DP_SPARE_SEQ_ENABLE_YES 1
|
||||
#define DP_AUDIO_CTRL 0x62
|
||||
#define DP_AUDIO_HBLANK_SYMBOLS 0x63
|
||||
#define DP_AUDIO_HBLANK_SYMBOLS_MASK 0x1ffff
|
||||
#define DP_AUDIO_HBLANK_SYMBOLS_VALUE_SHIFT 0
|
||||
#define DP_AUDIO_VBLANK_SYMBOLS 0x64
|
||||
#define DP_AUDIO_VBLANK_SYMBOLS_MASK 0x1ffff
|
||||
#define DP_AUDIO_VBLANK_SYMBOLS_SHIFT 0
|
||||
#define DP_GENERIC_INFOFRAME_HEADER 0x65
|
||||
#define DP_GENERIC_INFOFRAME_SUBPACK(i) (0x66 + (i))
|
||||
#define DP_TPG 0x6d
|
||||
#define DP_TPG_LANE3_CHANNELCODING_SHIFT 30
|
||||
#define DP_TPG_LANE3_CHANNELCODING_DISABLE (0 << 30)
|
||||
#define DP_TPG_LANE3_CHANNELCODING_ENABLE (1 << 30)
|
||||
#define DP_TPG_LANE3_SCRAMBLEREN_SHIFT 28
|
||||
#define DP_TPG_LANE3_SCRAMBLEREN_ENABLE_GALIOS (1 << 28)
|
||||
#define DP_TPG_LANE3_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 28)
|
||||
#define DP_TPG_LANE3_PATTERN_SHIFT 24
|
||||
#define DP_TPG_LANE3_PATTERN_DEFAULT_MASK (0xf << 24)
|
||||
#define DP_TPG_LANE3_PATTERN_NOPATTERN (0 << 24)
|
||||
#define DP_TPG_LANE3_PATTERN_TRAINING1 (1 << 24)
|
||||
#define DP_TPG_LANE3_PATTERN_TRAINING2 (2 << 24)
|
||||
#define DP_TPG_LANE3_PATTERN_TRAINING3 (3 << 24)
|
||||
#define DP_TPG_LANE3_PATTERN_D102 (4 << 24)
|
||||
#define DP_TPG_LANE3_PATTERN_SBLERRRATE (5 << 24)
|
||||
#define DP_TPG_LANE3_PATTERN_PRBS7 (6 << 24)
|
||||
#define DP_TPG_LANE3_PATTERN_CSTM (7 << 24)
|
||||
#define DP_TPG_LANE3_PATTERN_HBR2_COMPLIANCE (8 << 24)
|
||||
#define DP_TPG_LANE2_CHANNELCODING_SHIFT 22
|
||||
#define DP_TPG_LANE2_CHANNELCODING_DISABLE (0 << 22)
|
||||
#define DP_TPG_LANE2_CHANNELCODING_ENABLE (1 << 22)
|
||||
#define DP_TPG_LANE2_SCRAMBLEREN_SHIFT 20
|
||||
#define DP_TPG_LANE2_SCRAMBLEREN_DEFAULT_MASK (3 << 20)
|
||||
#define DP_TPG_LANE2_SCRAMBLEREN_DISABLE (0 << 20)
|
||||
#define DP_TPG_LANE2_SCRAMBLEREN_ENABLE_GALIOS (1 << 20)
|
||||
#define DP_TPG_LANE2_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 20)
|
||||
#define DP_TPG_LANE2_PATTERN_SHIFT 16
|
||||
#define DP_TPG_LANE2_PATTERN_DEFAULT_MASK (0xf << 16)
|
||||
#define DP_TPG_LANE2_PATTERN_NOPATTERN (0 << 16)
|
||||
#define DP_TPG_LANE2_PATTERN_TRAINING1 (1 << 16)
|
||||
#define DP_TPG_LANE2_PATTERN_TRAINING2 (2 << 16)
|
||||
#define DP_TPG_LANE2_PATTERN_TRAINING3 (3 << 16)
|
||||
#define DP_TPG_LANE2_PATTERN_D102 (4 << 16)
|
||||
#define DP_TPG_LANE2_PATTERN_SBLERRRATE (5 << 16)
|
||||
#define DP_TPG_LANE2_PATTERN_PRBS7 (6 << 16)
|
||||
#define DP_TPG_LANE2_PATTERN_CSTM (7 << 16)
|
||||
#define DP_TPG_LANE2_PATTERN_HBR2_COMPLIANCE (8 << 16)
|
||||
#define DP_TPG_LANE1_CHANNELCODING_SHIFT 14
|
||||
#define DP_TPG_LANE1_CHANNELCODING_DISABLE (0 << 14)
|
||||
#define DP_TPG_LANE1_CHANNELCODING_ENABLE (1 << 14)
|
||||
#define DP_TPG_LANE1_SCRAMBLEREN_SHIFT 12
|
||||
#define DP_TPG_LANE1_SCRAMBLEREN_DEFAULT_MASK (3 << 12)
|
||||
#define DP_TPG_LANE1_SCRAMBLEREN_DISABLE (0 << 12)
|
||||
#define DP_TPG_LANE1_SCRAMBLEREN_ENABLE_GALIOS (1 << 12)
|
||||
#define DP_TPG_LANE1_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 12)
|
||||
#define DP_TPG_LANE1_PATTERN_SHIFT 8
|
||||
#define DP_TPG_LANE1_PATTERN_DEFAULT_MASK (0xf << 8)
|
||||
#define DP_TPG_LANE1_PATTERN_NOPATTERN (0 << 8)
|
||||
#define DP_TPG_LANE1_PATTERN_TRAINING1 (1 << 8)
|
||||
#define DP_TPG_LANE1_PATTERN_TRAINING2 (2 << 8)
|
||||
#define DP_TPG_LANE1_PATTERN_TRAINING3 (3 << 8)
|
||||
#define DP_TPG_LANE1_PATTERN_D102 (4 << 8)
|
||||
#define DP_TPG_LANE1_PATTERN_SBLERRRATE (5 << 8)
|
||||
#define DP_TPG_LANE1_PATTERN_PRBS7 (6 << 8)
|
||||
#define DP_TPG_LANE1_PATTERN_CSTM (7 << 8)
|
||||
#define DP_TPG_LANE1_PATTERN_HBR2_COMPLIANCE (8 << 8)
|
||||
#define DP_TPG_LANE0_CHANNELCODING_SHIFT 6
|
||||
#define DP_TPG_LANE0_CHANNELCODING_DISABLE (0 << 6)
|
||||
#define DP_TPG_LANE0_CHANNELCODING_ENABLE (1 << 6)
|
||||
#define DP_TPG_LANE0_SCRAMBLEREN_SHIFT 4
|
||||
#define DP_TPG_LANE0_SCRAMBLEREN_DEFAULT_MASK (3 << 4)
|
||||
#define DP_TPG_LANE0_SCRAMBLEREN_DISABLE (0 << 4)
|
||||
#define DP_TPG_LANE0_SCRAMBLEREN_ENABLE_GALIOS (1 << 4)
|
||||
#define DP_TPG_LANE0_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 4)
|
||||
#define DP_TPG_LANE0_PATTERN_SHIFT 0
|
||||
#define DP_TPG_LANE0_PATTERN_DEFAULT_MASK 0xf
|
||||
#define DP_TPG_LANE0_PATTERN_NOPATTERN 0
|
||||
#define DP_TPG_LANE0_PATTERN_TRAINING1 1
|
||||
#define DP_TPG_LANE0_PATTERN_TRAINING2 2
|
||||
#define DP_TPG_LANE0_PATTERN_TRAINING3 3
|
||||
#define DP_TPG_LANE0_PATTERN_D102 4
|
||||
#define DP_TPG_LANE0_PATTERN_SBLERRRATE 5
|
||||
#define DP_TPG_LANE0_PATTERN_PRBS7 6
|
||||
#define DP_TPG_LANE0_PATTERN_CSTM 7
|
||||
#define DP_TPG_LANE0_PATTERN_HBR2_COMPLIANCE 8
|
||||
|
||||
enum {
|
||||
training_pattern_disabled = 0,
|
||||
training_pattern_1 = 1,
|
||||
training_pattern_2 = 2,
|
||||
training_pattern_3 = 3,
|
||||
training_pattern_none = 0xff
|
||||
};
|
||||
|
||||
enum tegra_dc_sor_protocol {
|
||||
SOR_DP,
|
||||
SOR_LVDS,
|
||||
};
|
||||
|
||||
#define SOR_LINK_SPEED_G1_62 6
|
||||
#define SOR_LINK_SPEED_G2_7 10
|
||||
#define SOR_LINK_SPEED_G5_4 20
|
||||
#define SOR_LINK_SPEED_LVDS 7
|
||||
|
||||
struct tegra_dp_link_config {
|
||||
int is_valid;
|
||||
|
||||
/* Supported configuration */
|
||||
u8 max_link_bw;
|
||||
u8 max_lane_count;
|
||||
int downspread;
|
||||
int support_enhanced_framing;
|
||||
u32 bits_per_pixel;
|
||||
int alt_scramber_reset_cap; /* true for eDP */
|
||||
int only_enhanced_framing; /* enhanced_frame_en ignored */
|
||||
int frame_in_ms;
|
||||
|
||||
/* Actual configuration */
|
||||
u8 link_bw;
|
||||
u8 lane_count;
|
||||
int enhanced_framing;
|
||||
int scramble_ena;
|
||||
|
||||
u32 activepolarity;
|
||||
u32 active_count;
|
||||
u32 tu_size;
|
||||
u32 active_frac;
|
||||
u32 watermark;
|
||||
|
||||
s32 hblank_sym;
|
||||
s32 vblank_sym;
|
||||
|
||||
/* Training data */
|
||||
u32 drive_current;
|
||||
u32 preemphasis;
|
||||
u32 postcursor;
|
||||
u8 aux_rd_interval;
|
||||
u8 tps3_supported;
|
||||
};
|
||||
|
||||
#define TEGRA_SOR_TIMEOUT_MS 1000
|
||||
#define TEGRA_SOR_ATTACH_TIMEOUT_MS 1000
|
||||
|
||||
int tegra_dc_sor_enable_dp(struct udevice *sor,
|
||||
const struct tegra_dp_link_config *link_cfg);
|
||||
int tegra_dc_sor_set_power_state(struct udevice *sor, int pu_pd);
|
||||
void tegra_dc_sor_set_dp_linkctl(struct udevice *dev, int ena,
|
||||
u8 training_pattern, const struct tegra_dp_link_config *link_cfg);
|
||||
void tegra_dc_sor_set_link_bandwidth(struct udevice *dev, u8 link_bw);
|
||||
void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count);
|
||||
void tegra_dc_sor_set_panel_power(struct udevice *sor,
|
||||
int power_up);
|
||||
void tegra_dc_sor_set_internal_panel(struct udevice *dev, int is_int);
|
||||
void tegra_dc_sor_read_link_config(struct udevice *dev, u8 *link_bw,
|
||||
u8 *lane_count);
|
||||
void tegra_dc_sor_set_lane_parm(struct udevice *dev,
|
||||
const struct tegra_dp_link_config *link_cfg);
|
||||
void tegra_dc_sor_power_down_unused_lanes(struct udevice *sor,
|
||||
const struct tegra_dp_link_config *link_cfg);
|
||||
int tegra_dc_sor_set_voltage_swing(struct udevice *sor,
|
||||
const struct tegra_dp_link_config *link_cfg);
|
||||
int tegra_sor_precharge_lanes(struct udevice *dev,
|
||||
const struct tegra_dp_link_config *cfg);
|
||||
void tegra_dp_disable_tx_pu(struct udevice *sor);
|
||||
void tegra_dp_set_pe_vs_pc(struct udevice *dev, u32 mask, u32 pe_reg,
|
||||
u32 vs_reg, u32 pc_reg, u8 pc_supported);
|
||||
|
||||
int tegra_dc_sor_attach(struct udevice *dc_dev, struct udevice *sor,
|
||||
const struct tegra_dp_link_config *link_cfg,
|
||||
const struct display_timing *timing);
|
||||
int tegra_dc_sor_detach(struct udevice *dc_dev, struct udevice *sor);
|
||||
|
||||
void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl,
|
||||
int *dc_reg_ctx);
|
||||
int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl);
|
||||
void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl,
|
||||
int *dc_reg_ctx);
|
||||
|
||||
int tegra_dc_sor_init(struct udevice **sorp);
|
||||
#endif
|
||||
Reference in New Issue
Block a user