GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/drivers/w1/Kconfig

@@ -0,0 +1,39 @@
+#
+# W1 subsystem configuration
+#
+
+menu "1-Wire support"
+
+config W1
+	bool "Enable 1-wire controllers support"
+	default no
+	depends on DM
+	help
+	  Support for the Dallas 1-Wire bus.
+
+if W1
+
+config W1_GPIO
+	bool "Enable 1-wire GPIO bitbanging"
+	default no
+	depends on DM_GPIO
+	help
+	  Emulate a 1-wire bus using a GPIO.
+
+config W1_MXC
+	bool "Enable 1-wire controller on i.MX processors"
+	default no
+	depends on ARCH_MX25 || ARCH_MX31 || ARCH_MX5
+	help
+	  Support the one wire controller found in some members of the NXP
+	  i.MX SoC family.
+	  There are currently two silicon variants:
+	  V1: i.MX21, i.MX27, i.MX31, i.MX51
+	  V2: i.MX25, i.MX35, i.MX50, i.MX53
+	  Newer i.MX SoCs such as the i.MX6 do not have one wire controllers.
+
+	  The driver supports both silicon variants.
+
+endif
+
+endmenu

source/bootloader/u-boot-2020.01/drivers/w1/Makefile

@@ -0,0 +1,4 @@
+obj-$(CONFIG_W1) += w1-uclass.o
+
+obj-$(CONFIG_W1_GPIO) += w1-gpio.o
+obj-$(CONFIG_W1_MXC) += mxc_w1.o

source/bootloader/u-boot-2020.01/drivers/w1/mxc_w1.c

@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for one wire controller in some i.MX Socs
+ *
+ * There are currently two silicon variants:
+ * V1: i.MX21, i.MX27, i.MX31, i.MX51
+ * V2: i.MX25, i.MX35, i.MX50, i.MX53
+ * Newer i.MX SoCs such as the i.MX6 do not have one wire controllers.
+ *
+ * The V1 controller only supports single bit operations.
+ * The V2 controller is backwards compatible on the register level but adds
+ * byte size operations and a "search ROM accelerator mode"
+ *
+ * This driver does not currently support the search ROM accelerator
+ *
+ * Copyright (c) 2018 Flowbird
+ * Martin Fuzzey <martin.fuzzey@flowbird.group>
+ */
+
+#include <asm/arch/clock.h>
+#include <common.h>
+#include <dm.h>
+#include <linux/io.h>
+#include <w1.h>
+
+struct mxc_w1_regs {
+	u16 control;
+#define MXC_W1_CONTROL_RPP	BIT(7)
+#define MXC_W1_CONTROL_PST	BIT(6)
+#define MXC_W1_CONTROL_WR(x)	BIT(5 - (x))
+#define MXC_W1_CONTROL_RDST	BIT(3)
+
+	u16 time_divider;
+	u16 reset;
+
+	/* Registers below on V2 silicon only */
+	u16 command;
+	u16 tx_rx;
+	u16 interrupt;
+#define MXC_W1_INTERRUPT_TBE	BIT(2)
+#define MXC_W1_INTERRUPT_TSRE	BIT(3)
+#define MXC_W1_INTERRUPT_RBF	BIT(4)
+#define MXC_W1_INTERRUPT_RSRF	BIT(5)
+
+	u16 interrupt_en;
+};
+
+struct mxc_w1_pdata {
+	struct mxc_w1_regs *regs;
+};
+
+/*
+ * this is the low level routine to read/write a bit on the One Wire
+ * interface on the hardware. It does write 0 if parameter bit is set
+ * to 0, otherwise a write 1/read.
+ */
+static u8 mxc_w1_touch_bit(struct mxc_w1_pdata *pdata, u8 bit)
+{
+	u16 *ctrl_addr = &pdata->regs->control;
+	u16 mask = MXC_W1_CONTROL_WR(bit);
+	unsigned int timeout_cnt = 400; /* Takes max. 120us according to
+					 * datasheet.
+					 */
+
+	writew(mask, ctrl_addr);
+
+	while (timeout_cnt--) {
+		if (!(readw(ctrl_addr) & mask))
+			break;
+
+		udelay(1);
+	}
+
+	return (readw(ctrl_addr) & MXC_W1_CONTROL_RDST) ? 1 : 0;
+}
+
+static u8 mxc_w1_read_byte(struct udevice *dev)
+{
+	struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
+	struct mxc_w1_regs *regs = pdata->regs;
+	u16 status;
+
+	if (dev_get_driver_data(dev) < 2) {
+		int i;
+		u8 ret = 0;
+
+		for (i = 0; i < 8; i++)
+			ret |= (mxc_w1_touch_bit(pdata, 1) << i);
+
+		return ret;
+	}
+
+	readw(&regs->tx_rx);
+	writew(0xFF, &regs->tx_rx);
+
+	do {
+		udelay(1); /* Without this bytes are sometimes duplicated... */
+		status = readw(&regs->interrupt);
+	} while (!(status & MXC_W1_INTERRUPT_RBF));
+
+	return (u8)readw(&regs->tx_rx);
+}
+
+static void mxc_w1_write_byte(struct udevice *dev, u8 byte)
+{
+	struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
+	struct mxc_w1_regs *regs = pdata->regs;
+	u16 status;
+
+	if (dev_get_driver_data(dev) < 2) {
+		int i;
+
+		for (i = 0; i < 8; i++)
+			mxc_w1_touch_bit(pdata, (byte >> i) & 0x1);
+
+		return;
+	}
+
+	readw(&regs->tx_rx);
+	writew(byte, &regs->tx_rx);
+
+	do {
+		udelay(1);
+		status = readw(&regs->interrupt);
+	} while (!(status & MXC_W1_INTERRUPT_TSRE));
+}
+
+static bool mxc_w1_reset(struct udevice *dev)
+{
+	struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
+	u16 reg_val;
+
+	writew(MXC_W1_CONTROL_RPP, &pdata->regs->control);
+
+	do {
+		reg_val = readw(&pdata->regs->control);
+	}  while (reg_val & MXC_W1_CONTROL_RPP);
+
+	return !(reg_val & MXC_W1_CONTROL_PST);
+}
+
+static u8 mxc_w1_triplet(struct udevice *dev, bool bdir)
+{
+	struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
+	u8 id_bit   = mxc_w1_touch_bit(pdata, 1);
+	u8 comp_bit = mxc_w1_touch_bit(pdata, 1);
+	u8 retval;
+
+	if (id_bit && comp_bit)
+		return 0x03;  /* error */
+
+	if (!id_bit && !comp_bit) {
+		/* Both bits are valid, take the direction given */
+		retval = bdir ? 0x04 : 0;
+	} else {
+		/* Only one bit is valid, take that direction */
+		bdir = id_bit;
+		retval = id_bit ? 0x05 : 0x02;
+	}
+
+	mxc_w1_touch_bit(pdata, bdir);
+
+	return retval;
+}
+
+static int mxc_w1_ofdata_to_platdata(struct udevice *dev)
+{
+	struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
+	fdt_addr_t addr;
+
+	addr = devfdt_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	pdata->regs = (struct mxc_w1_regs *)addr;
+
+	return 0;
+};
+
+static int mxc_w1_probe(struct udevice *dev)
+{
+	struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
+	unsigned int clkrate = mxc_get_clock(MXC_IPG_PERCLK);
+	unsigned int clkdiv;
+
+	if (clkrate < 10000000) {
+		dev_err(dev, "input clock frequency (%u Hz) too low\n",
+			clkrate);
+		return -EINVAL;
+	}
+
+	clkdiv = clkrate / 1000000;
+	clkrate /= clkdiv;
+	if (clkrate < 980000 || clkrate > 1020000) {
+		dev_err(dev, "Incorrect time base frequency %u Hz\n", clkrate);
+		return -EINVAL;
+	}
+
+	writew(clkdiv - 1, &pdata->regs->time_divider);
+
+	return 0;
+}
+
+static const struct w1_ops mxc_w1_ops = {
+	.read_byte	= mxc_w1_read_byte,
+	.reset		= mxc_w1_reset,
+	.triplet	= mxc_w1_triplet,
+	.write_byte	= mxc_w1_write_byte,
+};
+
+static const struct udevice_id mxc_w1_id[] = {
+	{ .compatible = "fsl,imx21-owire", .data = 1 },
+	{ .compatible = "fsl,imx27-owire", .data = 1 },
+	{ .compatible = "fsl,imx31-owire", .data = 1 },
+	{ .compatible = "fsl,imx51-owire", .data = 1 },
+
+	{ .compatible = "fsl,imx25-owire", .data = 2 },
+	{ .compatible = "fsl,imx35-owire", .data = 2 },
+	{ .compatible = "fsl,imx50-owire", .data = 2 },
+	{ .compatible = "fsl,imx53-owire", .data = 2 },
+	{ },
+};
+
+U_BOOT_DRIVER(mxc_w1_drv) = {
+	.id				= UCLASS_W1,
+	.name				= "mxc_w1_drv",
+	.of_match			= mxc_w1_id,
+	.ofdata_to_platdata		= mxc_w1_ofdata_to_platdata,
+	.ops				= &mxc_w1_ops,
+	.platdata_auto_alloc_size	= sizeof(struct mxc_w1_pdata),
+	.probe				= mxc_w1_probe,
+};

source/bootloader/u-boot-2020.01/drivers/w1/w1-gpio.c

@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Copyright (c) 2015 Free Electrons
+ * Copyright (c) 2015 NextThing Co
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <w1.h>
+
+#include <asm/gpio.h>
+
+#define W1_TIMING_A	6
+#define W1_TIMING_B	64
+#define W1_TIMING_C	60
+#define W1_TIMING_D	10
+#define W1_TIMING_E	9
+#define W1_TIMING_F	55
+#define W1_TIMING_G	0
+#define W1_TIMING_H	480
+#define W1_TIMING_I	70
+#define W1_TIMING_J	410
+
+struct w1_gpio_pdata {
+	struct gpio_desc	gpio;
+	u64			search_id;
+};
+
+static bool w1_gpio_read_bit(struct udevice *dev)
+{
+	struct w1_gpio_pdata *pdata = dev_get_platdata(dev);
+	int val;
+
+	dm_gpio_set_dir_flags(&pdata->gpio, GPIOD_IS_OUT);
+	udelay(W1_TIMING_A);
+
+	dm_gpio_set_dir_flags(&pdata->gpio, GPIOD_IS_IN);
+	udelay(W1_TIMING_E);
+
+	val = dm_gpio_get_value(&pdata->gpio);
+	if (val < 0)
+		debug("error in retrieving GPIO value");
+	udelay(W1_TIMING_F);
+
+	return val;
+}
+
+static u8 w1_gpio_read_byte(struct udevice *dev)
+{
+	int i;
+	u8 ret = 0;
+
+	for (i = 0; i < 8; ++i)
+		ret |= (w1_gpio_read_bit(dev) ? 1 : 0) << i;
+
+	return ret;
+}
+
+static void w1_gpio_write_bit(struct udevice *dev, bool bit)
+{
+	struct w1_gpio_pdata *pdata = dev_get_platdata(dev);
+
+	dm_gpio_set_dir_flags(&pdata->gpio, GPIOD_IS_OUT);
+
+	bit ? udelay(W1_TIMING_A) : udelay(W1_TIMING_C);
+
+	dm_gpio_set_value(&pdata->gpio, 1);
+
+	bit ? udelay(W1_TIMING_B) : udelay(W1_TIMING_D);
+}
+
+static void w1_gpio_write_byte(struct udevice *dev, u8 byte)
+{
+	int i;
+
+	for (i = 0; i < 8; ++i)
+		w1_gpio_write_bit(dev, (byte >> i) & 0x1);
+}
+
+static bool w1_gpio_reset(struct udevice *dev)
+{
+	struct w1_gpio_pdata *pdata = dev_get_platdata(dev);
+	int val;
+
+	/* initiate the reset pulse. first we must pull the bus to low */
+	dm_gpio_set_dir_flags(&pdata->gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	udelay(W1_TIMING_G);
+
+	dm_gpio_set_value(&pdata->gpio, 0);
+	/* wait for the specified time with the bus kept low */
+	udelay(W1_TIMING_H);
+
+	/* now we must read the presence pulse */
+	dm_gpio_set_dir_flags(&pdata->gpio, GPIOD_IS_IN);
+	udelay(W1_TIMING_I);
+
+	val = dm_gpio_get_value(&pdata->gpio);
+	if (val < 0)
+		debug("error in retrieving GPIO value");
+
+	/* if nobody pulled the bus down , it means nobody is on the bus */
+	if (val != 0)
+		return 1;
+	/* we have the bus pulled down, let's wait for the specified presence time */
+	udelay(W1_TIMING_J);
+
+	/* read again, the other end should leave the bus free */
+	val = dm_gpio_get_value(&pdata->gpio);
+	if (val < 0)
+		debug("error in retrieving GPIO value");
+
+	/* bus is not going up again, so we have an error */
+	if (val != 1)
+		return 1;
+
+	/* all good, presence detected */
+	return 0;
+}
+
+static u8 w1_gpio_triplet(struct udevice *dev, bool bdir)
+{
+	u8 id_bit   = w1_gpio_read_bit(dev);
+	u8 comp_bit = w1_gpio_read_bit(dev);
+	u8 retval;
+
+	if (id_bit && comp_bit)
+		return 0x03;  /* error */
+
+	if (!id_bit && !comp_bit) {
+		/* Both bits are valid, take the direction given */
+		retval = bdir ? 0x04 : 0;
+	} else {
+		/* Only one bit is valid, take that direction */
+		bdir = id_bit;
+		retval = id_bit ? 0x05 : 0x02;
+	}
+
+	w1_gpio_write_bit(dev, bdir);
+	return retval;
+}
+
+static const struct w1_ops w1_gpio_ops = {
+	.read_byte	= w1_gpio_read_byte,
+	.reset		= w1_gpio_reset,
+	.triplet	= w1_gpio_triplet,
+	.write_byte	= w1_gpio_write_byte,
+};
+
+static int w1_gpio_ofdata_to_platdata(struct udevice *dev)
+{
+	struct w1_gpio_pdata *pdata = dev_get_platdata(dev);
+	int ret;
+
+	ret = gpio_request_by_name(dev, "gpios", 0, &pdata->gpio, 0);
+	if (ret < 0)
+		printf("Error claiming GPIO %d\n", ret);
+
+	return ret;
+};
+
+static const struct udevice_id w1_gpio_id[] = {
+	{ "w1-gpio", 0 },
+	{ },
+};
+
+U_BOOT_DRIVER(w1_gpio_drv) = {
+	.id				= UCLASS_W1,
+	.name				= "w1_gpio_drv",
+	.of_match			= w1_gpio_id,
+	.ofdata_to_platdata		= w1_gpio_ofdata_to_platdata,
+	.ops				= &w1_gpio_ops,
+	.platdata_auto_alloc_size	= sizeof(struct w1_gpio_pdata),
+};

source/bootloader/u-boot-2020.01/drivers/w1/w1-uclass.c

@@ -0,0 +1,238 @@
+// SPDX-License-Identifier:	GPL-2.0+
+/*
+ *
+ * Copyright (c) 2015 Free Electrons
+ * Copyright (c) 2015 NextThing Co.
+ * Copyright (c) 2018 Microchip Technology, Inc.
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ * Eugen Hristev <eugen.hristev@microchip.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <w1.h>
+#include <w1-eeprom.h>
+
+#include <dm/device-internal.h>
+
+#define W1_MATCH_ROM	0x55
+#define W1_SKIP_ROM	0xcc
+#define W1_SEARCH	0xf0
+
+struct w1_bus {
+	u64	search_id;
+};
+
+static int w1_enumerate(struct udevice *bus)
+{
+	const struct w1_ops *ops = device_get_ops(bus);
+	struct w1_bus *w1 = dev_get_uclass_priv(bus);
+	u64 last_rn, rn = w1->search_id, tmp64;
+	bool last_device = false;
+	int search_bit, desc_bit = 64;
+	int last_zero = -1;
+	u8 triplet_ret = 0;
+	int i;
+
+	if (!ops->reset || !ops->write_byte || !ops->triplet)
+		return -ENOSYS;
+
+	while (!last_device) {
+		last_rn = rn;
+		rn = 0;
+
+		/*
+		 * Reset bus and all 1-wire device state machines
+		 * so they can respond to our requests.
+		 *
+		 * Return 0 - device(s) present, 1 - no devices present.
+		 */
+		if (ops->reset(bus)) {
+			debug("%s: No devices present on the wire.\n",
+			      __func__);
+			break;
+		}
+
+		/* Start the search */
+		ops->write_byte(bus, W1_SEARCH);
+		for (i = 0; i < 64; ++i) {
+			/* Determine the direction/search bit */
+			if (i == desc_bit)
+				/* took the 0 path last time, so take the 1 path */
+				search_bit = 1;
+			else if (i > desc_bit)
+				/* take the 0 path on the next branch */
+				search_bit = 0;
+			else
+				search_bit = ((last_rn >> i) & 0x1);
+
+			/* Read two bits and write one bit */
+			triplet_ret = ops->triplet(bus, search_bit);
+
+			/* quit if no device responded */
+			if ((triplet_ret & 0x03) == 0x03)
+				break;
+
+			/* If both directions were valid, and we took the 0 path... */
+			if (triplet_ret == 0)
+				last_zero = i;
+
+			/* extract the direction taken & update the device number */
+			tmp64 = (triplet_ret >> 2);
+			rn |= (tmp64 << i);
+		}
+
+		if ((triplet_ret & 0x03) != 0x03) {
+			if (desc_bit == last_zero || last_zero < 0) {
+				last_device = 1;
+				w1->search_id = 0;
+			} else {
+				w1->search_id = rn;
+			}
+			desc_bit = last_zero;
+
+			debug("%s: Detected new device 0x%llx (family 0x%x)\n",
+			      bus->name, rn, (u8)(rn & 0xff));
+
+			/* attempt to register as w1-eeprom device */
+			w1_eeprom_register_new_device(rn);
+		}
+	}
+
+	return 0;
+}
+
+int w1_get_bus(int busnum, struct udevice **busp)
+{
+	int ret, i = 0;
+
+	struct udevice *dev;
+
+	for (ret = uclass_first_device(UCLASS_W1, &dev);
+	     dev && !ret;
+	     ret = uclass_next_device(&dev), i++) {
+		if (i == busnum) {
+			*busp = dev;
+			return 0;
+		}
+	}
+
+	if (!ret) {
+		debug("Cannot find w1 bus %d\n", busnum);
+		ret = -ENODEV;
+	}
+
+	return ret;
+}
+
+u8 w1_get_device_family(struct udevice *dev)
+{
+	struct w1_device *w1 = dev_get_parent_platdata(dev);
+
+	return w1->id & 0xff;
+}
+
+int w1_reset_select(struct udevice *dev)
+{
+	struct w1_device *w1 = dev_get_parent_platdata(dev);
+	struct udevice *bus = dev_get_parent(dev);
+	const struct w1_ops *ops = device_get_ops(bus);
+	int i;
+
+	if (!ops->reset || !ops->write_byte)
+		return -ENOSYS;
+
+	ops->reset(bus);
+
+	ops->write_byte(bus, W1_MATCH_ROM);
+
+	for (i = 0; i < sizeof(w1->id); i++)
+		ops->write_byte(bus, (w1->id >> (i * 8)) & 0xff);
+
+	return 0;
+}
+
+int w1_read_byte(struct udevice *dev)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	const struct w1_ops *ops = device_get_ops(bus);
+
+	if (!ops->read_byte)
+		return -ENOSYS;
+
+	return ops->read_byte(bus);
+}
+
+int w1_read_buf(struct udevice *dev, u8 *buf, unsigned int count)
+{
+	int i, ret;
+
+	for (i = 0; i < count; i++) {
+		ret = w1_read_byte(dev);
+		if (ret < 0)
+			return ret;
+
+		buf[i] = ret & 0xff;
+	}
+
+	return 0;
+}
+
+int w1_write_byte(struct udevice *dev, u8 byte)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	const struct w1_ops *ops = device_get_ops(bus);
+
+	if (!ops->write_byte)
+		return -ENOSYS;
+
+	ops->write_byte(bus, byte);
+
+	return 0;
+}
+
+static int w1_post_probe(struct udevice *bus)
+{
+	w1_enumerate(bus);
+
+	return 0;
+}
+
+int w1_init(void)
+{
+	struct udevice *bus;
+	struct uclass *uc;
+	int ret;
+
+	ret = uclass_get(UCLASS_W1, &uc);
+	if (ret)
+		return ret;
+
+	uclass_foreach_dev(bus, uc) {
+		ret = device_probe(bus);
+		if (ret == -ENODEV) {	/* No such device. */
+			printf("W1 controller not available.\n");
+			continue;
+		}
+
+		if (ret) {		/* Other error. */
+			printf("W1 controller probe failed.\n");
+			continue;
+		}
+	}
+	return 0;
+}
+
+UCLASS_DRIVER(w1) = {
+	.name		= "w1",
+	.id		= UCLASS_W1,
+	.flags		= DM_UC_FLAG_SEQ_ALIAS,
+	.per_device_auto_alloc_size	= sizeof(struct w1_bus),
+	.post_probe	= w1_post_probe,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+	.post_bind	= dm_scan_fdt_dev,
+#endif
+	.per_child_platdata_auto_alloc_size     = sizeof(struct w1_device),
+};