GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/include/dm/platform_data/lpc32xx_hsuart.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com>
+ */
+
+#ifndef _LPC32XX_HSUART_PLAT_H
+#define _LPC32XX_HSUART_PLAT_H
+
+/**
+ * struct lpc32xx_hsuart_platdata - NXP LPC32xx HSUART platform data
+ *
+ * @base:               Base register address
+ */
+struct lpc32xx_hsuart_platdata {
+	unsigned long base;
+};
+
+#endif

source/bootloader/u-boot-2020.01/include/dm/platform_data/net_ethoc.h

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Cadence Design Systems Inc.
+ */
+
+#ifndef _ETHOC_H
+#define _ETHOC_H
+
+#include <net.h>
+
+#ifdef CONFIG_DM_ETH
+
+struct ethoc_eth_pdata {
+	struct eth_pdata eth_pdata;
+	phys_addr_t packet_base;
+};
+
+#endif
+
+#endif /* _ETHOC_H */

source/bootloader/u-boot-2020.01/include/dm/platform_data/pfe_dm_eth.h

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef __PFE_DM_ETH_H__
+#define __PFE_DM_ETH_H__
+#include <net.h>
+
+struct pfe_ddr_address {
+	void *ddr_pfe_baseaddr;
+	unsigned long ddr_pfe_phys_baseaddr;
+};
+
+struct pfe_eth_pdata {
+	struct eth_pdata pfe_eth_pdata_mac;
+	struct pfe_ddr_address pfe_ddr_addr;
+};
+#endif /* __PFE_DM_ETH_H__ */

source/bootloader/u-boot-2020.01/include/dm/platform_data/serial_bcm283x_mu.h

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Stephen Warren <swarren@wwwdotorg.org>
+ *
+ * Derived from pl01x code:
+ * Copyright (c) 2014 Google, Inc
+ */
+
+#ifndef __serial_bcm283x_mu_h
+#define __serial_bcm283x_mu_h
+
+/*
+ *Information about a serial port
+ *
+ * @base: Register base address
+ */
+struct bcm283x_mu_serial_platdata {
+	unsigned long base;
+	unsigned int clock;
+	bool skip_init;
+};
+
+#endif

source/bootloader/u-boot-2020.01/include/dm/platform_data/serial_coldfire.h

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015  Angelo Dureghello <angelo@sysam.it>
+ */
+
+#ifndef __serial_coldfire_h
+#define __serial_coldfire_h
+
+/*
+ * struct coldfire_serial_platdata - information about a coldfire port
+ *
+ * @base:               Uart port base register address
+ * @port:               Uart port index, for cpu with pinmux for uart / gpio
+ * baudrtatre:          Uart port baudrate
+ */
+struct coldfire_serial_platdata {
+	unsigned long base;
+	int port;
+	int baudrate;
+};
+
+#endif /* __serial_coldfire_h */

source/bootloader/u-boot-2020.01/include/dm/platform_data/serial_mxc.h

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014 Google, Inc
+ */
+
+#ifndef __serial_mxc_h
+#define __serial_mxc_h
+
+/* Information about a serial port */
+struct mxc_serial_platdata {
+	struct mxc_uart *reg;  /* address of registers in physical memory */
+	bool use_dte;
+};
+
+#endif

source/bootloader/u-boot-2020.01/include/dm/platform_data/serial_pl01x.h

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014 Google, Inc
+ */
+
+#ifndef __serial_pl01x_h
+#define __serial_pl01x_h
+
+enum pl01x_type {
+	TYPE_PL010,
+	TYPE_PL011,
+};
+
+/*
+ *Information about a serial port
+ *
+ * @base: Register base address
+ * @type: Port type
+ * @clock: Input clock rate, used for calculating the baud rate divisor
+ * @skip_init: Don't attempt to change port configuration (also means @clock
+ * is ignored)
+ */
+struct pl01x_serial_platdata {
+	unsigned long base;
+	enum pl01x_type type;
+	unsigned int clock;
+	bool skip_init;
+};
+
+#endif

source/bootloader/u-boot-2020.01/include/dm/platform_data/serial_pxa.h

@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
+ */
+
+#ifndef __SERIAL_PXA_H
+#define __SERIAL_PXA_H
+
+/*
+ * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can
+ * easily handle enabling of clock.
+ */
+#ifdef CONFIG_CPU_MONAHANS
+#define UART_CLK_BASE	CKENA_21_BTUART
+#define UART_CLK_REG	CKENA
+#define BTUART_INDEX	0
+#define FFUART_INDEX	1
+#define STUART_INDEX	2
+#elif CONFIG_CPU_PXA25X
+#define UART_CLK_BASE	(1 << 4)	/* HWUART */
+#define UART_CLK_REG	CKEN
+#define HWUART_INDEX	0
+#define STUART_INDEX	1
+#define FFUART_INDEX	2
+#define BTUART_INDEX	3
+#else /* PXA27x */
+#define UART_CLK_BASE	CKEN5_STUART
+#define UART_CLK_REG	CKEN
+#define STUART_INDEX	0
+#define FFUART_INDEX	1
+#define BTUART_INDEX	2
+#endif
+
+/*
+ * Only PXA250 has HWUART, to avoid poluting the code with more macros,
+ * artificially introduce this.
+ */
+#ifndef CONFIG_CPU_PXA25X
+#define HWUART_INDEX	0xff
+#endif
+
+/*
+ * struct pxa_serial_platdata - information about a PXA port
+ *
+ * @base:               Uart port base register address
+ * @port:               Uart port index, for cpu with pinmux for uart / gpio
+ * baudrtatre:          Uart port baudrate
+ */
+struct pxa_serial_platdata {
+	struct pxa_uart_regs *base;
+	int port;
+	int baudrate;
+};
+
+#endif /* __SERIAL_PXA_H */

source/bootloader/u-boot-2020.01/include/dm/platform_data/serial_sh.h

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014  Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (c) 2014  Renesas Electronics Corporation
+ */
+
+#ifndef __serial_sh_h
+#define __serial_sh_h
+
+enum sh_clk_mode {
+	INT_CLK,
+	EXT_CLK,
+};
+
+enum sh_serial_type {
+	PORT_SCI,
+	PORT_SCIF,
+	PORT_SCIFA,
+	PORT_SCIFB,
+};
+
+/*
+ * Information about SCIF port
+ *
+ * @base:	Register base address
+ * @clk:	Input clock rate, used for calculating the baud rate divisor
+ * @clk_mode:	Clock mode, set internal (INT) or external (EXT)
+ * @type:	Type of SCIF
+ */
+struct sh_serial_platdata {
+	unsigned long base;
+	unsigned int clk;
+	enum sh_clk_mode clk_mode;
+	enum sh_serial_type type;
+};
+#endif /* __serial_sh_h */

source/bootloader/u-boot-2020.01/include/dm/platform_data/spi_coldfire.h

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018  Angelo Dureghello <angelo@sysam.it>
+ */
+
+#ifndef __spi_coldfire_h
+#define __spi_coldfire_h
+
+#define MAX_CTAR_REGS		8
+#define MAX_CTAR_FIELDS		8
+
+/*
+ * struct coldfire_spi_platdata - information about a coldfire spi module
+ *
+ * @regs_addr: base address for module registers
+ * @speed_hz: default SCK frequency
+ * @mode: default SPI mode
+ * @num_cs: number of DSPI chipselect signals
+ */
+struct coldfire_spi_platdata {
+	fdt_addr_t regs_addr;
+	uint speed_hz;
+	uint mode;
+	uint num_cs;
+	uint ctar[MAX_CTAR_REGS][MAX_CTAR_FIELDS];
+};
+
+#endif /* __spi_coldfire_h */
+

source/bootloader/u-boot-2020.01/include/dm/platform_data/spi_davinci.h

@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __spi_davinci_h
+#define __spi_davinci_h
+
+struct davinci_spi_platdata {
+	struct davinci_spi_regs *regs;
+	u8 num_cs;	   /* total no. of CS available */
+};
+
+#endif /* __spi_davinci_h */

source/bootloader/u-boot-2020.01/include/dm/platform_data/spi_pl022.h

@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018
+ * Quentin Schulz, Bootlin, quentin.schulz@bootlin.com
+ *
+ * Structure for use with U_BOOT_DEVICE for pl022 SPI devices or to use
+ * in ofdata_to_platdata.
+ */
+
+#ifndef __spi_pl022_h
+#define __spi_pl022_h
+
+#include <fdtdec.h>
+
+struct pl022_spi_pdata {
+	fdt_addr_t addr;
+	fdt_size_t size;
+	unsigned int freq;
+};
+
+#endif /* __spi_pl022_h */