GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (C) 2017 Impinj
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __DT_BINDINGS_IMX7_POWER_H__
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#define __DT_BINDINGS_IMX7_POWER_H__
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#define IMX7_POWER_DOMAIN_MIPI_PHY 0
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#define IMX7_POWER_DOMAIN_PCIE_PHY 1
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#define IMX7_POWER_DOMAIN_USB_HSIC_PHY 2
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#endif
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
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*/
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#ifndef __DT_BINDINGS_IMX8MQ_POWER_H__
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#define __DT_BINDINGS_IMX8MQ_POWER_H__
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#define IMX8M_POWER_DOMAIN_MIPI 0
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#define IMX8M_POWER_DOMAIN_PCIE1 1
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#define IMX8M_POWER_DOMAIN_USB_OTG1 2
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#define IMX8M_POWER_DOMAIN_USB_OTG2 3
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#define IMX8M_POWER_DOMAIN_DDR1 4
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#define IMX8M_POWER_DOMAIN_GPU 5
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#define IMX8M_POWER_DOMAIN_VPU 6
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#define IMX8M_POWER_DOMAIN_DISP 7
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#define IMX8M_POWER_DOMAIN_MIPI_CSI1 8
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#define IMX8M_POWER_DOMAIN_MIPI_CSI2 9
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#define IMX8M_POWER_DOMAIN_PCIE2 10
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#endif
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@@ -0,0 +1,13 @@
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/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
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/*
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* Copyright (c) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#ifndef _DT_BINDINGS_MESON_G12A_POWER_H
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#define _DT_BINDINGS_MESON_G12A_POWER_H
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#define PWRC_G12A_VPU_ID 0
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#define PWRC_G12A_ETH_ID 1
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#endif
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@@ -0,0 +1,18 @@
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/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
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/*
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* Copyright (c) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#ifndef _DT_BINDINGS_MESON_SM1_POWER_H
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#define _DT_BINDINGS_MESON_SM1_POWER_H
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#define PWRC_SM1_VPU_ID 0
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#define PWRC_SM1_NNA_ID 1
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#define PWRC_SM1_USB_ID 2
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#define PWRC_SM1_PCIE_ID 3
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#define PWRC_SM1_GE2D_ID 4
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#define PWRC_SM1_AUDIO_ID 5
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#define PWRC_SM1_ETH_ID 6
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#endif
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@@ -0,0 +1,19 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 MediaTek Inc.
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*/
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#ifndef _DT_BINDINGS_MT7623_POWER_H
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#define _DT_BINDINGS_MT7623_POWER_H
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#define MT7623_POWER_DOMAIN_CONN 0
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#define MT7623_POWER_DOMAIN_DISP 1
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#define MT7623_POWER_DOMAIN_MFG 2
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#define MT7623_POWER_DOMAIN_VDEC 3
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#define MT7623_POWER_DOMAIN_ISP 4
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#define MT7623_POWER_DOMAIN_BDP 5
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#define MT7623_POWER_DOMAIN_ETH 6
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#define MT7623_POWER_DOMAIN_HIF 7
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#define MT7623_POWER_DOMAIN_IFR_MSC 8
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#endif /* _DT_BINDINGS_MT7623_POWER_H */
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@@ -0,0 +1,13 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 MediaTek Inc.
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*/
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#ifndef _DT_BINDINGS_MT7629_POWER_H
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#define _DT_BINDINGS_MT7629_POWER_H
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#define MT7629_POWER_DOMAIN_ETHSYS 0
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#define MT7629_POWER_DOMAIN_HIF0 1
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#define MT7629_POWER_DOMAIN_HIF1 2
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#endif /* _DT_BINDINGS_MT7629_POWER_H */
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@@ -0,0 +1,27 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __DT_BINDINGS_POWER_PX30_POWER_H__
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#define __DT_BINDINGS_POWER_PX30_POWER_H__
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/* VD_CORE */
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#define PX30_PD_A35_0 0
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#define PX30_PD_A35_1 1
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#define PX30_PD_A35_2 2
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#define PX30_PD_A35_3 3
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#define PX30_PD_SCU 4
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/* VD_LOGIC */
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#define PX30_PD_USB 5
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#define PX30_PD_DDR 6
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#define PX30_PD_SDCARD 7
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#define PX30_PD_CRYPTO 8
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#define PX30_PD_GMAC 9
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#define PX30_PD_MMC_NAND 10
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#define PX30_PD_VPU 11
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#define PX30_PD_VO 12
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#define PX30_PD_VI 13
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#define PX30_PD_GPU 14
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/* VD_PMU */
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#define PX30_PD_PMU 15
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#endif
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@@ -0,0 +1,34 @@
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/*
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* Copyright (C) 2016 Glider bvba
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__
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#define __DT_BINDINGS_POWER_R8A7790_SYSC_H__
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/*
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* These power domain indices match the numbers of the interrupt bits
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* representing the power areas in the various Interrupt Registers
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* (e.g. SYSCISR, Interrupt Status Register)
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*/
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#define R8A7790_PD_CA15_CPU0 0
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#define R8A7790_PD_CA15_CPU1 1
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#define R8A7790_PD_CA15_CPU2 2
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#define R8A7790_PD_CA15_CPU3 3
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#define R8A7790_PD_CA7_CPU0 5
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#define R8A7790_PD_CA7_CPU1 6
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#define R8A7790_PD_CA7_CPU2 7
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#define R8A7790_PD_CA7_CPU3 8
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#define R8A7790_PD_CA15_SCU 12
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#define R8A7790_PD_SH_4A 16
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#define R8A7790_PD_RGX 20
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#define R8A7790_PD_CA7_SCU 21
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#define R8A7790_PD_IMP 24
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/* Always-on power area */
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#define R8A7790_PD_ALWAYS_ON 32
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#endif /* __DT_BINDINGS_POWER_R8A7790_SYSC_H__ */
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@@ -0,0 +1,26 @@
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/*
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* Copyright (C) 2016 Glider bvba
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#ifndef __DT_BINDINGS_POWER_R8A7791_SYSC_H__
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#define __DT_BINDINGS_POWER_R8A7791_SYSC_H__
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/*
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* These power domain indices match the numbers of the interrupt bits
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* representing the power areas in the various Interrupt Registers
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* (e.g. SYSCISR, Interrupt Status Register)
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*/
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#define R8A7791_PD_CA15_CPU0 0
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#define R8A7791_PD_CA15_CPU1 1
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#define R8A7791_PD_CA15_SCU 12
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#define R8A7791_PD_SH_4A 16
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#define R8A7791_PD_SGX 20
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/* Always-on power area */
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#define R8A7791_PD_ALWAYS_ON 32
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#endif /* __DT_BINDINGS_POWER_R8A7791_SYSC_H__ */
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@@ -0,0 +1,26 @@
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/*
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* Copyright (C) 2016 Cogent Embedded Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#ifndef __DT_BINDINGS_POWER_R8A7792_SYSC_H__
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#define __DT_BINDINGS_POWER_R8A7792_SYSC_H__
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/*
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* These power domain indices match the numbers of the interrupt bits
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* representing the power areas in the various Interrupt Registers
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* (e.g. SYSCISR, Interrupt Status Register)
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*/
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#define R8A7792_PD_CA15_CPU0 0
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#define R8A7792_PD_CA15_CPU1 1
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#define R8A7792_PD_CA15_SCU 12
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#define R8A7792_PD_SGX 20
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#define R8A7792_PD_IMP 24
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/* Always-on power area */
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#define R8A7792_PD_ALWAYS_ON 32
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#endif /* __DT_BINDINGS_POWER_R8A7792_SYSC_H__ */
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@@ -0,0 +1,28 @@
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/*
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* Copyright (C) 2016 Glider bvba
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#ifndef __DT_BINDINGS_POWER_R8A7793_SYSC_H__
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#define __DT_BINDINGS_POWER_R8A7793_SYSC_H__
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/*
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* These power domain indices match the numbers of the interrupt bits
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* representing the power areas in the various Interrupt Registers
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* (e.g. SYSCISR, Interrupt Status Register)
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*
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* Note that R-Car M2-N is identical to R-Car M2-W w.r.t. power domains.
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*/
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#define R8A7793_PD_CA15_CPU0 0
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#define R8A7793_PD_CA15_CPU1 1
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#define R8A7793_PD_CA15_SCU 12
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#define R8A7793_PD_SH_4A 16
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#define R8A7793_PD_SGX 20
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/* Always-on power area */
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#define R8A7793_PD_ALWAYS_ON 32
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#endif /* __DT_BINDINGS_POWER_R8A7793_SYSC_H__ */
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@@ -0,0 +1,26 @@
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/*
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* Copyright (C) 2016 Glider bvba
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*
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* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
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*/
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#ifndef __DT_BINDINGS_POWER_R8A7794_SYSC_H__
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#define __DT_BINDINGS_POWER_R8A7794_SYSC_H__
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/*
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* These power domain indices match the numbers of the interrupt bits
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* representing the power areas in the various Interrupt Registers
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* (e.g. SYSCISR, Interrupt Status Register)
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*/
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#define R8A7794_PD_CA7_CPU0 5
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#define R8A7794_PD_CA7_CPU1 6
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#define R8A7794_PD_SH_4A 16
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#define R8A7794_PD_SGX 20
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#define R8A7794_PD_CA7_SCU 21
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/* Always-on power area */
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#define R8A7794_PD_ALWAYS_ON 32
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#endif /* __DT_BINDINGS_POWER_R8A7794_SYSC_H__ */
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@@ -0,0 +1,42 @@
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/*
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* Copyright (C) 2016 Glider bvba
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
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*/
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#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__
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#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__
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/*
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* These power domain indices match the numbers of the interrupt bits
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* representing the power areas in the various Interrupt Registers
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* (e.g. SYSCISR, Interrupt Status Register)
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*/
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#define R8A7795_PD_CA57_CPU0 0
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#define R8A7795_PD_CA57_CPU1 1
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#define R8A7795_PD_CA57_CPU2 2
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#define R8A7795_PD_CA57_CPU3 3
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#define R8A7795_PD_CA53_CPU0 5
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#define R8A7795_PD_CA53_CPU1 6
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#define R8A7795_PD_CA53_CPU2 7
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#define R8A7795_PD_CA53_CPU3 8
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#define R8A7795_PD_A3VP 9
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#define R8A7795_PD_CA57_SCU 12
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#define R8A7795_PD_CR7 13
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#define R8A7795_PD_A3VC 14
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#define R8A7795_PD_3DG_A 17
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#define R8A7795_PD_3DG_B 18
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#define R8A7795_PD_3DG_C 19
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#define R8A7795_PD_3DG_D 20
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#define R8A7795_PD_CA53_SCU 21
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#define R8A7795_PD_3DG_E 22
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#define R8A7795_PD_A3IR 24
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#define R8A7795_PD_A2VC0 25 /* ES1.x only */
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#define R8A7795_PD_A2VC1 26
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/* Always-on power area */
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#define R8A7795_PD_ALWAYS_ON 32
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#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */
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@@ -0,0 +1,36 @@
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/*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A7796_SYSC_H__
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#define __DT_BINDINGS_POWER_R8A7796_SYSC_H__
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|
||||
/*
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* These power domain indices match the numbers of the interrupt bits
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* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A7796_PD_CA57_CPU0 0
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#define R8A7796_PD_CA57_CPU1 1
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||||
#define R8A7796_PD_CA53_CPU0 5
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||||
#define R8A7796_PD_CA53_CPU1 6
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||||
#define R8A7796_PD_CA53_CPU2 7
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||||
#define R8A7796_PD_CA53_CPU3 8
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||||
#define R8A7796_PD_CA57_SCU 12
|
||||
#define R8A7796_PD_CR7 13
|
||||
#define R8A7796_PD_A3VC 14
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||||
#define R8A7796_PD_3DG_A 17
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||||
#define R8A7796_PD_3DG_B 18
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||||
#define R8A7796_PD_CA53_SCU 21
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||||
#define R8A7796_PD_A3IR 24
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||||
#define R8A7796_PD_A2VC0 25
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||||
#define R8A7796_PD_A2VC1 26
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||||
|
||||
/* Always-on power area */
|
||||
#define R8A7796_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A7796_SYSC_H__ */
|
||||
@@ -0,0 +1,29 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_POWER_R8A77965_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A77965_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A77965_PD_CA57_CPU0 0
|
||||
#define R8A77965_PD_CA57_CPU1 1
|
||||
#define R8A77965_PD_A3VP 9
|
||||
#define R8A77965_PD_CA57_SCU 12
|
||||
#define R8A77965_PD_CR7 13
|
||||
#define R8A77965_PD_A3VC 14
|
||||
#define R8A77965_PD_3DG_A 17
|
||||
#define R8A77965_PD_3DG_B 18
|
||||
#define R8A77965_PD_A2VC1 26
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A77965_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A77965_SYSC_H__ */
|
||||
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Cogent Embedded Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A77970_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A77970_PD_CA53_CPU0 5
|
||||
#define R8A77970_PD_CA53_CPU1 6
|
||||
#define R8A77970_PD_CA53_SCU 21
|
||||
#define R8A77970_PD_A2IR0 23
|
||||
#define R8A77970_PD_A3IR 24
|
||||
#define R8A77970_PD_A2IR1 27
|
||||
#define R8A77970_PD_A2DP 28
|
||||
#define R8A77970_PD_A2CN 29
|
||||
#define R8A77970_PD_A2SC0 30
|
||||
#define R8A77970_PD_A2SC1 31
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A77970_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A77970_SYSC_H__ */
|
||||
@@ -0,0 +1,43 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
* Copyright (C) 2018 Cogent Embedded, Inc.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A77980_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A77980_PD_A2SC2 0
|
||||
#define R8A77980_PD_A2SC3 1
|
||||
#define R8A77980_PD_A2SC4 2
|
||||
#define R8A77980_PD_A2DP0 3
|
||||
#define R8A77980_PD_A2DP1 4
|
||||
#define R8A77980_PD_CA53_CPU0 5
|
||||
#define R8A77980_PD_CA53_CPU1 6
|
||||
#define R8A77980_PD_CA53_CPU2 7
|
||||
#define R8A77980_PD_CA53_CPU3 8
|
||||
#define R8A77980_PD_A2CN 10
|
||||
#define R8A77980_PD_A3VIP0 11
|
||||
#define R8A77980_PD_A2IR5 12
|
||||
#define R8A77980_PD_CR7 13
|
||||
#define R8A77980_PD_A2IR4 15
|
||||
#define R8A77980_PD_CA53_SCU 21
|
||||
#define R8A77980_PD_A2IR0 23
|
||||
#define R8A77980_PD_A3IR 24
|
||||
#define R8A77980_PD_A3VIP1 25
|
||||
#define R8A77980_PD_A3VIP2 26
|
||||
#define R8A77980_PD_A2IR1 27
|
||||
#define R8A77980_PD_A2IR2 28
|
||||
#define R8A77980_PD_A2IR3 29
|
||||
#define R8A77980_PD_A2SC0 30
|
||||
#define R8A77980_PD_A2SC1 31
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A77980_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */
|
||||
@@ -0,0 +1,26 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A77990_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A77990_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A77990_PD_CA53_CPU0 5
|
||||
#define R8A77990_PD_CA53_CPU1 6
|
||||
#define R8A77990_PD_CR7 13
|
||||
#define R8A77990_PD_A3VC 14
|
||||
#define R8A77990_PD_3DG_A 17
|
||||
#define R8A77990_PD_3DG_B 18
|
||||
#define R8A77990_PD_CA53_SCU 21
|
||||
#define R8A77990_PD_A2VC1 26
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A77990_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A77990_SYSC_H__ */
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A77995_PD_CA53_CPU0 5
|
||||
#define R8A77995_PD_CA53_SCU 21
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A77995_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */
|
||||
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* Copyright © 2015 Broadcom
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H
|
||||
#define _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H
|
||||
|
||||
/* These power domain indices are the firmware interface's indices
|
||||
* minus one.
|
||||
*/
|
||||
#define RPI_POWER_DOMAIN_I2C0 0
|
||||
#define RPI_POWER_DOMAIN_I2C1 1
|
||||
#define RPI_POWER_DOMAIN_I2C2 2
|
||||
#define RPI_POWER_DOMAIN_VIDEO_SCALER 3
|
||||
#define RPI_POWER_DOMAIN_VPU1 4
|
||||
#define RPI_POWER_DOMAIN_HDMI 5
|
||||
#define RPI_POWER_DOMAIN_USB 6
|
||||
#define RPI_POWER_DOMAIN_VEC 7
|
||||
#define RPI_POWER_DOMAIN_JPEG 8
|
||||
#define RPI_POWER_DOMAIN_H264 9
|
||||
#define RPI_POWER_DOMAIN_V3D 10
|
||||
#define RPI_POWER_DOMAIN_ISP 11
|
||||
#define RPI_POWER_DOMAIN_UNICAM0 12
|
||||
#define RPI_POWER_DOMAIN_UNICAM1 13
|
||||
#define RPI_POWER_DOMAIN_CCP2RX 14
|
||||
#define RPI_POWER_DOMAIN_CSI2 15
|
||||
#define RPI_POWER_DOMAIN_CPI 16
|
||||
#define RPI_POWER_DOMAIN_DSI0 17
|
||||
#define RPI_POWER_DOMAIN_DSI1 18
|
||||
#define RPI_POWER_DOMAIN_TRANSPOSER 19
|
||||
#define RPI_POWER_DOMAIN_CCP2TX 20
|
||||
#define RPI_POWER_DOMAIN_CDP 21
|
||||
#define RPI_POWER_DOMAIN_ARM 22
|
||||
|
||||
#define RPI_POWER_DOMAIN_COUNT 23
|
||||
|
||||
#endif /* _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H */
|
||||
@@ -0,0 +1,53 @@
|
||||
#ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__
|
||||
#define __DT_BINDINGS_POWER_RK3399_POWER_H__
|
||||
|
||||
/* VD_CORE_L */
|
||||
#define RK3399_PD_A53_L0 0
|
||||
#define RK3399_PD_A53_L1 1
|
||||
#define RK3399_PD_A53_L2 2
|
||||
#define RK3399_PD_A53_L3 3
|
||||
#define RK3399_PD_SCU_L 4
|
||||
|
||||
/* VD_CORE_B */
|
||||
#define RK3399_PD_A72_B0 5
|
||||
#define RK3399_PD_A72_B1 6
|
||||
#define RK3399_PD_SCU_B 7
|
||||
|
||||
/* VD_LOGIC */
|
||||
#define RK3399_PD_TCPD0 8
|
||||
#define RK3399_PD_TCPD1 9
|
||||
#define RK3399_PD_CCI 10
|
||||
#define RK3399_PD_CCI0 11
|
||||
#define RK3399_PD_CCI1 12
|
||||
#define RK3399_PD_PERILP 13
|
||||
#define RK3399_PD_PERIHP 14
|
||||
#define RK3399_PD_VIO 15
|
||||
#define RK3399_PD_VO 16
|
||||
#define RK3399_PD_VOPB 17
|
||||
#define RK3399_PD_VOPL 18
|
||||
#define RK3399_PD_ISP0 19
|
||||
#define RK3399_PD_ISP1 20
|
||||
#define RK3399_PD_HDCP 21
|
||||
#define RK3399_PD_GMAC 22
|
||||
#define RK3399_PD_EMMC 23
|
||||
#define RK3399_PD_USB3 24
|
||||
#define RK3399_PD_EDP 25
|
||||
#define RK3399_PD_GIC 26
|
||||
#define RK3399_PD_SD 27
|
||||
#define RK3399_PD_SDIOAUDIO 28
|
||||
#define RK3399_PD_ALIVE 29
|
||||
|
||||
/* VD_CENTER */
|
||||
#define RK3399_PD_CENTER 30
|
||||
#define RK3399_PD_VCODEC 31
|
||||
#define RK3399_PD_VDU 32
|
||||
#define RK3399_PD_RGA 33
|
||||
#define RK3399_PD_IEP 34
|
||||
|
||||
/* VD_GPU */
|
||||
#define RK3399_PD_GPU 35
|
||||
|
||||
/* VD_PMU */
|
||||
#define RK3399_PD_PMU 36
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,28 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2015-2016, NVIDIA CORPORATION.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H
|
||||
#define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H
|
||||
|
||||
#define TEGRA186_POWER_DOMAIN_AUD 0
|
||||
#define TEGRA186_POWER_DOMAIN_DFD 1
|
||||
#define TEGRA186_POWER_DOMAIN_DISP 2
|
||||
#define TEGRA186_POWER_DOMAIN_DISPB 3
|
||||
#define TEGRA186_POWER_DOMAIN_DISPC 4
|
||||
#define TEGRA186_POWER_DOMAIN_ISPA 5
|
||||
#define TEGRA186_POWER_DOMAIN_NVDEC 6
|
||||
#define TEGRA186_POWER_DOMAIN_NVJPG 7
|
||||
#define TEGRA186_POWER_DOMAIN_MPE 8
|
||||
#define TEGRA186_POWER_DOMAIN_PCX 9
|
||||
#define TEGRA186_POWER_DOMAIN_SAX 10
|
||||
#define TEGRA186_POWER_DOMAIN_VE 11
|
||||
#define TEGRA186_POWER_DOMAIN_VIC 12
|
||||
#define TEGRA186_POWER_DOMAIN_XUSBA 13
|
||||
#define TEGRA186_POWER_DOMAIN_XUSBB 14
|
||||
#define TEGRA186_POWER_DOMAIN_XUSBC 15
|
||||
#define TEGRA186_POWER_DOMAIN_GPU 43
|
||||
#define TEGRA186_POWER_DOMAIN_MAX 44
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,39 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018 Xilinx, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
|
||||
#define _DT_BINDINGS_ZYNQMP_POWER_H
|
||||
|
||||
#define PD_USB_0 22
|
||||
#define PD_USB_1 23
|
||||
#define PD_TTC_0 24
|
||||
#define PD_TTC_1 25
|
||||
#define PD_TTC_2 26
|
||||
#define PD_TTC_3 27
|
||||
#define PD_SATA 28
|
||||
#define PD_ETH_0 29
|
||||
#define PD_ETH_1 30
|
||||
#define PD_ETH_2 31
|
||||
#define PD_ETH_3 32
|
||||
#define PD_UART_0 33
|
||||
#define PD_UART_1 34
|
||||
#define PD_SPI_0 35
|
||||
#define PD_SPI_1 36
|
||||
#define PD_I2C_0 37
|
||||
#define PD_I2C_1 38
|
||||
#define PD_SD_0 39
|
||||
#define PD_SD_1 40
|
||||
#define PD_DP 41
|
||||
#define PD_GDMA 42
|
||||
#define PD_ADMA 43
|
||||
#define PD_NAND 44
|
||||
#define PD_QSPI 45
|
||||
#define PD_GPIO 46
|
||||
#define PD_CAN_0 47
|
||||
#define PD_CAN_1 48
|
||||
#define PD_GPU 58
|
||||
#define PD_PCIE 59
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user