GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/lotus/ddr/Makefile

@@ -0,0 +1,4 @@
+obj-y += ddr_cmd_ctl.o
+obj-y += cmd_ddr_training.o
+obj-$(CONFIG_TARGET_XMFALCON) += ddr_training_xmfalcon.o
+obj-$(CONFIG_TARGET_XMORCA) += ddr_training_xmorca.o

source/bootloader/u-boot-2020.01/lotus/ddr/cmd_ddr_training.c

@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <linux/io.h>
+#include "ddr_if.h"
+#include "linux/lotus/i2c.h"
+#include "linux/lotus/securec.h"
+
+#define DDR_CMD_DATAEYE_STR         "dataeye"
+#define DDR_CMD_GCAI_INFO         "gcai-info"
+static struct ddr_training_result *g_ddrtr_result;
+
+static int ddr_map_show(void);
+
+static int cmd_ddr_match(const char *str, int *cmd)
+{
+	if (!strncmp(str, DDR_CMD_DATAEYE_STR, sizeof(DDR_CMD_DATAEYE_STR))) {
+		*cmd = DDR_TRAINING_CMD_DATAEYE;
+	} else if (!strncmp(str, DDR_CMD_GCAI_INFO,
+		sizeof(DDR_CMD_GCAI_INFO))) {
+		*cmd = DDR_CMD_SHOW_GCAI_INFO;
+	} else {
+		printf("Command [ddr %s] is not supported\n", str);
+		return -1;
+	}
+
+	return 0;
+}
+
+static int cmd_ddr_handle(int cmd)
+{
+	if (cmd == DDR_TRAINING_CMD_DATAEYE)
+		return	get_result(g_ddrtr_result);
+
+	return 0;
+}
+
+static int cmd_ddr_dispatch(int cmd)
+{
+	int result;
+
+	result = cmd_ddr_handle(cmd);
+	if (result < 0)
+		return -1;
+
+	switch (cmd) {
+	case DDR_TRAINING_CMD_DATAEYE:
+		ddr_cmd_result_display(g_ddrtr_result, DDR_TRAINING_CMD_DATAEYE);
+		break;
+	case DDR_CMD_SHOW_GCAI_INFO:
+		ddr_map_show();
+		break;
+	default:
+		break;
+	}
+
+	return result;
+}
+
+static int do_ddr_training(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	const char *str = NULL;
+	int cmd;
+	int ret = 0;
+
+	if (argc != 2)
+		return -1;
+
+	str = argv[1];
+
+	if (cmd_ddr_match(str, &cmd)) {
+		ret = -1;
+		goto out;
+	}
+
+	g_ddrtr_result = malloc(sizeof(struct ddr_training_result));
+	if (g_ddrtr_result == NULL) {
+		printf("Fail to alloc DDR Training result memory!\n");
+		ret = -1;
+		goto out;
+	}
+
+	if (cmd_ddr_dispatch(cmd)) {
+		ret = -1;
+		goto out;
+	}
+
+out:
+	if (g_ddrtr_result)
+		free(g_ddrtr_result);
+
+	return ret;
+}
+
+static int get_ddr4_bank_group_cnt(void)
+{
+	u32 reg;
+
+	reg = readl(DDRC_AXI_BASE + DDRC_DDR_INFO_REG_OFFSET);
+	reg &= DDR_BG_NUM_MASK;
+
+	return reg ? 4 : 2; /* 1:4-bg, 0: 2-bg */
+}
+
+static int get_ddr_type(void)
+{
+	u32 type = DDR3_TYPE;
+	u32 v = readl(DDRC_TOP_FEATURE) & 0x7;
+
+	switch (v) {
+	case 1:
+		type = DDR3_TYPE;
+		break;
+	case 2:
+		type = DDR4_TYPE;
+		break;
+	case 3:
+		type = LPDDR4_TYPE;
+		break;
+	default:
+		type = v;
+		break;
+	}
+
+	return type;
+}
+
+static int get_ddr_bank_cnt(int rank_cnt)
+{
+	int type, bank_cnt;
+
+	type = get_ddr_type();
+
+	switch (type) {
+	case LPDDR4_TYPE:
+		/* GCAI DDR support 2-chans */
+		bank_cnt = LPDDR4_CHANNEL_NUM * rank_cnt *
+			LPDDR4_BANK_NUM_OF_RANK;
+		break;
+	case DDR4_TYPE:
+		/* Get DDR4 bank group cnt */
+		int bg_cnt;
+
+		bg_cnt = get_ddr4_bank_group_cnt();
+		bank_cnt = DDR4_BANK_NUM_OF_BG * bg_cnt;
+		break;
+	case DDR3_TYPE:
+		/* DDR3 support single channel multi ranks */
+		bank_cnt = rank_cnt * LPDDR4_BANK_NUM_OF_RANK;
+	default:
+		bank_cnt = -1;
+		break;
+	}
+
+	return bank_cnt;
+}
+
+static int show_ddr_info(char *buf, unsigned int *rank_cnt,
+	unsigned int *bank_cnt, unsigned int *block_cnt)
+{
+	struct gcai_base_info *gcaiinfo;
+	int ret;
+
+	gcaiinfo = (struct gcai_base_info *)buf;
+	*rank_cnt = (unsigned int)gcaiinfo->cs_num;
+
+	*bank_cnt = get_ddr_bank_cnt(*rank_cnt);
+	if (*bank_cnt <= 0) {
+		printf("%s-%d: get_ddr_bank_cnt err\n", __func__, __LINE__);
+		return -1;
+	}
+
+	*block_cnt = (*bank_cnt) * 8;
+
+	ret = get_ddr_type();
+	if (ret == LPDDR4_TYPE)
+		printf("GCAI LPDDR4: channel=2, ");
+	else if (ret == DDR4_TYPE)
+		printf("GCAI DDR4: channel=1, ");
+	else {
+		printf("not support GCAI DDR type!\n");
+		return -1;
+	}
+
+	printf("rank=%u, bank=%u, block=%u\n", *rank_cnt, *bank_cnt,
+		*block_cnt);
+
+	return 0;
+}
+
+static int show_gcai_bad_blk_info(char *bad_blk_info, int expect_len)
+{
+#ifdef CONFIG_LOTUS_I2C
+	int ret = 0, i = 0, actual_len = 64;
+	struct i2c_client client;
+	char *read_ptr = bad_blk_info;
+
+	hal_i2c_init(0);	/* i2c0 init */
+	client.i2c_num = 0;	/* read by i2c0 */
+	client.dev_addr = 0x50; /* dev addr without RD flag */
+	client.reg_width = 1;	/* per reg addr width is 1-Byte */
+
+	printf("=======begin to show GCAI DDR info=======\n");
+	for (i = 0; i < expect_len; i++) {
+		/* read reg addr start from [0x0, 0x63] */
+		client.reg_addr = i;
+		/* per reg read return 1-byte data */
+		ret = hal_i2c_recv(&client, (void *)read_ptr, 1);
+		if (ret) {
+			printf("%s: i2c recv err, ret=%d\n", __func__, ret);
+			break;
+		}
+		read_ptr++;
+	}
+
+	for (i = 0; i < actual_len; i++)
+		printf("bad_blk_info[%d]: 0x%x\n", i, bad_blk_info[i]);
+
+	return ret;
+#else
+	printf("%s: i2c is not enabled.\n", __func__);
+	return 0;
+#endif
+}
+
+static void show_bad_blk_config_reg(void)
+{
+	int i;
+	u32 reg, offset;
+
+	for (i = 0; i < BAD_BLK_MAP_REG_NUM; i++) {
+		offset = i * 4;
+		reg = readl(CHAN0_BAD_BLK_MAP_REG0 + offset);
+		printf("ch0: reg%d(0x%x): 0x%x\n", i, CHAN0_BAD_BLK_MAP_REG0 + offset,
+			reg);
+	}
+
+	for (i = 0; i < BAD_BLK_MAP_REG_NUM; i++) {
+		offset = i * 4;
+		reg = readl(CHAN1_BAD_BLK_MAP_REG0 + offset);
+		printf("ch1: reg%d(0x%x): 0x%x\n", i, CHAN1_BAD_BLK_MAP_REG0 + offset,
+			reg);
+	}
+	printf("=======end of show GCAI DDR info=======\n");
+}
+
+/*
+ * is_gcai_ddr - Identify whether use GCAI DDR.
+ * 1:GCAI DDR, 0:non-GCAI DDR.
+ */
+static int is_gcai_ddr(void)
+{
+	u32 reg;
+
+	reg = readl(REG_BASE_SCTL + GCAI_FLAG_REG_OFFSET);
+
+	return (reg & GCAI_FLAG_MASK) ? 1 : 0;
+}
+
+/*
+ * ddr_map_show - GCAI DDR bad blk remap info.
+ */
+static int ddr_map_show(void)
+{
+	char *bad_blk_info = NULL;
+	int ret, read_len = 256;
+	unsigned int rank_cnt, bank_cnt, blk_cnt;
+
+	if (!is_gcai_ddr()) {
+		printf("%s: not GCAI DDR, show nothing.\n", __func__);
+		ret = 0;
+		goto out;
+	}
+
+	bad_blk_info = malloc(read_len * sizeof(char));
+	if (bad_blk_info == NULL) {
+		printf("%s: out of memory!\n", __func__);
+		ret = -1;
+		goto out;
+	}
+
+	memset_s(bad_blk_info, read_len, 0xEE, read_len);
+
+	/* show bad blk info that read from i2c */
+	ret = show_gcai_bad_blk_info(bad_blk_info, read_len);
+	if (ret)
+		goto free_mem;
+
+	/* show ddr detail info */
+	ret = show_ddr_info(bad_blk_info, &rank_cnt, &bank_cnt, &blk_cnt);
+	if (ret)
+		goto free_mem;
+
+	/* show all bad blk config reg */
+	show_bad_blk_config_reg();
+
+free_mem:
+	free(bad_blk_info);
+out:
+	return ret;
+}
+
+U_BOOT_CMD(
+	ddr, CONFIG_SYS_MAXARGS, 0,	do_ddr_training,
+	"ddr training cmd",
+	"dataeye     - DDR dataeye training.\n"
+	"gcai-info     - show GCAI DDR bad block remap info.\n"
+);
+

source/bootloader/u-boot-2020.01/lotus/ddr/ddr_cmd_ctl.c

@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include "ddr_if.h"
+
+#ifndef PHY_DQ_BDL_LEVEL
+#define PHY_DQ_BDL_LEVEL	256
+#endif
+
+static void print_dataeye_win(unsigned int dq_num, unsigned int range,
+	unsigned int dq, unsigned int win)
+{
+	unsigned int k;
+
+	printf("%-4u", dq_num);
+	for (k = 0; k < PHY_DQ_BDL_LEVEL; k += 2) {
+		if (k >= (range >> DDR_DATAEYE_RESULT_BIT) &&
+			k <= (range & DDR_DATAEYE_RESULT_MASK))
+			printf("%-1s", "-");
+		else
+			printf("%-1s", "X");
+	}
+	printf(" %-4u  %-4u  %-4u %-4u\n", range >> 16, range & 0xffff, dq, win);
+}
+
+static void print_dataeye_title(void)
+{
+	unsigned int k;
+
+	printf("%-4s", "DQ");
+	for (k = 0; k < PHY_DQ_BDL_LEVEL; k++) {
+		if (k % 8 == 0) /* Print out the CA number which is a multiple of 4 */
+			printf("%-4u", k);
+	}
+	printf(" %-4s  %-4s  %-4s %-4s\n", "MIN", "MAX", "AVG", "WIN");
+}
+
+static void ddr_cmd_result_print_write_dataeye(const struct ddr_training_data *ddrtr_data,
+	unsigned int win_min, unsigned int win_max, unsigned int win_sum)
+{
+	unsigned int i, j;
+	unsigned int dq_num, dq, win;
+
+	printf("Write window:\n");
+	printf("--------------------------------------------------------\n");
+	print_dataeye_title();
+	if (ddrtr_data->byte_num > DDR_PHY_BYTE_MAX) {
+		printf("byte num error, byte_num = %x", ddrtr_data->byte_num);
+		return;
+	}
+	for (j = 0; j < ddrtr_data->byte_num; j++) {
+		for (i = 0; i < DDR_PHY_BIT_NUM; i++) {
+			dq_num = (j << 3) + i; /* shift left 3: 8 bit */
+			if (dq_num >= DDR_PHY_BIT_MAX)
+				return;
+
+			win = ddrtr_data->write.ddr_bit_best[dq_num] >> DDR_DATAEYE_RESULT_BIT;
+			if (win < win_min)
+				win_min = win;
+			if (win > win_max)
+				win_max = win;
+			win_sum += win;
+			dq =  ddrtr_data->write.ddr_bit_best[dq_num] & DDR_DATAEYE_RESULT_MASK;
+			print_dataeye_win(dq_num,
+				ddrtr_data->write.ddr_bit_result[dq_num], dq, win);
+		}
+	}
+	printf("--------------------------------------------------------\n");
+	printf("Sum WIN: %u. Avg WIN: %u\n", win_sum,
+		win_sum / (ddrtr_data->byte_num * DDR_PHY_BIT_NUM));
+	printf("Min WIN: %u. DQ Index: ", win_min);
+	for (i = 0; i < DDR_PHY_BIT_MAX; i++) {
+		win = ddrtr_data->write.ddr_bit_best[i] >> DDR_DATAEYE_RESULT_BIT;
+		if (win == win_min)
+			printf("%u ", i);
+	}
+	printf("\nMax WIN: %u. DQ Index: ", win_max);
+	for (i = 0; i < DDR_PHY_BIT_MAX; i++) {
+		win = ddrtr_data->write.ddr_bit_best[i] >> DDR_DATAEYE_RESULT_BIT;
+		if (win == win_max)
+			printf("%u ", i);
+	}
+	printf("\n\n");
+}
+
+static void ddr_cmd_result_print_read_dataeye(const struct ddr_training_data *ddrtr_data,
+	unsigned int win_min, unsigned int win_max, unsigned int win_sum)
+{
+	unsigned int i, j;
+	unsigned int dq_num, dq, win;
+
+	if (ddrtr_data->byte_num > DDR_PHY_BYTE_MAX) {
+		printf("Invalid  byte_num = %d", ddrtr_data->byte_num);
+		return;
+	}
+	printf("Read window:\n");
+	printf("--------------------------------------------------------\n");
+	print_dataeye_title();
+	for (j = 0; j < ddrtr_data->byte_num; j++) {
+		for (i = 0; i < DDR_PHY_BIT_NUM; i++) {
+			dq_num = (j << 3) + i; /* shift left 3: 8 bit */
+			if (dq_num >= DDR_PHY_BIT_MAX)
+				return;
+
+			win = ddrtr_data->read.ddr_bit_best[dq_num] >> DDR_DATAEYE_RESULT_BIT;
+			if (win < win_min)
+				win_min = win;
+			if (win > win_max)
+				win_max = win;
+			win_sum += win;
+			dq = ddrtr_data->read.ddr_bit_best[dq_num] & DDR_DATAEYE_RESULT_MASK;
+			print_dataeye_win(dq_num,
+				ddrtr_data->read.ddr_bit_result[dq_num], dq, win);
+		}
+	}
+	printf("--------------------------------------------------------\n");
+	printf("Sum WIN: %u. Avg WIN: %u\n", win_sum,
+		win_sum / (ddrtr_data->byte_num * DDR_PHY_BIT_NUM));
+	printf("Min WIN: %u. DQ Index: ", win_min);
+	for (i = 0; i < DDR_PHY_BIT_MAX; i++) {
+		win = ddrtr_data->read.ddr_bit_best[i] >> DDR_DATAEYE_RESULT_BIT;
+		if (win == win_min)
+			printf("%u ", i);
+	}
+	printf("\nMax WIN: %u. DQ Index: ", win_max);
+	for (i = 0; i < DDR_PHY_BIT_MAX; i++) {
+		win = ddrtr_data->read.ddr_bit_best[i] >> DDR_DATAEYE_RESULT_BIT;
+		if (win == win_max)
+			printf("%u ", i);
+	}
+	printf("\n\n");
+}
+
+static void ddr_cmd_result_print_dataeye(const struct ddr_training_data *ddrtr_data)
+{
+	/* Write window */
+	ddr_cmd_result_print_write_dataeye(ddrtr_data, PHY_DQ_BDL_LEVEL, 0, 0);
+
+	/* Read window */
+	ddr_cmd_result_print_read_dataeye(ddrtr_data, PHY_DQ_BDL_LEVEL, 0, 0);
+}
+
+
+static void ddr_cmd_result_print_by_rank(const struct ddr_training_result *ddrtr_result,
+	unsigned int cmd, unsigned int phy_index, unsigned int rank_index)
+{
+	const struct rank_data *rank = &ddrtr_result->phy[phy_index].rank[rank_index];
+
+	printf("\r\n[PHY%u][RANK%u]:\r\n", phy_index, rank_index);
+	if (DDR_TRAINING_CMD_DATAEYE & cmd)
+		ddr_cmd_result_print_dataeye(&rank->ddrtr_data);
+
+}
+
+static void ddr_cmd_result_print_by_phy(const struct ddr_training_result *ddrtr_result,
+	unsigned int cmd, unsigned int phy_index)
+{
+	int i;
+
+	if (phy_index >= DDR_PHY_NUM) {
+		printf("Array index phy_idx out of range");
+		return;
+	}
+	if (ddrtr_result->phy[phy_index].rank_num > DDR_SUPPORT_RANK_MAX) {
+		printf("loop upper limit rank number out of range, rank_num = %x",
+			ddrtr_result->phy[phy_index].rank_num);
+		return;
+	}
+
+	for (i = 0; i < ddrtr_result->phy[phy_index].rank_num; i++)
+		ddr_cmd_result_print_by_rank(ddrtr_result, cmd, phy_index, i);
+}
+
+void ddr_cmd_result_display(const struct ddr_training_result *ddrtr_result, unsigned int cmd)
+{
+	int i;
+
+	if (ddrtr_result == NULL) {
+		printf("Pointer parameter ddrtr_result is NULL!");
+		return;
+	}
+	if (ddrtr_result->phy_num > DDR_PHY_NUM)
+		return;
+
+	for (i = 0; i < ddrtr_result->phy_num; i++)
+		ddr_cmd_result_print_by_phy(ddrtr_result, cmd, i);
+
+	show_win_reg();
+}
+
+

source/bootloader/u-boot-2020.01/lotus/ddr/ddr_if.h

@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _DDR_IF_H
+#define _DDR_IF_H
+
+#define DDR_PHY_BYTE_MAX		4
+#define DDR_PHY_BIT_NUM			8
+
+/* Max bit 32 */
+#define DDR_PHY_BIT_MAX			(DDR_PHY_BYTE_MAX * DDR_PHY_BIT_NUM)
+/* Max phy number */
+#define DDR_SUPPORT_PHY_MAX		2
+/* Max rank number */
+#define DDR_SUPPORT_RANK_MAX		2
+
+#define DDR_DATAEYE_RESULT_MASK		0xffff
+#define DDR_DATAEYE_RESULT_BIT		16
+
+#define DDR_TRAINING_CMD_DATAEYE	(1 << 5)
+#define DDR_CMD_SHOW_GCAI_INFO		(1 << 0)
+
+/* phy number */
+#define DDR_PHY_NUM			1
+
+#define DDRC_BASE			0x120D0000
+#define DDRC_AXI_BASE			(DDRC_BASE + 0x1000)
+
+#define DDRC_TOP_FEATURE		(DDRC_BASE + 0)
+#define DDR3_TYPE			1
+#define DDR4_TYPE			2
+#define LPDDR4_TYPE			3
+
+#define DDRC_DDR_INFO_REG_OFFSET	0x98
+#define DDR_BG_NUM_MASK			(0x1 << 28)
+
+#define LPDDR4_CHANNEL_NUM		0x2
+#define LPDDR4_BANK_NUM_OF_RANK		0x8
+#define DDR4_BANK_NUM_OF_BG		0x4
+
+#define GCAI_FLAG_REG_OFFSET		0x134
+#define GCAI_FLAG_MASK			(0x1 << 4)
+
+#define BAD_BLK_MAP_REG_NUM		0x40
+#define CHAN0_BAD_BLK_MAP_REG_OFFSET	0x578
+#define CHAN1_BAD_BLK_MAP_REG_OFFSET	0x678
+#define CHAN0_BAD_BLK_MAP_REG0	(DDRC_AXI_BASE + CHAN0_BAD_BLK_MAP_REG_OFFSET)
+#define CHAN1_BAD_BLK_MAP_REG0	(DDRC_AXI_BASE + CHAN1_BAD_BLK_MAP_REG_OFFSET)
+
+struct training_data {
+	unsigned int ddr_bit_result[DDR_PHY_BIT_MAX];
+	unsigned int ddr_bit_best[DDR_PHY_BIT_MAX];
+	unsigned int ddr_win_sum;
+};
+
+struct ddr_training_data {
+	unsigned int byte_num;
+	struct training_data read;
+	struct training_data write;
+};
+
+struct rank_data {
+	unsigned int rank_idx;
+	struct ddr_training_data ddrtr_data;
+};
+
+struct phy_data {
+	unsigned int rank_num;
+	struct rank_data rank[DDR_SUPPORT_RANK_MAX];
+};
+
+struct ddr_training_result {
+	unsigned int phy_num;
+	struct phy_data phy[DDR_SUPPORT_PHY_MAX];
+};
+
+struct gcai_base_info {
+	u8 unused0;
+	u8 type;
+	u8 cs_num;
+	u8 cs0_cap;
+	u8 cs1_cap;
+	u8 unused1;
+	u8 unused2;
+	u8 unused3;
+	u8 unused4;
+};
+
+void ddr_cmd_result_display(const struct ddr_training_result *ddrtr_result, unsigned int cmd);
+int get_result(struct ddr_training_result *result);
+void show_win_reg(void);
+#endif /* _DDR_IF_H */
+

source/bootloader/u-boot-2020.01/lotus/ddr/ddr_training_xmfalcon.c

@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <command.h>
+#include <linux/io.h>
+#include "ddr_if.h"
+
+#define REG_DQ_W_BDL_BASE	0x12104110
+#define REG_DQ_R_BDL_BASE	0x12104130
+#define REG_DQ_RES_SW		0x12101020
+
+int get_result(struct ddr_training_result *result)
+{
+	int i, j;
+	unsigned int *result_w, *result_r, *best_w, *best_r;
+
+	memset(result, 0, sizeof(struct ddr_training_result));
+
+	result->phy_num = DDR_PHY_NUM;
+
+	result->phy[0].rank_num = 1;
+
+	result->phy[0].rank[0].rank_idx = 0;
+
+	result->phy[0].rank[0].ddrtr_data.byte_num = 4;
+
+	result_w = result->phy[0].rank[0].ddrtr_data.write.ddr_bit_result;
+	result_r = result->phy[0].rank[0].ddrtr_data.read.ddr_bit_result;
+
+	for (i = 0; i < 4; i++) {
+		for (j = 0; j < 4; j++) {
+			unsigned int v = readl(REG_DQ_W_BDL_BASE + 0x1000 * i + j * 4);
+
+			result_w[i * 8 + j * 2] |= v & 0xff;
+			result_w[i * 8 + j * 2 + 1] |= (v >> 16) & 0xff;
+
+		}
+	}
+
+	for (i = 0; i < 4; i++) {
+		for (j = 0; j < 4; j++) {
+			unsigned int v = readl(REG_DQ_R_BDL_BASE + 0x1000 * i + j * 4);
+
+			result_r[i * 8 + j * 2] |= v & 0xff;
+			result_r[i * 8 + j * 2 + 1] |= (v >> 16) & 0xff;
+
+		}
+	}
+
+	/* Switch to getting min bdl */
+	writel(1, REG_DQ_RES_SW);
+
+	for (i = 0; i < 4; i++) {
+		for (j = 0; j < 4; j++) {
+			unsigned int v = readl(REG_DQ_W_BDL_BASE + 0x1000 * i + j * 4);
+
+			result_w[i * 8 + j * 2] |= (v & 0xff) << DDR_DATAEYE_RESULT_BIT;
+			result_w[i * 8 + j * 2 + 1] |= (v >> 16 & 0xff) << DDR_DATAEYE_RESULT_BIT;
+		}
+	}
+
+	for (i = 0; i < 4; i++) {
+		for (j = 0; j < 4; j++) {
+			unsigned int v = readl(REG_DQ_R_BDL_BASE + 0x1000 * i + j * 4);
+
+			result_r[i * 8 + j * 2] |= (v & 0xff) << DDR_DATAEYE_RESULT_BIT;
+			result_r[i * 8 + j * 2 + 1] |= (v >> 16 & 0xff) << DDR_DATAEYE_RESULT_BIT;
+		}
+	}
+
+	/* Restore function mode */
+	writel(0, REG_DQ_RES_SW);
+
+	best_w = result->phy[0].rank[0].ddrtr_data.write.ddr_bit_best;
+	best_r = result->phy[0].rank[0].ddrtr_data.read.ddr_bit_best;
+	for (i = 0; i < DDR_PHY_BIT_MAX; ++i) {
+		unsigned int res;
+		unsigned short max, min;
+
+		res = result_w[i];
+		min = res >> DDR_DATAEYE_RESULT_BIT;
+		max = (res & DDR_DATAEYE_RESULT_MASK) *  2 - min;
+		result_w[i] = (min << DDR_DATAEYE_RESULT_BIT) | max;
+		best_w[i] = (res & DDR_DATAEYE_RESULT_MASK) | ((max - min) << DDR_DATAEYE_RESULT_BIT);
+
+		res = result_r[i];
+		min = res >> DDR_DATAEYE_RESULT_BIT;
+		max = (res & DDR_DATAEYE_RESULT_MASK) *  2 - min;
+		result_r[i] = (min << DDR_DATAEYE_RESULT_BIT) | max;
+		best_r[i] = (res & DDR_DATAEYE_RESULT_MASK) | ((max - min) << DDR_DATAEYE_RESULT_BIT);
+
+	}
+
+	return 0;
+}
+
+void show_win_reg(void)
+{
+	int i;
+
+	printf("DDR DQ Win REGs\n");
+	printf("------------------------------------------------------\n");
+	printf("Avg BDL of Writing:\n");
+	writel(0x0, REG_DQ_RES_SW);
+	for (i = 0; i < 4; ++i) {
+		unsigned long addr = REG_DQ_W_BDL_BASE + 0x1000 * i;
+
+		print_buffer(addr, (void *)addr, 4, 4, 4);
+	}
+
+	printf("Min BDL of Writing:\n");
+	writel(0x1, REG_DQ_RES_SW);
+	for (i = 0; i < 4; ++i) {
+		unsigned long addr = REG_DQ_W_BDL_BASE + 0x1000 * i;
+
+		print_buffer(addr, (void *)addr, 4, 4, 4);
+	}
+
+	printf("Avg BDL of Reading:\n");
+	writel(0x0, REG_DQ_RES_SW);
+	for (i = 0; i < 4; ++i) {
+		unsigned long addr = REG_DQ_R_BDL_BASE + 0x1000 * i;
+
+		print_buffer(addr, (void *)addr, 4, 4, 4);
+	}
+
+	printf("Min BDL of Reading:\n");
+	writel(0x1, REG_DQ_RES_SW);
+	for (i = 0; i < 4; ++i) {
+		unsigned long addr = REG_DQ_R_BDL_BASE + 0x1000 * i;
+
+		print_buffer(addr, (void *)addr, 4, 4, 4);
+	}
+
+	writel(0x0, REG_DQ_RES_SW);
+}
+

source/bootloader/u-boot-2020.01/lotus/ddr/ddr_training_xmorca.c

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <command.h>
+#include <linux/io.h>
+#include "ddr_if.h"
+
+int get_result(struct ddr_training_result *result)
+{
+	return 0;
+}
+
+void show_win_reg(void)
+{
+}
+