GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,965 @@
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/*
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* Copyright (c) LOTUS. All rights reserved.
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*/
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#include "fmc100.h"
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#include <common.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <malloc.h>
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#include <linux/lotus/match_table.h>
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#include <asm/arch/platform.h>
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void fmc100_ecc0_switch(struct fmc_host* const host, unsigned char op)
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{
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unsigned int config;
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#if EC_DBG
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unsigned int cmp_cfg;
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config = fmc_read(host, FMC_CFG);
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fmc_pr(EC_DBG, "\t *-Get CFG[%#x]%#x\n", FMC_CFG, config);
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if (op)
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cmp_cfg = host->fmc_cfg;
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else
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cmp_cfg = host->fmc_cfg_ecc0;
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if (cmp_cfg != config)
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db_msg("Warning: FMC config[%#x] is different.\n",
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cmp_cfg);
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#endif
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if (op == ENABLE) {
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config = host->fmc_cfg_ecc0;
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} else if (op == DISABLE) {
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config = host->fmc_cfg;
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} else {
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db_msg("Error: Invalid opcode: %d\n", op);
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return;
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}
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fmc_write(host, FMC_CFG, config);
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fmc_pr(EC_DBG, "\t *-Set CFG[%#x]%#x\n", FMC_CFG, config);
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}
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static void set_dma_addr_reg(struct fmc_host *host)
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{
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unsigned int reg;
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reg = host->dma_buffer;
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fmc_write(host, FMC_DMA_SADDR_D0, reg);
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fmc_pr(DMA_DB, "\t|-Set DMA_SADDR_D0[%#x]%#x\n", FMC_DMA_SADDR_D0, reg);
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/* get hight 32 bits */
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reg = ((unsigned long)host->dma_buffer & FMC_DMA_SADDRH_MASK) >> 32;
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fmc_write(host, FMC_DMA_SADDRH_D0, reg);
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fmc_pr(DMA_DB, "\t|-Set DMA_SADDRH_D0[%#x]%#x\n", FMC_DMA_SADDRH_D0, reg);
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reg = host->dma_oob;
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fmc_write(host, FMC_DMA_SADDR_OOB, reg);
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fmc_pr(DMA_DB, "\t|-Set DMA_SADDR_OOB[%#x]%#x\n", FMC_DMA_SADDR_OOB,
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reg);
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/* get hight 32 bits */
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reg = ((unsigned long)host->dma_oob & FMC_DMA_SADDRH_MASK) >> 32;
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fmc_write(host, FMC_DMA_SADDRH_OOB, reg);
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fmc_pr(DMA_DB, "\t|-Set DMA_SADDRH_OOB[%#x]%#x\n", FMC_DMA_SADDRH_OOB,
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reg);
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}
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static void set_addr_reg(struct fmc_host *host)
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{
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unsigned int reg;
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struct nand_chip *chip = host->chip;
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unsigned char pages_per_block_shift;
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unsigned int block_num;
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unsigned int block_num_h;
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unsigned int page_num;
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pages_per_block_shift = chip->phys_erase_shift - chip->page_shift;
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block_num = host->addr_value[1] >> pages_per_block_shift;
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block_num_h = block_num >> REG_CNT_HIGH_BLOCK_NUM_SHIFT;
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reg = fmc_addrh_set(block_num_h);
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fmc_write(host, FMC_ADDRH, reg);
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fmc_pr(REG_DB, "|-Set ADDRH[%#x]%#x\n", FMC_ADDRH, reg);
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page_num = host->addr_value[1] - (block_num << pages_per_block_shift);
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reg = ((block_num & REG_CNT_BLOCK_NUM_MASK) << REG_CNT_BLOCK_NUM_SHIFT) |
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((page_num & REG_CNT_PAGE_NUM_MASK) << REG_CNT_PAGE_NUM_SHIFT);
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fmc_write(host, FMC_ADDRL, reg);
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fmc_pr(REG_DB, "|-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
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}
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/****************************************************************************/
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static void set_cs_addr_reg(enum OP op, struct fmc_host *host)
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{
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unsigned int reg;
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struct fmc_spi *spi = host->spi;
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unsigned char iftype = 0;
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unsigned char dummy = 0;
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reg = FMC_INT_CLR_ALL;
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fmc_write(host, FMC_INT_CLR, reg);
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fmc_pr(WR_DBG, "|-Set INT_CLR[%#x]%#x\n", FMC_INT_CLR, reg);
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if (op == READ) {
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iftype = spi->read->iftype;
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dummy = spi->read->dummy;
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} else if (op == WRITE) {
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iftype = spi->write->iftype;
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} else {
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iftype = spi->erase->iftype;
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}
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reg = op_cfg_fm_cs(host->cmd_op.cs) |
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OP_CFG_OEN_EN |
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op_cfg_mem_if_type(iftype) |
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op_cfg_dummy_num(dummy);
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fmc_write(host, FMC_OP_CFG, reg);
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fmc_pr(REG_DB, "|-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
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set_addr_reg(host);
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}
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static void pageprog_fmc_op(struct fmc_host* const host, struct fmc_spi* const spi)
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{
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unsigned int reg;
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reg = op_ctrl_wr_opcode(spi->write->cmd) | op_ctrl_dma_op(OP_TYPE_DMA) |
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op_ctrl_rw_op(RW_OP_WRITE) | OP_CTRL_DMA_OP_READY;
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fmc_write(host, FMC_OP_CTRL, reg);
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fmc_pr(WR_DBG, "|-Set OP_CTRL[%#x]%#x\n", FMC_OP_CTRL, reg);
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fmc_dma_wait_int_finish(host);
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}
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static void fmc100_send_cmd_pageprog(struct fmc_host *host)
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{
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struct fmc_spi *spi = host->spi;
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unsigned char *fmc_ip = NULL;
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int ret;
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#ifndef CONFIG_SYS_DCACHE_OFF
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unsigned int dma_align_len;
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#endif
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fmc_pr(WR_DBG, "\n*-Enter Dma page program!\n");
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fmc_ip = get_fmc_ip();
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if (*fmc_ip) {
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printf("Warning: FMC IP is busy, Please try again.\n");
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udelay(1); /* delay 1 us */
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return;
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} else {
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fmc_dev_type_switch(FLASH_TYPE_SPI_NAND);
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(*fmc_ip)++;
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}
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ret = spi->driver->write_enable(spi);
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if (ret) {
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db_msg("Error: Dma program write enable failed! ret: %#x\n", ret);
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goto end;
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}
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host->set_system_clock(spi->write, ENABLE);
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if (ecc0_flag == 1) {
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fmc100_ecc0_switch(host, ENABLE);
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fmc_write(host, FMC_DMA_LEN, host->oobsize);
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}
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set_cs_addr_reg(WRITE, host);
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if (ecc0_flag != 1)
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*host->epm = 0x0000;
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#ifndef CONFIG_SYS_DCACHE_OFF
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dma_align_len = ((host->pagesize + host->oobsize +
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CONFIG_SYS_CACHELINE_SIZE - 1) & ~(CONFIG_SYS_CACHELINE_SIZE - 1));
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flush_dcache_range(host->dma_buffer, host->dma_buffer + dma_align_len);
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#endif
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set_dma_addr_reg(host);
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pageprog_fmc_op(host, spi);
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if (ecc0_flag == 1)
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fmc100_ecc0_switch(host, DISABLE);
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ret = spi->driver->wait_ready(spi);
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if (ret)
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db_msg("Error: Dma program wait ready failed! status: %#x\n", ret);
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end:
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(*fmc_ip)--;
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fmc_pr(WR_DBG, "*-End Dma page program!\n");
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}
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static void fmc100_send_cmd_readstart(struct fmc_host *host)
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{
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unsigned int reg;
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struct fmc_spi *spi = host->spi;
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unsigned char *fmc_ip = NULL;
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#ifndef CONFIG_SYS_DCACHE_OFF
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unsigned int dma_align_len;
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#endif
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fmc_pr(RD_DBG, "\n\t*-Start Dma page read\n");
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fmc_ip = get_fmc_ip();
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if (*fmc_ip) {
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printf("Warning: FMC IP is busy, Please try again.\n");
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udelay(1); /* delay 1 us */
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return;
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} else {
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fmc_dev_type_switch(FLASH_TYPE_SPI_NAND);
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(*fmc_ip)++;
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}
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host->set_system_clock(spi->read, ENABLE);
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if (ecc0_flag == 1 && (host->cmd_op.l_cmd != NAND_CMD_READOOB)) {
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fmc100_ecc0_switch(host, ENABLE);
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fmc_write(host, FMC_DMA_LEN, host->oobsize);
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}
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if (host->cmd_op.l_cmd == NAND_CMD_READOOB)
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host->cmd_op.op_cfg = op_ctrl_rd_op_sel(RD_OP_READ_OOB);
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else
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host->cmd_op.op_cfg = op_ctrl_rd_op_sel(RD_OP_READ_ALL_PAGE);
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set_cs_addr_reg(READ, host);
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#ifndef CONFIG_SYS_DCACHE_OFF
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dma_align_len = ((host->pagesize + host->oobsize +
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CONFIG_SYS_CACHELINE_SIZE - 1) & ~(CONFIG_SYS_CACHELINE_SIZE - 1));
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invalidate_dcache_range(host->dma_buffer, host->dma_buffer + dma_align_len);
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#endif
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set_dma_addr_reg(host);
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reg = op_ctrl_rd_opcode(spi->read->cmd) |
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host->cmd_op.op_cfg | op_ctrl_dma_op(OP_TYPE_DMA) |
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op_ctrl_rw_op(RW_OP_READ) | OP_CTRL_DMA_OP_READY;
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fmc_write(host, FMC_OP_CTRL, reg);
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fmc_pr(RD_DBG, "\t|-Set OP_CTRL[%#x]%#x\n", FMC_OP_CTRL, reg);
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fmc_dma_wait_int_finish(host);
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if (ecc0_flag == 1 && (host->cmd_op.l_cmd != NAND_CMD_READOOB))
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fmc100_ecc0_switch(host, DISABLE);
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#ifndef CONFIG_SYS_DCACHE_OFF
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invalidate_dcache_range(host->dma_buffer, host->dma_buffer + dma_align_len);
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#endif
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(*fmc_ip)--;
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fmc_pr(RD_DBG, "\t*-End Dma page read\n");
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}
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static void erase_fmc_op(struct fmc_host* const host, struct fmc_spi* const spi)
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{
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unsigned int reg;
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reg = FMC_INT_CLR_ALL;
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fmc_write(host, FMC_INT_CLR, reg);
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fmc_pr(ER_DBG, "\t|-Set INT_CLR[%#x]%#x\n", FMC_INT_CLR, reg);
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reg = spi->erase->cmd;
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fmc_write(host, FMC_CMD, fmc_cmd_cmd1(reg));
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fmc_pr(ER_DBG, "\t|-Set CMD[%#x]%#x\n", FMC_CMD, reg);
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reg = fmc_addrl_block_h_mask(host->addr_value[1]) |
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fmc_addrl_block_l_mask(host->addr_value[0]);
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fmc_write(host, FMC_ADDRL, reg);
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fmc_pr(ER_DBG, "\t|-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
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reg = op_cfg_fm_cs(host->cmd_op.cs) | OP_CFG_OEN_EN |
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op_cfg_mem_if_type(spi->erase->iftype) |
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op_cfg_addr_num(STD_OP_ADDR_NUM) |
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op_cfg_dummy_num(spi->erase->dummy);
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fmc_write(host, FMC_OP_CFG, reg);
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fmc_pr(ER_DBG, "\t|-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
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reg = fmc_op_cmd1_en(ENABLE) | fmc_op_addr_en(ENABLE) |
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FMC_OP_REG_OP_START;
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fmc_write(host, FMC_OP, reg);
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fmc_pr(ER_DBG, "\t|-Set OP[%#x]%#x\n", FMC_OP, reg);
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fmc_cmd_wait_cpu_finish(host);
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}
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static void fmc100_send_cmd_erase(struct fmc_host *host)
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{
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struct fmc_spi *spi = host->spi;
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unsigned char *fmc_ip = NULL;
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int ret;
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if (ER_DBG)
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printf("\n");
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fmc_pr(ER_DBG, "\t*-Start send cmd erase!\n");
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fmc_ip = get_fmc_ip();
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if (*fmc_ip) {
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printf("Warning: FMC IP is busy, Please try again.\n");
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udelay(1); /* delay 1 us */
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return;
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} else {
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fmc_dev_type_switch(FLASH_TYPE_SPI_NAND);
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(*fmc_ip)++;
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}
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ret = spi->driver->write_enable(spi);
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if (ret) {
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db_msg("Error: Erase write enable failed! ret: %#x\n", ret);
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goto end;
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}
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host->set_system_clock(spi->erase, ENABLE);
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erase_fmc_op(host, spi);
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ret = spi->driver->wait_ready(spi);
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fmc_pr(ER_DBG, "\t|-Erase wait ready, ret: %#x\n", ret);
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if (ret)
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db_msg("Error: Erase wait ready fail! status: %#x\n", ret);
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end:
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(*fmc_ip)--;
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fmc_pr(ER_DBG, "\t*-End send cmd erase!\n");
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}
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static void fmc100_send_cmd_status(struct fmc_host* const host)
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{
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unsigned int status;
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unsigned char addr = STATUS_ADDR;
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struct fmc_spi *spi = host->spi;
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unsigned char *fmc_ip = get_fmc_ip();
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if (*fmc_ip) {
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printf("Warning: FMC IP is busy, Please try again.\n");
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udelay(1); /* delay 1 us */
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return;
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} else {
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fmc_dev_type_switch(FLASH_TYPE_SPI_NAND);
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(*fmc_ip)++;
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}
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if (host->cmd_op.l_cmd == NAND_CMD_GET_FEATURES)
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addr = PROTECT_ADDR;
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if (spi_nand_feature_op(spi, GET_OP, addr, &status)) {
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printf("get protect addr failed!\n");
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(*fmc_ip)--;
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return;
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}
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fmc_pr((ER_DBG || WR_DBG), "\t*-Get status[%#x]: %#x\n", addr, status);
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(*fmc_ip)--;
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}
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static void fmc100_send_cmd_readid(struct fmc_host *host)
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{
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unsigned int reg;
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fmc_pr(BT_DBG, "\t|*-Start send cmd read ID\n");
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fmc100_ecc0_switch(host, ENABLE);
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reg = fmc_cmd_cmd1(SPI_CMD_RDID);
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fmc_write(host, FMC_CMD, reg);
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fmc_pr(BT_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
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reg = READ_ID_ADDR;
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fmc_write(host, FMC_ADDRL, reg);
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fmc_pr(BT_DBG, "\t||-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
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reg = op_cfg_fm_cs(host->cmd_op.cs) | OP_CFG_OEN_EN |
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op_cfg_addr_num(READ_ID_ADDR_NUM);
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fmc_write(host, FMC_OP_CFG, reg);
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fmc_pr(BT_DBG, "\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
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reg = fmc_data_num_cnt(MAX_SPI_NAND_ID_LEN);
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fmc_write(host, FMC_DATA_NUM, reg);
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fmc_pr(BT_DBG, "\t||-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg);
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reg = fmc_op_cmd1_en(ENABLE) | fmc_op_addr_en(ENABLE) |
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fmc_op_read_data_en(ENABLE) | FMC_OP_REG_OP_START;
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fmc_write(host, FMC_OP, reg);
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fmc_pr(BT_DBG, "\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
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host->addr_cycle = 0x0;
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fmc_cmd_wait_cpu_finish(host);
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fmc100_ecc0_switch(host, DISABLE);
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fmc_pr(BT_DBG, "\t|*-End read flash ID\n");
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}
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static void fmc100_send_cmd_reset(struct fmc_host* const host)
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{
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unsigned int reg;
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fmc_pr(BT_DBG, "\t|*-Start send cmd reset\n");
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reg = fmc_cmd_cmd1(SPI_CMD_RESET);
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fmc_write(host, FMC_CMD, reg);
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fmc_pr(BT_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
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reg = op_cfg_fm_cs(host->cmd_op.cs) | OP_CFG_OEN_EN;
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fmc_write(host, FMC_OP_CFG, reg);
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fmc_pr(BT_DBG, "\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
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reg = fmc_op_cmd1_en(ENABLE) | FMC_OP_REG_OP_START;
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fmc_write(host, FMC_OP, reg);
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fmc_pr(BT_DBG, "\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
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||||
|
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fmc_cmd_wait_cpu_finish(host);
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||||
|
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fmc_pr(BT_DBG, "\t|*-End send cmd reset\n");
|
||||
}
|
||||
|
||||
static unsigned char fmc100_read_byte(struct mtd_info* const mtd)
|
||||
{
|
||||
struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
struct fmc_host *host = chip->priv;
|
||||
unsigned char value;
|
||||
unsigned char ret_val = 0;
|
||||
|
||||
if (host->cmd_op.l_cmd == NAND_CMD_READID) {
|
||||
value = readb(host->iobase + host->offset);
|
||||
host->offset++;
|
||||
if (host->cmd_op.data_no == host->offset)
|
||||
host->cmd_op.l_cmd = 0;
|
||||
return value;
|
||||
}
|
||||
|
||||
if (host->cmd_op.cmd == NAND_CMD_STATUS) {
|
||||
value = fmc_read(host, FMC_STATUS);
|
||||
if (host->cmd_op.l_cmd == NAND_CMD_GET_FEATURES) {
|
||||
fmc_pr((ER_DBG || WR_DBG), "\t\tRead BP status: %#x\n",
|
||||
value);
|
||||
if (any_bp_enable(value))
|
||||
ret_val |= NAND_STATUS_WP;
|
||||
|
||||
host->cmd_op.l_cmd = NAND_CMD_STATUS;
|
||||
}
|
||||
|
||||
if (!(value & STATUS_OIP_MASK))
|
||||
ret_val |= NAND_STATUS_READY;
|
||||
|
||||
if ((chip->state == FL_ERASING) &&
|
||||
(value & STATUS_E_FAIL_MASK)) {
|
||||
fmc_pr(ER_DBG, "\t\tGet erase status: %#x\n", value);
|
||||
ret_val |= NAND_STATUS_FAIL;
|
||||
}
|
||||
|
||||
if ((chip->state == FL_WRITING) &&
|
||||
(value & STATUS_P_FAIL_MASK)) {
|
||||
fmc_pr(WR_DBG, "\t\tGet write status: %#x\n", value);
|
||||
ret_val |= NAND_STATUS_FAIL;
|
||||
}
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
if (host->cmd_op.l_cmd == NAND_CMD_READOOB) {
|
||||
value = readb((unsigned char *)
|
||||
((unsigned char *)(uintptr_t)host->dma_oob + host->offset));
|
||||
host->offset++;
|
||||
return value;
|
||||
}
|
||||
|
||||
host->offset++;
|
||||
|
||||
return readb(host->buffer + host->column + host->offset - 1);
|
||||
}
|
||||
|
||||
static unsigned short fmc100_read_word(struct mtd_info *mtd)
|
||||
{
|
||||
struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
struct fmc_host *host = chip->priv;
|
||||
|
||||
return readw(host->buffer + host->column + host->offset);
|
||||
}
|
||||
|
||||
static void fmc100_write_buf(struct mtd_info* const mtd, const u_char* const buf, int len)
|
||||
{
|
||||
struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
struct fmc_host *host = chip->priv;
|
||||
|
||||
if (buf == chip->oob_poi)
|
||||
memcpy((unsigned char *)(uintptr_t)host->dma_oob, buf, len);
|
||||
else
|
||||
memcpy((unsigned char *)(uintptr_t)host->dma_buffer, buf, len);
|
||||
return;
|
||||
}
|
||||
|
||||
static void fmc100_read_buf(struct mtd_info* const mtd, u_char* const buf, int len)
|
||||
{
|
||||
struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
struct fmc_host *host = chip->priv;
|
||||
|
||||
if (buf == chip->oob_poi)
|
||||
memcpy(buf, (unsigned char *)(uintptr_t)host->dma_oob, len);
|
||||
else
|
||||
memcpy(buf, (unsigned char *)(uintptr_t)host->dma_buffer, len);
|
||||
return;
|
||||
}
|
||||
|
||||
static void fmc100_select_chip(struct mtd_info* const mtd, int chipselect)
|
||||
{
|
||||
struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
struct fmc_host *host = chip->priv;
|
||||
|
||||
if (chipselect < 0)
|
||||
return;
|
||||
|
||||
if (chipselect > CONFIG_SPI_NAND_MAX_CHIP_NUM)
|
||||
db_bug("Error: Invalid chipselect: %d\n", chipselect);
|
||||
|
||||
if (host->mtd != mtd)
|
||||
host->mtd = mtd;
|
||||
|
||||
if (!(chip->options & NAND_BROKEN_XD))
|
||||
if ((chip->state == FL_ERASING) || (chip->state == FL_WRITING))
|
||||
host->cmd_op.l_cmd = NAND_CMD_GET_FEATURES;
|
||||
}
|
||||
|
||||
static void read_nand_id_op(struct fmc_host *host, unsigned int command)
|
||||
{
|
||||
host->offset = 0;
|
||||
host->cmd_op.l_cmd = command & 0xff;
|
||||
memset((u_char *)(host->iobase), 0, MAX_SPI_NAND_ID_LEN);
|
||||
host->cmd_op.data_no = MAX_SPI_NAND_ID_LEN;
|
||||
host->send_cmd_readid(host);
|
||||
}
|
||||
|
||||
static void fmc100_cmdfunc(struct mtd_info* const mtd,
|
||||
unsigned int command,
|
||||
int column, int page_addr)
|
||||
{
|
||||
struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
struct fmc_host *host = chip->priv;
|
||||
|
||||
switch (command) {
|
||||
case NAND_CMD_RESET:
|
||||
host->send_cmd_reset(host);
|
||||
chip->dev_ready(mtd);
|
||||
break;
|
||||
case NAND_CMD_READID:
|
||||
read_nand_id_op(host, command);
|
||||
break;
|
||||
case NAND_CMD_GET_FEATURES:
|
||||
case NAND_CMD_STATUS:
|
||||
host->cmd_op.l_cmd = command & 0xff;
|
||||
host->cmd_op.cmd = NAND_CMD_STATUS;
|
||||
host->send_cmd_status(host);
|
||||
break;
|
||||
case NAND_CMD_READOOB:
|
||||
host->offset = 0;
|
||||
host->cmd_op.l_cmd = command & 0xff;
|
||||
/* use same command as normal read */
|
||||
host->cmd_op.cmd = command & 0xff;
|
||||
case NAND_CMD_READ0:
|
||||
if (command == NAND_CMD_READ0)
|
||||
host->cmd_op.l_cmd = command & 0xff;
|
||||
host->addr_value[1] = page_addr;
|
||||
host->send_cmd_readstart(host);
|
||||
break;
|
||||
case NAND_CMD_SEQIN:
|
||||
host->addr_value[1] = page_addr;
|
||||
break;
|
||||
case NAND_CMD_PAGEPROG:
|
||||
host->offset = 0;
|
||||
host->send_cmd_pageprog(host);
|
||||
break;
|
||||
case NAND_CMD_ERASE1:
|
||||
host->cmd_op.l_cmd = command & 0xff;
|
||||
host->addr_value[0] = page_addr;
|
||||
/* page_addr to block_addr, move right 16 bits */
|
||||
host->addr_value[1] = (unsigned int)page_addr >> 16;
|
||||
/* erase operation need a seral of command sequences */
|
||||
host->send_cmd_erase(host);
|
||||
break;
|
||||
case NAND_CMD_ERASE2:
|
||||
case NAND_CMD_READSTART:
|
||||
break;
|
||||
default:
|
||||
printf("%s not support command 0x%08x:\n", mtd->name, command);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int fmc100_dev_ready(struct mtd_info* const mtd)
|
||||
{
|
||||
unsigned int reg;
|
||||
/* just a big number, so move 12 bits */
|
||||
unsigned long deadline = 1 << 12;
|
||||
struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
struct fmc_host *host = chip->priv;
|
||||
|
||||
do {
|
||||
reg = op_cfg_fm_cs(host->cmd_op.cs) | OP_CFG_OEN_EN;
|
||||
fmc_write(host, FMC_OP_CFG, reg);
|
||||
|
||||
reg = fmc_op_read_status_en(ENABLE) | FMC_OP_REG_OP_START;
|
||||
fmc_write(host, FMC_OP, reg);
|
||||
|
||||
fmc_cmd_wait_cpu_finish(host);
|
||||
|
||||
reg = fmc_read(host, FMC_STATUS);
|
||||
if (!(reg & STATUS_OIP_MASK))
|
||||
return 1;
|
||||
|
||||
udelay(1); /* delay 1 us */
|
||||
} while (deadline--);
|
||||
|
||||
#ifndef CONFIG_SYS_NAND_QUIET_TEST
|
||||
printf("Warning: Wait SPI nand ready timeout, status: %#x\n", reg);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* 'host->epm' only use the first oobfree[0] field, it looks very simple, But..
|
||||
*/
|
||||
static struct nand_ecclayout nand_ecc_default = {
|
||||
.oobfree = {{2, 30} }
|
||||
};
|
||||
|
||||
#ifdef CONFIG_FS_MAY_NOT_YAFFS2
|
||||
static struct nand_ecclayout nand_ecc_2k16bit = {
|
||||
.oobfree = {{2, 6} }
|
||||
};
|
||||
|
||||
static struct nand_ecclayout nand_ecc_4k16bit = {
|
||||
.oobfree = {{2, 14} }
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct nand_config_info fmc_spi_nand_config_table[] = {
|
||||
{NAND_PAGE_4K, NAND_ECC_24BIT, 200, &nand_ecc_default},
|
||||
#ifdef CONFIG_FS_MAY_NOT_YAFFS2
|
||||
{NAND_PAGE_4K, NAND_ECC_16BIT, 128, &nand_ecc_4k16bit},
|
||||
#endif
|
||||
{NAND_PAGE_4K, NAND_ECC_8BIT, 128, &nand_ecc_default},
|
||||
{NAND_PAGE_4K, NAND_ECC_0BIT, 32, &nand_ecc_default},
|
||||
|
||||
{NAND_PAGE_2K, NAND_ECC_24BIT, 128, &nand_ecc_default},
|
||||
#ifdef CONFIG_FS_MAY_NOT_YAFFS2
|
||||
{NAND_PAGE_2K, NAND_ECC_16BIT, 64, &nand_ecc_2k16bit},
|
||||
#endif
|
||||
{NAND_PAGE_2K, NAND_ECC_8BIT, 64, &nand_ecc_default},
|
||||
{NAND_PAGE_2K, NAND_ECC_0BIT, 32, &nand_ecc_default},
|
||||
|
||||
{0, 0, 0, NULL},
|
||||
};
|
||||
|
||||
/*
|
||||
* Auto-sensed the page size and ecc type value. driver will try each of page
|
||||
* size and ecc type one by one till flash can be read and wrote accurately.
|
||||
* so the page size and ecc type is match adaptively without switch on the board
|
||||
*/
|
||||
static struct nand_config_info *fmc100_get_config_type_info(struct mtd_info *mtd)
|
||||
{
|
||||
struct nand_config_info *best = NULL;
|
||||
struct nand_config_info *info = fmc_spi_nand_config_table;
|
||||
struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
for (; info->layout; info++) {
|
||||
if (match_page_type_to_size(info->pagetype) != mtd->writesize)
|
||||
continue;
|
||||
|
||||
if (mtd->oobsize < info->oobsize)
|
||||
continue;
|
||||
|
||||
if (!best || (best->ecctype < info->ecctype))
|
||||
best = info;
|
||||
}
|
||||
/* All SPI NAND are small-page,SLC */
|
||||
chip->bits_per_cell = 1;
|
||||
return best;
|
||||
}
|
||||
|
||||
static void fmc100_set_oob_info(struct mtd_info* const mtd,
|
||||
struct nand_config_info* const info)
|
||||
{
|
||||
struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
struct fmc_host *host = chip->priv;
|
||||
|
||||
if (info->ecctype != NAND_ECC_0BIT)
|
||||
mtd->oobsize = info->oobsize;
|
||||
|
||||
host->oobsize = mtd->oobsize;
|
||||
host->dma_oob = host->dma_buffer + host->pagesize;
|
||||
host->bbm = (u_char *)(host->buffer + host->pagesize +
|
||||
FMC_BAD_BLOCK_POS);
|
||||
|
||||
chip->ecc.layout = info->layout;
|
||||
|
||||
/* EB bytes locate in the bottom two of CTRL(30) */
|
||||
host->epm = (u_short *)(host->buffer + host->pagesize +
|
||||
chip->ecc.layout->oobfree[0].offset + EB_NORMAL);
|
||||
|
||||
#ifdef CONFIG_FS_MAY_NOT_YAFFS2
|
||||
|
||||
if (info->ecctype == NAND_ECC_16BIT) {
|
||||
if (host->pagesize == _2K)
|
||||
/* EB bits locate in the bottom two of CTRL(6) */
|
||||
host->epm = (u_short *)(host->buffer + host->pagesize +
|
||||
chip->ecc.layout->oobfree[0].offset + EB_2K_16_BIT);
|
||||
else if (host->pagesize == _4K)
|
||||
/* EB bit locate in the bottom two of CTRL(14) */
|
||||
host->epm = (u_short *)(host->buffer + host->pagesize +
|
||||
chip->ecc.layout->oobfree[0].offset + EB_4K_16_BIT);
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
static unsigned int fmc100_get_ecc_reg(struct fmc_host* const host,
|
||||
struct nand_config_info* const info)
|
||||
{
|
||||
host->ecctype = info->ecctype;
|
||||
|
||||
return fmc_cfg_ecc_type(match_ecc_type_to_reg(info->ecctype));
|
||||
}
|
||||
|
||||
static unsigned int fmc100_get_page_reg(struct fmc_host* const host,
|
||||
struct nand_config_info* const info)
|
||||
{
|
||||
host->pagesize = match_page_type_to_size(info->pagetype);
|
||||
|
||||
return fmc_cfg_page_size(match_page_type_to_reg(info->pagetype));
|
||||
}
|
||||
|
||||
static int fmc100_get_block_reg(struct fmc_host* const host,
|
||||
struct nand_config_info* const info, unsigned int* const block_val)
|
||||
{
|
||||
unsigned int block_reg = 0;
|
||||
unsigned int page_per_block;
|
||||
struct mtd_info *mtd = NULL;
|
||||
|
||||
if (info == NULL || host == NULL || host->mtd == NULL) {
|
||||
printf("para err!\n");
|
||||
return -1;
|
||||
}
|
||||
mtd = host->mtd;
|
||||
host->block_page_mask = ((mtd->erasesize / mtd->writesize) - 1);
|
||||
page_per_block = mtd->erasesize / match_page_type_to_size(info->pagetype);
|
||||
switch (page_per_block) {
|
||||
case _64_PAGES:
|
||||
block_reg = BLOCK_SIZE_64_PAGE;
|
||||
break;
|
||||
case _128_PAGES:
|
||||
block_reg = BLOCK_SIZE_128_PAGE;
|
||||
break;
|
||||
case _256_PAGES:
|
||||
block_reg = BLOCK_SIZE_256_PAGE;
|
||||
break;
|
||||
case _512_PAGES:
|
||||
block_reg = BLOCK_SIZE_512_PAGE;
|
||||
break;
|
||||
default:
|
||||
db_msg("Can't support block %#x and page %#x size\n",
|
||||
mtd->erasesize, mtd->writesize);
|
||||
}
|
||||
*block_val = fmc_cfg_block_size(block_reg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void fmc100_set_fmc_cfg_reg(struct mtd_info* const mtd,
|
||||
struct nand_config_info* const type_info)
|
||||
{
|
||||
struct nand_chip *chip = NULL;
|
||||
struct fmc_host *host = NULL;
|
||||
unsigned int page_reg;
|
||||
unsigned int ecc_reg;
|
||||
unsigned int block_reg;
|
||||
unsigned int reg_fmc_cfg;
|
||||
if (mtd == NULL || type_info == NULL)
|
||||
return;
|
||||
chip = mtd_to_nand(mtd);
|
||||
if (chip == NULL || chip->priv == NULL)
|
||||
return;
|
||||
host = chip->priv;
|
||||
ecc_reg = fmc100_get_ecc_reg(host, type_info);
|
||||
page_reg = fmc100_get_page_reg(host, type_info);
|
||||
if (fmc100_get_block_reg(host, type_info, &block_reg))
|
||||
return;
|
||||
|
||||
reg_fmc_cfg = fmc_read(host, FMC_CFG);
|
||||
reg_fmc_cfg &= ~(PAGE_SIZE_MASK | ECC_TYPE_MASK | BLOCK_SIZE_MASK);
|
||||
reg_fmc_cfg |= ecc_reg | page_reg | block_reg;
|
||||
fmc_write(host, FMC_CFG, reg_fmc_cfg);
|
||||
|
||||
/* max number of correctible bit errors per ecc step */
|
||||
mtd->ecc_strength = host->ecctype;
|
||||
|
||||
/* Save value of FMC_CFG and FMC_CFG_ECC0 to turn on/off ECC */
|
||||
host->fmc_cfg = reg_fmc_cfg;
|
||||
host->fmc_cfg_ecc0 = (host->fmc_cfg & ~ECC_TYPE_MASK) | ECC_TYPE_0BIT;
|
||||
fmc_pr(BT_DBG, "\t|-Save FMC_CFG[%#x]: %#x and FMC_CFG_ECC0: %#x\n",
|
||||
FMC_CFG, host->fmc_cfg, host->fmc_cfg_ecc0);
|
||||
}
|
||||
|
||||
static int fmc100_set_config_info(struct mtd_info* const mtd)
|
||||
{
|
||||
struct nand_config_info *type_info = NULL;
|
||||
|
||||
fmc_pr(BT_DBG, "\t*-Start match PageSize and EccType\n");
|
||||
|
||||
type_info = fmc100_get_config_type_info(mtd);
|
||||
if (!type_info)
|
||||
db_bug(ERR_STR_DRIVER "pagesize: %d and oobsize: %d.\n",
|
||||
mtd->writesize, mtd->oobsize);
|
||||
|
||||
/* Set the page_size, ecc_type, block_size of FMC_CFG[0x0] register */
|
||||
fmc100_set_fmc_cfg_reg(mtd, type_info);
|
||||
|
||||
fmc_pr(BT_DBG, "\t|- PageSize %s EccType %s OOB Size %d\n",
|
||||
nand_page_name(type_info->pagetype),
|
||||
nand_ecc_name(type_info->ecctype), type_info->oobsize);
|
||||
|
||||
fmc100_set_oob_info(mtd, type_info);
|
||||
|
||||
fmc_pr(BT_DBG, "\t*-End match PageSize and EccType\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void fmc100_chip_init(struct nand_chip* const chip)
|
||||
{
|
||||
if (!chip->IO_ADDR_R)
|
||||
chip->IO_ADDR_R = (void __iomem *)CONFIG_FMC_BUFFER_BASE;
|
||||
chip->IO_ADDR_W = chip->IO_ADDR_R;
|
||||
memset((char *)chip->IO_ADDR_R, 0xff, FMC100_BUFFER_LEN);
|
||||
|
||||
chip->read_byte = fmc100_read_byte;
|
||||
chip->read_word = fmc100_read_word;
|
||||
chip->write_buf = fmc100_write_buf;
|
||||
chip->read_buf = fmc100_read_buf;
|
||||
|
||||
chip->select_chip = fmc100_select_chip;
|
||||
|
||||
chip->cmdfunc = fmc100_cmdfunc;
|
||||
chip->dev_ready = fmc100_dev_ready;
|
||||
|
||||
chip->chip_delay = FMC_CHIP_DELAY;
|
||||
|
||||
chip->options = NAND_BBT_SCANNED | NAND_BROKEN_XD;
|
||||
|
||||
chip->ecc.layout = NULL;
|
||||
chip->ecc.mode = NAND_ECC_NONE;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
int host_data_init(struct fmc_host *host)
|
||||
{
|
||||
unsigned long align_mask;
|
||||
|
||||
host->addr_cycle = 0;
|
||||
host->addr_value[0] = 0;
|
||||
host->addr_value[1] = 0;
|
||||
host->cache_addr_value[0] = ~0;
|
||||
host->cache_addr_value[1] = ~0;
|
||||
|
||||
fmc_pr(BT_DBG, "\t|||-Malloc memory for dma buffer\n");
|
||||
host->buforg = kmalloc((FMC100_BUFFER_LEN + FMC_DMA_ALIGN),
|
||||
GFP_KERNEL);
|
||||
if (!host->buforg) {
|
||||
db_msg("Error: Can't malloc memory for SPI Nand driver.\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
memset(host->buforg, 0xff, FMC100_BUFFER_LEN + FMC_DMA_ALIGN);
|
||||
|
||||
/* DMA need 32 bytes alignment */
|
||||
align_mask = FMC_DMA_ALIGN - 1;
|
||||
host->dma_buffer = (uintptr_t)(host->buforg + align_mask) & ~align_mask;
|
||||
|
||||
host->buffer = (char *)(uintptr_t)host->dma_buffer;
|
||||
memset(host->buffer, 0xff, FMC100_BUFFER_LEN);
|
||||
|
||||
host->send_cmd_pageprog = fmc100_send_cmd_pageprog;
|
||||
host->send_cmd_status = fmc100_send_cmd_status;
|
||||
host->send_cmd_readstart = fmc100_send_cmd_readstart;
|
||||
host->send_cmd_erase = fmc100_send_cmd_erase;
|
||||
host->send_cmd_readid = fmc100_send_cmd_readid;
|
||||
host->send_cmd_reset = fmc100_send_cmd_reset;
|
||||
host->set_system_clock = fmc_set_fmc_system_clock;
|
||||
|
||||
return 0;
|
||||
}
|
||||
/*****************************************************************************/
|
||||
int fmc100_host_init(struct fmc_host *host)
|
||||
{
|
||||
unsigned int reg;
|
||||
unsigned int flash_type;
|
||||
int ret;
|
||||
|
||||
if (!host)
|
||||
return -1;
|
||||
fmc_pr(BT_DBG, "\t||*-Start SPI Nand host init\n");
|
||||
host->iobase = (void __iomem *)CONFIG_FMC_BUFFER_BASE;
|
||||
host->regbase = (void __iomem *)CONFIG_FMC_REG_BASE;
|
||||
if (!host->iobase || !host->regbase)
|
||||
return -1;
|
||||
reg = fmc_read(host, FMC_CFG);
|
||||
flash_type = (reg & FLASH_SEL_MASK) >> FLASH_SEL_SHIFT;
|
||||
if (flash_type != FLASH_TYPE_SPI_NAND) {
|
||||
db_msg("Error: Flash type isn't SPI Nand. reg: %#x\n", reg);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if ((reg & OP_MODE_MASK) == OP_MODE_BOOT) {
|
||||
reg |= fmc_cfg_op_mode(OP_MODE_NORMAL);
|
||||
fmc_write(host, FMC_CFG, reg);
|
||||
fmc_pr(BT_DBG, "\t|||-Set CFG[%#x]%#x\n", FMC_CFG, reg);
|
||||
}
|
||||
|
||||
host->fmc_cfg = reg;
|
||||
host->fmc_cfg_ecc0 = (reg & ~ECC_TYPE_MASK) | ECC_TYPE_0BIT;
|
||||
|
||||
reg = fmc_read(host, FMC_GLOBAL_CFG);
|
||||
if (reg & FMC_GLOBAL_CFG_WP_ENABLE) {
|
||||
reg &= ~FMC_GLOBAL_CFG_WP_ENABLE;
|
||||
fmc_write(host, FMC_GLOBAL_CFG, reg);
|
||||
}
|
||||
|
||||
ret = host_data_init(host);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* ecc0_flag for ecc0 read/write */
|
||||
ecc0_flag = 0;
|
||||
|
||||
reg = timing_cfg_tcsh(CS_HOLD_TIME) |
|
||||
timing_cfg_tcss(CS_SETUP_TIME) |
|
||||
timing_cfg_tshsl(CS_DESELECT_TIME);
|
||||
fmc_write(host, FMC_SPI_TIMING_CFG, reg);
|
||||
fmc_pr(BT_DBG, "\t|||-Set TIMING[%#x]%#x\n", FMC_SPI_TIMING_CFG, reg);
|
||||
|
||||
reg = ALL_BURST_ENABLE;
|
||||
fmc_write(host, FMC_DMA_AHB_CTRL, reg);
|
||||
fmc_pr(BT_DBG, "\t|||-Set DMA_AHB[%#x]%#x\n", FMC_DMA_AHB_CTRL, reg);
|
||||
|
||||
fmc_pr(BT_DBG, "\t|||-Register SPI Nand ID table and ecc probe\n");
|
||||
fmc_spi_nand_ids_register();
|
||||
nand_oob_resize = fmc100_set_config_info;
|
||||
|
||||
fmc_pr(BT_DBG, "\t||*-End SPI Nand host init\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
void fmc100_spi_nand_init(struct fmc_host *host)
|
||||
{
|
||||
struct nand_chip *chip = host->chip;
|
||||
|
||||
fmc_pr(BT_DBG, "\t|*-Start fmc100 SPI Nand init\n");
|
||||
|
||||
/* Set system clock and enable controller */
|
||||
fmc_pr(BT_DBG, "\t||-Set system clock and Enable Controller\n");
|
||||
if (host->set_system_clock)
|
||||
host->set_system_clock(NULL, ENABLE);
|
||||
|
||||
/* Fmc nand_chip struct init */
|
||||
fmc_pr(BT_DBG, "\t||-fmc100 struct nand_chip init\n");
|
||||
chip->priv = host;
|
||||
fmc100_chip_init(chip);
|
||||
|
||||
fmc_pr(BT_DBG, "\t|*-End fmc100 SPI Nand init\n");
|
||||
}
|
||||
Reference in New Issue
Block a user