GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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// SPDX-License-Identifier: GPL-2.0+
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#include <common.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <phy.h>
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#define MIIM_EPHY_SUB_CFG 0x12
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#define MIIM_EPHY_SUB_WDATA 0x13
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#define MIIM_EPHY_SUB_RDATA 0x14
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#define EPHY_TRIM_REG_BASE (0x12020000 + 0x8a2c)
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typedef union { /* FEPHY TRIM */
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uint32_t all;
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struct {
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uint32_t efuse_tx_100_fs :4;
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uint32_t efuse_tx_10_outr :4;
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uint32_t efuse_tx_10_fs :4;
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uint32_t efuse_rcal_code_rt :4;
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uint32_t reserved :16;
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} bitc;
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} EPHY_TRIM_REG;
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static int ephy_phy_extread(struct phy_device *phydev, int addr,
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int devaddr, int regnum)
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{
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int val;
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int sub_cfg;
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sub_cfg = (0<<15) | (devaddr << 8) | (regnum << 0);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_EPHY_SUB_CFG, sub_cfg);
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val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_EPHY_SUB_RDATA);
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return val;
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}
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static int ephy_phy_extwrite(struct phy_device *phydev, int addr,
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int devaddr, int regnum, u16 val)
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{
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int sub_cfg;
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_EPHY_SUB_WDATA, val);
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sub_cfg = (1<<15) | (devaddr << 8) | (regnum << 0);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_EPHY_SUB_CFG, sub_cfg);
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return 0;
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}
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static int ephy_config(struct phy_device *phydev)
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{
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unsigned int reg;
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EPHY_TRIM_REG ephy_trim_reg;
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/* Set green LED for Link, yellow LED for Active */
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//set LED to 0 (page 25 reg 0 3:2:0)
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reg = phydev->drv->readext(phydev, 0, 0x19, 0x00);
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reg &= ~(0x07);
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reg |= 0x03;
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phydev->drv->writeext(phydev, 0, 0x19, 0x00, reg);
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/* Set RG_EPHY_TX_100_LPF fix 4 to Improve the waveform */
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//set RG_EPHY_TX_100_LPF(page 0 reg 33 7:4)
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reg = phydev->drv->readext(phydev, 0, 0x0, 0x21);
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reg &= ~(0xf0);
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reg |= 0x40;
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phydev->drv->writeext(phydev, 0, 0x0, 0x21, reg);
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//page 12 reg 4
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phydev->drv->writeext(phydev, 0, 0x0c, 0x4, 0x10);
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ephy_trim_reg.all = readl(EPHY_TRIM_REG_BASE);
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if (!ephy_trim_reg.all) {
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ephy_trim_reg.bitc.efuse_tx_10_outr = 0;
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ephy_trim_reg.bitc.efuse_tx_10_fs = 0;
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ephy_trim_reg.bitc.efuse_tx_100_fs = 4;
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ephy_trim_reg.bitc.efuse_rcal_code_rt = 8;
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}
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pr_info("trim_reg:0x%x\n", ephy_trim_reg.all);
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pr_info("tx_100_fs:0x%x tx_10_outr:0x%x\n", ephy_trim_reg.bitc.efuse_tx_100_fs, ephy_trim_reg.bitc.efuse_tx_10_outr);
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pr_info("tx_10_fs:0x%x rcal_code:0x%x\n", ephy_trim_reg.bitc.efuse_tx_10_fs, ephy_trim_reg.bitc.efuse_rcal_code_rt);
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if (ephy_trim_reg.all) {
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//set EPHY_TX_10_OUTR to 0 (page 0 reg 9 11:8)
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reg = phydev->drv->readext(phydev, 0, 0, 0x09);
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reg &= ~(0xf << 8);
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reg |= (ephy_trim_reg.bitc.efuse_tx_10_outr << 8);
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phydev->drv->writeext(phydev, 0, 0, 0x09, reg);
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//set EPHY_TX_10_FS to 0 (page 0 reg 9 7:4)
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reg = phydev->drv->readext(phydev, 0, 0, 0x09);
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reg &= ~(0xf << 4);
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reg |= (ephy_trim_reg.bitc.efuse_tx_10_fs << 4);
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phydev->drv->writeext(phydev, 0, 0, 0x09, reg);
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//set EPHY_TX_100_FS to 4 (page 0 reg 33 3:0)
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reg = phydev->drv->readext(phydev, 0, 0, 0x21);
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reg &= ~(0xf << 0);
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reg |= (ephy_trim_reg.bitc.efuse_tx_100_fs << 0);
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phydev->drv->writeext(phydev, 0, 0, 0x21, reg);
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// set EPHY_RCAL_CODE_FT to 8 (page 0 reg 34 7:4)
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reg = phydev->drv->readext(phydev, 0, 0, 0x22);
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reg &= ~(0xf << 4);
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reg |= (ephy_trim_reg.bitc.efuse_rcal_code_rt << 4);
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phydev->drv->writeext(phydev, 0, 0, 0x22, reg);
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}
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genphy_config_aneg(phydev);
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return 0;
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}
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static int ephy_aneg_done(struct phy_device *phydev)
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{
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unsigned int reg;
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reg = phydev->drv->readext(phydev, 0, 0x11, 0x20);
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pr_info("[EPHY]:0x%x\n", reg);
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return 1;
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}
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/* Support for ePHY PHY */
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static struct phy_driver ephy_driver = {
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.name = "ePHY",
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.uid = 0x0243991f,
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.mask = 0xffffffff,
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.features = PHY_BASIC_FEATURES,
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.config = &ephy_config,
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.startup = &genphy_startup,
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.shutdown = &genphy_shutdown,
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.readext = &ephy_phy_extread,
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.writeext = &ephy_phy_extwrite,
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.aneg_done = &ephy_aneg_done,
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};
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int phy_ephy_init(void)
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{
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phy_register(&ephy_driver);
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return 0;
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}
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