GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1 @@
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obj-y += hw_decompress.o
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@@ -0,0 +1,5 @@
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/*
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* Copyright (c) LOTUS. All rights reserved.
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*/
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#include "hw_decompress_v1.c"
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@@ -0,0 +1,330 @@
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/*
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* Copyright (c) LOTUS. All rights reserved.
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*/
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#include "hw_decompress_v1.h"
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#include <linux/lotus/hw_decompress.h>
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#include <asm/io.h>
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#ifndef error
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#define error(fmt, args...) do { \
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printf("ERROR: " pr_fmt(fmt) "\nat %s:%d/%s()\n", \
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##args, __FILE__, __LINE__, __func__); \
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} while (0)
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#include <common.h>
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#endif
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#include <compiler.h>
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#if (defined CONFIG_TARGET_XMFALCON)
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#include "hw_decompress_xmfalcon.c"
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#elif (defined CONFIG_TARGET_XMORCA)
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#include "hw_decompress_xmorca.c"
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#endif
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unsigned int hw_dec_type;
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unsigned int hw_dec_sop;
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unsigned int hw_dec_eop;
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unsigned int hw_dec_cur_blk;
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unsigned int hw_blk_total_num;
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void hw_dec_sop_eop_first_set(int block_num)
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{
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if (block_num == 1) {
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hw_dec_sop = 1;
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hw_dec_eop = 1;
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} else {
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hw_dec_sop = 1;
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hw_dec_eop = 0;
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}
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hw_dec_cur_blk = 0;
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hw_blk_total_num = block_num;
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}
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static inline void hw_dec_work_en_set(int work_en_flg)
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{
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/* Enable the emar */
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writel(work_en_flg, HW_DEC_REG_BASE_ADDR + EAMR_WORK_EN_REG_OFST);
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}
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static inline void hw_dec_rtn_baddr_set(unsigned int addr)
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{
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writel(addr, HW_DEC_REG_BASE_ADDR + DPRS_DATA_RTN_BADDR);
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}
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static inline void hw_dec_dprs_data_baddr_set(unsigned int addr)
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{
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writel(addr, HW_DEC_REG_BASE_ADDR + DPRS_DATA_INFO_BADDR);
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}
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static inline void hw_dec_data_rtn_len_set(unsigned int len)
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{
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writel(len, HW_DEC_REG_BASE_ADDR + DPRS_DATA_RTN_LEN);
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}
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static inline void hw_dec_dprs_data_len_set(unsigned int len)
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{
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writel(len, HW_DEC_REG_BASE_ADDR + DPRS_DATA_INFO_LEN);
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}
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static inline void hw_dec_crc_check_en(unsigned int crc_en)
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{
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writel(crc_en, HW_DEC_REG_BASE_ADDR + CRC_CHECK_EN);
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}
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static inline void hw_dec_data_crc32_set(unsigned int crc32)
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{
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writel(crc32, HW_DEC_REG_BASE_ADDR + DPRS_DATA_CRC32);
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}
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static inline unsigned int hw_dec_buf_status_get(void)
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{
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return readl(HW_DEC_REG_BASE_ADDR + BUF_INFO);
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}
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static inline unsigned int hw_dec_dprs_rtn_status_get(void)
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{
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return readl(HW_DEC_REG_BASE_ADDR + DPRS_RTN_INFO);
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}
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static inline void hw_dec_buf_status_clr(void)
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{
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writel(0x1, HW_DEC_REG_BASE_ADDR + BUF_INFO_CLR);
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}
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static inline void hw_dec_dprs_rtn_status_clr(void)
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{
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writel(0x1, HW_DEC_REG_BASE_ADDR + RLT_INFO_CLR);
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}
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static void hw_dec_intr_en_set(int blk_intr_en, int task_intr_en)
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{
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u_intr_en intr_en;
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intr_en.bits.task_intrpt_en = task_intr_en;
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intr_en.bits.block_intrpt_en = blk_intr_en;
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writel(intr_en.u32, HW_DEC_REG_BASE_ADDR + INT_EN_REG_ADDR);
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}
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static inline unsigned int hw_dec_intr_status_get(void)
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{
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return readl(HW_DEC_REG_BASE_ADDR + INT_STATUS_REG_ADDR);
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}
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static void hw_dec_block_intr_status_clr(void)
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{
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u_intr_clr intr_clr;
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intr_clr.u32 = readl(HW_DEC_REG_BASE_ADDR + INT_CLEAR_REG_ADDR);
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intr_clr.bits.block_intrpt_clr = 0x1;
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writel(intr_clr.u32, HW_DEC_REG_BASE_ADDR + INT_CLEAR_REG_ADDR);
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}
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static void hw_dec_task_intr_status_clr(void)
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{
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u_intr_clr intr_clr;
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intr_clr.u32 = readl(HW_DEC_REG_BASE_ADDR + INT_CLEAR_REG_ADDR);
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intr_clr.bits.task_intrpt_clr = 0x1;
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writel(intr_clr.u32, HW_DEC_REG_BASE_ADDR + INT_CLEAR_REG_ADDR);
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}
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int hw_dec_intr_proc(int irq, const void *para)
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{
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u_buf_status buf_status;
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u_intr_status intr_status;
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u_dprs_rtn_status dprs_status;
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int ret = 0;
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intr_status.u32 = hw_dec_intr_status_get();
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if (intr_status.bits.block_intrpt) {
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buf_status.u32 = hw_dec_buf_status_get();
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if (buf_status.bits.aval_flg)
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hw_dec_buf_status_clr();
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hw_dec_block_intr_status_clr();
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}
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if (intr_status.bits.task_intrpt) {
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dprs_status.u32 = hw_dec_dprs_rtn_status_get();
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if (dprs_status.bits.aval_flg) {
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if (dprs_status.bits.err_info)
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ret = -2; /* -2:failed */
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hw_dec_dprs_rtn_status_clr();
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}
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hw_dec_task_intr_status_clr();
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goto out;
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}
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ret = -1;
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out:
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return ret;
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}
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void hw_dec_start(unsigned int src_baddr,
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unsigned int dst_baddr,
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unsigned int src_len,
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unsigned int dst_len,
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unsigned int crc_en,
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unsigned int crc32,
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unsigned int dec_type)
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{
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unsigned int val;
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if (hw_dec_sop) {
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if (!dec_type) {
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/* set the parameters of output buffer */
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hw_dec_rtn_baddr_set(dst_baddr);
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hw_dec_data_rtn_len_set(dst_len);
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} else {
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/* set the parameter of output buffer */
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hw_dec_dprs_data_baddr_set(dst_baddr);
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hw_dec_dprs_data_len_set(page_nr(dst_len) * 4); /* 4:Align */
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}
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}
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/* set the parameter of input buffer */
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writel(src_baddr, HW_DEC_REG_BASE_ADDR + DPRS_DATA_SRC_BADDR);
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val = src_len |
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(hw_dec_eop << 28) | (hw_dec_sop << 29) | (!dec_type << 31); /* 28,29,31 Move Left bit */
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writel(val, HW_DEC_REG_BASE_ADDR + DPRS_DATA_SRC_LEN);
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hw_dec_crc_check_en(crc_en);
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}
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static inline void delay(unsigned int num)
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{
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volatile unsigned int i;
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for (i = 0; i < (100 * num); i++) /* 100: Cycle */
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__asm__ __volatile__("nop");
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}
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int hw_dec_wait_finish(void)
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{
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int ret;
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int times = 0;
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do {
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ret = hw_dec_intr_proc(HW_DEC_INTR, NULL);
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times++;
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if (times > 2000000) { /* 2000000 ms */
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error("hardware decompress overtime!\n");
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break;
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}
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delay(1);
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} while (-1 == ret);
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return ret;
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}
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int hw_dec_decompress(const unsigned char *dst, int* const dstlen,
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const unsigned char *src, int srclen,
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const void *unused)
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{
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int ret;
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hw_dec_sop_eop_first_set(1);
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if (dstlen == NULL)
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return -1;
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hw_dec_start((unsigned int)(uintptr_t)src, (unsigned int)(uintptr_t)dst,
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srclen, *dstlen, 1, 0, hw_dec_type);
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ret = hw_dec_wait_finish();
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*dstlen = readl(HW_DEC_REG_BASE_ADDR + DPRS_RTN_LEN);
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if (ret)
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return -1;
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return 0;
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}
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static int set_sop_and_eop(hw_decompress_op_type op_type)
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{
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if (op_type == HW_DECOMPRESS_OP_START) {
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hw_dec_sop = 1;
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hw_dec_eop = 0;
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} else if (op_type == HW_DECOMPRESS_OP_CONTINUE) {
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hw_dec_sop = 0;
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hw_dec_eop = 0;
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} else if (op_type == HW_DECOMPRESS_OP_END) {
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hw_dec_sop = 0;
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hw_dec_eop = 1;
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} else if (op_type == HW_DECOMPRESS_OP_ONCE) {
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hw_dec_sop = 1;
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hw_dec_eop = 1;
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} else {
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return -1;
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}
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return 0;
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}
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/*
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* Support decompressing gzip file by sections
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*/
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int hw_dec_decompress_ex(hw_decompress_op_type op_type, const unsigned char *dst,
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unsigned int *dstlen, const unsigned char *src, unsigned int srclen)
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{
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if ((dst == NULL) || (src == NULL) || (dstlen == NULL)) {
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return -1;
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}
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if ((*dstlen == 0) || (srclen == 0)) {
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return -1;
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}
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int ret = set_sop_and_eop(op_type);
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if (ret != 0) {
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return -1;
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}
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hw_dec_type = 0;
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const unsigned int crc_en = 1;
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hw_dec_start((unsigned int)(uintptr_t)src, (unsigned int)(uintptr_t)dst,
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srclen, *dstlen, crc_en, 0, hw_dec_type);
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if ((op_type == HW_DECOMPRESS_OP_END) || (op_type == HW_DECOMPRESS_OP_ONCE)) {
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ret = hw_dec_wait_finish();
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*dstlen = readl(HW_DEC_REG_BASE_ADDR + DPRS_RTN_LEN);
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if (ret != 0) {
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return ret;
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}
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}
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return 0;
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}
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void hw_dec_init(void)
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{
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/* enable decompress clock */
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enable_decompress_clock();
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/* Init the emar interface */
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writel(0, HW_DEC_REG_BASE_ADDR + EAMR_RID_REG_OFST);
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writel(0x3, HW_DEC_REG_BASE_ADDR + EAMR_ROSD_REG_OFST);
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writel(0, HW_DEC_REG_BASE_ADDR + EAMR_WID_REG_OFST);
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writel(0x3, HW_DEC_REG_BASE_ADDR + EAMR_WOSD_REG_OFST);
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/* Enable interrupt */
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hw_dec_intr_en_set(0x1, 0x1);
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/* Enable emar */
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hw_dec_work_en_set(0x1);
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}
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void hw_dec_uinit(void)
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{
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hw_dec_work_en_set(0x0);
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hw_dec_intr_en_set(0x0, 0x0);
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/* disable decompress clock */
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disable_decompress_clock();
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}
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@@ -0,0 +1,129 @@
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/*
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* Copyright (c) LOTUS. All rights reserved.
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*/
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#ifndef HW_DECOMPRESS_V1_H
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#define HW_DECOMPRESS_V1_H
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#include <asm/arch/platform.h>
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#define PAGE_SIZE 4096
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#define page_nr(x) (((x) + PAGE_SIZE - 1) / PAGE_SIZE)
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/* The base address for emar */
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#define HW_DEC_REG_BASE_ADDR (GZIP_REG_BASE)
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/* The global init registers for emar interface */
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#define EAMR_RID_REG_OFST 0x0110UL
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#define EAMR_ROSD_REG_OFST 0x0114UL
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#define EAMR_WID_REG_OFST 0x0128UL
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#define EAMR_WOSD_REG_OFST 0x012CUL
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/* The enable register */
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#define EAMR_WORK_EN_REG_OFST 0x0118UL
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#define DPRS_DATA_SRC_BADDR 0x2058UL
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#define DPRS_DATA_SRC_LEN 0x205CUL
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/* Decompress parameter reigsters for page address */
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#define DPRS_DATA_RTN_BADDR 0x2038UL
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#define DPRS_DATA_RTN_LEN 0x203CUL
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/* Decompress parameter registers for page data */
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#define DPRS_DATA_INFO_BADDR 0x2030UL
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#define DPRS_DATA_INFO_LEN 0x2034UL
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#define DPRS_DATA_CRC32 0x2040UL
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#define CRC_CHECK_EN 0x4018UL
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/* The status registers */
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#define BUF_INFO 0x2098UL
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#define DPRS_RTN_INFO 0x209CUL
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#define DPRS_RTN_LEN 0x2090UL
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#define BUF_INFO_CLR 0x20A8UL
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#define RLT_INFO_CLR 0x20ACUL
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/* The intr registers */
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#define INT_EN_REG_ADDR 0x0130UL
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#define INT_STATUS_REG_ADDR 0x013CUL
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#define INT_CLEAR_REG_ADDR 0x0148UL
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#define TASK_MODE_REG 0x214CUL
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/* Define the union u_dprs_data_buf_info */
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typedef union {
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/* Define the struct bits */
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struct {
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unsigned int buf_len : 24; /* [23..0] */
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unsigned int buf_id : 2; /* [25..24] */
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unsigned int reserved_1 : 2; /* [27..26] */
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unsigned int eop : 1; /* [28] */
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unsigned int sop : 1; /* [29] */
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unsigned int reserved_0 : 1; /* [30] */
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unsigned int mode : 1; /* [31] */
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} bits;
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/* Define an unsigned member */
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unsigned int u32;
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} u_dprs_data_buf_info;
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typedef union {
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struct {
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unsigned int buf_id : 2; /* [1:0] */
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unsigned int rsv : 29; /* [30:2] */
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unsigned int aval_flg : 1; /* [31] */
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} bits;
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unsigned int u32;
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} u_buf_status;
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typedef union {
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struct {
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unsigned int err_info : 8; /* [7:0] */
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unsigned int rsv : 23; /* [30:8] */
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unsigned int aval_flg : 1; /* [31] */
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} bits;
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unsigned int u32;
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} u_dprs_rtn_status;
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/* Define the union U_INT_EN */
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typedef union {
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/* Define the struct bits */
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struct {
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unsigned int reserved_0 : 10;
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unsigned int block_intrpt_en : 1; /* [10] */
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unsigned int task_intrpt_en : 1; /* [11] */
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unsigned int reserved_1 : 20; /* [31..12] */
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} bits;
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/* Define an unsigned member */
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unsigned int u32;
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} u_intr_en;
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typedef union {
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/* Define the struct bits */
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struct {
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unsigned int reserved_0 : 10;
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unsigned int block_intrpt : 1; /* [10] */
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unsigned int task_intrpt : 1; /* [11] */
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unsigned int reserved_1 : 20; /* [31..12] */
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} bits;
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/* Define an unsigned member */
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unsigned int u32;
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} u_intr_status;
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typedef union {
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/* Define the struct bits */
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struct {
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unsigned int reserved_0 : 10;
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unsigned int block_intrpt_clr : 1; /* [10] */
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unsigned int task_intrpt_clr : 1; /* [11] */
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unsigned int reserved_1 : 20; /* [31..12] */
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} bits;
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/* Define an unsigned member */
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unsigned int u32;
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} u_intr_clr;
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||||
#endif /* end HW_DECOMPRESS_V1_H */
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@@ -0,0 +1,29 @@
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/*
|
||||
* Copyright (c) LOTUS. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <config.h>
|
||||
|
||||
#define PERI_CRG100 (CRG_REG_BASE + 0x190)
|
||||
|
||||
#define GZIP_REG_CRG PERI_CRG100
|
||||
#define GZIP_CLKEN (0x1<<0)
|
||||
|
||||
static void disable_decompress_clock(void)
|
||||
{
|
||||
unsigned int regval;
|
||||
|
||||
regval = readl(GZIP_REG_CRG);
|
||||
regval &= ~GZIP_CLKEN;
|
||||
writel(regval, GZIP_REG_CRG);
|
||||
}
|
||||
|
||||
static void enable_decompress_clock(void)
|
||||
{
|
||||
unsigned int regval;
|
||||
|
||||
regval = readl(GZIP_REG_CRG);
|
||||
regval |= GZIP_CLKEN;
|
||||
writel(regval, GZIP_REG_CRG);
|
||||
}
|
||||
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (c) LOTUS. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <config.h>
|
||||
|
||||
#define PERI_CRG100 0x190
|
||||
|
||||
#define GZIP_OFFSET PERI_CRG100
|
||||
#define GZIP_CLKEN (0x1<<0)
|
||||
|
||||
#ifndef GZIP_REG_BASE
|
||||
#define GZIP_REG_BASE 0x11310000
|
||||
#endif
|
||||
|
||||
#define HW_DEC_REG_BASE_ADDR (GZIP_REG_BASE)
|
||||
|
||||
static void disable_decompress_clock(void)
|
||||
{
|
||||
unsigned int regval;
|
||||
|
||||
regval = readl(CRG_REG_BASE + GZIP_OFFSET);
|
||||
regval &= ~GZIP_CLKEN;
|
||||
writel(regval, CRG_REG_BASE + GZIP_OFFSET);
|
||||
}
|
||||
|
||||
static void enable_decompress_clock(void)
|
||||
{
|
||||
unsigned int regval;
|
||||
|
||||
regval = readl(CRG_REG_BASE + GZIP_OFFSET);
|
||||
regval |= GZIP_CLKEN;
|
||||
writel(regval, CRG_REG_BASE + GZIP_OFFSET);
|
||||
}
|
||||
Reference in New Issue
Block a user