GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

This commit is contained in:
lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
21813 changed files with 4413081 additions and 0 deletions
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ifneq ($(MCU), )
include Makefile.riscv
else
include Makefile.linux
endif
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ISP_DIR := $(shell cd ../.. && /bin/pwd)
SDK_DIR ?= $(shell cd $(ISP_DIR)/../../../.. && /bin/pwd)
include $(SDK_DIR)/build/base.mk
include $(ISP_DIR)/sensor/plat.mk
LIB_NAME := libsns_ox05b1s
SRCS := $(wildcard *.c)
SDK_USR_CFLAGS += -I$(GMP_DIR)/include
SDK_USR_CFLAGS += -I$(GMP_DIR)/usr/include
SDK_USR_CFLAGS += -I$(ISP_DIR)/include
SDK_USR_CFLAGS += -I$(ISP_DIR)/../include
SDK_USR_CFLAGS += -I.
AT := @
$(info SRCS=$(SRCS))
include $(SDK_DIR)/build/sdk_lib_rules.mk
@@ -0,0 +1,3 @@
SRCS-y += ox05b1s.c
SRCS-y += ox05b1s_ctrl.c
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#ifndef __OX05B1S_H__
#define __OX05B1S_H__
#include "sns_comm.h"
#ifdef __cplusplus
extern "C" {
#endif
#define OX05B1S_FULL_LINES_MAX 0xFFFF
#define OX05B1S_VMAX_1M_LINEAR 0x424
#define OX05B1S_VMAX_5M_LINEAR 0x850
#define OX05B1S_EXP_OFFSET 30
// OX05B1S Register Address
#define OX05B1S_REG_ADDR_EXP_H 0x3501
#define OX05B1S_REG_ADDR_EXP_L 0x3502
#define OX05B1S_REG_ADDR_AGC_H 0x3508 //BIT[3:0]
#define OX05B1S_REG_ADDR_AGC_L 0x3509 //BIT[7:4]
#define OX05B1S_REG_ADDR_DGC_H 0x350a //BIT[3:0]
#define OX05B1S_REG_ADDR_DGC_M 0x350b //BIT[7:0]
#define OX05B1S_REG_ADDR_DGC_L 0x350c //BIT[7:6]
#define OX05B1S_VMAX_H_ADDR 0x380E
#define OX05B1S_VMAX_L_ADDR 0x380F
typedef enum {
OX05B1S_REG_EXP_H = 0,
OX05B1S_REG_EXP_L,
OX05B1S_REG_AGC_L,
OX05B1S_REG_AGC_H,
OX05B1S_REG_DGC_L,
OX05B1S_REG_DGC_M,
OX05B1S_REG_DGC_H,
OX05B1S_REG_VMAX_H,
OX05B1S_REG_VMAX_L,
OX05B1S_REG_MAX_NUM
} ox05b1s_reg_index;
#ifdef __cplusplus
}
#endif
#endif // __OX05B1S_H__
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#ifndef __OX05B1S_CTRL_H__
#define __OX05B1S_CTRL_H__
#include "sns_comm.h"
#ifdef __cplusplus
extern "C" {
#endif
#define OX05B1S_I2C_ADDR 0x6c
#define OX05B1S_ADDR_BYTE 2
#define OX05B1S_DATA_BYTE 1
#define OX05B1S_1M_LINEAR_MODE 1
#define OX05B1S_5M_LINEAR_MODE 2
xmedia_s32 ox05b1s_i2c_init(xmedia_u32 dev, xmedia_s8 i2c_dev, xmedia_u32 i2c_addr);
xmedia_s32 ox05b1s_i2c_exit(xmedia_u32 dev);
xmedia_s32 ox05b1s_read_reg(xmedia_u32 dev, xmedia_u32 addr, xmedia_u32 *data);
xmedia_s32 ox05b1s_write_reg(xmedia_u32 dev, xmedia_u32 addr, xmedia_u32 data);
xmedia_s32 ox05b1s_set_mirror_flip(xmedia_u32 dev, xmedia_bool mirror_en, xmedia_bool flip_en);
xmedia_s32 ox05b1s_init_image(xmedia_u32 dev, xmedia_u8 img_mode, xmedia_sensor_work_mode work_mode);
xmedia_s32 ox05b1s_set_slave_addr(xmedia_u32 dev, xmedia_u32 slave_addr);
#ifdef __cplusplus
}
#endif
#endif //__OX05B1S_CTRL_H__
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#ifndef __OX05B1S_EX_H__
#define __OX05B1S_EX_H__
#ifdef __cplusplus
extern "C" {
#endif
// Piris attr
static const xmedia_isp_piris_attr g_ox05b1s_piris_attr = {
0,
1,
94,
62,
// Step-F number mapping table. Must be from small to large. F1.0 is 1024 and F32.0 is 1
{ 30, 35, 40, 45, 50, 56, 61, 67, 73, 79, 85, 92, 98, 105, 112, 120, 127, 135, 143, 150, 158,
166, 174, 183, 191, 200, 208, 217, 225, 234, 243, 252, 261, 270, 279, 289, 298, 307, 316, 325, 335, 344,
353, 362, 372, 381, 390, 399, 408, 417, 426, 435, 444, 453, 462, 470, 478, 486, 493, 500, 506, 512 },
XMEDIA_ISP_IRIS_F_NO_1_4,
XMEDIA_ISP_IRIS_F_NO_5_6
};
static const xmedia_isp_awb_ccm g_ox05b1s_awb_ccm = {
4,
{
{
7200,
{ 402,32891,32791,32833,426,32873,19,32922,391},
},
{
5000, //ct
{ 402,32885,32797,32859,467,32888,36,32965,417}, //ccm
},
{
3800, //ct
{ 399,32856,32823,32873,429,32836,39,32963,412}, //ccm
},
{
2500, //ct
{ 538,33004,32814,32846,375,32809,127,33216,577}, //ccm
},
},
};
static const xmedia_isp_awb_agc_table g_ox05b1s_awb_agc_table = {
/* bvalid */
1,
/* 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768 */
/* saturation */
{120,100,100,100,100,100,90,80,80,80,80,80,80,80,80,80}
};
#ifdef __cplusplus
}
#endif
#endif