GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "../bl1_private.h"
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/*******************************************************************************
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* TODO: Function that does the first bit of architectural setup.
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******************************************************************************/
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void bl1_arch_setup(void)
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{
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}
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/*
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* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <context.h>
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#include <common/debug.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <plat/common/platform.h>
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#include <smccc_helpers.h>
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#include "../bl1_private.h"
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/*
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* Following arrays will be used for context management.
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* There are 2 instances, for the Secure and Non-Secure contexts.
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*/
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static cpu_context_t bl1_cpu_context[2];
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static smc_ctx_t bl1_smc_context[2];
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/* Following contains the next cpu context pointer. */
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static void *bl1_next_cpu_context_ptr;
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/* Following contains the next smc context pointer. */
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static void *bl1_next_smc_context_ptr;
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/* Following functions are used for SMC context handling */
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void *smc_get_ctx(unsigned int security_state)
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{
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assert(sec_state_is_valid(security_state));
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return &bl1_smc_context[security_state];
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}
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void smc_set_next_ctx(unsigned int security_state)
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{
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assert(sec_state_is_valid(security_state));
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bl1_next_smc_context_ptr = &bl1_smc_context[security_state];
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}
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void *smc_get_next_ctx(void)
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{
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return bl1_next_smc_context_ptr;
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}
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/* Following functions are used for CPU context handling */
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void *cm_get_context(uint32_t security_state)
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{
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assert(sec_state_is_valid(security_state));
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return &bl1_cpu_context[security_state];
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}
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void cm_set_next_context(void *context)
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{
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assert(context != NULL);
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bl1_next_cpu_context_ptr = context;
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}
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void *cm_get_next_context(void)
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{
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return bl1_next_cpu_context_ptr;
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}
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/*******************************************************************************
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* Following function copies GP regs r0-r4, lr and spsr,
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* from the CPU context to the SMC context structures.
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******************************************************************************/
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static void copy_cpu_ctx_to_smc_ctx(const regs_t *cpu_reg_ctx,
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smc_ctx_t *next_smc_ctx)
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{
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next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0);
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next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1);
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next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2);
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next_smc_ctx->r3 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R3);
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next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR);
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next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR);
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next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR);
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}
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/*******************************************************************************
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* Following function flushes the SMC & CPU context pointer and its data.
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******************************************************************************/
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static void flush_smc_and_cpu_ctx(void)
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{
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flush_dcache_range((uintptr_t)&bl1_next_smc_context_ptr,
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sizeof(bl1_next_smc_context_ptr));
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flush_dcache_range((uintptr_t)bl1_next_smc_context_ptr,
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sizeof(smc_ctx_t));
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flush_dcache_range((uintptr_t)&bl1_next_cpu_context_ptr,
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sizeof(bl1_next_cpu_context_ptr));
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flush_dcache_range((uintptr_t)bl1_next_cpu_context_ptr,
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sizeof(cpu_context_t));
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}
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/*******************************************************************************
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* This function prepares the context for Secure/Normal world images.
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* Normal world images are transitioned to HYP(if supported) else SVC.
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******************************************************************************/
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void bl1_prepare_next_image(unsigned int image_id)
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{
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unsigned int security_state, mode = MODE32_svc;
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image_desc_t *desc;
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entry_point_info_t *next_bl_ep;
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/* Get the image descriptor. */
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desc = bl1_plat_get_image_desc(image_id);
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assert(desc != NULL);
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/* Get the entry point info. */
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next_bl_ep = &desc->ep_info;
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/* Get the image security state. */
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security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
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/* Prepare the SPSR for the next BL image. */
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if ((security_state != SECURE) && (GET_VIRT_EXT(read_id_pfr1()) != 0U)) {
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mode = MODE32_hyp;
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}
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next_bl_ep->spsr = SPSR_MODE32(mode, SPSR_T_ARM,
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SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
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/* Allow platform to make change */
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bl1_plat_set_ep_info(image_id, next_bl_ep);
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/* Prepare the cpu context for the next BL image. */
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cm_init_my_context(next_bl_ep);
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cm_prepare_el3_exit(security_state);
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cm_set_next_context(cm_get_context(security_state));
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/* Prepare the smc context for the next BL image. */
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smc_set_next_ctx(security_state);
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copy_cpu_ctx_to_smc_ctx(get_regs_ctx(cm_get_next_context()),
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smc_get_next_ctx());
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/*
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* If the next image is non-secure, then we need to program the banked
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* non secure sctlr. This is not required when the next image is secure
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* because in AArch32, we expect the secure world to have the same
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* SCTLR settings.
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*/
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if (security_state == NON_SECURE) {
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cpu_context_t *ctx = cm_get_context(security_state);
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u_register_t ns_sctlr;
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/* Temporarily set the NS bit to access NS SCTLR */
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write_scr(read_scr() | SCR_NS_BIT);
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isb();
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ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR);
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write_sctlr(ns_sctlr);
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isb();
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write_scr(read_scr() & ~SCR_NS_BIT);
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isb();
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}
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/*
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* Flush the SMC & CPU context and the (next)pointers,
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* to access them after caches are disabled.
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*/
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flush_smc_and_cpu_ctx();
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/* Indicate that image is in execution state. */
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desc->state = IMAGE_STATE_EXECUTED;
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print_entry_point_info(next_bl_ep);
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}
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@@ -0,0 +1,99 @@
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/*
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* Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <context.h>
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#include <el3_common_macros.S>
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#include <smccc_helpers.h>
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#include <smccc_macros.S>
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.globl bl1_vector_table
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.globl bl1_entrypoint
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/* -----------------------------------------------------
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* Setup the vector table to support SVC & MON mode.
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* -----------------------------------------------------
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*/
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vector_base bl1_vector_table
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b bl1_entrypoint
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b report_exception /* Undef */
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b bl1_aarch32_smc_handler /* SMC call */
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b report_prefetch_abort /* Prefetch abort */
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b report_data_abort /* Data abort */
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b report_exception /* Reserved */
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b report_exception /* IRQ */
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b report_exception /* FIQ */
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/* -----------------------------------------------------
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* bl1_entrypoint() is the entry point into the trusted
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* firmware code when a cpu is released from warm or
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* cold reset.
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* -----------------------------------------------------
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*/
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func bl1_entrypoint
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/* ---------------------------------------------------------------------
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* If the reset address is programmable then bl1_entrypoint() is
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* executed only on the cold boot path. Therefore, we can skip the warm
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* boot mailbox mechanism.
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* ---------------------------------------------------------------------
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*/
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el3_entrypoint_common \
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_init_sctlr=1 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=bl1_vector_table \
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_pie_fixup_size=0
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/* -----------------------------------------------------
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* Perform BL1 setup
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* -----------------------------------------------------
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*/
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bl bl1_setup
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/* -----------------------------------------------------
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* Jump to main function.
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* -----------------------------------------------------
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*/
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bl bl1_main
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/* -----------------------------------------------------
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* Jump to next image.
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* -----------------------------------------------------
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*/
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/*
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* Get the smc_context for next BL image,
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* program the gp/system registers and save it in `r4`.
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*/
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bl smc_get_next_ctx
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mov r4, r0
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/* Only turn-off MMU if going to secure world */
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ldr r5, [r4, #SMC_CTX_SCR]
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tst r5, #SCR_NS_BIT
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bne skip_mmu_off
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/*
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* MMU needs to be disabled because both BL1 and BL2/BL2U execute
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* in PL1, and therefore share the same address space.
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* BL2/BL2U will initialize the address space according to its
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* own requirement.
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*/
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bl disable_mmu_icache_secure
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stcopr r0, TLBIALL
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dsb sy
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isb
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skip_mmu_off:
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/* Restore smc_context from `r4` and exit secure monitor mode. */
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mov r0, r4
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monitor_exit
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endfunc bl1_entrypoint
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@@ -0,0 +1,165 @@
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/*
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* Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl1/bl1.h>
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#include <common/bl_common.h>
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#include <context.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include <smccc_helpers.h>
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#include <smccc_macros.S>
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.globl bl1_aarch32_smc_handler
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func bl1_aarch32_smc_handler
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/* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
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str lr, [sp, #SMC_CTX_LR_MON]
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/* ------------------------------------------------
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* SMC in BL1 is handled assuming that the MMU is
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* turned off by BL2.
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* ------------------------------------------------
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*/
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/* ----------------------------------------------
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* Detect if this is a RUN_IMAGE or other SMC.
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* ----------------------------------------------
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*/
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mov lr, #BL1_SMC_RUN_IMAGE
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cmp lr, r0
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bne smc_handler
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/* ------------------------------------------------
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* Make sure only Secure world reaches here.
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* ------------------------------------------------
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*/
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ldcopr r8, SCR
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tst r8, #SCR_NS_BIT
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blne report_exception
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/* ---------------------------------------------------------------------
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* Pass control to next secure image.
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* Here it expects r1 to contain the address of a entry_point_info_t
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* structure describing the BL entrypoint.
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* ---------------------------------------------------------------------
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*/
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mov r8, r1
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mov r0, r1
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bl bl1_print_next_bl_ep_info
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#if SPIN_ON_BL1_EXIT
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bl print_debug_loop_message
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debug_loop:
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b debug_loop
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#endif
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mov r0, r8
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bl bl1_plat_prepare_exit
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stcopr r0, TLBIALL
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dsb sy
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isb
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/*
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* Extract PC and SPSR based on struct `entry_point_info_t`
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* and load it in LR and SPSR registers respectively.
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*/
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ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET]
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ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)]
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msr spsr_xc, r1
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/* Some BL32 stages expect lr_svc to provide the BL33 entry address */
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cps #MODE32_svc
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ldr lr, [r8, #ENTRY_POINT_INFO_LR_SVC_OFFSET]
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cps #MODE32_mon
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add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET
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ldm r8, {r0, r1, r2, r3}
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exception_return
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endfunc bl1_aarch32_smc_handler
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/* -----------------------------------------------------
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* Save Secure/Normal world context and jump to
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* BL1 SMC handler.
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* -----------------------------------------------------
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*/
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func smc_handler
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/* -----------------------------------------------------
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* Save the GP registers.
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* -----------------------------------------------------
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*/
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smccc_save_gp_mode_regs
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/*
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* `sp` still points to `smc_ctx_t`. Save it to a register
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* and restore the C runtime stack pointer to `sp`.
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*/
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mov r6, sp
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ldr sp, [r6, #SMC_CTX_SP_MON]
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ldr r0, [r6, #SMC_CTX_SCR]
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and r7, r0, #SCR_NS_BIT /* flags */
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/* Switch to Secure Mode */
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bic r0, #SCR_NS_BIT
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stcopr r0, SCR
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isb
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/* If caller is from Secure world then turn on the MMU */
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tst r7, #SCR_NS_BIT
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bne skip_mmu_on
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/* Turn on the MMU */
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mov r0, #DISABLE_DCACHE
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bl enable_mmu_svc_mon
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/*
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* Invalidate `smc_ctx_t` in data cache to prevent dirty data being
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* used.
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*/
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mov r0, r6
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mov r1, #SMC_CTX_SIZE
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bl inv_dcache_range
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/* Enable the data cache. */
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ldcopr r9, SCTLR
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orr r9, r9, #SCTLR_C_BIT
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stcopr r9, SCTLR
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isb
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skip_mmu_on:
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/* Prepare arguments for BL1 SMC wrapper. */
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ldr r0, [r6, #SMC_CTX_GPREG_R0] /* smc_fid */
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mov r1, #0 /* cookie */
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mov r2, r6 /* handle */
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mov r3, r7 /* flags */
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bl bl1_smc_wrapper
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/* Get the smc_context for next BL image */
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bl smc_get_next_ctx
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mov r4, r0
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/* Only turn-off MMU if going to secure world */
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ldr r5, [r4, #SMC_CTX_SCR]
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tst r5, #SCR_NS_BIT
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bne skip_mmu_off
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/* Disable the MMU */
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bl disable_mmu_icache_secure
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stcopr r0, TLBIALL
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dsb sy
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isb
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skip_mmu_off:
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/* -----------------------------------------------------
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* Do the transition to next BL image.
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* -----------------------------------------------------
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*/
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mov r0, r4
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monitor_exit
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endfunc smc_handler
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