GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,35 @@
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/*
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* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include "../bl1_private.h"
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/*******************************************************************************
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* Function that does the first bit of architectural setup that affects
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* execution in the non-secure address space.
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******************************************************************************/
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void bl1_arch_setup(void)
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{
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/* Set the next EL to be AArch64 */
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write_scr_el3(read_scr_el3() | SCR_RW_BIT);
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}
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/*******************************************************************************
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* Set the Secure EL1 required architectural state
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******************************************************************************/
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void bl1_arch_next_el_setup(void)
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{
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u_register_t next_sctlr;
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/* Use the same endianness than the current BL */
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next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT);
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/* Set SCTLR Secure EL1 */
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next_sctlr |= SCTLR_EL1_RES1;
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write_sctlr_el1(next_sctlr);
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}
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@@ -0,0 +1,131 @@
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/*
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* Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <context.h>
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#include <common/debug.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <plat/common/platform.h>
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#include "../bl1_private.h"
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/* Following contains the cpu context pointers. */
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static void *bl1_cpu_context_ptr[2];
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entry_point_info_t *bl2_ep_info;
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void *cm_get_context(uint32_t security_state)
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{
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assert(sec_state_is_valid(security_state));
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return bl1_cpu_context_ptr[security_state];
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}
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void cm_set_context(void *context, uint32_t security_state)
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{
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assert(sec_state_is_valid(security_state));
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bl1_cpu_context_ptr[security_state] = context;
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}
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#if ENABLE_RME
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/*******************************************************************************
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* This function prepares the entry point information to run BL2 in Root world,
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* i.e. EL3, for the case when FEAT_RME is enabled.
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******************************************************************************/
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void bl1_prepare_next_image(unsigned int image_id)
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{
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image_desc_t *bl2_desc;
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assert(image_id == BL2_IMAGE_ID);
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/* Get the image descriptor. */
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bl2_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
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assert(bl2_desc != NULL);
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/* Get the entry point info. */
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bl2_ep_info = &bl2_desc->ep_info;
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bl2_ep_info->spsr = (uint32_t)SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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/*
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* Flush cache since bl2_ep_info is accessed after MMU is disabled
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* before jumping to BL2.
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*/
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flush_dcache_range((uintptr_t)bl2_ep_info, sizeof(entry_point_info_t));
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/* Indicate that image is in execution state. */
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bl2_desc->state = IMAGE_STATE_EXECUTED;
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/* Print debug info and flush the console before running BL2. */
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print_entry_point_info(bl2_ep_info);
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}
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#else
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/*******************************************************************************
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* This function prepares the context for Secure/Normal world images.
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* Normal world images are transitioned to EL2(if supported) else EL1.
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******************************************************************************/
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void bl1_prepare_next_image(unsigned int image_id)
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{
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/*
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* Following array will be used for context management.
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* There are 2 instances, for the Secure and Non-Secure contexts.
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*/
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static cpu_context_t bl1_cpu_context[2];
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unsigned int security_state, mode = MODE_EL1;
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image_desc_t *desc;
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entry_point_info_t *next_bl_ep;
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#if CTX_INCLUDE_AARCH32_REGS
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/*
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* Ensure that the build flag to save AArch32 system registers in CPU
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* context is not set for AArch64-only platforms.
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*/
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if (el_implemented(1) == EL_IMPL_A64ONLY) {
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ERROR("EL1 supports AArch64-only. Please set build flag "
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"CTX_INCLUDE_AARCH32_REGS = 0\n");
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panic();
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}
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#endif
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/* Get the image descriptor. */
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desc = bl1_plat_get_image_desc(image_id);
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assert(desc != NULL);
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/* Get the entry point info. */
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next_bl_ep = &desc->ep_info;
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/* Get the image security state. */
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security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
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/* Setup the Secure/Non-Secure context if not done already. */
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if (cm_get_context(security_state) == NULL)
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cm_set_context(&bl1_cpu_context[security_state], security_state);
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/* Prepare the SPSR for the next BL image. */
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if ((security_state != SECURE) && (el_implemented(2) != EL_IMPL_NONE)) {
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mode = MODE_EL2;
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}
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next_bl_ep->spsr = (uint32_t)SPSR_64((uint64_t) mode,
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(uint64_t)MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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/* Allow platform to make change */
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bl1_plat_set_ep_info(image_id, next_bl_ep);
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/* Prepare the context for the next BL image. */
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cm_init_my_context(next_bl_ep);
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cm_prepare_el3_exit(security_state);
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/* Indicate that image is in execution state. */
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desc->state = IMAGE_STATE_EXECUTED;
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print_entry_point_info(next_bl_ep);
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}
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#endif /* ENABLE_RME */
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@@ -0,0 +1,108 @@
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/*
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* Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <common/bl_common.h>
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#include <el3_common_macros.S>
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.globl bl1_entrypoint
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.globl bl1_run_bl2_in_root
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/* -----------------------------------------------------
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* bl1_entrypoint() is the entry point into the trusted
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* firmware code when a cpu is released from warm or
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* cold reset.
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* -----------------------------------------------------
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*/
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func bl1_entrypoint
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/* ---------------------------------------------------------------------
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* If the reset address is programmable then bl1_entrypoint() is
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* executed only on the cold boot path. Therefore, we can skip the warm
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* boot mailbox mechanism.
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* ---------------------------------------------------------------------
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*/
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el3_entrypoint_common \
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_init_sctlr=1 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=bl1_exceptions \
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_pie_fixup_size=0
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/* --------------------------------------------------------------------
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* Perform BL1 setup
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* --------------------------------------------------------------------
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*/
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bl bl1_setup
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#if ENABLE_PAUTH
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/* --------------------------------------------------------------------
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* Program APIAKey_EL1 and enable pointer authentication.
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* --------------------------------------------------------------------
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*/
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bl pauth_init_enable_el3
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#endif /* ENABLE_PAUTH */
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/* --------------------------------------------------------------------
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* Initialize platform and jump to our c-entry point
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* for this type of reset.
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* --------------------------------------------------------------------
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*/
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bl bl1_main
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#if ENABLE_PAUTH
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/* --------------------------------------------------------------------
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* Disable pointer authentication before jumping to next boot image.
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* --------------------------------------------------------------------
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*/
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bl pauth_disable_el3
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#endif /* ENABLE_PAUTH */
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/* --------------------------------------------------
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* Do the transition to next boot image.
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* --------------------------------------------------
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*/
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#if ENABLE_RME
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b bl1_run_bl2_in_root
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#else
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b el3_exit
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#endif
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endfunc bl1_entrypoint
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/* -----------------------------------------------------
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* void bl1_run_bl2_in_root();
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* This function runs BL2 in root/EL3 when RME is enabled.
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* -----------------------------------------------------
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*/
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func bl1_run_bl2_in_root
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/* read bl2_ep_info */
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adrp x20, bl2_ep_info
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add x20, x20, :lo12:bl2_ep_info
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ldr x20, [x20]
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/* ---------------------------------------------
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* MMU needs to be disabled because BL2 executes
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* in EL3. It will initialize the address space
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* according to its own requirements.
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* ---------------------------------------------
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*/
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bl disable_mmu_icache_el3
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tlbi alle3
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ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
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msr elr_el3, x0
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msr spsr_el3, x1
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ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
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ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
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ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
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ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
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exception_return
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endfunc bl1_run_bl2_in_root
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@@ -0,0 +1,289 @@
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/*
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* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl1/bl1.h>
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#include <common/bl_common.h>
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#include <context.h>
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/* -----------------------------------------------------------------------------
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* Very simple stackless exception handlers used by BL1.
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* -----------------------------------------------------------------------------
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*/
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.globl bl1_exceptions
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vector_base bl1_exceptions
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/* -----------------------------------------------------
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* Current EL with SP0 : 0x0 - 0x200
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionSP0
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mov x0, #SYNC_EXCEPTION_SP_EL0
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SynchronousExceptionSP0
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vector_entry IrqSP0
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mov x0, #IRQ_SP_EL0
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry IrqSP0
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vector_entry FiqSP0
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mov x0, #FIQ_SP_EL0
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry FiqSP0
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vector_entry SErrorSP0
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mov x0, #SERROR_SP_EL0
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SErrorSP0
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/* -----------------------------------------------------
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* Current EL with SPx: 0x200 - 0x400
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionSPx
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mov x0, #SYNC_EXCEPTION_SP_ELX
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SynchronousExceptionSPx
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vector_entry IrqSPx
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mov x0, #IRQ_SP_ELX
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry IrqSPx
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vector_entry FiqSPx
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mov x0, #FIQ_SP_ELX
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry FiqSPx
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vector_entry SErrorSPx
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mov x0, #SERROR_SP_ELX
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SErrorSPx
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/* -----------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionA64
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/* Enable the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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/* Expect only SMC exceptions */
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mrs x30, esr_el3
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ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x30, #EC_AARCH64_SMC
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b.ne unexpected_sync_exception
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b smc_handler64
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end_vector_entry SynchronousExceptionA64
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vector_entry IrqA64
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mov x0, #IRQ_AARCH64
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry IrqA64
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vector_entry FiqA64
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mov x0, #FIQ_AARCH64
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry FiqA64
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vector_entry SErrorA64
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mov x0, #SERROR_AARCH64
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SErrorA64
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/* -----------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionA32
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mov x0, #SYNC_EXCEPTION_AARCH32
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SynchronousExceptionA32
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vector_entry IrqA32
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mov x0, #IRQ_AARCH32
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry IrqA32
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vector_entry FiqA32
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mov x0, #FIQ_AARCH32
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry FiqA32
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vector_entry SErrorA32
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mov x0, #SERROR_AARCH32
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SErrorA32
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func smc_handler64
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/* ----------------------------------------------
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* Detect if this is a RUN_IMAGE or other SMC.
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* ----------------------------------------------
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*/
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mov x30, #BL1_SMC_RUN_IMAGE
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cmp x30, x0
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b.ne smc_handler
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/* ------------------------------------------------
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* Make sure only Secure world reaches here.
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* ------------------------------------------------
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*/
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mrs x30, scr_el3
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tst x30, #SCR_NS_BIT
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b.ne unexpected_sync_exception
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/* ----------------------------------------------
|
||||
* Handling RUN_IMAGE SMC. First switch back to
|
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* SP_EL0 for the C runtime stack.
|
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* ----------------------------------------------
|
||||
*/
|
||||
ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
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msr spsel, #MODE_SP_EL0
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mov sp, x30
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|
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/* ---------------------------------------------------------------------
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* Pass EL3 control to next BL image.
|
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* Here it expects X1 with the address of a entry_point_info_t
|
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* structure describing the next BL image entrypoint.
|
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* ---------------------------------------------------------------------
|
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*/
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mov x20, x1
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mov x0, x20
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bl bl1_print_next_bl_ep_info
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ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
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msr elr_el3, x0
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msr spsr_el3, x1
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ubfx x0, x1, #MODE_EL_SHIFT, #2
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cmp x0, #MODE_EL3
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b.ne unexpected_sync_exception
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bl disable_mmu_icache_el3
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tlbi alle3
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dsb ish /* ERET implies ISB, so it is not needed here */
|
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#if SPIN_ON_BL1_EXIT
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bl print_debug_loop_message
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debug_loop:
|
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b debug_loop
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#endif
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mov x0, x20
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bl bl1_plat_prepare_exit
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ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
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ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
|
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ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
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ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
|
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exception_return
|
||||
endfunc smc_handler64
|
||||
|
||||
unexpected_sync_exception:
|
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mov x0, #SYNC_EXCEPTION_AARCH64
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||||
bl plat_report_exception
|
||||
no_ret plat_panic_handler
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Save Secure/Normal world context and jump to
|
||||
* BL1 SMC handler.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
smc_handler:
|
||||
/* -----------------------------------------------------
|
||||
* Save x0-x29 and ARMv8.3-PAuth (if enabled) registers.
|
||||
* If Secure Cycle Counter is not disabled in MDCR_EL3
|
||||
* when ARMv8.5-PMU is implemented, save PMCR_EL0 and
|
||||
* disable Cycle Counter.
|
||||
* TODO: Revisit to store only SMCCC specified registers.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
bl prepare_el3_entry
|
||||
|
||||
#if ENABLE_PAUTH
|
||||
/* -----------------------------------------------------
|
||||
* Load and program stored APIAKey firmware key.
|
||||
* Re-enable pointer authentication in EL3, as it was
|
||||
* disabled before jumping to the next boot image.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
bl pauth_load_bl1_apiakey_enable
|
||||
#endif
|
||||
/* -----------------------------------------------------
|
||||
* Populate the parameters for the SMC handler. We
|
||||
* already have x0-x4 in place. x5 will point to a
|
||||
* cookie (not used now). x6 will point to the context
|
||||
* structure (SP_EL3) and x7 will contain flags we need
|
||||
* to pass to the handler.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
mov x5, xzr
|
||||
mov x6, sp
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Restore the saved C runtime stack value which will
|
||||
* become the new SP_EL0 i.e. EL3 runtime stack. It was
|
||||
* saved in the 'cpu_context' structure prior to the last
|
||||
* ERET from EL3.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Switch back to SP_EL0 for the C runtime stack.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
msr spsel, #MODE_SP_EL0
|
||||
mov sp, x12
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there
|
||||
* is a world switch during SMC handling.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
mrs x16, spsr_el3
|
||||
mrs x17, elr_el3
|
||||
mrs x18, scr_el3
|
||||
stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
|
||||
str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
|
||||
|
||||
/* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
|
||||
bfi x7, x18, #0, #1
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Go to BL1 SMC handler.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
bl bl1_smc_handler
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Do the transition to next BL image.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
b el3_exit
|
||||
Reference in New Issue
Block a user