GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include "../bl2_private.h"
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/*******************************************************************************
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* Place holder function to perform any S-EL1 specific architectural setup. At
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* the moment there is nothing to do.
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******************************************************************************/
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void bl2_arch_setup(void)
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{
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/* Give access to FP/SIMD registers */
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write_cpacr(CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE));
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}
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@@ -0,0 +1,72 @@
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/*
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* Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <el3_common_macros.S>
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.globl bl2_entrypoint
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#if BL2_IN_XIP_MEM
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#define FIXUP_SIZE 0
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#else
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#define FIXUP_SIZE ((BL2_LIMIT) - (BL2_BASE))
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#endif
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func bl2_entrypoint
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/* Save arguments x0-x3 from previous Boot loader */
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mov x20, x0
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mov x21, x1
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mov x22, x2
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mov x23, x3
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el3_entrypoint_common \
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_init_sctlr=1 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=bl2_el3_exceptions \
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_pie_fixup_size=FIXUP_SIZE
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/* ---------------------------------------------
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* Restore parameters of boot rom
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* ---------------------------------------------
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*/
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mov x0, x20
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mov x1, x21
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mov x2, x22
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mov x3, x23
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/* ---------------------------------------------
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* Perform BL2 setup
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* ---------------------------------------------
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*/
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bl bl2_el3_setup
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#if ENABLE_PAUTH
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/* ---------------------------------------------
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* Program APIAKey_EL1 and enable pointer authentication.
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* ---------------------------------------------
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*/
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bl pauth_init_enable_el3
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#endif /* ENABLE_PAUTH */
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/* ---------------------------------------------
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* Jump to main function.
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* ---------------------------------------------
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*/
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bl bl2_main
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/* ---------------------------------------------
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* Should never reach this point.
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* ---------------------------------------------
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*/
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no_ret plat_panic_handler
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endfunc bl2_entrypoint
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@@ -0,0 +1,131 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl1/bl1.h>
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#include <common/bl_common.h>
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#include <context.h>
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/* -----------------------------------------------------------------------------
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* Very simple stackless exception handlers used by BL2.
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* -----------------------------------------------------------------------------
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*/
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.globl bl2_el3_exceptions
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vector_base bl2_el3_exceptions
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/* -----------------------------------------------------
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* Current EL with SP0 : 0x0 - 0x200
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionSP0
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mov x0, #SYNC_EXCEPTION_SP_EL0
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SynchronousExceptionSP0
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vector_entry IrqSP0
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mov x0, #IRQ_SP_EL0
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry IrqSP0
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vector_entry FiqSP0
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mov x0, #FIQ_SP_EL0
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry FiqSP0
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vector_entry SErrorSP0
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mov x0, #SERROR_SP_EL0
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SErrorSP0
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/* -----------------------------------------------------
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* Current EL with SPx: 0x200 - 0x400
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionSPx
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mov x0, #SYNC_EXCEPTION_SP_ELX
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SynchronousExceptionSPx
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vector_entry IrqSPx
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mov x0, #IRQ_SP_ELX
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry IrqSPx
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vector_entry FiqSPx
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mov x0, #FIQ_SP_ELX
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry FiqSPx
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vector_entry SErrorSPx
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mov x0, #SERROR_SP_ELX
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SErrorSPx
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/* -----------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionA64
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mov x0, #SYNC_EXCEPTION_AARCH64
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SynchronousExceptionA64
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vector_entry IrqA64
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mov x0, #IRQ_AARCH64
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry IrqA64
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vector_entry FiqA64
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mov x0, #FIQ_AARCH64
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry FiqA64
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vector_entry SErrorA64
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mov x0, #SERROR_AARCH64
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SErrorA64
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/* -----------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionA32
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mov x0, #SYNC_EXCEPTION_AARCH32
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SynchronousExceptionA32
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vector_entry IrqA32
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mov x0, #IRQ_AARCH32
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry IrqA32
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vector_entry FiqA32
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mov x0, #FIQ_AARCH32
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry FiqA32
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vector_entry SErrorA32
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mov x0, #SERROR_AARCH32
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SErrorA32
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@@ -0,0 +1,141 @@
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/*
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* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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.globl bl2_entrypoint
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func bl2_entrypoint
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/*---------------------------------------------
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* Save arguments x0 - x3 from BL1 for future
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* use.
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* ---------------------------------------------
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*/
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mov x20, x0
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mov x21, x1
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mov x22, x2
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mov x23, x3
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/* ---------------------------------------------
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* Set the exception vector to something sane.
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* ---------------------------------------------
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*/
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adr x0, early_exceptions
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msr vbar_el1, x0
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isb
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/* ---------------------------------------------
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* Enable the SError interrupt now that the
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* exception vectors have been setup.
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* ---------------------------------------------
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*/
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msr daifclr, #DAIF_ABT_BIT
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/* ---------------------------------------------
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* Enable the instruction cache, stack pointer
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* and data access alignment checks and disable
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* speculative loads.
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* ---------------------------------------------
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*/
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mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el1
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orr x0, x0, x1
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bic x0, x0, #SCTLR_DSSBS_BIT
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msr sctlr_el1, x0
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isb
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/* ---------------------------------------------
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* Invalidate the RW memory used by the BL2
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* image. This includes the data and NOBITS
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* sections. This is done to safeguard against
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* possible corruption of this memory by dirty
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* cache lines in a system cache as a result of
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* use by an earlier boot loader stage.
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* ---------------------------------------------
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*/
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adr x0, __RW_START__
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adr x1, __RW_END__
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sub x1, x1, x0
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bl inv_dcache_range
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/* ---------------------------------------------
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* Zero out NOBITS sections. There are 2 of them:
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* - the .bss section;
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* - the coherent memory section.
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* ---------------------------------------------
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*/
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adrp x0, __BSS_START__
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add x0, x0, :lo12:__BSS_START__
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adrp x1, __BSS_END__
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add x1, x1, :lo12:__BSS_END__
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sub x1, x1, x0
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bl zeromem
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#if USE_COHERENT_MEM
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adrp x0, __COHERENT_RAM_START__
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add x0, x0, :lo12:__COHERENT_RAM_START__
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adrp x1, __COHERENT_RAM_END_UNALIGNED__
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add x1, x1, :lo12:__COHERENT_RAM_END_UNALIGNED__
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sub x1, x1, x0
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bl zeromem
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#endif
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/* --------------------------------------------
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* Allocate a stack whose memory will be marked
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* as Normal-IS-WBWA when the MMU is enabled.
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* There is no risk of reading stale stack
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* memory after enabling the MMU as only the
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* primary cpu is running at the moment.
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* --------------------------------------------
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*/
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bl plat_set_my_stack
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/* ---------------------------------------------
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* Initialize the stack protector canary before
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* any C code is called.
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* ---------------------------------------------
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*/
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#if STACK_PROTECTOR_ENABLED
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bl update_stack_protector_canary
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#endif
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/* ---------------------------------------------
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* Perform BL2 setup
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* ---------------------------------------------
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*/
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mov x0, x20
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mov x1, x21
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mov x2, x22
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mov x3, x23
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bl bl2_setup
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#if ENABLE_PAUTH
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/* ---------------------------------------------
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* Program APIAKey_EL1
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* and enable pointer authentication.
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* ---------------------------------------------
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*/
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bl pauth_init_enable_el1
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#endif /* ENABLE_PAUTH */
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/* ---------------------------------------------
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* Jump to main function.
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* ---------------------------------------------
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*/
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bl bl2_main
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/* ---------------------------------------------
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* Should never reach this point.
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* ---------------------------------------------
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*/
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no_ret plat_panic_handler
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endfunc bl2_entrypoint
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@@ -0,0 +1,67 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <el3_common_macros.S>
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.globl bl2_entrypoint
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func bl2_entrypoint
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/* Save arguments x0-x3 from previous Boot loader */
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mov x20, x0
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mov x21, x1
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mov x22, x2
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mov x23, x3
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el3_entrypoint_common \
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_init_sctlr=0 \
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_warm_boot_mailbox=0 \
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_secondary_cold_boot=0 \
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_init_memory=0 \
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_init_c_runtime=1 \
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_exception_vectors=bl2_el3_exceptions \
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_pie_fixup_size=0
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/* ---------------------------------------------
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* Restore parameters of boot rom
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* ---------------------------------------------
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*/
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mov x0, x20
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mov x1, x21
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mov x2, x22
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mov x3, x23
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/* ---------------------------------------------
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* Perform BL2 setup
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* ---------------------------------------------
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*/
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bl bl2_setup
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#if ENABLE_PAUTH
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/* ---------------------------------------------
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* Program APIAKey_EL1 and enable pointer authentication.
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* ---------------------------------------------
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*/
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bl pauth_init_enable_el3
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#endif /* ENABLE_PAUTH */
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/* ---------------------------------------------
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* Jump to main function.
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* ---------------------------------------------
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*/
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bl bl2_main
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/* ---------------------------------------------
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* Should never reach this point.
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* ---------------------------------------------
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*/
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no_ret plat_panic_handler
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endfunc bl2_entrypoint
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@@ -0,0 +1,45 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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.globl bl2_run_next_image
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func bl2_run_next_image
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mov x20,x0
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/* ---------------------------------------------
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* MMU needs to be disabled because both BL2 and BL31 execute
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* in EL3, and therefore share the same address space.
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* BL31 will initialize the address space according to its
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* own requirement.
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* ---------------------------------------------
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*/
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bl disable_mmu_icache_el3
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tlbi alle3
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bl bl2_el3_plat_prepare_exit
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#if ENABLE_PAUTH
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/* ---------------------------------------------
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* Disable pointer authentication before jumping
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* to next boot image.
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* ---------------------------------------------
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*/
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bl pauth_disable_el3
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#endif /* ENABLE_PAUTH */
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ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
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msr elr_el3, x0
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msr spsr_el3, x1
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ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
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ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
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ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
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ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
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exception_return
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endfunc bl2_run_next_image
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