GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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Address decoding flow and address translation units of Marvell Armada 8K SoC family
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===================================================================================
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::
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+--------------------------------------------------------------------------------------------------+
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| +-------------+ +--------------+ |
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| | Memory +----- DRAM CS | |
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|+------------+ +-----------+ +-----------+ | Controller | +--------------+ |
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|| AP DMA | | | | | +-------------+ |
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|| SD/eMMC | | CA72 CPUs | | AP MSS | +-------------+ |
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|| MCI-0/1 | | | | | | Memory | |
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|+------+-----+ +--+--------+ +--------+--+ +------------+ | Controller | +-------------+ |
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| | | | | +----- Translaton | |AP | |
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| | | | | | +-------------+ |Configuration| |
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| | | +-----+ +-------------------------Space | |
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| | | +-------------+ | CCU | +-------------+ |
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| | | | MMU +---------+ Windows | +-----------+ +-------------+ |
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| | +-| translation | | Lookup +---- +--------- AP SPI | |
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| | +-------------+ | | | | +-------------+ |
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| | +-------------+ | | | IO | +-------------+ |
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| +------------| SMMU +---------+ | | Windows +--------- AP MCI0/1 | |
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| | translation | +------------+ | Lookup | +-------------+ |
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| +---------+---+ | | +-------------+ |
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| - | | +--------- AP STM | |
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| +----------------- | | +-------------+ |
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| AP | | +-+---------+ |
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+---------------------------------------------------------------|----------------------------------+
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+-------------|-------------------------------------------------|----------------------------------+
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| CP | +-------------+ +------+-----+ +-------------------+ |
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| | | | | +------- SB CFG Space | |
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| | | DIOB | | | +-------------------+ |
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| | | Windows ----------------- IOB | +-------------------+ |
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| | | Control | | Windows +------| SB PCIe-0 - PCIe2 | |
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| | | | | Lookup | +-------------------+ |
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| | +------+------+ | | +-------------------+ |
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| | | | +------+ SB NAND | |
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| | | +------+-----+ +-------------------+ |
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| | | | |
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| | | | |
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| +------------------+ +------------+ +------+-----+ +-------------------+ |
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| | Network Engine | | | | +------- SB SPI-0/SPI-1 | |
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| | Security Engine | | PCIe, MSS | | RUNIT | +-------------------+ |
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| | SATA, USB | | DMA | | Windows | +-------------------+ |
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| | SD/eMMC | | | | Lookup +------- SB Device Bus | |
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| | TDM, I2C | | | | | +-------------------+ |
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| +------------------+ +------------+ +------------+ |
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| |
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+--------------------------------------------------------------------------------------------------+
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+58
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AMB - AXI MBUS address decoding
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===============================
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AXI to M-bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs.
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The Runit offers a second level of address windows lookup. It is used to map
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transaction towards the CD BootROM, SPI0, SPI1 and Device bus (NOR).
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The Runit contains eight configurable windows. Each window defines a contiguous,
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address space and the properties associated with that address space.
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::
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Unit Bank ATTR
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Device-Bus DEV_BOOT_CS 0x2F
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DEV_CS0 0x3E
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DEV_CS1 0x3D
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DEV_CS2 0x3B
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DEV_CS3 0x37
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SPI-0 SPI_A_CS0 0x1E
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SPI_A_CS1 0x5E
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SPI_A_CS2 0x9E
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SPI_A_CS3 0xDE
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SPI_A_CS4 0x1F
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SPI_A_CS5 0x5F
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SPI_A_CS6 0x9F
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SPI_A_CS7 0xDF
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SPI SPI_B_CS0 0x1A
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SPI_B_CS1 0x5A
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SPI_B_CS2 0x9A
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SPI_B_CS3 0xDA
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BOOT_ROM BOOT_ROM 0x1D
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UART UART 0x01
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Mandatory functions
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-------------------
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- marvell_get_amb_memory_map
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Returns the AMB windows configuration and the number of windows
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Mandatory structures
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--------------------
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- amb_memory_map
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Array that include the configuration of the windows. Every window/entry is a
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struct which has 2 parameters:
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- Base address of the window
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- Attribute of the window
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Examples
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--------
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.. code:: c
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struct addr_map_win amb_memory_map[] = {
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{0xf900, AMB_DEV_CS0_ID},
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};
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+33
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Marvell CCU address decoding bindings
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=====================================
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CCU configuration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs.
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The CCU node includes a description of the address decoding configuration.
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Mandatory functions
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-------------------
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- marvell_get_ccu_memory_map
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Return the CCU windows configuration and the number of windows of the
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specific AP.
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Mandatory structures
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--------------------
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- ccu_memory_map
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Array that includes the configuration of the windows. Every window/entry is
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a struct which has 3 parameters:
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- Base address of the window
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- Size of the window
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- Target-ID of the window
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Example
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-------
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.. code:: c
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struct addr_map_win ccu_memory_map[] = {
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{0x00000000f2000000, 0x00000000e000000, IO_0_TID}, /* IO window */
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};
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+46
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Marvell IO WIN address decoding bindings
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========================================
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IO Window configuration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
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The IO WIN includes a description of the address decoding configuration.
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Transactions that are decoded by CCU windows as IO peripheral, have an additional
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layer of decoding. This additional address decoding layer defines one of the
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following targets:
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- **0x0** = BootRom
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- **0x1** = STM (Serial Trace Macro-cell, a programmer's port into trace stream)
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- **0x2** = SPI direct access
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- **0x3** = PCIe registers
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- **0x4** = MCI Port
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- **0x5** = PCIe port
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Mandatory functions
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-------------------
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- marvell_get_io_win_memory_map
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Returns the IO windows configuration and the number of windows of the
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specific AP.
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Mandatory structures
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--------------------
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- io_win_memory_map
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Array that include the configuration of the windows. Every window/entry is
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a struct which has 3 parameters:
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- Base address of the window
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- Size of the window
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- Target-ID of the window
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Example
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-------
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.. code:: c
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struct addr_map_win io_win_memory_map[] = {
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{0x00000000fe000000, 0x000000001f00000, PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/
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{0x00000000ffe00000, 0x000000000100000, PCIE_REGS_TID}, /* PCI-REG window 64Kb for PCIe-reg*/
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{0x00000000f6000000, 0x000000000100000, MCIPHY_TID}, /* MCI window 1Mb for PHY-reg*/
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};
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+52
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Marvell IOB address decoding bindings
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=====================================
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IO bridge configuration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
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The IOB includes a description of the address decoding configuration.
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IOB supports up to n (in CP110 n=24) windows for external memory transaction.
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When a transaction passes through the IOB, its address is compared to each of
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the enabled windows. If there is a hit and it passes the security checks, it is
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advanced to the target port.
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Mandatory functions
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-------------------
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- marvell_get_iob_memory_map
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Returns the IOB windows configuration and the number of windows
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Mandatory structures
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--------------------
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- iob_memory_map
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Array that includes the configuration of the windows. Every window/entry is
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a struct which has 3 parameters:
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- Base address of the window
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- Size of the window
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- Target-ID of the window
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Target ID options
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-----------------
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- **0x0** = Internal configuration space
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- **0x1** = MCI0
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- **0x2** = PEX1_X1
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- **0x3** = PEX2_X1
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- **0x4** = PEX0_X4
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- **0x5** = NAND flash
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- **0x6** = RUNIT (NOR/SPI/BootRoom)
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- **0x7** = MCI1
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Example
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.. code:: c
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struct addr_map_win iob_memory_map[] = {
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{0x00000000f7000000, 0x0000000001000000, PEX1_TID}, /* PEX1_X1 window */
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{0x00000000f8000000, 0x0000000001000000, PEX2_TID}, /* PEX2_X1 window */
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{0x00000000f6000000, 0x0000000001000000, PEX0_TID}, /* PEX0_X4 window */
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{0x00000000f9000000, 0x0000000001000000, NAND_TID} /* NAND window */
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};
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