GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <imx_uart.h>
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#include <platform_def.h>
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.globl imx_crash_uart_init
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.globl imx_crash_uart_putc
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/* -----------------------------------------------
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* int imx_crash_uart_init(uintptr_t base_addr,
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* unsigned int uart_clk, unsigned int baud_rate)
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* Function to initialize the console without a
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* C Runtime to print debug information. This
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* function will be accessed by console_init and
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* crash reporting.
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* In: r0 - console base address
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* r1 - Uart clock in Hz
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* r2 - Baud rate
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* Out: return 1 on success else 0 on error
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* Clobber list : r1, r2, r3, r4
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* -----------------------------------------------
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*/
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func imx_crash_uart_init
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/* Free up r1 as a scratch reg */
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mov r4, r0
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mov r0, r1
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/* Reset UART via CR2 */
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add r1, r4, #IMX_UART_CR2_OFFSET
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movs r3, #0
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str r3, [r4, #IMX_UART_CR2_OFFSET]
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/* Wait for reset complete */
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__wait_cr2_reset:
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ldr r3, [r1, #0]
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ands r3, #IMX_UART_CR2_SRST
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beq __wait_cr2_reset
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/* Enable UART */
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movs r3, #IMX_UART_CR1_UARTEN
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mov r1, r2
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str r3, [r4, #IMX_UART_CR1_OFFSET]
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/*
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* Ignore RTC/CTS - disable reset
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* Magic value #16423 =>
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* IMX_UART_CR2_IRTS | IMX_UART_CR2_WS | IMX_UART_CR2_TXEN | IMX_UART_CR2_RXEN | IMX_UART_CR2_SRST
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*/
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movw r3, #16423
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str r3, [r4, #IMX_UART_CR2_OFFSET]
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/*
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* No parity, autobaud detect-old, rxdmuxsel=1 (fixed i.mx7)
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* Magic value => #132
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* IMX_UART_CR3_ADNIMP | IMX_UART_CR3_RXDMUXSEL
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*/
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movs r3, #132
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str r3, [r4, #IMX_UART_CR3_OFFSET]
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/*
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* Set CTS FIFO trigger to 32 bytes bits 15:10
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* Magic value => #32768
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* FIFO trigger bitmask 100000
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* */
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mov r3, #32768
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str r3, [r4, #IMX_UART_CR4_OFFSET]
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/*
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* TX/RX-thresh = 2 bytes, DCE (bit6 = 0), refclk @24MHz / 4
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* Magic value #2562
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* IMX_UART_FCR_TXTL(TX_RX_THRESH) | IMX_UART_FCR_RXTL(TX_RX_THRESH) | IMX_UART_FCR_RFDIV2
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*/
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#ifdef IMX_UART_DTE
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movw r3, #2626
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#else
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movw r3, #2562
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#endif
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str r3, [r4, #IMX_UART_FCR_OFFSET]
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/* This BIR should be set to 0x0F prior to writing the BMR */
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movs r3, #15
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str r3, [r4, #IMX_UART_BIR_OFFSET]
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/* Hard-code to 115200 @ 24 MHz */
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movs r0, #104
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str r0, [r4, #IMX_UART_BMR_OFFSET]
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/* Indicate success */
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movs r0, #1
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bx lr
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endfunc imx_crash_uart_init
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/* --------------------------------------------------------
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* int imx_crash_uart_putc(int c, uintptr_t base_addr)
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* Function to output a character over the console. It
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* returns the character printed on success or -1 on error.
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* In : r0 - character to be printed
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* r1 - console base address
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* Out : return -1 on error else return character.
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* Clobber list : r2
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* --------------------------------------------------------
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*/
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func imx_crash_uart_putc
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/* Output specified character to UART shift-register */
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str r0, [r1, #IMX_UART_TXD_OFFSET]
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/* Wait for transmit IMX_UART_STAT2_OFFSET.IMX_UART_STAT2_TXDC == 1 */
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__putc_spin_ready:
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ldr r2, [r1, #IMX_UART_STAT2_OFFSET]
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ands r2, #IMX_UART_STAT2_TXDC
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beq __putc_spin_ready
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/* Transmit complete do we need to fixup \n to \n\r */
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cmp r0, #10
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beq __putc_fixup_lf
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/* No fixup necessary - exit here */
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movs r0, #0
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bx lr
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/* Fixup \n to \n\r */
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__putc_fixup_lf:
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movs r0, #13
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b imx_crash_uart_putc
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endfunc imx_crash_uart_putc
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@@ -0,0 +1,181 @@
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/*
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* Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <lib/mmio.h>
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#include <imx_uart.h>
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/* TX/RX FIFO threshold */
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#define TX_RX_THRESH 2
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struct clk_div_factors {
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uint32_t fcr_div;
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uint32_t bmr_div;
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};
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static struct clk_div_factors clk_div[] = {
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{
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.fcr_div = IMX_UART_FCR_RFDIV1,
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.bmr_div = 1,
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},
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{
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.fcr_div = IMX_UART_FCR_RFDIV2,
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.bmr_div = 2,
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},
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{
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.fcr_div = IMX_UART_FCR_RFDIV3,
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.bmr_div = 3,
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},
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{
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.fcr_div = IMX_UART_FCR_RFDIV4,
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.bmr_div = 4,
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},
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{
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.fcr_div = IMX_UART_FCR_RFDIV5,
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.bmr_div = 5,
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},
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{
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.fcr_div = IMX_UART_FCR_RFDIV6,
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.bmr_div = 6,
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},
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{
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.fcr_div = IMX_UART_FCR_RFDIV7,
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.bmr_div = 7,
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},
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};
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static void write_reg(uintptr_t base, uint32_t offset, uint32_t val)
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{
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mmio_write_32(base + offset, val);
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}
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static uint32_t read_reg(uintptr_t base, uint32_t offset)
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{
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return mmio_read_32(base + offset);
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}
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int console_imx_uart_core_init(uintptr_t base_addr, unsigned int uart_clk,
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unsigned int baud_rate)
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{
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uint32_t val;
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uint8_t clk_idx = 1;
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/* Reset UART */
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write_reg(base_addr, IMX_UART_CR2_OFFSET, 0);
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do {
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val = read_reg(base_addr, IMX_UART_CR2_OFFSET);
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} while (!(val & IMX_UART_CR2_SRST));
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/* Enable UART */
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write_reg(base_addr, IMX_UART_CR1_OFFSET, IMX_UART_CR1_UARTEN);
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/* Ignore RTS, 8N1, enable tx/rx, disable reset */
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val = (IMX_UART_CR2_IRTS | IMX_UART_CR2_WS | IMX_UART_CR2_TXEN |
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IMX_UART_CR2_RXEN | IMX_UART_CR2_SRST);
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write_reg(base_addr, IMX_UART_CR2_OFFSET, val);
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/* No parity, autobaud detect-old, rxdmuxsel=1 (fixed i.mx7) */
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val = IMX_UART_CR3_ADNIMP | IMX_UART_CR3_RXDMUXSEL;
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write_reg(base_addr, IMX_UART_CR3_OFFSET, val);
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/* Set CTS FIFO trigger to 32 bytes bits 15:10 */
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write_reg(base_addr, IMX_UART_CR4_OFFSET, 0x8000);
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/* TX/RX-thresh = 2 bytes, DTE (bit6 = 0), refclk @24MHz / 4 */
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val = IMX_UART_FCR_TXTL(TX_RX_THRESH) | IMX_UART_FCR_RXTL(TX_RX_THRESH) |
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clk_div[clk_idx].fcr_div;
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#ifdef IMX_UART_DTE
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/* Set DTE (bit6 = 1) */
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val |= IMX_UART_FCR_DCEDTE;
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#endif
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write_reg(base_addr, IMX_UART_FCR_OFFSET, val);
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/*
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* The equation for BAUD rate calculation is
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* RefClk = Supplied clock / FCR_DIVx
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*
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* BAUD = Refclk
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* ------------
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* 16 x (UBMR + 1/ UBIR + 1)
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*
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* We write 0x0f into UBIR to remove the 16 mult
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* BAUD = 6000000
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* ------------
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* 16 x (UBMR + 1/ 15 + 1)
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*/
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write_reg(base_addr, IMX_UART_BIR_OFFSET, 0x0f);
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val = ((uart_clk / clk_div[clk_idx].bmr_div) / baud_rate) - 1;
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write_reg(base_addr, IMX_UART_BMR_OFFSET, val);
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return 0;
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}
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/* --------------------------------------------------------
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* int console_core_putc(int c, uintptr_t base_addr)
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* Function to output a character over the console. It
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* returns the character printed on success or -1 on error.
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* In : r0 - character to be printed
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* r1 - console base address
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* Out : return -1 on error else return character.
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* Clobber list : r2
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* --------------------------------------------------------
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*/
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int console_imx_uart_core_putc(int c, uintptr_t base_addr)
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{
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uint32_t val;
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if (c == '\n')
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console_imx_uart_core_putc('\r', base_addr);
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/* Write data */
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write_reg(base_addr, IMX_UART_TXD_OFFSET, c);
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/* Wait for transmit */
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do {
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val = read_reg(base_addr, IMX_UART_STAT2_OFFSET);
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} while (!(val & IMX_UART_STAT2_TXDC));
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return 0;
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}
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/*
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* Function to get a character from the console.
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* It returns the character grabbed on success
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* or -1 on error.
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* In : r0 - console base address
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* Clobber list : r0, r1
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* ---------------------------------------------
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*/
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int console_imx_uart_core_getc(uintptr_t base_addr)
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{
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uint32_t val;
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val = read_reg(base_addr, IMX_UART_TS_OFFSET);
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if (val & IMX_UART_TS_RXEMPTY)
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return -1;
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val = read_reg(base_addr, IMX_UART_RXD_OFFSET);
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return (int)(val & 0x000000FF);
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}
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/*
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* Function to force a write of all buffered
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* data that hasn't been output.
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* In : r0 - console base address
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* Out : void
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* Clobber list : r0, r1
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* ---------------------------------------------
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*/
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void console_imx_uart_core_flush(uintptr_t base_addr)
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{
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}
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@@ -0,0 +1,163 @@
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/*
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* Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef IMX_UART_H
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#define IMX_UART_H
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#include <drivers/console.h>
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#define IMX_UART_RXD_OFFSET 0x00
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#define IMX_UART_RXD_CHARRDY BIT(15)
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#define IMX_UART_RXD_ERR BIT(14)
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#define IMX_UART_RXD_OVERRUN BIT(13)
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#define IMX_UART_RXD_FRMERR BIT(12)
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#define IMX_UART_RXD_BRK BIT(11)
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#define IMX_UART_RXD_PRERR BIT(10)
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#define IMX_UART_TXD_OFFSET 0x40
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#define IMX_UART_CR1_OFFSET 0x80
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#define IMX_UART_CR1_ADEN BIT(15)
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#define IMX_UART_CR1_ADBR BIT(14)
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#define IMX_UART_CR1_TRDYEN BIT(13)
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#define IMX_UART_CR1_IDEN BIT(12)
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#define IMX_UART_CR1_RRDYEN BIT(9)
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#define IMX_UART_CR1_RXDMAEN BIT(8)
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#define IMX_UART_CR1_IREN BIT(7)
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#define IMX_UART_CR1_TXMPTYEN BIT(6)
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#define IMX_UART_CR1_RTSDEN BIT(5)
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#define IMX_UART_CR1_SNDBRK BIT(4)
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#define IMX_UART_CR1_TXDMAEN BIT(3)
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#define IMX_UART_CR1_ATDMAEN BIT(2)
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#define IMX_UART_CR1_DOZE BIT(1)
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#define IMX_UART_CR1_UARTEN BIT(0)
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#define IMX_UART_CR2_OFFSET 0x84
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#define IMX_UART_CR2_ESCI BIT(15)
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#define IMX_UART_CR2_IRTS BIT(14)
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#define IMX_UART_CR2_CTSC BIT(13)
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#define IMX_UART_CR2_CTS BIT(12)
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#define IMX_UART_CR2_ESCEN BIT(11)
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#define IMX_UART_CR2_PREN BIT(8)
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#define IMX_UART_CR2_PROE BIT(7)
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#define IMX_UART_CR2_STPB BIT(6)
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#define IMX_UART_CR2_WS BIT(5)
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#define IMX_UART_CR2_RTSEN BIT(4)
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#define IMX_UART_CR2_ATEN BIT(3)
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#define IMX_UART_CR2_TXEN BIT(2)
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#define IMX_UART_CR2_RXEN BIT(1)
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#define IMX_UART_CR2_SRST BIT(0)
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#define IMX_UART_CR3_OFFSET 0x88
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#define IMX_UART_CR3_DTREN BIT(13)
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#define IMX_UART_CR3_PARERREN BIT(12)
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#define IMX_UART_CR3_FARERREN BIT(11)
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#define IMX_UART_CR3_DSD BIT(10)
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#define IMX_UART_CR3_DCD BIT(9)
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#define IMX_UART_CR3_RI BIT(8)
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#define IMX_UART_CR3_ADNIMP BIT(7)
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#define IMX_UART_CR3_RXDSEN BIT(6)
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#define IMX_UART_CR3_AIRINTEN BIT(5)
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#define IMX_UART_CR3_AWAKEN BIT(4)
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#define IMX_UART_CR3_DTRDEN BIT(3)
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#define IMX_UART_CR3_RXDMUXSEL BIT(2)
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#define IMX_UART_CR3_INVT BIT(1)
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#define IMX_UART_CR3_ACIEN BIT(0)
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#define IMX_UART_CR4_OFFSET 0x8c
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#define IMX_UART_CR4_INVR BIT(9)
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#define IMX_UART_CR4_ENIRI BIT(8)
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#define IMX_UART_CR4_WKEN BIT(7)
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#define IMX_UART_CR4_IDDMAEN BIT(6)
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#define IMX_UART_CR4_IRSC BIT(5)
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#define IMX_UART_CR4_LPBYP BIT(4)
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#define IMX_UART_CR4_TCEN BIT(3)
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#define IMX_UART_CR4_BKEN BIT(2)
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#define IMX_UART_CR4_OREN BIT(1)
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#define IMX_UART_CR4_DREN BIT(0)
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#define IMX_UART_FCR_OFFSET 0x90
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#define IMX_UART_FCR_TXTL_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12) |\
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BIT(11) | BIT(10))
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#define IMX_UART_FCR_TXTL(x) ((x) << 10)
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#define IMX_UART_FCR_RFDIV_MASK (BIT(9) | BIT(8) | BIT(7))
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#define IMX_UART_FCR_RFDIV7 (BIT(9) | BIT(8))
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#define IMX_UART_FCR_RFDIV1 (BIT(9) | BIT(7))
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#define IMX_UART_FCR_RFDIV2 BIT(9)
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#define IMX_UART_FCR_RFDIV3 (BIT(8) | BIT(7))
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#define IMX_UART_FCR_RFDIV4 BIT(8)
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#define IMX_UART_FCR_RFDIV5 BIT(7)
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#define IMX_UART_FCR_RFDIV6 0
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#define IMX_UART_FCR_DCEDTE BIT(6)
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#define IMX_UART_FCR_RXTL_MASK (BIT(5) | BIT(4) | BIT(3) | BIT(2) |\
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BIT(1) | BIT(0))
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#define IMX_UART_FCR_RXTL(x) x
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#define IMX_UART_STAT1_OFFSET 0x94
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#define IMX_UART_STAT1_PARITYERR BIT(15)
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#define IMX_UART_STAT1_RTSS BIT(14)
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#define IMX_UART_STAT1_TRDY BIT(13)
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#define IMX_UART_STAT1_RTSD BIT(12)
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#define IMX_UART_STAT1_ESCF BIT(11)
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#define IMX_UART_STAT1_FRAMEERR BIT(10)
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#define IMX_UART_STAT1_RRDY BIT(9)
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#define IMX_UART_STAT1_AGTIM BIT(8)
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#define IMX_UART_STAT1_DTRD BIT(7)
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#define IMX_UART_STAT1_RXDS BIT(6)
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#define IMX_UART_STAT1_AIRINT BIT(5)
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#define IMX_UART_STAT1_AWAKE BIT(4)
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#define IMX_UART_STAT1_SAD BIT(3)
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#define IMX_UART_STAT2_OFFSET 0x98
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||||
#define IMX_UART_STAT2_ADET BIT(15)
|
||||
#define IMX_UART_STAT2_TXFE BIT(14)
|
||||
#define IMX_UART_STAT2_DTRF BIT(13)
|
||||
#define IMX_UART_STAT2_IDLE BIT(12)
|
||||
#define IMX_UART_STAT2_ACST BIT(11)
|
||||
#define IMX_UART_STAT2_RIDELT BIT(10)
|
||||
#define IMX_UART_STAT2_RIIN BIT(9)
|
||||
#define IMX_UART_STAT2_IRINT BIT(8)
|
||||
#define IMX_UART_STAT2_WAKE BIT(7)
|
||||
#define IMX_UART_STAT2_DCDDELT BIT(6)
|
||||
#define IMX_UART_STAT2_DCDIN BIT(5)
|
||||
#define IMX_UART_STAT2_RTSF BIT(4)
|
||||
#define IMX_UART_STAT2_TXDC BIT(3)
|
||||
#define IMX_UART_STAT2_BRCD BIT(2)
|
||||
#define IMX_UART_STAT2_ORE BIT(1)
|
||||
#define IMX_UART_STAT2_RCR BIT(0)
|
||||
|
||||
#define IMX_UART_ESC_OFFSET 0x9c
|
||||
|
||||
#define IMX_UART_TIM_OFFSET 0xa0
|
||||
|
||||
#define IMX_UART_BIR_OFFSET 0xa4
|
||||
|
||||
#define IMX_UART_BMR_OFFSET 0xa8
|
||||
|
||||
#define IMX_UART_BRC_OFFSET 0xac
|
||||
|
||||
#define IMX_UART_ONEMS_OFFSET 0xb0
|
||||
|
||||
#define IMX_UART_TS_OFFSET 0xb4
|
||||
#define IMX_UART_TS_FRCPERR BIT(13)
|
||||
#define IMX_UART_TS_LOOP BIT(12)
|
||||
#define IMX_UART_TS_DBGEN BIT(11)
|
||||
#define IMX_UART_TS_LOOPIR BIT(10)
|
||||
#define IMX_UART_TS_RXDBG BIT(9)
|
||||
#define IMX_UART_TS_TXEMPTY BIT(6)
|
||||
#define IMX_UART_TS_RXEMPTY BIT(5)
|
||||
#define IMX_UART_TS_TXFULL BIT(4)
|
||||
#define IMX_UART_TS_RXFULL BIT(3)
|
||||
#define IMX_UART_TS_SOFTRST BIT(0)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
int console_imx_uart_register(uintptr_t baseaddr,
|
||||
uint32_t clock,
|
||||
uint32_t baud,
|
||||
console_t *console);
|
||||
#endif /*__ASSEMBLER__*/
|
||||
|
||||
#endif /* IMX_UART_H */
|
||||
Reference in New Issue
Block a user