GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <lib/mmio.h>
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#include <imx_uart.h>
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/* TX/RX FIFO threshold */
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#define TX_RX_THRESH 2
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struct clk_div_factors {
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uint32_t fcr_div;
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uint32_t bmr_div;
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};
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static struct clk_div_factors clk_div[] = {
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{
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.fcr_div = IMX_UART_FCR_RFDIV1,
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.bmr_div = 1,
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},
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{
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.fcr_div = IMX_UART_FCR_RFDIV2,
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.bmr_div = 2,
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},
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{
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.fcr_div = IMX_UART_FCR_RFDIV3,
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.bmr_div = 3,
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},
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{
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.fcr_div = IMX_UART_FCR_RFDIV4,
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.bmr_div = 4,
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},
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{
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.fcr_div = IMX_UART_FCR_RFDIV5,
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.bmr_div = 5,
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},
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{
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.fcr_div = IMX_UART_FCR_RFDIV6,
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.bmr_div = 6,
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},
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{
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.fcr_div = IMX_UART_FCR_RFDIV7,
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.bmr_div = 7,
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},
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};
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static void write_reg(uintptr_t base, uint32_t offset, uint32_t val)
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{
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mmio_write_32(base + offset, val);
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}
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static uint32_t read_reg(uintptr_t base, uint32_t offset)
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{
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return mmio_read_32(base + offset);
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}
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int console_imx_uart_core_init(uintptr_t base_addr, unsigned int uart_clk,
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unsigned int baud_rate)
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{
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uint32_t val;
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uint8_t clk_idx = 1;
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/* Reset UART */
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write_reg(base_addr, IMX_UART_CR2_OFFSET, 0);
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do {
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val = read_reg(base_addr, IMX_UART_CR2_OFFSET);
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} while (!(val & IMX_UART_CR2_SRST));
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/* Enable UART */
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write_reg(base_addr, IMX_UART_CR1_OFFSET, IMX_UART_CR1_UARTEN);
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/* Ignore RTS, 8N1, enable tx/rx, disable reset */
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val = (IMX_UART_CR2_IRTS | IMX_UART_CR2_WS | IMX_UART_CR2_TXEN |
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IMX_UART_CR2_RXEN | IMX_UART_CR2_SRST);
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write_reg(base_addr, IMX_UART_CR2_OFFSET, val);
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/* No parity, autobaud detect-old, rxdmuxsel=1 (fixed i.mx7) */
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val = IMX_UART_CR3_ADNIMP | IMX_UART_CR3_RXDMUXSEL;
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write_reg(base_addr, IMX_UART_CR3_OFFSET, val);
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/* Set CTS FIFO trigger to 32 bytes bits 15:10 */
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write_reg(base_addr, IMX_UART_CR4_OFFSET, 0x8000);
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/* TX/RX-thresh = 2 bytes, DTE (bit6 = 0), refclk @24MHz / 4 */
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val = IMX_UART_FCR_TXTL(TX_RX_THRESH) | IMX_UART_FCR_RXTL(TX_RX_THRESH) |
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clk_div[clk_idx].fcr_div;
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#ifdef IMX_UART_DTE
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/* Set DTE (bit6 = 1) */
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val |= IMX_UART_FCR_DCEDTE;
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#endif
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write_reg(base_addr, IMX_UART_FCR_OFFSET, val);
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/*
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* The equation for BAUD rate calculation is
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* RefClk = Supplied clock / FCR_DIVx
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*
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* BAUD = Refclk
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* ------------
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* 16 x (UBMR + 1/ UBIR + 1)
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*
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* We write 0x0f into UBIR to remove the 16 mult
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* BAUD = 6000000
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* ------------
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* 16 x (UBMR + 1/ 15 + 1)
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*/
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write_reg(base_addr, IMX_UART_BIR_OFFSET, 0x0f);
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val = ((uart_clk / clk_div[clk_idx].bmr_div) / baud_rate) - 1;
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write_reg(base_addr, IMX_UART_BMR_OFFSET, val);
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return 0;
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}
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/* --------------------------------------------------------
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* int console_core_putc(int c, uintptr_t base_addr)
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* Function to output a character over the console. It
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* returns the character printed on success or -1 on error.
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* In : r0 - character to be printed
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* r1 - console base address
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* Out : return -1 on error else return character.
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* Clobber list : r2
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* --------------------------------------------------------
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*/
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int console_imx_uart_core_putc(int c, uintptr_t base_addr)
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{
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uint32_t val;
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if (c == '\n')
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console_imx_uart_core_putc('\r', base_addr);
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/* Write data */
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write_reg(base_addr, IMX_UART_TXD_OFFSET, c);
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/* Wait for transmit */
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do {
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val = read_reg(base_addr, IMX_UART_STAT2_OFFSET);
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} while (!(val & IMX_UART_STAT2_TXDC));
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return 0;
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}
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/*
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* Function to get a character from the console.
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* It returns the character grabbed on success
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* or -1 on error.
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* In : r0 - console base address
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* Clobber list : r0, r1
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* ---------------------------------------------
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*/
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int console_imx_uart_core_getc(uintptr_t base_addr)
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{
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uint32_t val;
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val = read_reg(base_addr, IMX_UART_TS_OFFSET);
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if (val & IMX_UART_TS_RXEMPTY)
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return -1;
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val = read_reg(base_addr, IMX_UART_RXD_OFFSET);
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return (int)(val & 0x000000FF);
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}
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/*
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* Function to force a write of all buffered
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* data that hasn't been output.
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* In : r0 - console base address
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* Out : void
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* Clobber list : r0, r1
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* ---------------------------------------------
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*/
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void console_imx_uart_core_flush(uintptr_t base_addr)
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{
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}
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