GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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/* IO Window unit device driver for Marvell AP807, AP807 and AP810 SoCs */
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#include <inttypes.h>
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#include <stdint.h>
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#include <common/debug.h>
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#include <drivers/marvell/io_win.h>
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#include <lib/mmio.h>
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#include <armada_common.h>
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#include <mvebu.h>
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#include <mvebu_def.h>
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#if LOG_LEVEL >= LOG_LEVEL_INFO
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#define DEBUG_ADDR_MAP
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#endif
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/* common defines */
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#define WIN_ENABLE_BIT (0x1)
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/* Physical address of the base of the window = {Addr[19:0],20`h0} */
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#define ADDRESS_SHIFT (20 - 4)
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#define ADDRESS_MASK (0xFFFFFFF0)
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#define IO_WIN_ALIGNMENT_1M (0x100000)
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#define IO_WIN_ALIGNMENT_64K (0x10000)
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/* AP registers */
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#define IO_WIN_ALR_OFFSET(ap, win) (MVEBU_IO_WIN_BASE(ap) + 0x0 + \
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(0x10 * win))
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#define IO_WIN_AHR_OFFSET(ap, win) (MVEBU_IO_WIN_BASE(ap) + 0x8 + \
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(0x10 * win))
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#define IO_WIN_CR_OFFSET(ap, win) (MVEBU_IO_WIN_BASE(ap) + 0xC + \
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(0x10 * win))
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/* For storage of CR, ALR, AHR abd GCR */
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static uint32_t io_win_regs_save[MVEBU_IO_WIN_MAX_WINS * 3 + 1];
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static void io_win_check(struct addr_map_win *win)
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{
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/* for IO The base is always 1M aligned */
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/* check if address is aligned to 1M */
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if (IS_NOT_ALIGN(win->base_addr, IO_WIN_ALIGNMENT_1M)) {
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win->base_addr = ALIGN_UP(win->base_addr, IO_WIN_ALIGNMENT_1M);
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NOTICE("%s: Align up the base address to 0x%" PRIx64 "\n",
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__func__, win->base_addr);
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}
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/* size parameter validity check */
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if (IS_NOT_ALIGN(win->win_size, IO_WIN_ALIGNMENT_1M)) {
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win->win_size = ALIGN_UP(win->win_size, IO_WIN_ALIGNMENT_1M);
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NOTICE("%s: Aligning size to 0x%" PRIx64 "\n",
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__func__, win->win_size);
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}
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}
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static void io_win_enable_window(int ap_index, struct addr_map_win *win,
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uint32_t win_num)
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{
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uint32_t alr, ahr;
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uint64_t end_addr;
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if (win->target_id < 0 || win->target_id >= MVEBU_IO_WIN_MAX_WINS) {
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ERROR("target ID = %d, is invalid\n", win->target_id);
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return;
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}
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if ((win_num == 0) || (win_num > MVEBU_IO_WIN_MAX_WINS)) {
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ERROR("Enabling wrong IOW window %d!\n", win_num);
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return;
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}
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/* calculate the end-address */
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end_addr = (win->base_addr + win->win_size - 1);
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alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK);
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alr |= WIN_ENABLE_BIT;
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ahr = (uint32_t)((end_addr >> ADDRESS_SHIFT) & ADDRESS_MASK);
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/* write start address and end address for IO window */
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mmio_write_32(IO_WIN_ALR_OFFSET(ap_index, win_num), alr);
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mmio_write_32(IO_WIN_AHR_OFFSET(ap_index, win_num), ahr);
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/* write window target */
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mmio_write_32(IO_WIN_CR_OFFSET(ap_index, win_num), win->target_id);
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}
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static void io_win_disable_window(int ap_index, uint32_t win_num)
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{
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uint32_t win_reg;
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if ((win_num == 0) || (win_num > MVEBU_IO_WIN_MAX_WINS)) {
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ERROR("Disabling wrong IOW window %d!\n", win_num);
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return;
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}
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win_reg = mmio_read_32(IO_WIN_ALR_OFFSET(ap_index, win_num));
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win_reg &= ~WIN_ENABLE_BIT;
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mmio_write_32(IO_WIN_ALR_OFFSET(ap_index, win_num), win_reg);
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}
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/* Insert/Remove temporary window for using the out-of reset default
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* CPx base address to access the CP configuration space prior to
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* the further base address update in accordance with address mapping
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* design.
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*
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* NOTE: Use the same window array for insertion and removal of
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* temporary windows.
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*/
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void iow_temp_win_insert(int ap_index, struct addr_map_win *win, int size)
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{
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uint32_t win_id;
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for (int i = 0; i < size; i++) {
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win_id = MVEBU_IO_WIN_MAX_WINS - i - 1;
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io_win_check(win);
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io_win_enable_window(ap_index, win, win_id);
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win++;
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}
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}
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/*
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* NOTE: Use the same window array for insertion and removal of
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* temporary windows.
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*/
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void iow_temp_win_remove(int ap_index, struct addr_map_win *win, int size)
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{
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uint32_t win_id;
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/* Start from the last window and do not touch Win0 */
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for (int i = 0; i < size; i++) {
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uint64_t base;
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uint32_t target;
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win_id = MVEBU_IO_WIN_MAX_WINS - i - 1;
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target = mmio_read_32(IO_WIN_CR_OFFSET(ap_index, win_id));
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base = mmio_read_32(IO_WIN_ALR_OFFSET(ap_index, win_id));
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base &= ~WIN_ENABLE_BIT;
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base <<= ADDRESS_SHIFT;
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if ((win->target_id != target) || (win->base_addr != base)) {
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ERROR("%s: Trying to remove bad window-%d!\n",
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__func__, win_id);
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continue;
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}
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io_win_disable_window(ap_index, win_id);
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win++;
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}
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}
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#ifdef DEBUG_ADDR_MAP
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static void dump_io_win(int ap_index)
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{
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uint32_t trgt_id, win_id;
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uint32_t alr, ahr;
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uint64_t start, end;
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/* Dump all IO windows */
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printf("\tbank target start end\n");
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printf("\t----------------------------------------------------\n");
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for (win_id = 0; win_id < MVEBU_IO_WIN_MAX_WINS; win_id++) {
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alr = mmio_read_32(IO_WIN_ALR_OFFSET(ap_index, win_id));
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if (alr & WIN_ENABLE_BIT) {
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alr &= ~WIN_ENABLE_BIT;
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ahr = mmio_read_32(IO_WIN_AHR_OFFSET(ap_index, win_id));
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trgt_id = mmio_read_32(IO_WIN_CR_OFFSET(ap_index,
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win_id));
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start = ((uint64_t)alr << ADDRESS_SHIFT);
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end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT);
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printf("\tio-win %d 0x%016" PRIx64 " 0x%016" PRIx64 "\n",
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trgt_id, start, end);
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}
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}
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printf("\tio-win gcr is %x\n",
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mmio_read_32(MVEBU_IO_WIN_BASE(ap_index) +
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MVEBU_IO_WIN_GCR_OFFSET));
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}
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#endif
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static void iow_save_win_range(int ap_id, int win_first, int win_last,
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uint32_t *buffer)
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{
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int win_id, idx;
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/* Save IOW */
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for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) {
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buffer[idx++] = mmio_read_32(IO_WIN_CR_OFFSET(ap_id, win_id));
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buffer[idx++] = mmio_read_32(IO_WIN_ALR_OFFSET(ap_id, win_id));
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buffer[idx++] = mmio_read_32(IO_WIN_AHR_OFFSET(ap_id, win_id));
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}
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buffer[idx] = mmio_read_32(MVEBU_IO_WIN_BASE(ap_id) +
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MVEBU_IO_WIN_GCR_OFFSET);
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}
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static void iow_restore_win_range(int ap_id, int win_first, int win_last,
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uint32_t *buffer)
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{
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int win_id, idx;
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/* Restore IOW */
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for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) {
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mmio_write_32(IO_WIN_CR_OFFSET(ap_id, win_id), buffer[idx++]);
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mmio_write_32(IO_WIN_ALR_OFFSET(ap_id, win_id), buffer[idx++]);
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mmio_write_32(IO_WIN_AHR_OFFSET(ap_id, win_id), buffer[idx++]);
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}
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mmio_write_32(MVEBU_IO_WIN_BASE(ap_id) + MVEBU_IO_WIN_GCR_OFFSET,
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buffer[idx++]);
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}
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void iow_save_win_all(int ap_id)
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{
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iow_save_win_range(ap_id, 0, MVEBU_IO_WIN_MAX_WINS - 1,
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io_win_regs_save);
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}
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void iow_restore_win_all(int ap_id)
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{
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iow_restore_win_range(ap_id, 0, MVEBU_IO_WIN_MAX_WINS - 1,
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io_win_regs_save);
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}
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int init_io_win(int ap_index)
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{
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struct addr_map_win *win;
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uint32_t win_id, win_reg;
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uint32_t win_count;
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INFO("Initializing IO WIN Address decoding\n");
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/* Get the array of the windows and its size */
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marvell_get_io_win_memory_map(ap_index, &win, &win_count);
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if (win_count <= 0)
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INFO("no windows configurations found\n");
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if (win_count > MVEBU_IO_WIN_MAX_WINS) {
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INFO("number of windows is bigger than %d\n",
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MVEBU_IO_WIN_MAX_WINS);
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return 0;
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}
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/* Get the default target id to set the GCR */
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win_reg = marvell_get_io_win_gcr_target(ap_index);
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mmio_write_32(MVEBU_IO_WIN_BASE(ap_index) + MVEBU_IO_WIN_GCR_OFFSET,
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win_reg);
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/* disable all IO windows */
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for (win_id = 1; win_id < MVEBU_IO_WIN_MAX_WINS; win_id++)
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io_win_disable_window(ap_index, win_id);
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/* enable relevant windows, starting from win_id = 1 because
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* index 0 dedicated for BootROM
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*/
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for (win_id = 1; win_id <= win_count; win_id++, win++) {
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io_win_check(win);
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io_win_enable_window(ap_index, win, win_id);
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}
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#ifdef DEBUG_ADDR_MAP
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dump_io_win(ap_index);
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#endif
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INFO("Done IO WIN Address decoding Initializing\n");
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return 0;
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}
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