GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,176 @@
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/*
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* Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stddef.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <drivers/nand.h>
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#include <lib/utils.h>
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#include <platform_def.h>
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/*
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* Define a single nand_device used by specific NAND frameworks.
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*/
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static struct nand_device nand_dev;
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#pragma weak plat_get_scratch_buffer
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void plat_get_scratch_buffer(void **buffer_addr, size_t *buf_size)
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{
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static uint8_t scratch_buff[PLATFORM_MTD_MAX_PAGE_SIZE];
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assert(buffer_addr != NULL);
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assert(buf_size != NULL);
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*buffer_addr = (void *)scratch_buff;
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*buf_size = sizeof(scratch_buff);
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}
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int nand_read(unsigned int offset, uintptr_t buffer, size_t length,
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size_t *length_read)
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{
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unsigned int block = offset / nand_dev.block_size;
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unsigned int end_block = (offset + length - 1U) / nand_dev.block_size;
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unsigned int page_start =
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(offset % nand_dev.block_size) / nand_dev.page_size;
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unsigned int nb_pages = nand_dev.block_size / nand_dev.page_size;
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unsigned int start_offset = offset % nand_dev.page_size;
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unsigned int page;
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unsigned int bytes_read;
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int is_bad;
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int ret;
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uint8_t *scratch_buff;
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size_t scratch_buff_size;
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plat_get_scratch_buffer((void **)&scratch_buff, &scratch_buff_size);
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assert(scratch_buff != NULL);
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VERBOSE("Block %u - %u, page_start %u, nb %u, length %zu, offset %u\n",
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block, end_block, page_start, nb_pages, length, offset);
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*length_read = 0UL;
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if (((start_offset != 0U) || (length % nand_dev.page_size) != 0U) &&
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(scratch_buff_size < nand_dev.page_size)) {
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return -EINVAL;
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}
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while (block <= end_block) {
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is_bad = nand_dev.mtd_block_is_bad(block);
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if (is_bad < 0) {
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return is_bad;
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}
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if (is_bad == 1) {
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/* Skip the block */
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uint32_t max_block =
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nand_dev.size / nand_dev.block_size;
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block++;
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end_block++;
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if ((block < max_block) && (end_block < max_block)) {
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continue;
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}
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return -EIO;
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}
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for (page = page_start; page < nb_pages; page++) {
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if ((start_offset != 0U) ||
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(length < nand_dev.page_size)) {
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ret = nand_dev.mtd_read_page(
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&nand_dev,
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(block * nb_pages) + page,
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(uintptr_t)scratch_buff);
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if (ret != 0) {
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return ret;
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}
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bytes_read = MIN((size_t)(nand_dev.page_size -
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start_offset),
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length);
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memcpy((uint8_t *)buffer,
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scratch_buff + start_offset,
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bytes_read);
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start_offset = 0U;
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} else {
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ret = nand_dev.mtd_read_page(&nand_dev,
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(block * nb_pages) + page,
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buffer);
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if (ret != 0) {
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return ret;
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}
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bytes_read = nand_dev.page_size;
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}
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length -= bytes_read;
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buffer += bytes_read;
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*length_read += bytes_read;
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if (length == 0U) {
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break;
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}
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}
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page_start = 0U;
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block++;
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}
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return 0;
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}
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int nand_seek_bb(uintptr_t base, unsigned int offset, size_t *extra_offset)
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{
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unsigned int block;
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unsigned int offset_block;
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unsigned int max_block;
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int is_bad;
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size_t count_bb = 0U;
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block = base / nand_dev.block_size;
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if (offset != 0U) {
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offset_block = (base + offset - 1U) / nand_dev.block_size;
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} else {
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offset_block = block;
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}
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max_block = nand_dev.size / nand_dev.block_size;
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while (block <= offset_block) {
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if (offset_block >= max_block) {
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return -EIO;
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}
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is_bad = nand_dev.mtd_block_is_bad(block);
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if (is_bad < 0) {
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return is_bad;
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}
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if (is_bad == 1) {
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count_bb++;
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offset_block++;
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}
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block++;
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}
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*extra_offset = count_bb * nand_dev.block_size;
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return 0;
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}
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struct nand_device *get_nand_device(void)
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{
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return &nand_dev;
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}
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@@ -0,0 +1,443 @@
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/*
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* Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stddef.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <drivers/raw_nand.h>
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#include <lib/utils.h>
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#include <platform_def.h>
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#define ONFI_SIGNATURE_ADDR 0x20U
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/* CRC calculation */
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#define CRC_POLYNOM 0x8005U
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#define CRC_INIT_VALUE 0x4F4EU
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/* Status register */
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#define NAND_STATUS_READY BIT(6)
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static struct rawnand_device rawnand_dev;
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#pragma weak plat_get_raw_nand_data
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int plat_get_raw_nand_data(struct rawnand_device *device)
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{
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return 0;
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}
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static int nand_send_cmd(uint8_t cmd, unsigned int tim)
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{
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struct nand_req req;
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zeromem(&req, sizeof(struct nand_req));
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req.nand = rawnand_dev.nand_dev;
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req.type = NAND_REQ_CMD | cmd;
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req.inst_delay = tim;
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return rawnand_dev.ops->exec(&req);
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}
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static int nand_send_addr(uint8_t addr, unsigned int tim)
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{
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struct nand_req req;
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zeromem(&req, sizeof(struct nand_req));
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req.nand = rawnand_dev.nand_dev;
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req.type = NAND_REQ_ADDR;
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req.addr = &addr;
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req.inst_delay = tim;
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return rawnand_dev.ops->exec(&req);
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}
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static int nand_send_wait(unsigned int delay, unsigned int tim)
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{
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struct nand_req req;
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zeromem(&req, sizeof(struct nand_req));
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req.nand = rawnand_dev.nand_dev;
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req.type = NAND_REQ_WAIT;
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req.inst_delay = tim;
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req.delay_ms = delay;
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return rawnand_dev.ops->exec(&req);
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}
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static int nand_read_data(uint8_t *data, unsigned int length, bool use_8bit)
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{
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struct nand_req req;
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zeromem(&req, sizeof(struct nand_req));
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req.nand = rawnand_dev.nand_dev;
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req.type = NAND_REQ_DATAIN | (use_8bit ? NAND_REQ_BUS_WIDTH_8 : 0U);
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req.addr = data;
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req.length = length;
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return rawnand_dev.ops->exec(&req);
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}
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int nand_change_read_column_cmd(unsigned int offset, uintptr_t buffer,
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unsigned int len)
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{
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int ret;
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uint8_t addr[2];
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unsigned int i;
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ret = nand_send_cmd(NAND_CMD_CHANGE_1ST, 0U);
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if (ret != 0) {
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return ret;
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}
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if (rawnand_dev.nand_dev->buswidth == NAND_BUS_WIDTH_16) {
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offset /= 2U;
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}
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addr[0] = offset;
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addr[1] = offset >> 8;
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for (i = 0; i < 2U; i++) {
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ret = nand_send_addr(addr[i], 0U);
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if (ret != 0) {
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return ret;
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}
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}
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ret = nand_send_cmd(NAND_CMD_CHANGE_2ND, NAND_TCCS_MIN);
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if (ret != 0) {
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return ret;
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}
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return nand_read_data((uint8_t *)buffer, len, false);
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}
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int nand_read_page_cmd(unsigned int page, unsigned int offset,
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uintptr_t buffer, unsigned int len)
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{
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uint8_t addr[5];
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uint8_t i = 0U;
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uint8_t j;
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int ret;
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VERBOSE(">%s page %u offset %u buffer 0x%lx\n", __func__, page, offset,
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buffer);
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if (rawnand_dev.nand_dev->buswidth == NAND_BUS_WIDTH_16) {
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offset /= 2U;
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}
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addr[i++] = offset;
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addr[i++] = offset >> 8;
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addr[i++] = page;
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addr[i++] = page >> 8;
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if (rawnand_dev.nand_dev->size > SZ_128M) {
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addr[i++] = page >> 16;
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}
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ret = nand_send_cmd(NAND_CMD_READ_1ST, 0U);
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if (ret != 0) {
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return ret;
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}
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for (j = 0U; j < i; j++) {
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ret = nand_send_addr(addr[j], 0U);
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if (ret != 0) {
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return ret;
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}
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}
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ret = nand_send_cmd(NAND_CMD_READ_2ND, NAND_TWB_MAX);
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if (ret != 0) {
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return ret;
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}
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ret = nand_send_wait(PSEC_TO_MSEC(NAND_TR_MAX), NAND_TRR_MIN);
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if (ret != 0) {
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return ret;
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}
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if (buffer != 0U) {
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ret = nand_read_data((uint8_t *)buffer, len, false);
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}
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return ret;
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}
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static int nand_status(uint8_t *status)
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{
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int ret;
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ret = nand_send_cmd(NAND_CMD_STATUS, NAND_TWHR_MIN);
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if (ret != 0) {
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return ret;
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}
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if (status != NULL) {
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ret = nand_read_data(status, 1U, true);
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}
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return ret;
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}
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int nand_wait_ready(unsigned int delay_ms)
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{
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uint8_t status;
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int ret;
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uint64_t timeout;
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/* Wait before reading status */
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udelay(1);
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ret = nand_status(NULL);
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if (ret != 0) {
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return ret;
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}
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timeout = timeout_init_us(delay_ms * 1000U);
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while (!timeout_elapsed(timeout)) {
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ret = nand_read_data(&status, 1U, true);
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if (ret != 0) {
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return ret;
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}
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if ((status & NAND_STATUS_READY) != 0U) {
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return nand_send_cmd(NAND_CMD_READ_1ST, 0U);
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}
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udelay(10);
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}
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return -ETIMEDOUT;
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}
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#if NAND_ONFI_DETECT
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static uint16_t nand_check_crc(uint16_t crc, uint8_t *data_in,
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unsigned int data_len)
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{
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uint32_t i;
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uint32_t j;
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uint32_t bit;
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for (i = 0U; i < data_len; i++) {
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uint8_t cur_param = *data_in++;
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for (j = BIT(7); j != 0U; j >>= 1) {
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bit = crc & BIT(15);
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crc <<= 1;
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if ((cur_param & j) != 0U) {
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bit ^= BIT(15);
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}
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if (bit != 0U) {
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crc ^= CRC_POLYNOM;
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}
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}
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crc &= GENMASK(15, 0);
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}
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return crc;
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}
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static int nand_read_id(uint8_t addr, uint8_t *id, unsigned int size)
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{
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int ret;
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ret = nand_send_cmd(NAND_CMD_READID, 0U);
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if (ret != 0) {
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return ret;
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}
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ret = nand_send_addr(addr, NAND_TWHR_MIN);
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if (ret != 0) {
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return ret;
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}
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return nand_read_data(id, size, true);
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}
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static int nand_reset(void)
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{
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int ret;
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ret = nand_send_cmd(NAND_CMD_RESET, NAND_TWB_MAX);
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if (ret != 0) {
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return ret;
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}
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return nand_send_wait(PSEC_TO_MSEC(NAND_TRST_MAX), 0U);
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}
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static int nand_read_param_page(void)
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{
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struct nand_param_page page;
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uint8_t addr = 0U;
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int ret;
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ret = nand_send_cmd(NAND_CMD_READ_PARAM_PAGE, 0U);
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if (ret != 0) {
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return ret;
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}
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ret = nand_send_addr(addr, NAND_TWB_MAX);
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if (ret != 0) {
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return ret;
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}
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ret = nand_send_wait(PSEC_TO_MSEC(NAND_TR_MAX), NAND_TRR_MIN);
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if (ret != 0) {
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return ret;
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}
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ret = nand_read_data((uint8_t *)&page, sizeof(page), true);
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if (ret != 0) {
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return ret;
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}
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if (strncmp((char *)&page.page_sig, "ONFI", 4) != 0) {
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WARN("Error ONFI detection\n");
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return -EINVAL;
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}
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if (nand_check_crc(CRC_INIT_VALUE, (uint8_t *)&page, 254U) !=
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page.crc16) {
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WARN("Error reading param\n");
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return -EINVAL;
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}
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if ((page.features & ONFI_FEAT_BUS_WIDTH_16) != 0U) {
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rawnand_dev.nand_dev->buswidth = NAND_BUS_WIDTH_16;
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} else {
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rawnand_dev.nand_dev->buswidth = NAND_BUS_WIDTH_8;
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}
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rawnand_dev.nand_dev->block_size = page.num_pages_per_blk *
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page.bytes_per_page;
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rawnand_dev.nand_dev->page_size = page.bytes_per_page;
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rawnand_dev.nand_dev->size = page.num_pages_per_blk *
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page.bytes_per_page *
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page.num_blk_in_lun * page.num_lun;
|
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|
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if (page.nb_ecc_bits != GENMASK_32(7, 0)) {
|
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rawnand_dev.nand_dev->ecc.max_bit_corr = page.nb_ecc_bits;
|
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rawnand_dev.nand_dev->ecc.size = SZ_512;
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}
|
||||
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VERBOSE("Page size %u, block_size %u, Size %llu, ecc %u, buswidth %u\n",
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rawnand_dev.nand_dev->page_size,
|
||||
rawnand_dev.nand_dev->block_size, rawnand_dev.nand_dev->size,
|
||||
rawnand_dev.nand_dev->ecc.max_bit_corr,
|
||||
rawnand_dev.nand_dev->buswidth);
|
||||
|
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return 0;
|
||||
}
|
||||
|
||||
static int detect_onfi(void)
|
||||
{
|
||||
int ret;
|
||||
char id[4];
|
||||
|
||||
ret = nand_reset();
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = nand_read_id(ONFI_SIGNATURE_ADDR, (uint8_t *)id, sizeof(id));
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (strncmp(id, "ONFI", sizeof(id)) != 0) {
|
||||
WARN("NAND Non ONFI detected\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
return nand_read_param_page();
|
||||
}
|
||||
#endif
|
||||
|
||||
static int nand_mtd_block_is_bad(unsigned int block)
|
||||
{
|
||||
unsigned int nbpages_per_block = rawnand_dev.nand_dev->block_size /
|
||||
rawnand_dev.nand_dev->page_size;
|
||||
uint8_t bbm_marker[2];
|
||||
uint8_t page;
|
||||
int ret;
|
||||
|
||||
for (page = 0U; page < 2U; page++) {
|
||||
ret = nand_read_page_cmd(block * nbpages_per_block,
|
||||
rawnand_dev.nand_dev->page_size,
|
||||
(uintptr_t)bbm_marker,
|
||||
sizeof(bbm_marker));
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
if ((bbm_marker[0] != GENMASK_32(7, 0)) ||
|
||||
(bbm_marker[1] != GENMASK_32(7, 0))) {
|
||||
WARN("Block %u is bad\n", block);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nand_mtd_read_page_raw(struct nand_device *nand, unsigned int page,
|
||||
uintptr_t buffer)
|
||||
{
|
||||
return nand_read_page_cmd(page, 0U, buffer,
|
||||
rawnand_dev.nand_dev->page_size);
|
||||
}
|
||||
|
||||
void nand_raw_ctrl_init(const struct nand_ctrl_ops *ops)
|
||||
{
|
||||
rawnand_dev.ops = ops;
|
||||
}
|
||||
|
||||
int nand_raw_init(unsigned long long *size, unsigned int *erase_size)
|
||||
{
|
||||
rawnand_dev.nand_dev = get_nand_device();
|
||||
if (rawnand_dev.nand_dev == NULL) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
rawnand_dev.nand_dev->mtd_block_is_bad = nand_mtd_block_is_bad;
|
||||
rawnand_dev.nand_dev->mtd_read_page = nand_mtd_read_page_raw;
|
||||
rawnand_dev.nand_dev->ecc.mode = NAND_ECC_NONE;
|
||||
|
||||
if ((rawnand_dev.ops->setup == NULL) ||
|
||||
(rawnand_dev.ops->exec == NULL)) {
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
#if NAND_ONFI_DETECT
|
||||
if (detect_onfi() != 0) {
|
||||
WARN("Detect ONFI failed\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
if (plat_get_raw_nand_data(&rawnand_dev) != 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
assert((rawnand_dev.nand_dev->page_size != 0U) &&
|
||||
(rawnand_dev.nand_dev->block_size != 0U) &&
|
||||
(rawnand_dev.nand_dev->size != 0U));
|
||||
|
||||
*size = rawnand_dev.nand_dev->size;
|
||||
*erase_size = rawnand_dev.nand_dev->block_size;
|
||||
|
||||
rawnand_dev.ops->setup(rawnand_dev.nand_dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,324 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <errno.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <drivers/spi_nand.h>
|
||||
#include <lib/utils.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#define SPI_NAND_MAX_ID_LEN 4U
|
||||
#define DELAY_US_400MS 400000U
|
||||
#define MACRONIX_ID 0xC2U
|
||||
|
||||
static struct spinand_device spinand_dev;
|
||||
|
||||
#pragma weak plat_get_spi_nand_data
|
||||
int plat_get_spi_nand_data(struct spinand_device *device)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spi_nand_reg(bool read_reg, uint8_t reg, uint8_t *val,
|
||||
enum spi_mem_data_dir dir)
|
||||
{
|
||||
struct spi_mem_op op;
|
||||
|
||||
zeromem(&op, sizeof(struct spi_mem_op));
|
||||
if (read_reg) {
|
||||
op.cmd.opcode = SPI_NAND_OP_GET_FEATURE;
|
||||
} else {
|
||||
op.cmd.opcode = SPI_NAND_OP_SET_FEATURE;
|
||||
}
|
||||
|
||||
op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
|
||||
op.addr.val = reg;
|
||||
op.addr.nbytes = 1U;
|
||||
op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
|
||||
op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
|
||||
op.data.dir = dir;
|
||||
op.data.nbytes = 1U;
|
||||
op.data.buf = val;
|
||||
|
||||
return spi_mem_exec_op(&op);
|
||||
}
|
||||
|
||||
static int spi_nand_read_reg(uint8_t reg, uint8_t *val)
|
||||
{
|
||||
return spi_nand_reg(true, reg, val, SPI_MEM_DATA_IN);
|
||||
}
|
||||
|
||||
static int spi_nand_write_reg(uint8_t reg, uint8_t val)
|
||||
{
|
||||
return spi_nand_reg(false, reg, &val, SPI_MEM_DATA_OUT);
|
||||
}
|
||||
|
||||
static int spi_nand_update_cfg(uint8_t mask, uint8_t val)
|
||||
{
|
||||
int ret;
|
||||
uint8_t cfg = spinand_dev.cfg_cache;
|
||||
|
||||
cfg &= ~mask;
|
||||
cfg |= val;
|
||||
|
||||
if (cfg == spinand_dev.cfg_cache) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret = spi_nand_write_reg(SPI_NAND_REG_CFG, cfg);
|
||||
if (ret == 0) {
|
||||
spinand_dev.cfg_cache = cfg;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int spi_nand_ecc_enable(bool enable)
|
||||
{
|
||||
return spi_nand_update_cfg(SPI_NAND_CFG_ECC_EN,
|
||||
enable ? SPI_NAND_CFG_ECC_EN : 0U);
|
||||
}
|
||||
|
||||
static int spi_nand_quad_enable(uint8_t manufacturer_id)
|
||||
{
|
||||
bool enable = false;
|
||||
|
||||
if (manufacturer_id != MACRONIX_ID) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (spinand_dev.spi_read_cache_op.data.buswidth ==
|
||||
SPI_MEM_BUSWIDTH_4_LINE) {
|
||||
enable = true;
|
||||
}
|
||||
|
||||
return spi_nand_update_cfg(SPI_NAND_CFG_QE,
|
||||
enable ? SPI_NAND_CFG_QE : 0U);
|
||||
}
|
||||
|
||||
static int spi_nand_wait_ready(uint8_t *status)
|
||||
{
|
||||
int ret;
|
||||
uint64_t timeout = timeout_init_us(DELAY_US_400MS);
|
||||
|
||||
while (!timeout_elapsed(timeout)) {
|
||||
ret = spi_nand_read_reg(SPI_NAND_REG_STATUS, status);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
VERBOSE("%s Status %x\n", __func__, *status);
|
||||
if ((*status & SPI_NAND_STATUS_BUSY) == 0U) {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static int spi_nand_reset(void)
|
||||
{
|
||||
struct spi_mem_op op;
|
||||
uint8_t status;
|
||||
int ret;
|
||||
|
||||
zeromem(&op, sizeof(struct spi_mem_op));
|
||||
op.cmd.opcode = SPI_NAND_OP_RESET;
|
||||
op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
|
||||
|
||||
ret = spi_mem_exec_op(&op);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
return spi_nand_wait_ready(&status);
|
||||
}
|
||||
|
||||
static int spi_nand_read_id(uint8_t *id)
|
||||
{
|
||||
struct spi_mem_op op;
|
||||
|
||||
zeromem(&op, sizeof(struct spi_mem_op));
|
||||
op.cmd.opcode = SPI_NAND_OP_READ_ID;
|
||||
op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
|
||||
op.data.dir = SPI_MEM_DATA_IN;
|
||||
op.data.nbytes = SPI_NAND_MAX_ID_LEN;
|
||||
op.data.buf = id;
|
||||
op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
|
||||
|
||||
return spi_mem_exec_op(&op);
|
||||
}
|
||||
|
||||
static int spi_nand_load_page(unsigned int page)
|
||||
{
|
||||
struct spi_mem_op op;
|
||||
uint32_t block_nb = page / spinand_dev.nand_dev->block_size;
|
||||
uint32_t page_nb = page - (block_nb * spinand_dev.nand_dev->page_size);
|
||||
uint32_t nbpages_per_block = spinand_dev.nand_dev->block_size /
|
||||
spinand_dev.nand_dev->page_size;
|
||||
uint32_t block_sh = __builtin_ctz(nbpages_per_block) + 1U;
|
||||
|
||||
zeromem(&op, sizeof(struct spi_mem_op));
|
||||
op.cmd.opcode = SPI_NAND_OP_LOAD_PAGE;
|
||||
op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
|
||||
op.addr.val = (block_nb << block_sh) | page_nb;
|
||||
op.addr.nbytes = 3U;
|
||||
op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
|
||||
|
||||
return spi_mem_exec_op(&op);
|
||||
}
|
||||
|
||||
static int spi_nand_read_from_cache(unsigned int page, unsigned int offset,
|
||||
uint8_t *buffer, unsigned int len)
|
||||
{
|
||||
uint32_t nbpages_per_block = spinand_dev.nand_dev->block_size /
|
||||
spinand_dev.nand_dev->page_size;
|
||||
uint32_t block_nb = page / nbpages_per_block;
|
||||
uint32_t page_sh = __builtin_ctz(spinand_dev.nand_dev->page_size) + 1U;
|
||||
|
||||
spinand_dev.spi_read_cache_op.addr.val = offset;
|
||||
|
||||
if ((spinand_dev.nand_dev->nb_planes > 1U) && ((block_nb % 2U) == 1U)) {
|
||||
spinand_dev.spi_read_cache_op.addr.val |= 1U << page_sh;
|
||||
}
|
||||
|
||||
spinand_dev.spi_read_cache_op.data.buf = buffer;
|
||||
spinand_dev.spi_read_cache_op.data.nbytes = len;
|
||||
|
||||
return spi_mem_exec_op(&spinand_dev.spi_read_cache_op);
|
||||
}
|
||||
|
||||
static int spi_nand_read_page(unsigned int page, unsigned int offset,
|
||||
uint8_t *buffer, unsigned int len,
|
||||
bool ecc_enabled)
|
||||
{
|
||||
uint8_t status;
|
||||
int ret;
|
||||
|
||||
ret = spi_nand_ecc_enable(ecc_enabled);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = spi_nand_load_page(page);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = spi_nand_wait_ready(&status);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = spi_nand_read_from_cache(page, offset, buffer, len);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (ecc_enabled && ((status & SPI_NAND_STATUS_ECC_UNCOR) != 0U)) {
|
||||
return -EBADMSG;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spi_nand_mtd_block_is_bad(unsigned int block)
|
||||
{
|
||||
unsigned int nbpages_per_block = spinand_dev.nand_dev->block_size /
|
||||
spinand_dev.nand_dev->page_size;
|
||||
uint8_t bbm_marker[2];
|
||||
int ret;
|
||||
|
||||
ret = spi_nand_read_page(block * nbpages_per_block,
|
||||
spinand_dev.nand_dev->page_size,
|
||||
bbm_marker, sizeof(bbm_marker), false);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
if ((bbm_marker[0] != GENMASK_32(7, 0)) ||
|
||||
(bbm_marker[1] != GENMASK_32(7, 0))) {
|
||||
WARN("Block %u is bad\n", block);
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spi_nand_mtd_read_page(struct nand_device *nand, unsigned int page,
|
||||
uintptr_t buffer)
|
||||
{
|
||||
return spi_nand_read_page(page, 0, (uint8_t *)buffer,
|
||||
spinand_dev.nand_dev->page_size, true);
|
||||
}
|
||||
|
||||
int spi_nand_init(unsigned long long *size, unsigned int *erase_size)
|
||||
{
|
||||
uint8_t id[SPI_NAND_MAX_ID_LEN];
|
||||
int ret;
|
||||
|
||||
spinand_dev.nand_dev = get_nand_device();
|
||||
if (spinand_dev.nand_dev == NULL) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
spinand_dev.nand_dev->mtd_block_is_bad = spi_nand_mtd_block_is_bad;
|
||||
spinand_dev.nand_dev->mtd_read_page = spi_nand_mtd_read_page;
|
||||
spinand_dev.nand_dev->nb_planes = 1;
|
||||
|
||||
spinand_dev.spi_read_cache_op.cmd.opcode = SPI_NAND_OP_READ_FROM_CACHE;
|
||||
spinand_dev.spi_read_cache_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
|
||||
spinand_dev.spi_read_cache_op.addr.nbytes = 2U;
|
||||
spinand_dev.spi_read_cache_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
|
||||
spinand_dev.spi_read_cache_op.dummy.nbytes = 1U;
|
||||
spinand_dev.spi_read_cache_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
|
||||
spinand_dev.spi_read_cache_op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
|
||||
|
||||
if (plat_get_spi_nand_data(&spinand_dev) != 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
assert((spinand_dev.nand_dev->page_size != 0U) &&
|
||||
(spinand_dev.nand_dev->block_size != 0U) &&
|
||||
(spinand_dev.nand_dev->size != 0U));
|
||||
|
||||
ret = spi_nand_reset();
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = spi_nand_read_id(id);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = spi_nand_read_reg(SPI_NAND_REG_CFG, &spinand_dev.cfg_cache);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = spi_nand_quad_enable(id[1]);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
VERBOSE("SPI_NAND Detected ID 0x%x\n", id[1]);
|
||||
|
||||
VERBOSE("Page size %u, Block size %u, size %llu\n",
|
||||
spinand_dev.nand_dev->page_size,
|
||||
spinand_dev.nand_dev->block_size,
|
||||
spinand_dev.nand_dev->size);
|
||||
|
||||
*size = spinand_dev.nand_dev->size;
|
||||
*erase_size = spinand_dev.nand_dev->block_size;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,387 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <errno.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <drivers/spi_nor.h>
|
||||
#include <lib/utils.h>
|
||||
|
||||
#define SR_WIP BIT(0) /* Write in progress */
|
||||
#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
|
||||
#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
|
||||
#define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
|
||||
|
||||
/* Defined IDs for supported memories */
|
||||
#define SPANSION_ID 0x01U
|
||||
#define MACRONIX_ID 0xC2U
|
||||
#define MICRON_ID 0x2CU
|
||||
|
||||
#define BANK_SIZE 0x1000000U
|
||||
|
||||
#define SPI_READY_TIMEOUT_US 40000U
|
||||
|
||||
static struct nor_device nor_dev;
|
||||
|
||||
#pragma weak plat_get_nor_data
|
||||
int plat_get_nor_data(struct nor_device *device)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spi_nor_reg(uint8_t reg, uint8_t *buf, size_t len,
|
||||
enum spi_mem_data_dir dir)
|
||||
{
|
||||
struct spi_mem_op op;
|
||||
|
||||
zeromem(&op, sizeof(struct spi_mem_op));
|
||||
op.cmd.opcode = reg;
|
||||
op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
|
||||
op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
|
||||
op.data.dir = dir;
|
||||
op.data.nbytes = len;
|
||||
op.data.buf = buf;
|
||||
|
||||
return spi_mem_exec_op(&op);
|
||||
}
|
||||
|
||||
static inline int spi_nor_read_id(uint8_t *id)
|
||||
{
|
||||
return spi_nor_reg(SPI_NOR_OP_READ_ID, id, 1U, SPI_MEM_DATA_IN);
|
||||
}
|
||||
|
||||
static inline int spi_nor_read_cr(uint8_t *cr)
|
||||
{
|
||||
return spi_nor_reg(SPI_NOR_OP_READ_CR, cr, 1U, SPI_MEM_DATA_IN);
|
||||
}
|
||||
|
||||
static inline int spi_nor_read_sr(uint8_t *sr)
|
||||
{
|
||||
return spi_nor_reg(SPI_NOR_OP_READ_SR, sr, 1U, SPI_MEM_DATA_IN);
|
||||
}
|
||||
|
||||
static inline int spi_nor_read_fsr(uint8_t *fsr)
|
||||
{
|
||||
return spi_nor_reg(SPI_NOR_OP_READ_FSR, fsr, 1U, SPI_MEM_DATA_IN);
|
||||
}
|
||||
|
||||
static inline int spi_nor_write_en(void)
|
||||
{
|
||||
return spi_nor_reg(SPI_NOR_OP_WREN, NULL, 0U, SPI_MEM_DATA_OUT);
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if device is ready.
|
||||
*
|
||||
* Return 0 if ready, 1 if busy or a negative error code otherwise
|
||||
*/
|
||||
static int spi_nor_ready(void)
|
||||
{
|
||||
uint8_t sr;
|
||||
int ret;
|
||||
|
||||
ret = spi_nor_read_sr(&sr);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
if ((nor_dev.flags & SPI_NOR_USE_FSR) != 0U) {
|
||||
uint8_t fsr;
|
||||
|
||||
ret = spi_nor_read_fsr(&fsr);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
return (((fsr & FSR_READY) != 0U) && ((sr & SR_WIP) == 0U)) ?
|
||||
0 : 1;
|
||||
}
|
||||
|
||||
return (((sr & SR_WIP) == 0U) ? 0 : 1);
|
||||
}
|
||||
|
||||
static int spi_nor_wait_ready(void)
|
||||
{
|
||||
int ret;
|
||||
uint64_t timeout = timeout_init_us(SPI_READY_TIMEOUT_US);
|
||||
|
||||
while (!timeout_elapsed(timeout)) {
|
||||
ret = spi_nor_ready();
|
||||
if (ret <= 0) {
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static int spi_nor_macronix_quad_enable(void)
|
||||
{
|
||||
uint8_t sr;
|
||||
int ret;
|
||||
|
||||
ret = spi_nor_read_sr(&sr);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
if ((sr & SR_QUAD_EN_MX) != 0U) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret = spi_nor_write_en();
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
sr |= SR_QUAD_EN_MX;
|
||||
ret = spi_nor_reg(SPI_NOR_OP_WRSR, &sr, 1U, SPI_MEM_DATA_OUT);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = spi_nor_wait_ready();
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = spi_nor_read_sr(&sr);
|
||||
if ((ret != 0) || ((sr & SR_QUAD_EN_MX) == 0U)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spi_nor_write_sr_cr(uint8_t *sr_cr)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = spi_nor_write_en();
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = spi_nor_reg(SPI_NOR_OP_WRSR, sr_cr, 2U, SPI_MEM_DATA_OUT);
|
||||
if (ret != 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = spi_nor_wait_ready();
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spi_nor_quad_enable(void)
|
||||
{
|
||||
uint8_t sr_cr[2];
|
||||
int ret;
|
||||
|
||||
ret = spi_nor_read_cr(&sr_cr[1]);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
if ((sr_cr[1] & CR_QUAD_EN_SPAN) != 0U) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
sr_cr[1] |= CR_QUAD_EN_SPAN;
|
||||
ret = spi_nor_read_sr(&sr_cr[0]);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = spi_nor_write_sr_cr(sr_cr);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = spi_nor_read_cr(&sr_cr[1]);
|
||||
if ((ret != 0) || ((sr_cr[1] & CR_QUAD_EN_SPAN) == 0U)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spi_nor_clean_bar(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (nor_dev.selected_bank == 0U) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
nor_dev.selected_bank = 0U;
|
||||
|
||||
ret = spi_nor_write_en();
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
return spi_nor_reg(nor_dev.bank_write_cmd, &nor_dev.selected_bank,
|
||||
1U, SPI_MEM_DATA_OUT);
|
||||
}
|
||||
|
||||
static int spi_nor_write_bar(uint32_t offset)
|
||||
{
|
||||
uint8_t selected_bank = offset / BANK_SIZE;
|
||||
int ret;
|
||||
|
||||
if (selected_bank == nor_dev.selected_bank) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret = spi_nor_write_en();
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = spi_nor_reg(nor_dev.bank_write_cmd, &selected_bank,
|
||||
1U, SPI_MEM_DATA_OUT);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
nor_dev.selected_bank = selected_bank;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spi_nor_read_bar(void)
|
||||
{
|
||||
uint8_t selected_bank = 0U;
|
||||
int ret;
|
||||
|
||||
ret = spi_nor_reg(nor_dev.bank_read_cmd, &selected_bank,
|
||||
1U, SPI_MEM_DATA_IN);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
nor_dev.selected_bank = selected_bank;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int spi_nor_read(unsigned int offset, uintptr_t buffer, size_t length,
|
||||
size_t *length_read)
|
||||
{
|
||||
size_t remain_len;
|
||||
int ret;
|
||||
|
||||
*length_read = 0U;
|
||||
nor_dev.read_op.addr.val = offset;
|
||||
nor_dev.read_op.data.buf = (void *)buffer;
|
||||
|
||||
VERBOSE("%s offset %u length %zu\n", __func__, offset, length);
|
||||
|
||||
while (length != 0U) {
|
||||
if ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U) {
|
||||
ret = spi_nor_write_bar(nor_dev.read_op.addr.val);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
remain_len = (BANK_SIZE * (nor_dev.selected_bank + 1)) -
|
||||
nor_dev.read_op.addr.val;
|
||||
nor_dev.read_op.data.nbytes = MIN(length, remain_len);
|
||||
} else {
|
||||
nor_dev.read_op.data.nbytes = length;
|
||||
}
|
||||
|
||||
ret = spi_mem_exec_op(&nor_dev.read_op);
|
||||
if (ret != 0) {
|
||||
spi_nor_clean_bar();
|
||||
return ret;
|
||||
}
|
||||
|
||||
length -= nor_dev.read_op.data.nbytes;
|
||||
nor_dev.read_op.addr.val += nor_dev.read_op.data.nbytes;
|
||||
nor_dev.read_op.data.buf += nor_dev.read_op.data.nbytes;
|
||||
*length_read += nor_dev.read_op.data.nbytes;
|
||||
}
|
||||
|
||||
if ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U) {
|
||||
ret = spi_nor_clean_bar();
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int spi_nor_init(unsigned long long *size, unsigned int *erase_size)
|
||||
{
|
||||
int ret;
|
||||
uint8_t id;
|
||||
|
||||
/* Default read command used */
|
||||
nor_dev.read_op.cmd.opcode = SPI_NOR_OP_READ;
|
||||
nor_dev.read_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
|
||||
nor_dev.read_op.addr.nbytes = 3U;
|
||||
nor_dev.read_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
|
||||
nor_dev.read_op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
|
||||
nor_dev.read_op.data.dir = SPI_MEM_DATA_IN;
|
||||
|
||||
if (plat_get_nor_data(&nor_dev) != 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
assert(nor_dev.size != 0U);
|
||||
|
||||
if (nor_dev.size > BANK_SIZE) {
|
||||
nor_dev.flags |= SPI_NOR_USE_BANK;
|
||||
}
|
||||
|
||||
*size = nor_dev.size;
|
||||
|
||||
ret = spi_nor_read_id(&id);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
if ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U) {
|
||||
switch (id) {
|
||||
case SPANSION_ID:
|
||||
nor_dev.bank_read_cmd = SPINOR_OP_BRRD;
|
||||
nor_dev.bank_write_cmd = SPINOR_OP_BRWR;
|
||||
break;
|
||||
default:
|
||||
nor_dev.bank_read_cmd = SPINOR_OP_RDEAR;
|
||||
nor_dev.bank_write_cmd = SPINOR_OP_WREAR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (nor_dev.read_op.data.buswidth == 4U) {
|
||||
switch (id) {
|
||||
case MACRONIX_ID:
|
||||
INFO("Enable Macronix quad support\n");
|
||||
ret = spi_nor_macronix_quad_enable();
|
||||
break;
|
||||
case MICRON_ID:
|
||||
break;
|
||||
default:
|
||||
ret = spi_nor_quad_enable();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if ((ret == 0) && ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U)) {
|
||||
ret = spi_nor_read_bar();
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
@@ -0,0 +1,289 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <inttypes.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <drivers/spi_mem.h>
|
||||
#include <lib/utils_def.h>
|
||||
#include <libfdt.h>
|
||||
|
||||
#define SPI_MEM_DEFAULT_SPEED_HZ 100000U
|
||||
|
||||
/*
|
||||
* struct spi_slave - Representation of a SPI slave.
|
||||
*
|
||||
* @max_hz: Maximum speed for this slave in Hertz.
|
||||
* @cs: ID of the chip select connected to the slave.
|
||||
* @mode: SPI mode to use for this slave (see SPI mode flags).
|
||||
* @ops: Ops defined by the bus.
|
||||
*/
|
||||
struct spi_slave {
|
||||
unsigned int max_hz;
|
||||
unsigned int cs;
|
||||
unsigned int mode;
|
||||
const struct spi_bus_ops *ops;
|
||||
};
|
||||
|
||||
static struct spi_slave spi_slave;
|
||||
|
||||
static bool spi_mem_check_buswidth_req(uint8_t buswidth, bool tx)
|
||||
{
|
||||
switch (buswidth) {
|
||||
case 1U:
|
||||
return true;
|
||||
|
||||
case 2U:
|
||||
if ((tx && (spi_slave.mode & (SPI_TX_DUAL | SPI_TX_QUAD)) !=
|
||||
0U) ||
|
||||
(!tx && (spi_slave.mode & (SPI_RX_DUAL | SPI_RX_QUAD)) !=
|
||||
0U)) {
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
|
||||
case 4U:
|
||||
if ((tx && (spi_slave.mode & SPI_TX_QUAD) != 0U) ||
|
||||
(!tx && (spi_slave.mode & SPI_RX_QUAD) != 0U)) {
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool spi_mem_supports_op(const struct spi_mem_op *op)
|
||||
{
|
||||
if (!spi_mem_check_buswidth_req(op->cmd.buswidth, true)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if ((op->addr.nbytes != 0U) &&
|
||||
!spi_mem_check_buswidth_req(op->addr.buswidth, true)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if ((op->dummy.nbytes != 0U) &&
|
||||
!spi_mem_check_buswidth_req(op->dummy.buswidth, true)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if ((op->data.nbytes != 0U) &&
|
||||
!spi_mem_check_buswidth_req(op->data.buswidth,
|
||||
op->data.dir == SPI_MEM_DATA_OUT)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static int spi_mem_set_speed_mode(void)
|
||||
{
|
||||
const struct spi_bus_ops *ops = spi_slave.ops;
|
||||
int ret;
|
||||
|
||||
ret = ops->set_speed(spi_slave.max_hz);
|
||||
if (ret != 0) {
|
||||
VERBOSE("Cannot set speed (err=%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = ops->set_mode(spi_slave.mode);
|
||||
if (ret != 0) {
|
||||
VERBOSE("Cannot set mode (err=%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spi_mem_check_bus_ops(const struct spi_bus_ops *ops)
|
||||
{
|
||||
bool error = false;
|
||||
|
||||
if (ops->claim_bus == NULL) {
|
||||
VERBOSE("Ops claim bus is not defined\n");
|
||||
error = true;
|
||||
}
|
||||
|
||||
if (ops->release_bus == NULL) {
|
||||
VERBOSE("Ops release bus is not defined\n");
|
||||
error = true;
|
||||
}
|
||||
|
||||
if (ops->exec_op == NULL) {
|
||||
VERBOSE("Ops exec op is not defined\n");
|
||||
error = true;
|
||||
}
|
||||
|
||||
if (ops->set_speed == NULL) {
|
||||
VERBOSE("Ops set speed is not defined\n");
|
||||
error = true;
|
||||
}
|
||||
|
||||
if (ops->set_mode == NULL) {
|
||||
VERBOSE("Ops set mode is not defined\n");
|
||||
error = true;
|
||||
}
|
||||
|
||||
return error ? -EINVAL : 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* spi_mem_exec_op() - Execute a memory operation.
|
||||
* @op: The memory operation to execute.
|
||||
*
|
||||
* This function first checks that @op is supported and then tries to execute
|
||||
* it.
|
||||
*
|
||||
* Return: 0 in case of success, a negative error code otherwise.
|
||||
*/
|
||||
int spi_mem_exec_op(const struct spi_mem_op *op)
|
||||
{
|
||||
const struct spi_bus_ops *ops = spi_slave.ops;
|
||||
int ret;
|
||||
|
||||
VERBOSE("%s: cmd:%x mode:%d.%d.%d.%d addqr:%" PRIx64 " len:%x\n",
|
||||
__func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
|
||||
op->dummy.buswidth, op->data.buswidth,
|
||||
op->addr.val, op->data.nbytes);
|
||||
|
||||
if (!spi_mem_supports_op(op)) {
|
||||
WARN("Error in spi_mem_support\n");
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
ret = ops->claim_bus(spi_slave.cs);
|
||||
if (ret != 0) {
|
||||
WARN("Error claim_bus\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = ops->exec_op(op);
|
||||
|
||||
ops->release_bus();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* spi_mem_init_slave() - SPI slave device initialization.
|
||||
* @fdt: Pointer to the device tree blob.
|
||||
* @bus_node: Offset of the bus node.
|
||||
* @ops: The SPI bus ops defined.
|
||||
*
|
||||
* This function first checks that @ops are supported and then tries to find
|
||||
* a SPI slave device.
|
||||
*
|
||||
* Return: 0 in case of success, a negative error code otherwise.
|
||||
*/
|
||||
int spi_mem_init_slave(void *fdt, int bus_node, const struct spi_bus_ops *ops)
|
||||
{
|
||||
int ret;
|
||||
int mode = 0;
|
||||
int nchips = 0;
|
||||
int bus_subnode = 0;
|
||||
const fdt32_t *cuint = NULL;
|
||||
|
||||
ret = spi_mem_check_bus_ops(ops);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
fdt_for_each_subnode(bus_subnode, fdt, bus_node) {
|
||||
nchips++;
|
||||
}
|
||||
|
||||
if (nchips != 1) {
|
||||
ERROR("Only one SPI device is currently supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
fdt_for_each_subnode(bus_subnode, fdt, bus_node) {
|
||||
/* Get chip select */
|
||||
cuint = fdt_getprop(fdt, bus_subnode, "reg", NULL);
|
||||
if (cuint == NULL) {
|
||||
ERROR("Chip select not well defined\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
spi_slave.cs = fdt32_to_cpu(*cuint);
|
||||
|
||||
/* Get max slave frequency */
|
||||
spi_slave.max_hz = SPI_MEM_DEFAULT_SPEED_HZ;
|
||||
cuint = fdt_getprop(fdt, bus_subnode,
|
||||
"spi-max-frequency", NULL);
|
||||
if (cuint != NULL) {
|
||||
spi_slave.max_hz = fdt32_to_cpu(*cuint);
|
||||
}
|
||||
|
||||
/* Get mode */
|
||||
if ((fdt_getprop(fdt, bus_subnode, "spi-cpol", NULL)) != NULL) {
|
||||
mode |= SPI_CPOL;
|
||||
}
|
||||
if ((fdt_getprop(fdt, bus_subnode, "spi-cpha", NULL)) != NULL) {
|
||||
mode |= SPI_CPHA;
|
||||
}
|
||||
if ((fdt_getprop(fdt, bus_subnode, "spi-cs-high", NULL)) !=
|
||||
NULL) {
|
||||
mode |= SPI_CS_HIGH;
|
||||
}
|
||||
if ((fdt_getprop(fdt, bus_subnode, "spi-3wire", NULL)) !=
|
||||
NULL) {
|
||||
mode |= SPI_3WIRE;
|
||||
}
|
||||
if ((fdt_getprop(fdt, bus_subnode, "spi-half-duplex", NULL)) !=
|
||||
NULL) {
|
||||
mode |= SPI_PREAMBLE;
|
||||
}
|
||||
|
||||
/* Get dual/quad mode */
|
||||
cuint = fdt_getprop(fdt, bus_subnode, "spi-tx-bus-width", NULL);
|
||||
if (cuint != NULL) {
|
||||
switch (fdt32_to_cpu(*cuint)) {
|
||||
case 1U:
|
||||
break;
|
||||
case 2U:
|
||||
mode |= SPI_TX_DUAL;
|
||||
break;
|
||||
case 4U:
|
||||
mode |= SPI_TX_QUAD;
|
||||
break;
|
||||
default:
|
||||
WARN("spi-tx-bus-width %u not supported\n",
|
||||
fdt32_to_cpu(*cuint));
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
cuint = fdt_getprop(fdt, bus_subnode, "spi-rx-bus-width", NULL);
|
||||
if (cuint != NULL) {
|
||||
switch (fdt32_to_cpu(*cuint)) {
|
||||
case 1U:
|
||||
break;
|
||||
case 2U:
|
||||
mode |= SPI_RX_DUAL;
|
||||
break;
|
||||
case 4U:
|
||||
mode |= SPI_RX_QUAD;
|
||||
break;
|
||||
default:
|
||||
WARN("spi-rx-bus-width %u not supported\n",
|
||||
fdt32_to_cpu(*cuint));
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
spi_slave.mode = mode;
|
||||
spi_slave.ops = ops;
|
||||
}
|
||||
|
||||
return spi_mem_set_speed_mode();
|
||||
}
|
||||
Reference in New Issue
Block a user