GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright 2021 NXP
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef CSR_H
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#define CSR_H
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#define t_anib 0
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#define t_dbyte 0x10000
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#define t_master 0x20000
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#define t_acsm 0x40000
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#define t_initeng 0x90000
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#define t_drtub 0xc0000
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#define t_apbonly 0xd0000
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#define csr_dbyte_misc_mode_addr 0x00
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#define csr_micro_cont_mux_sel_addr 0x00
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#define csr_uct_shadow_regs 0x04
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#define csr_cal_uclk_info_addr 0x08
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#define csr_seq0bdly0_addr 0x0b
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#define csr_seq0bdly1_addr 0x0c
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#define csr_seq0bdly2_addr 0x0d
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#define csr_seq0bdly3_addr 0x0e
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#define csr_seq0bdisable_flag0_addr 0x0c
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#define csr_seq0bdisable_flag1_addr 0x0d
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#define csr_seq0bdisable_flag2_addr 0x0e
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#define csr_seq0bdisable_flag3_addr 0x0f
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#define csr_seq0bdisable_flag4_addr 0x10
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#define csr_seq0bdisable_flag5_addr 0x11
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#define csr_seq0bdisable_flag6_addr 0x12
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#define csr_seq0bdisable_flag7_addr 0x13
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#define csr_dfi_mode_addr 0x18
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#define csr_tristate_mode_ca_addr 0x19
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#define csr_dfiphyupd_addr 0x21
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#define csr_dqs_preamble_control_addr 0x24
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#define csr_master_x4config_addr 0x25
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#define csr_enable_cs_multicast_addr 0x27
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#define csr_acx4_anib_dis_addr 0x2c
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#define csr_dmipin_present_addr 0x2d
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#define csr_ard_ptr_init_val_addr 0x2e
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#define csr_dct_write_prot 0x31
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#define csr_uct_write_only_shadow 0x32
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#define csr_uct_write_prot 0x33
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#define csr_uct_dat_write_only_shadow 0x34
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#define csr_dbyte_dll_mode_cntrl_addr 0x3a
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#define csr_atx_impedance_addr 0x43
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#define csr_dq_dqs_rcv_cntrl_addr 0x43
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#define csr_cal_offsets_addr 0x45
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#define csr_tx_impedance_ctrl1_addr 0x49
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#define csr_dq_dqs_rcv_cntrl1_addr 0x4a
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#define csr_tx_odt_drv_stren_addr 0x4d
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#define csr_cal_drv_str0_addr 0x50
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#define csr_atx_slew_rate_addr 0x55
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#define csr_proc_odt_time_ctl_addr 0x56
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#define csr_mem_alert_control_addr 0x5b
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#define csr_mem_alert_control2_addr 0x5c
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#define csr_tx_slew_rate_addr 0x5f
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#define csr_mem_reset_l_addr 0x60
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#define csr_dfi_camode_addr 0x75
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#define csr_dll_gain_ctl_addr 0x7c
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#define csr_dll_lockparam_addr 0x7d
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#define csr_ucclk_hclk_enables_addr 0x80
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#define csr_acsm_playback0x0_addr 0x80
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#define csr_acsm_playback1x0_addr 0x81
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#define csr_cal_rate_addr 0x88
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#define csr_cal_zap_addr 0x89
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#define csr_cal_misc2_addr 0x98
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#define csr_micro_reset_addr 0x99
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#define csr_dfi_rd_data_cs_dest_map_addr 0xb0
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#define csr_vref_in_global_addr 0xb2
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#define csr_dfi_wr_data_cs_dest_map_addr 0xb4
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#define csr_pll_pwr_dn_addr 0xc3
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#define csr_pll_ctrl2_addr 0xc5
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#define csr_pll_ctrl1_addr 0xc7
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#define csr_pll_test_mode_addr 0xca
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#define csr_pll_ctrl4_addr 0xcc
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#define csr_dfi_freq_xlat0_addr 0xf0
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#define csr_acsm_ctrl0_addr 0xf0
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#define csr_dfi_freq_ratio_addr 0xfa
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#define csr_acsm_ctrl13_addr 0xfd
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#define csr_tx_pre_drv_mode_lsb 8
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#define csr_tx_pre_n_lsb 4
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#define csr_tx_pre_p_lsb 0
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#define csr_atx_pre_drv_mode_lsb 8
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#define csr_atx_pre_n_lsb 4
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#define csr_atx_pre_p_lsb 0
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#define csr_wdqsextension_lsb 8
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#define csr_lp4sttc_pre_bridge_rx_en_lsb 7
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#define csr_lp4postamble_ext_lsb 6
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#define csr_lp4tgl_two_tck_tx_dqs_pre_lsb 5
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#define csr_position_dfe_init_lsb 2
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#define csr_two_tck_tx_dqs_pre_lsb 1
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#define csr_two_tck_rx_dqs_pre_lsb 0
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#define csr_dll_rx_preamble_mode_lsb 1
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#define csr_odtstren_n_lsb 6
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#define csr_drv_stren_fsdq_n_lsb 6
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#define csr_drv_stren_fsdq_p_lsb 0
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#define csr_adrv_stren_n_lsb 5
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#define csr_adrv_stren_p_lsb 0
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#define csr_cal_drv_str_pu50_lsb 4
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#define csr_cal_once_lsb 5
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#define csr_cal_interval_lsb 0
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#define csr_cal_run_lsb 4
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#define csr_global_vref_in_dac_lsb 3
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#define csr_gain_curr_adj_lsb 7
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#define csr_major_mode_dbyte_lsb 4
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#define csr_dfe_ctrl_lsb 2
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#define csr_ext_vref_range_lsb 1
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#define csr_sel_analog_vref_lsb 0
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#define csr_malertsync_bypass_lsb 0
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#define csr_ck_dis_val_lsb 2
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#define csr_ddr2tmode_lsb 1
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#define csr_dis_dyn_adr_tri_lsb 0
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#define csr_dbyte_disable_lsb 2
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#define csr_power_down_rcvr_lsb 0
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#define csr_power_down_rcvr_dqs_lsb 9
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#define csr_rx_pad_standby_en_lsb 10
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#define csr_rx_pad_standby_en_mask 0x400
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#define csr_x4tg_lsb 0
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#define csr_reset_to_micro_mask 0x8
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#define csr_protect_mem_reset_mask 0x2
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#define csr_stall_to_micro_mask 0x1
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#define uct_write_prot_shadow_mask 0x1
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#define csr_acsm_par_mode_mask 0x4000
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#define csr_acsm_cke_enb_lsb 0
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#define csr_dfiphyupd_threshold_lsb 8
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#define csr_dfiphyupd_threshold_msb 11
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#define csr_dfiphyupd_threshold_mask 0xf00
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#define csr_dfi_rd_destm0_lsb 0
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#define csr_dfi_rd_destm1_lsb 2
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#define csr_dfi_rd_destm2_lsb 4
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#define csr_dfi_rd_destm3_lsb 6
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#define csr_dfi_wr_destm0_lsb 0
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#define csr_dfi_wr_destm1_lsb 2
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#define csr_dfi_wr_destm2_lsb 4
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#define csr_dfi_wr_destm3_lsb 6
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#define csr_acsm_2t_mode_mask 0x40
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#define csr_cal_misc2_err_dis 13
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#define csr_cal_offset_pdc_lsb 6
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#define csr_cal_offset_pdc_msb 9
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#define csr_cal_offset_pdc_mask 0xe0
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#define csr_cal_drv_pdth_mask 0x3c0
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struct impedance_mapping {
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int ohm;
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int code;
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};
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#endif
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File diff suppressed because it is too large
Load Diff
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#
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# Copyright 2021 NXP
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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#
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#-----------------------------------------------------------------------------
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# SNPS ddr phy driver files
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DDR_PHY_C =
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DDR_PHY_H =
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$(DDR_PHY_C): $(DDR_PHY_H) $(COMMON_HDRS) src
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@cp -r "$(DDR_PHY_PATH)/$@" "$(SRC_DIR)/$@"
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$(DDR_PHY_H): src
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@cp -r "$(DDR_PHY_PATH)/$@" "$(SRC_DIR)/$@"
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#------------------------------------------------
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@@ -0,0 +1,106 @@
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/*
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* Copyright 2021 NXP
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef _INPUT_H_
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#define _INPUT_H_
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enum dram_types {
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DDR4,
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DDR3,
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LPDDR4,
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LPDDR3,
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LPDDR2,
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DDR5,
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};
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enum dimm_types {
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UDIMM,
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SODIMM,
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RDIMM,
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LRDIMM,
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NODIMM,
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};
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struct input_basic {
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enum dram_types dram_type;
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enum dimm_types dimm_type;
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int lp4x_mode; /* 0x1 = lpddr4x mode, when dram_type is lpddr4
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*/
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/* not used for protocols other than lpddr4 */
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int num_dbyte; /* number of dbytes physically instantiated */
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int num_active_dbyte_dfi0; /* number of active dbytes to be
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* controlled by dfi0
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*/
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int num_active_dbyte_dfi1; /* number of active dbytes to be
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* controlled by dfi1. Not used for
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* protocols other than lpddr3 and
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* lpddr4
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*/
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int num_anib; /* number of anibs physically instantiated */
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int num_rank_dfi0; /* number of ranks in dfi0 channel */
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int num_rank_dfi1; /* number of ranks in dfi1 channel */
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int dram_data_width; /* 4,8,16 or 32 depending on protocol and dram
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* type
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*/
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int num_pstates;
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int frequency; /* memclk frequency in mhz -- round up */
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int pll_bypass; /* pll bypass enable */
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int dfi_freq_ratio; /* selected dfi frequency ratio */
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int dfi1exists; /* whether they phy config has dfi1 channel */
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int train2d;
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int hard_macro_ver;
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int read_dbienable;
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int dfi_mode; /* no longer used */
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};
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struct input_advanced {
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int d4rx_preamble_length;
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int d4tx_preamble_length;
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int ext_cal_res_val; /* external pull-down resistor */
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int is2ttiming;
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int odtimpedance;
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int tx_impedance;
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int atx_impedance;
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int mem_alert_en;
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int mem_alert_puimp;
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int mem_alert_vref_level;
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int mem_alert_sync_bypass;
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int dis_dyn_adr_tri;
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int phy_mstr_train_interval;
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int phy_mstr_max_req_to_ack;
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int wdqsext;
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int cal_interval;
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int cal_once;
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int dram_byte_swap;
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int rx_en_back_off;
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int train_sequence_ctrl;
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int phy_gen2_umctl_opt;
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int phy_gen2_umctl_f0rc5x;
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int tx_slew_rise_dq;
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int tx_slew_fall_dq;
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int tx_slew_rise_ac;
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int tx_slew_fall_ac;
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int enable_high_clk_skew_fix;
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int disable_unused_addr_lns;
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int phy_init_sequence_num;
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int cs_mode; /* rdimm */
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int cast_cs_to_cid; /* rdimm */
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};
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struct input {
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struct input_basic basic;
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struct input_advanced adv;
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unsigned int mr[7];
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unsigned int cs_d0;
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unsigned int cs_d1;
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unsigned int mirror;
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unsigned int odt[4];
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unsigned int rcw[16];
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unsigned int rcw3x;
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unsigned int vref;
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};
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#endif
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,352 @@
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/*
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* Copyright 2021 NXP
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#if !defined(PHY_H) && defined(NXP_WARM_BOOT)
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#define PHY_H
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#include <flash_info.h>
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/* To store sector size to be erase on flash*/
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#define PHY_ERASE_SIZE F_SECTOR_ERASE_SZ
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/*Structure to save DDR controller timing register 0 and 4 values*/
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struct ddr_ctrl_reg_values {
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uint32_t timing_cfg0;
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uint32_t timing_cfg4;
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};
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/*Structure to implement address-data map tuples to store PHY training values*/
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struct phy_training_values {
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uint32_t addr;
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uint16_t data;
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};
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/* Saves PHY Training Register values after cold reset
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*@param[in] phy_ptr array to store addresses of PHYs
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*@param[in] address_to_store address to save PHY training register values
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*on flash
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*@param[in] num_of_phy the number of PHY for which training values are
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*to be saved
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*@param[in] train2d flag to store whether 2D training registers are to
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*be saved or not
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*@param[in] ddrctrl_regs to save ddr controller registers in case
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*NXP_APPLY_MAX_CDD is applied
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*
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*PHY training values will be stored on flash at contigous memory in the order:
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*1D training registers, 2D training registers
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*for each PHY
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*
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*if train2d is false saving 2D training registers will be skipped
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*/
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int save_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_store,
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uint32_t num_of_phy, int train2d
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#ifdef NXP_APPLY_MAX_CDD
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, struct ddr_ctrl_reg_values *ddrctrl_regs
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#endif
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);
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/*Restores PHY Training Register values after warm reset
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*@param[in] phy_ptr array to store addresses of PHYs
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*@param[in] address_to_store address to retrieve PHY training register
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*values from flash
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*@param[in] num_of_phy the number of PHY for which training values are
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*to be restored
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*@param[in] train2d flag to store whether 2D training registers are
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*to be restored or not
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*@param[in] ddrctrl_regs to restore ddr controller registers in case
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*NXP_APPLY_MAX_CDD is applied
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*if train2d is false saving 2D training registers will be skipped
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*/
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int restore_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_restore,
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uint32_t num_of_phy, int train2d
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#ifdef NXP_APPLY_MAX_CDD
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, struct ddr_ctrl_reg_values *ddrctrl_regs
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#endif
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);
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/*
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* Address data tuples to store the PHY 1D
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*/
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struct phy_training_values training_1D_values[] = {
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{0x200B2, 0}, {0x200CB, 0}, {0x10043, 0}, {0x11043, 0},
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{0x12043, 0}, {0x13043, 0}, {0x14043, 0}, {0x15043, 0},
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{0x16043, 0}, {0x17043, 0}, {0x18043, 0}, {0x10143, 0},
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{0x11143, 0}, {0x12143, 0}, {0x13143, 0}, {0x14143, 0},
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{0x15143, 0}, {0x16143, 0}, {0x17143, 0}, {0x18143, 0},
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{0x10080, 0}, {0x11080, 0}, {0x12080, 0}, {0x13080, 0},
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{0x14080, 0}, {0x15080, 0}, {0x16080, 0}, {0x17080, 0},
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{0x18080, 0}, {0x10180, 0}, {0x11180, 0}, {0x12180, 0},
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{0x13180, 0}, {0x14180, 0}, {0x15180, 0}, {0x16180, 0},
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{0x17180, 0}, {0x18180, 0}, {0x10081, 0}, {0x11081, 0},
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{0x12081, 0}, {0x13081, 0}, {0x14081, 0}, {0x15081, 0},
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{0x16081, 0}, {0x17081, 0}, {0x18081, 0}, {0x10181, 0},
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{0x11181, 0}, {0x12181, 0}, {0x13181, 0}, {0x14181, 0},
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{0x15181, 0}, {0x16181, 0}, {0x17181, 0}, {0x18181, 0},
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{0x10082, 0}, {0x11082, 0}, {0x12082, 0}, {0x13082, 0},
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{0x14082, 0}, {0x15082, 0}, {0x16082, 0}, {0x17082, 0},
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{0x18082, 0}, {0x10182, 0}, {0x11182, 0}, {0x12182, 0},
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{0x13182, 0}, {0x14182, 0}, {0x15182, 0}, {0x16182, 0},
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{0x17182, 0}, {0x18182, 0}, {0x10083, 0}, {0x11083, 0},
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{0x12083, 0}, {0x13083, 0}, {0x14083, 0}, {0x15083, 0},
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{0x16083, 0}, {0x17083, 0}, {0x18083, 0}, {0x10183, 0},
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{0x11183, 0}, {0x12183, 0}, {0x13183, 0}, {0x14183, 0},
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{0x15183, 0}, {0x16183, 0}, {0x17183, 0}, {0x18183, 0},
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{0x100D0, 0}, {0x110D0, 0}, {0x120D0, 0}, {0x130D0, 0},
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{0x140D0, 0}, {0x150D0, 0}, {0x160D0, 0}, {0x170D0, 0},
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{0x180D0, 0}, {0x101D0, 0}, {0x111D0, 0}, {0x121D0, 0},
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{0x131D0, 0}, {0x141D0, 0}, {0x151D0, 0}, {0x161D0, 0},
|
||||
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|
||||
{0x105C3, 0}, {0x115C3, 0}, {0x125C3, 0}, {0x135C3, 0},
|
||||
{0x145C3, 0}, {0x155C3, 0}, {0x165C3, 0}, {0x175C3, 0},
|
||||
{0x185C3, 0}, {0x106C3, 0}, {0x116C3, 0}, {0x126C3, 0},
|
||||
{0x136C3, 0}, {0x146C3, 0}, {0x156C3, 0}, {0x166C3, 0},
|
||||
{0x176C3, 0}, {0x186C3, 0}, {0x107C3, 0}, {0x117C3, 0},
|
||||
{0x127C3, 0}, {0x137C3, 0}, {0x147C3, 0}, {0x157C3, 0},
|
||||
{0x167C3, 0}, {0x177C3, 0}, {0x187C3, 0}, {0x108C3, 0},
|
||||
{0x118C3, 0}, {0x128C3, 0}, {0x138C3, 0}, {0x148C3, 0},
|
||||
{0x158C3, 0}, {0x168C3, 0}, {0x178C3, 0}, {0x188C3, 0},
|
||||
{0x10020, 0}, {0x11020, 0}, {0x12020, 0}, {0x13020, 0},
|
||||
{0x14020, 0}, {0x15020, 0}, {0x16020, 0}, {0x17020, 0},
|
||||
{0x18020, 0}, {0x2007D, 0}, {0x20077, 0}
|
||||
};
|
||||
|
||||
/*
|
||||
*Array to store the PHY 2D Training register addresses
|
||||
*/
|
||||
struct phy_training_values training_2D_values[] = {
|
||||
{0x1008C, 0}, {0x1108C, 0}, {0x1208C, 0}, {0x1308C, 0},
|
||||
{0x1408C, 0}, {0x1508C, 0}, {0x1608C, 0}, {0x1708C, 0},
|
||||
{0x1808C, 0}, {0x1018C, 0}, {0x1118C, 0}, {0x1218C, 0},
|
||||
{0x1318C, 0}, {0x1418C, 0}, {0x1518C, 0}, {0x1618C, 0},
|
||||
{0x1718C, 0}, {0x1818C, 0}, {0x10040, 0}, {0x11040, 0},
|
||||
{0x12040, 0}, {0x13040, 0}, {0x14040, 0}, {0x15040, 0},
|
||||
{0x16040, 0}, {0x17040, 0}, {0x18040, 0}, {0x10140, 0},
|
||||
{0x11140, 0}, {0x12140, 0}, {0x13140, 0}, {0x14140, 0},
|
||||
{0x15140, 0}, {0x16140, 0}, {0x17140, 0}, {0x18140, 0},
|
||||
{0x10240, 0}, {0x11240, 0}, {0x12240, 0}, {0x13240, 0},
|
||||
{0x14240, 0}, {0x15240, 0}, {0x16240, 0}, {0x17240, 0},
|
||||
{0x18240, 0}, {0x10340, 0}, {0x11340, 0}, {0x12340, 0},
|
||||
{0x13340, 0}, {0x14340, 0}, {0x15340, 0}, {0x16340, 0},
|
||||
{0x17340, 0}, {0x18340, 0}, {0x10440, 0}, {0x11440, 0},
|
||||
{0x12440, 0}, {0x13440, 0}, {0x14440, 0}, {0x15440, 0},
|
||||
{0x16440, 0}, {0x17440, 0}, {0x18440, 0}, {0x10540, 0},
|
||||
{0x11540, 0}, {0x12540, 0}, {0x13540, 0}, {0x14540, 0},
|
||||
{0x15540, 0}, {0x16540, 0}, {0x17540, 0}, {0x18540, 0},
|
||||
{0x10640, 0}, {0x11640, 0}, {0x12640, 0}, {0x13640, 0},
|
||||
{0x14640, 0}, {0x15640, 0}, {0x16640, 0}, {0x17640, 0},
|
||||
{0x18640, 0}, {0x10740, 0}, {0x11740, 0}, {0x12740, 0},
|
||||
{0x13740, 0}, {0x14740, 0}, {0x15740, 0}, {0x16740, 0},
|
||||
{0x17740, 0}, {0x18740, 0}, {0x10840, 0}, {0x11840, 0},
|
||||
{0x12840, 0}, {0x13840, 0}, {0x14840, 0}, {0x15840, 0},
|
||||
{0x16840, 0}, {0x17840, 0}, {0x18840, 0}, {0x10030, 0},
|
||||
{0x11030, 0}, {0x12030, 0}, {0x13030, 0}, {0x14030, 0},
|
||||
{0x15030, 0}, {0x16030, 0}, {0x17030, 0}, {0x18030, 0},
|
||||
{0x10130, 0}, {0x11130, 0}, {0x12130, 0}, {0x13130, 0},
|
||||
{0x14130, 0}, {0x15130, 0}, {0x16130, 0}, {0x17130, 0},
|
||||
{0x18130, 0}, {0x10230, 0}, {0x11230, 0}, {0x12230, 0},
|
||||
{0x13230, 0}, {0x14230, 0}, {0x15230, 0}, {0x16230, 0},
|
||||
{0x17230, 0}, {0x18230, 0}, {0x10330, 0}, {0x11330, 0},
|
||||
{0x12330, 0}, {0x13330, 0}, {0x14330, 0}, {0x15330, 0},
|
||||
{0x16330, 0}, {0x17330, 0}, {0x18330, 0}, {0x10430, 0},
|
||||
{0x11430, 0}, {0x12430, 0}, {0x13430, 0}, {0x14430, 0},
|
||||
{0x15430, 0}, {0x16430, 0}, {0x17430, 0}, {0x18430, 0},
|
||||
{0x10530, 0}, {0x11530, 0}, {0x12530, 0}, {0x13530, 0},
|
||||
{0x14530, 0}, {0x15530, 0}, {0x16530, 0}, {0x17530, 0},
|
||||
{0x18530, 0}, {0x10630, 0}, {0x11630, 0}, {0x12630, 0},
|
||||
{0x13630, 0}, {0x14630, 0}, {0x15630, 0}, {0x16630, 0},
|
||||
{0x17630, 0}, {0x18630, 0}, {0x10730, 0}, {0x11730, 0},
|
||||
{0x12730, 0}, {0x13730, 0}, {0x14730, 0}, {0x15730, 0},
|
||||
{0x16730, 0}, {0x17730, 0}, {0x18730, 0}, {0x10830, 0},
|
||||
{0x11830, 0}, {0x12830, 0}, {0x13830, 0}, {0x14830, 0},
|
||||
{0x15830, 0}, {0x16830, 0}, {0x17830, 0}, {0x18830, 0}
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,632 @@
|
||||
/*
|
||||
* Copyright 2021 NXP
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PIE_H
|
||||
#define PIE_H
|
||||
|
||||
struct pie {
|
||||
uint32_t addr;
|
||||
uint16_t data;
|
||||
};
|
||||
|
||||
static const struct pie pie_udimm[] = {
|
||||
{0x90000, 0x10},
|
||||
{0x90001, 0x400},
|
||||
{0x90002, 0x10e},
|
||||
{0x90003, 0x0},
|
||||
{0x90004, 0x0},
|
||||
{0x90005, 0x8},
|
||||
{0x90029, 0xb},
|
||||
{0x9002a, 0x480},
|
||||
{0x9002b, 0x109},
|
||||
{0x9002c, 0x8},
|
||||
{0x9002d, 0x448},
|
||||
{0x9002e, 0x139},
|
||||
{0x9002f, 0x8},
|
||||
{0x90030, 0x478},
|
||||
{0x90031, 0x109},
|
||||
{0x90032, 0x2},
|
||||
{0x90033, 0x10},
|
||||
{0x90034, 0x139},
|
||||
{0x90035, 0xb},
|
||||
{0x90036, 0x7c0},
|
||||
{0x90037, 0x139},
|
||||
{0x90038, 0x44},
|
||||
{0x90039, 0x633},
|
||||
{0x9003a, 0x159},
|
||||
{0x9003b, 0x14f},
|
||||
{0x9003c, 0x630},
|
||||
{0x9003d, 0x159},
|
||||
{0x9003e, 0x47},
|
||||
{0x9003f, 0x633},
|
||||
{0x90040, 0x149},
|
||||
{0x90041, 0x4f},
|
||||
{0x90042, 0x633},
|
||||
{0x90043, 0x179},
|
||||
{0x90044, 0x8},
|
||||
{0x90045, 0xe0},
|
||||
{0x90046, 0x109},
|
||||
{0x90047, 0x0},
|
||||
{0x90048, 0x7c8},
|
||||
{0x90049, 0x109},
|
||||
{0x9004a, 0x0},
|
||||
{0x9004b, 0x1},
|
||||
{0x9004c, 0x8},
|
||||
{0x9004d, 0x0},
|
||||
{0x9004e, 0x45a},
|
||||
{0x9004f, 0x9},
|
||||
{0x90050, 0x0},
|
||||
{0x90051, 0x448},
|
||||
{0x90052, 0x109},
|
||||
{0x90053, 0x40},
|
||||
{0x90054, 0x633},
|
||||
{0x90055, 0x179},
|
||||
{0x90056, 0x1},
|
||||
{0x90057, 0x618},
|
||||
{0x90058, 0x109},
|
||||
{0x90059, 0x40c0},
|
||||
{0x9005a, 0x633},
|
||||
{0x9005b, 0x149},
|
||||
{0x9005c, 0x8},
|
||||
{0x9005d, 0x4},
|
||||
{0x9005e, 0x48},
|
||||
{0x9005f, 0x4040},
|
||||
{0x90060, 0x633},
|
||||
{0x90061, 0x149},
|
||||
{0x90062, 0x0},
|
||||
{0x90063, 0x4},
|
||||
{0x90064, 0x48},
|
||||
{0x90065, 0x40},
|
||||
{0x90066, 0x633},
|
||||
{0x90067, 0x149},
|
||||
{0x90068, 0x10},
|
||||
{0x90069, 0x4},
|
||||
{0x9006a, 0x18},
|
||||
{0x9006b, 0x0},
|
||||
{0x9006c, 0x4},
|
||||
{0x9006d, 0x78},
|
||||
{0x9006e, 0x549},
|
||||
{0x9006f, 0x633},
|
||||
{0x90070, 0x159},
|
||||
{0x90071, 0xd49},
|
||||
{0x90072, 0x633},
|
||||
{0x90073, 0x159},
|
||||
{0x90074, 0x94a},
|
||||
{0x90075, 0x633},
|
||||
{0x90076, 0x159},
|
||||
{0x90077, 0x441},
|
||||
{0x90078, 0x633},
|
||||
{0x90079, 0x149},
|
||||
{0x9007a, 0x42},
|
||||
{0x9007b, 0x633},
|
||||
{0x9007c, 0x149},
|
||||
{0x9007d, 0x1},
|
||||
{0x9007e, 0x633},
|
||||
{0x9007f, 0x149},
|
||||
{0x90080, 0x0},
|
||||
{0x90081, 0xe0},
|
||||
{0x90082, 0x109},
|
||||
{0x90083, 0xa},
|
||||
{0x90084, 0x10},
|
||||
{0x90085, 0x109},
|
||||
{0x90086, 0x9},
|
||||
{0x90087, 0x3c0},
|
||||
{0x90088, 0x149},
|
||||
{0x90089, 0x9},
|
||||
{0x9008a, 0x3c0},
|
||||
{0x9008b, 0x159},
|
||||
{0x9008c, 0x18},
|
||||
{0x9008d, 0x10},
|
||||
{0x9008e, 0x109},
|
||||
{0x9008f, 0x0},
|
||||
{0x90090, 0x3c0},
|
||||
{0x90091, 0x109},
|
||||
{0x90092, 0x18},
|
||||
{0x90093, 0x4},
|
||||
{0x90094, 0x48},
|
||||
{0x90095, 0x18},
|
||||
{0x90096, 0x4},
|
||||
{0x90097, 0x58},
|
||||
{0x90098, 0xb},
|
||||
{0x90099, 0x10},
|
||||
{0x9009a, 0x109},
|
||||
{0x9009b, 0x1},
|
||||
{0x9009c, 0x10},
|
||||
{0x9009d, 0x109},
|
||||
{0x9009e, 0x5},
|
||||
{0x9009f, 0x7c0},
|
||||
{0x900a0, 0x109},
|
||||
{0x900a1, 0x0},
|
||||
{0x900a2, 0x8140},
|
||||
{0x900a3, 0x10c},
|
||||
{0x900a4, 0x10},
|
||||
{0x900a5, 0x8138},
|
||||
{0x900a6, 0x10c},
|
||||
{0x900a7, 0x8},
|
||||
{0x900a8, 0x7c8},
|
||||
{0x900a9, 0x101},
|
||||
{0x900aa, 0x8},
|
||||
{0x900ab, 0x448},
|
||||
{0x900ac, 0x109},
|
||||
{0x900ad, 0xf},
|
||||
{0x900ae, 0x7c0},
|
||||
{0x900af, 0x109},
|
||||
{0x900b0, 0x47},
|
||||
{0x900b1, 0x630},
|
||||
{0x900b2, 0x109},
|
||||
{0x900b3, 0x8},
|
||||
{0x900b4, 0x618},
|
||||
{0x900b5, 0x109},
|
||||
{0x900b6, 0x8},
|
||||
{0x900b7, 0xe0},
|
||||
{0x900b8, 0x109},
|
||||
{0x900b9, 0x0},
|
||||
{0x900ba, 0x7c8},
|
||||
{0x900bb, 0x109},
|
||||
{0x900bc, 0x8},
|
||||
{0x900bd, 0x8140},
|
||||
{0x900be, 0x10c},
|
||||
{0x900bf, 0x0},
|
||||
{0x900c0, 0x478},
|
||||
{0x900c1, 0x109},
|
||||
{0x900c2, 0x0},
|
||||
{0x900c3, 0x1},
|
||||
{0x900c4, 0x8},
|
||||
{0x900c5, 0x8},
|
||||
{0x900c6, 0x4},
|
||||
{0x900c7, 0x8},
|
||||
{0x900c8, 0x8},
|
||||
{0x900c9, 0x7c8},
|
||||
{0x900ca, 0x101},
|
||||
{0x90006, 0x0},
|
||||
{0x90007, 0x0},
|
||||
{0x90008, 0x8},
|
||||
{0x90009, 0x0},
|
||||
{0x9000a, 0x0},
|
||||
{0x9000b, 0x0},
|
||||
{0xd00e7, 0x400},
|
||||
{0x90017, 0x0},
|
||||
{0x90026, 0x2b},
|
||||
};
|
||||
|
||||
static const struct pie pie_rdimm[] = {
|
||||
{0x90000, 0x10},
|
||||
{0x90001, 0x400},
|
||||
{0x90002, 0x10e},
|
||||
{0x90003, 0x0},
|
||||
{0x90004, 0x0},
|
||||
{0x90005, 0x8},
|
||||
{0x40000, 0x10},
|
||||
{0x40020, 0x0},
|
||||
{0x40040, 0x0},
|
||||
{0x40060, 0x0},
|
||||
{0x40001, 0x70a},
|
||||
{0x40021, 0x7005},
|
||||
{0x40041, 0x0},
|
||||
{0x40061, 0x2001},
|
||||
{0x40002, 0x4010},
|
||||
{0x40022, 0x0},
|
||||
{0x40042, 0x0},
|
||||
{0x40062, 0x0},
|
||||
{0x90029, 0x10},
|
||||
{0x9002a, 0x400},
|
||||
{0x9002b, 0x16e},
|
||||
{0x9002c, 0x8},
|
||||
{0x9002d, 0x370},
|
||||
{0x9002e, 0x169},
|
||||
{0x9002f, 0x8},
|
||||
{0x90030, 0x7aa},
|
||||
{0x90031, 0x6a},
|
||||
{0x90032, 0x10},
|
||||
{0x90033, 0x7b2},
|
||||
{0x90034, 0x6a},
|
||||
{0x90035, 0x0},
|
||||
{0x90036, 0x48a},
|
||||
{0x90037, 0x6a},
|
||||
{0x90038, 0x9},
|
||||
{0x90039, 0x480},
|
||||
{0x9003a, 0x16a},
|
||||
{0x9003b, 0x4},
|
||||
{0x9003c, 0x790},
|
||||
{0x9003d, 0x16a},
|
||||
{0x9003e, 0xc},
|
||||
{0x9003f, 0x408},
|
||||
{0x90040, 0x169},
|
||||
{0x90041, 0xa},
|
||||
{0x90042, 0x0},
|
||||
{0x90043, 0x68},
|
||||
{0x90044, 0x0},
|
||||
{0x90045, 0x408},
|
||||
{0x90046, 0x169},
|
||||
{0x90047, 0x1},
|
||||
{0x90048, 0x480},
|
||||
{0x90049, 0x16a},
|
||||
{0x9004a, 0xb},
|
||||
{0x9004b, 0x480},
|
||||
{0x9004c, 0x109},
|
||||
{0x9004d, 0x8},
|
||||
{0x9004e, 0x448},
|
||||
{0x9004f, 0x139},
|
||||
{0x90050, 0x78},
|
||||
{0x90051, 0x8},
|
||||
{0x90052, 0x139},
|
||||
{0x90053, 0x2},
|
||||
{0x90054, 0x10},
|
||||
{0x90055, 0x139},
|
||||
{0x90056, 0xb},
|
||||
{0x90057, 0x7c0},
|
||||
{0x90058, 0x139},
|
||||
{0x90059, 0x44},
|
||||
{0x9005a, 0x633},
|
||||
{0x9005b, 0x159},
|
||||
{0x9005c, 0x14f},
|
||||
{0x9005d, 0x630},
|
||||
{0x9005e, 0x159},
|
||||
{0x9005f, 0x47},
|
||||
{0x90060, 0x633},
|
||||
{0x90061, 0x149},
|
||||
{0x90062, 0x4f},
|
||||
{0x90063, 0x633},
|
||||
{0x90064, 0x179},
|
||||
{0x90065, 0x8},
|
||||
{0x90066, 0xe0},
|
||||
{0x90067, 0x109},
|
||||
{0x90068, 0x0},
|
||||
{0x90069, 0x7c8},
|
||||
{0x9006a, 0x109},
|
||||
{0x9006b, 0x0},
|
||||
{0x9006c, 0x1},
|
||||
{0x9006d, 0x8},
|
||||
{0x9006e, 0x0},
|
||||
{0x9006f, 0x45a},
|
||||
{0x90070, 0x9},
|
||||
{0x90071, 0x0},
|
||||
{0x90072, 0x448},
|
||||
{0x90073, 0x109},
|
||||
{0x90074, 0x40},
|
||||
{0x90075, 0x633},
|
||||
{0x90076, 0x179},
|
||||
{0x90077, 0x1},
|
||||
{0x90078, 0x618},
|
||||
{0x90079, 0x109},
|
||||
{0x9007a, 0x40c0},
|
||||
{0x9007b, 0x633},
|
||||
{0x9007c, 0x149},
|
||||
{0x9007d, 0x8},
|
||||
{0x9007e, 0x4},
|
||||
{0x9007f, 0x48},
|
||||
{0x90080, 0x4040},
|
||||
{0x90081, 0x633},
|
||||
{0x90082, 0x149},
|
||||
{0x90083, 0x0},
|
||||
{0x90084, 0x4},
|
||||
{0x90085, 0x48},
|
||||
{0x90086, 0x40},
|
||||
{0x90087, 0x633},
|
||||
{0x90088, 0x149},
|
||||
{0x90089, 0x10},
|
||||
{0x9008a, 0x4},
|
||||
{0x9008b, 0x18},
|
||||
{0x9008c, 0x0},
|
||||
{0x9008d, 0x4},
|
||||
{0x9008e, 0x78},
|
||||
{0x9008f, 0x549},
|
||||
{0x90090, 0x633},
|
||||
{0x90091, 0x159},
|
||||
{0x90092, 0xd49},
|
||||
{0x90093, 0x633},
|
||||
{0x90094, 0x159},
|
||||
{0x90095, 0x94a},
|
||||
{0x90096, 0x633},
|
||||
{0x90097, 0x159},
|
||||
{0x90098, 0x441},
|
||||
{0x90099, 0x633},
|
||||
{0x9009a, 0x149},
|
||||
{0x9009b, 0x42},
|
||||
{0x9009c, 0x633},
|
||||
{0x9009d, 0x149},
|
||||
{0x9009e, 0x1},
|
||||
{0x9009f, 0x633},
|
||||
{0x900a0, 0x149},
|
||||
{0x900a1, 0x0},
|
||||
{0x900a2, 0xe0},
|
||||
{0x900a3, 0x109},
|
||||
{0x900a4, 0xa},
|
||||
{0x900a5, 0x10},
|
||||
{0x900a6, 0x109},
|
||||
{0x900a7, 0x9},
|
||||
{0x900a8, 0x3c0},
|
||||
{0x900a9, 0x149},
|
||||
{0x900aa, 0x9},
|
||||
{0x900ab, 0x3c0},
|
||||
{0x900ac, 0x159},
|
||||
{0x900ad, 0x18},
|
||||
{0x900ae, 0x10},
|
||||
{0x900af, 0x109},
|
||||
{0x900b0, 0x0},
|
||||
{0x900b1, 0x3c0},
|
||||
{0x900b2, 0x109},
|
||||
{0x900b3, 0x18},
|
||||
{0x900b4, 0x4},
|
||||
{0x900b5, 0x48},
|
||||
{0x900b6, 0x18},
|
||||
{0x900b7, 0x4},
|
||||
{0x900b8, 0x58},
|
||||
{0x900b9, 0xb},
|
||||
{0x900ba, 0x10},
|
||||
{0x900bb, 0x109},
|
||||
{0x900bc, 0x1},
|
||||
{0x900bd, 0x10},
|
||||
{0x900be, 0x109},
|
||||
{0x900bf, 0x5},
|
||||
{0x900c0, 0x7c0},
|
||||
{0x900c1, 0x109},
|
||||
{0x900c2, 0x3},
|
||||
{0x900c3, 0x370},
|
||||
{0x900c4, 0x169},
|
||||
{0x900c5, 0x3},
|
||||
{0x900c6, 0x8},
|
||||
{0x900c7, 0x139},
|
||||
{0x900c8, 0x0},
|
||||
{0x900c9, 0x400},
|
||||
{0x900ca, 0x16e},
|
||||
{0x900cb, 0x8},
|
||||
{0x900cc, 0x478},
|
||||
{0x900cd, 0x109},
|
||||
{0x900ce, 0x0},
|
||||
{0x900cf, 0x8140},
|
||||
{0x900d0, 0x10c},
|
||||
{0x900d1, 0x10},
|
||||
{0x900d2, 0x8138},
|
||||
{0x900d3, 0x10c},
|
||||
{0x900d4, 0x8},
|
||||
{0x900d5, 0x7c8},
|
||||
{0x900d6, 0x101},
|
||||
{0x900d7, 0x7a},
|
||||
{0x900d8, 0x8},
|
||||
{0x900d9, 0x109},
|
||||
{0x900da, 0x8},
|
||||
{0x900db, 0x448},
|
||||
{0x900dc, 0x109},
|
||||
{0x900dd, 0xf},
|
||||
{0x900de, 0x7c0},
|
||||
{0x900df, 0x109},
|
||||
{0x900e0, 0x47},
|
||||
{0x900e1, 0x630},
|
||||
{0x900e2, 0x109},
|
||||
{0x900e3, 0x8},
|
||||
{0x900e4, 0x618},
|
||||
{0x900e5, 0x109},
|
||||
{0x900e6, 0x8},
|
||||
{0x900e7, 0xe0},
|
||||
{0x900e8, 0x109},
|
||||
{0x900e9, 0x0},
|
||||
{0x900ea, 0x8},
|
||||
{0x900eb, 0x109},
|
||||
{0x900ec, 0x0},
|
||||
{0x900ed, 0x7c8},
|
||||
{0x900ee, 0x109},
|
||||
{0x900ef, 0x8},
|
||||
{0x900f0, 0x8140},
|
||||
{0x900f1, 0x10c},
|
||||
{0x900f2, 0x0},
|
||||
{0x900f3, 0x478},
|
||||
{0x900f4, 0x109},
|
||||
{0x900f5, 0x0},
|
||||
{0x900f6, 0x1},
|
||||
{0x900f7, 0x8},
|
||||
{0x900f8, 0x8},
|
||||
{0x900f9, 0x4},
|
||||
{0x900fa, 0x8},
|
||||
{0x900fb, 0x8},
|
||||
{0x900fc, 0x7c8},
|
||||
{0x900fd, 0x101},
|
||||
{0x90006, 0x0},
|
||||
{0x90007, 0x0},
|
||||
{0x90008, 0x8},
|
||||
{0x90009, 0x0},
|
||||
{0x9000a, 0x0},
|
||||
{0x9000b, 0x0},
|
||||
{0xd00e7, 0x400},
|
||||
{0x90017, 0x0},
|
||||
{0x90026, 0x3a},
|
||||
};
|
||||
|
||||
static const struct pie pie_lrdimm[] = {
|
||||
{0x90000, 0x10},
|
||||
{0x90001, 0x400},
|
||||
{0x90002, 0x10e},
|
||||
{0x90003, 0x0},
|
||||
{0x90004, 0x0},
|
||||
{0x90005, 0x8},
|
||||
{0x90029, 0xb},
|
||||
{0x9002a, 0x480},
|
||||
{0x9002b, 0x109},
|
||||
{0x9002c, 0x8},
|
||||
{0x9002d, 0x448},
|
||||
{0x9002e, 0x139},
|
||||
{0x9002f, 0x78},
|
||||
{0x90030, 0x8},
|
||||
{0x90031, 0x139},
|
||||
{0x90032, 0x2},
|
||||
{0x90033, 0x10},
|
||||
{0x90034, 0x139},
|
||||
{0x90035, 0xb},
|
||||
{0x90036, 0x7c0},
|
||||
{0x90037, 0x139},
|
||||
{0x90038, 0x44},
|
||||
{0x90039, 0x633},
|
||||
{0x9003a, 0x159},
|
||||
{0x9003b, 0x14f},
|
||||
{0x9003c, 0x630},
|
||||
{0x9003d, 0x159},
|
||||
{0x9003e, 0x47},
|
||||
{0x9003f, 0x633},
|
||||
{0x90040, 0x149},
|
||||
{0x90041, 0x4f},
|
||||
{0x90042, 0x633},
|
||||
{0x90043, 0x179},
|
||||
{0x90044, 0x8},
|
||||
{0x90045, 0xe0},
|
||||
{0x90046, 0x109},
|
||||
{0x90047, 0x0},
|
||||
{0x90048, 0x7c8},
|
||||
{0x90049, 0x109},
|
||||
{0x9004a, 0x0},
|
||||
{0x9004b, 0x1},
|
||||
{0x9004c, 0x8},
|
||||
{0x9004d, 0x0},
|
||||
{0x9004e, 0x45a},
|
||||
{0x9004f, 0x9},
|
||||
{0x90050, 0x0},
|
||||
{0x90051, 0x448},
|
||||
{0x90052, 0x109},
|
||||
{0x90053, 0x40},
|
||||
{0x90054, 0x633},
|
||||
{0x90055, 0x179},
|
||||
{0x90056, 0x1},
|
||||
{0x90057, 0x618},
|
||||
{0x90058, 0x109},
|
||||
{0x90059, 0x40c0},
|
||||
{0x9005a, 0x633},
|
||||
{0x9005b, 0x149},
|
||||
{0x9005c, 0x8},
|
||||
{0x9005d, 0x4},
|
||||
{0x9005e, 0x48},
|
||||
{0x9005f, 0x4040},
|
||||
{0x90060, 0x633},
|
||||
{0x90061, 0x149},
|
||||
{0x90062, 0x0},
|
||||
{0x90063, 0x4},
|
||||
{0x90064, 0x48},
|
||||
{0x90065, 0x40},
|
||||
{0x90066, 0x633},
|
||||
{0x90067, 0x149},
|
||||
{0x90068, 0x10},
|
||||
{0x90069, 0x4},
|
||||
{0x9006a, 0x18},
|
||||
{0x9006b, 0x0},
|
||||
{0x9006c, 0x4},
|
||||
{0x9006d, 0x78},
|
||||
{0x9006e, 0x549},
|
||||
{0x9006f, 0x633},
|
||||
{0x90070, 0x159},
|
||||
{0x90071, 0xd49},
|
||||
{0x90072, 0x633},
|
||||
{0x90073, 0x159},
|
||||
{0x90074, 0x94a},
|
||||
{0x90075, 0x633},
|
||||
{0x90076, 0x159},
|
||||
{0x90077, 0x441},
|
||||
{0x90078, 0x633},
|
||||
{0x90079, 0x149},
|
||||
{0x9007a, 0x42},
|
||||
{0x9007b, 0x633},
|
||||
{0x9007c, 0x149},
|
||||
{0x9007d, 0x1},
|
||||
{0x9007e, 0x633},
|
||||
{0x9007f, 0x149},
|
||||
{0x90080, 0x0},
|
||||
{0x90081, 0xe0},
|
||||
{0x90082, 0x109},
|
||||
{0x90083, 0xa},
|
||||
{0x90084, 0x10},
|
||||
{0x90085, 0x109},
|
||||
{0x90086, 0x9},
|
||||
{0x90087, 0x3c0},
|
||||
{0x90088, 0x149},
|
||||
{0x90089, 0x9},
|
||||
{0x9008a, 0x3c0},
|
||||
{0x9008b, 0x159},
|
||||
{0x9008c, 0x18},
|
||||
{0x9008d, 0x10},
|
||||
{0x9008e, 0x109},
|
||||
{0x9008f, 0x0},
|
||||
{0x90090, 0x3c0},
|
||||
{0x90091, 0x109},
|
||||
{0x90092, 0x18},
|
||||
{0x90093, 0x4},
|
||||
{0x90094, 0x48},
|
||||
{0x90095, 0x18},
|
||||
{0x90096, 0x4},
|
||||
{0x90097, 0x58},
|
||||
{0x90098, 0xb},
|
||||
{0x90099, 0x10},
|
||||
{0x9009a, 0x109},
|
||||
{0x9009b, 0x1},
|
||||
{0x9009c, 0x10},
|
||||
{0x9009d, 0x109},
|
||||
{0x9009e, 0x5},
|
||||
{0x9009f, 0x7c0},
|
||||
{0x900a0, 0x109},
|
||||
{0x900a1, 0x3},
|
||||
{0x900a2, 0x8},
|
||||
{0x900a3, 0x139},
|
||||
{0x900a4, 0x0},
|
||||
{0x900a5, 0x400},
|
||||
{0x900a6, 0x16e},
|
||||
{0x900a7, 0x8},
|
||||
{0x900a8, 0x478},
|
||||
{0x900a9, 0x109},
|
||||
{0x900aa, 0x0},
|
||||
{0x900ab, 0x8140},
|
||||
{0x900ac, 0x10c},
|
||||
{0x900ad, 0x10},
|
||||
{0x900ae, 0x8138},
|
||||
{0x900af, 0x10c},
|
||||
{0x900b0, 0x8},
|
||||
{0x900b1, 0x7c8},
|
||||
{0x900b2, 0x101},
|
||||
{0x900b3, 0x7a},
|
||||
{0x900b4, 0x8},
|
||||
{0x900b5, 0x109},
|
||||
{0x900b6, 0x8},
|
||||
{0x900b7, 0x448},
|
||||
{0x900b8, 0x109},
|
||||
{0x900b9, 0xf},
|
||||
{0x900ba, 0x7c0},
|
||||
{0x900bb, 0x109},
|
||||
{0x900bc, 0x47},
|
||||
{0x900bd, 0x630},
|
||||
{0x900be, 0x109},
|
||||
{0x900bf, 0x8},
|
||||
{0x900c0, 0x618},
|
||||
{0x900c1, 0x109},
|
||||
{0x900c2, 0x8},
|
||||
{0x900c3, 0xe0},
|
||||
{0x900c4, 0x109},
|
||||
{0x900c5, 0x0},
|
||||
{0x900c6, 0x8},
|
||||
{0x900c7, 0x109},
|
||||
{0x900c8, 0x0},
|
||||
{0x900c9, 0x7c8},
|
||||
{0x900ca, 0x109},
|
||||
{0x900cb, 0x8},
|
||||
{0x900cc, 0x8140},
|
||||
{0x900cd, 0x10c},
|
||||
{0x900ce, 0x0},
|
||||
{0x900cf, 0x478},
|
||||
{0x900d0, 0x109},
|
||||
{0x900d1, 0x0},
|
||||
{0x900d2, 0x1},
|
||||
{0x900d3, 0x8},
|
||||
{0x900d4, 0x8},
|
||||
{0x900d5, 0x4},
|
||||
{0x900d6, 0x8},
|
||||
{0x900d7, 0x8},
|
||||
{0x900d8, 0x7c8},
|
||||
{0x900d9, 0x101},
|
||||
{0x90006, 0x0},
|
||||
{0x90007, 0x0},
|
||||
{0x90008, 0x8},
|
||||
{0x90009, 0x0},
|
||||
{0x9000a, 0x0},
|
||||
{0x9000b, 0x0},
|
||||
{0xd00e7, 0x400},
|
||||
{0x90017, 0x0},
|
||||
{0x90026, 0x2e},
|
||||
};
|
||||
#endif
|
||||
Reference in New Issue
Block a user