GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
+4484
File diff suppressed because it is too large
Load Diff
+2108
File diff suppressed because it is too large
Load Diff
+95
@@ -0,0 +1,95 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2021, Renesas Electronics Corporation.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define RCAR_DDR_VERSION "rev.0.41"
|
||||
#define DRAM_CH_CNT 0x04
|
||||
#define SLICE_CNT 0x04
|
||||
#define CS_CNT 0x02
|
||||
|
||||
/* order : CS0A, CS0B, CS1A, CS1B */
|
||||
#define CSAB_CNT (CS_CNT * 2)
|
||||
|
||||
/* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */
|
||||
#define CHAB_CNT (DRAM_CH_CNT * 2)
|
||||
|
||||
/* pll setting */
|
||||
#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
|
||||
#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
|
||||
|
||||
/* for ddr deisity setting */
|
||||
#define DBMEMCONF_REG(d3, row, bank, col, dw) \
|
||||
(((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
|
||||
|
||||
#define DBMEMCONF_REGD(density) \
|
||||
(DBMEMCONF_REG((density) % 2, ((density) + 1) / \
|
||||
2 + (29 - 3 - 10 - 2), 3, 10, 2))
|
||||
|
||||
#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
|
||||
|
||||
/* refresh mode */
|
||||
#define DBSC_REFINTS (0x0)
|
||||
|
||||
/* system registers */
|
||||
#define CPG_FRQCRB (CPG_BASE + 0x0004U)
|
||||
|
||||
#define CPG_PLLECR (CPG_BASE + 0x00D0U)
|
||||
#define CPG_MSTPSR5 (CPG_BASE + 0x003CU)
|
||||
#define CPG_SRCR4 (CPG_BASE + 0x00BCU)
|
||||
#define CPG_PLL3CR (CPG_BASE + 0x00DCU)
|
||||
#define CPG_ZB3CKCR (CPG_BASE + 0x0380U)
|
||||
#define CPG_FRQCRD (CPG_BASE + 0x00E4U)
|
||||
#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U)
|
||||
#define CPG_CPGWPR (CPG_BASE + 0x0900U)
|
||||
#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U)
|
||||
|
||||
#define CPG_FRQCRB_KICK_BIT BIT(31)
|
||||
#define CPG_PLLECR_PLL3E_BIT BIT(3)
|
||||
#define CPG_PLLECR_PLL3ST_BIT BIT(11)
|
||||
#define CPG_ZB3CKCR_ZB3ST_BIT BIT(11)
|
||||
|
||||
#define RST_BASE (0xE6160000U)
|
||||
#define RST_MODEMR (RST_BASE + 0x0060U)
|
||||
|
||||
#define LIFEC_CHIPID(x) (0xE6110040U + 0x04U * (x))
|
||||
|
||||
/* DBSC registers */
|
||||
#include "../ddr_regs.h"
|
||||
|
||||
#define DBSC_DBMONCONF4 0xE6793010U
|
||||
|
||||
#define DBSC_PLL_LOCK(ch) (0xE6794054U + 0x100U * (ch))
|
||||
#define DBSC_PLL_LOCK_0 0xE6794054U
|
||||
#define DBSC_PLL_LOCK_1 0xE6794154U
|
||||
#define DBSC_PLL_LOCK_2 0xE6794254U
|
||||
#define DBSC_PLL_LOCK_3 0xE6794354U
|
||||
|
||||
/* STAT registers */
|
||||
#define MSTAT_SL_INIT 0xE67E8000U
|
||||
#define MSTAT_REF_ARS 0xE67E8004U
|
||||
#define MSTATQ_STATQC 0xE67E8008U
|
||||
#define MSTATQ_WTENABLE 0xE67E8030U
|
||||
#define MSTATQ_WTREFRESH 0xE67E8034U
|
||||
#define MSTATQ_WTSETTING0 0xE67E8038U
|
||||
#define MSTATQ_WTSETTING1 0xE67E803CU
|
||||
|
||||
#define QOS_BASE1 (0xE67F0000U)
|
||||
#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U)
|
||||
#define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U)
|
||||
#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U)
|
||||
#define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U)
|
||||
#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U)
|
||||
#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U)
|
||||
#define QOSCTRL_EC (QOS_BASE1 + 0x003CU)
|
||||
#define QOSCTRL_EMS (QOS_BASE1 + 0x0040U)
|
||||
#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U)
|
||||
#define QOSCTRL_BERR (QOS_BASE1 + 0x0054U)
|
||||
#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U)
|
||||
#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U)
|
||||
|
||||
/* other module */
|
||||
#define THS1_THCTR 0xE6198020U
|
||||
#define THS1_TEMP 0xE6198028U
|
||||
+7
@@ -0,0 +1,7 @@
|
||||
#
|
||||
# Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
BL2_SOURCES += drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
|
||||
+5887
File diff suppressed because it is too large
Load Diff
+441
@@ -0,0 +1,441 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_OFS_H3 0x0400
|
||||
#define DDR_PHY_ADR_V_REGSET_OFS_H3 0x0600
|
||||
#define DDR_PHY_ADR_I_REGSET_OFS_H3 0x0680
|
||||
#define DDR_PHY_ADR_G_REGSET_OFS_H3 0x0700
|
||||
#define DDR_PI_REGSET_OFS_H3 0x0200
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_SIZE_H3 0x80
|
||||
#define DDR_PHY_ADR_V_REGSET_SIZE_H3 0x80
|
||||
#define DDR_PHY_ADR_I_REGSET_SIZE_H3 0x80
|
||||
#define DDR_PHY_ADR_G_REGSET_SIZE_H3 0x80
|
||||
#define DDR_PI_REGSET_SIZE_H3 0x100
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_NUM_H3 88
|
||||
#define DDR_PHY_ADR_V_REGSET_NUM_H3 37
|
||||
#define DDR_PHY_ADR_I_REGSET_NUM_H3 37
|
||||
#define DDR_PHY_ADR_G_REGSET_NUM_H3 59
|
||||
#define DDR_PI_REGSET_NUM_H3 181
|
||||
|
||||
static const uint32_t DDR_PHY_SLICE_REGSET_H3[DDR_PHY_SLICE_REGSET_NUM_H3] = {
|
||||
/*0400*/ 0x000004f0,
|
||||
/*0401*/ 0x00000000,
|
||||
/*0402*/ 0x00000000,
|
||||
/*0403*/ 0x00000100,
|
||||
/*0404*/ 0x01003c0c,
|
||||
/*0405*/ 0x02003c0c,
|
||||
/*0406*/ 0x00010300,
|
||||
/*0407*/ 0x04000100,
|
||||
/*0408*/ 0x00000300,
|
||||
/*0409*/ 0x000700c0,
|
||||
/*040a*/ 0x00b00201,
|
||||
/*040b*/ 0x00000020,
|
||||
/*040c*/ 0x00000000,
|
||||
/*040d*/ 0x00000000,
|
||||
/*040e*/ 0x00000000,
|
||||
/*040f*/ 0x00000000,
|
||||
/*0410*/ 0x00000000,
|
||||
/*0411*/ 0x00000000,
|
||||
/*0412*/ 0x00000000,
|
||||
/*0413*/ 0x09000000,
|
||||
/*0414*/ 0x04080000,
|
||||
/*0415*/ 0x04080400,
|
||||
/*0416*/ 0x00000000,
|
||||
/*0417*/ 0x32103210,
|
||||
/*0418*/ 0x00800708,
|
||||
/*0419*/ 0x000f000c,
|
||||
/*041a*/ 0x00000100,
|
||||
/*041b*/ 0x55aa55aa,
|
||||
/*041c*/ 0x33cc33cc,
|
||||
/*041d*/ 0x0ff00ff0,
|
||||
/*041e*/ 0x0f0ff0f0,
|
||||
/*041f*/ 0x00008e38,
|
||||
/*0420*/ 0x76543210,
|
||||
/*0421*/ 0x00000001,
|
||||
/*0422*/ 0x00000000,
|
||||
/*0423*/ 0x00000000,
|
||||
/*0424*/ 0x00000000,
|
||||
/*0425*/ 0x00000000,
|
||||
/*0426*/ 0x00000000,
|
||||
/*0427*/ 0x00000000,
|
||||
/*0428*/ 0x00000000,
|
||||
/*0429*/ 0x00000000,
|
||||
/*042a*/ 0x00000000,
|
||||
/*042b*/ 0x00000000,
|
||||
/*042c*/ 0x00000000,
|
||||
/*042d*/ 0x00000000,
|
||||
/*042e*/ 0x00000000,
|
||||
/*042f*/ 0x00000000,
|
||||
/*0430*/ 0x00000000,
|
||||
/*0431*/ 0x00000000,
|
||||
/*0432*/ 0x00000000,
|
||||
/*0433*/ 0x00200000,
|
||||
/*0434*/ 0x08200820,
|
||||
/*0435*/ 0x08200820,
|
||||
/*0436*/ 0x08200820,
|
||||
/*0437*/ 0x08200820,
|
||||
/*0438*/ 0x08200820,
|
||||
/*0439*/ 0x00000820,
|
||||
/*043a*/ 0x03000300,
|
||||
/*043b*/ 0x03000300,
|
||||
/*043c*/ 0x03000300,
|
||||
/*043d*/ 0x03000300,
|
||||
/*043e*/ 0x00000300,
|
||||
/*043f*/ 0x00000000,
|
||||
/*0440*/ 0x00000000,
|
||||
/*0441*/ 0x00000000,
|
||||
/*0442*/ 0x00000000,
|
||||
/*0443*/ 0x00a000a0,
|
||||
/*0444*/ 0x00a000a0,
|
||||
/*0445*/ 0x00a000a0,
|
||||
/*0446*/ 0x00a000a0,
|
||||
/*0447*/ 0x00a000a0,
|
||||
/*0448*/ 0x00a000a0,
|
||||
/*0449*/ 0x00a000a0,
|
||||
/*044a*/ 0x00a000a0,
|
||||
/*044b*/ 0x00a000a0,
|
||||
/*044c*/ 0x01040109,
|
||||
/*044d*/ 0x00000200,
|
||||
/*044e*/ 0x01000000,
|
||||
/*044f*/ 0x00000200,
|
||||
/*0450*/ 0x4041a151,
|
||||
/*0451*/ 0xc00141a0,
|
||||
/*0452*/ 0x0e0100c0,
|
||||
/*0453*/ 0x0010000c,
|
||||
/*0454*/ 0x0c064208,
|
||||
/*0455*/ 0x000f0c18,
|
||||
/*0456*/ 0x00e00140,
|
||||
/*0457*/ 0x00000c20
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_V_REGSET_H3[DDR_PHY_ADR_V_REGSET_NUM_H3] = {
|
||||
/*0600*/ 0x00000000,
|
||||
/*0601*/ 0x00000000,
|
||||
/*0602*/ 0x00000000,
|
||||
/*0603*/ 0x00000000,
|
||||
/*0604*/ 0x00000000,
|
||||
/*0605*/ 0x00000000,
|
||||
/*0606*/ 0x00000002,
|
||||
/*0607*/ 0x00000000,
|
||||
/*0608*/ 0x00000000,
|
||||
/*0609*/ 0x00000000,
|
||||
/*060a*/ 0x00400320,
|
||||
/*060b*/ 0x00000040,
|
||||
/*060c*/ 0x00dcba98,
|
||||
/*060d*/ 0x00000000,
|
||||
/*060e*/ 0x00dcba98,
|
||||
/*060f*/ 0x01000000,
|
||||
/*0610*/ 0x00020003,
|
||||
/*0611*/ 0x00000000,
|
||||
/*0612*/ 0x00000000,
|
||||
/*0613*/ 0x00000000,
|
||||
/*0614*/ 0x00002a01,
|
||||
/*0615*/ 0x00000015,
|
||||
/*0616*/ 0x00000015,
|
||||
/*0617*/ 0x0000002a,
|
||||
/*0618*/ 0x00000033,
|
||||
/*0619*/ 0x0000000c,
|
||||
/*061a*/ 0x0000000c,
|
||||
/*061b*/ 0x00000033,
|
||||
/*061c*/ 0x00418820,
|
||||
/*061d*/ 0x003f0000,
|
||||
/*061e*/ 0x0000003f,
|
||||
/*061f*/ 0x0002006e,
|
||||
/*0620*/ 0x02000200,
|
||||
/*0621*/ 0x02000200,
|
||||
/*0622*/ 0x00000200,
|
||||
/*0623*/ 0x42080010,
|
||||
/*0624*/ 0x00000003
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_I_REGSET_H3[DDR_PHY_ADR_I_REGSET_NUM_H3] = {
|
||||
/*0680*/ 0x04040404,
|
||||
/*0681*/ 0x00000404,
|
||||
/*0682*/ 0x00000000,
|
||||
/*0683*/ 0x00000000,
|
||||
/*0684*/ 0x00000000,
|
||||
/*0685*/ 0x00000000,
|
||||
/*0686*/ 0x00000002,
|
||||
/*0687*/ 0x00000000,
|
||||
/*0688*/ 0x00000000,
|
||||
/*0689*/ 0x00000000,
|
||||
/*068a*/ 0x00400320,
|
||||
/*068b*/ 0x00000040,
|
||||
/*068c*/ 0x00000000,
|
||||
/*068d*/ 0x00000000,
|
||||
/*068e*/ 0x00000000,
|
||||
/*068f*/ 0x01000000,
|
||||
/*0690*/ 0x00020003,
|
||||
/*0691*/ 0x00000000,
|
||||
/*0692*/ 0x00000000,
|
||||
/*0693*/ 0x00000000,
|
||||
/*0694*/ 0x00002a01,
|
||||
/*0695*/ 0x00000015,
|
||||
/*0696*/ 0x00000015,
|
||||
/*0697*/ 0x0000002a,
|
||||
/*0698*/ 0x00000033,
|
||||
/*0699*/ 0x0000000c,
|
||||
/*069a*/ 0x0000000c,
|
||||
/*069b*/ 0x00000033,
|
||||
/*069c*/ 0x00000000,
|
||||
/*069d*/ 0x00000000,
|
||||
/*069e*/ 0x00000000,
|
||||
/*069f*/ 0x0002006e,
|
||||
/*06a0*/ 0x02000200,
|
||||
/*06a1*/ 0x02000200,
|
||||
/*06a2*/ 0x00000200,
|
||||
/*06a3*/ 0x42080010,
|
||||
/*06a4*/ 0x00000003
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_G_REGSET_H3[DDR_PHY_ADR_G_REGSET_NUM_H3] = {
|
||||
/*0700*/ 0x00000001,
|
||||
/*0701*/ 0x00000000,
|
||||
/*0702*/ 0x00000005,
|
||||
/*0703*/ 0x04000f00,
|
||||
/*0704*/ 0x00020080,
|
||||
/*0705*/ 0x00020055,
|
||||
/*0706*/ 0x00000000,
|
||||
/*0707*/ 0x00000000,
|
||||
/*0708*/ 0x00000000,
|
||||
/*0709*/ 0x00000050,
|
||||
/*070a*/ 0x00000000,
|
||||
/*070b*/ 0x01010100,
|
||||
/*070c*/ 0x00000200,
|
||||
/*070d*/ 0x00001102,
|
||||
/*070e*/ 0x00000000,
|
||||
/*070f*/ 0x000f1f00,
|
||||
/*0710*/ 0x0f1f0f1f,
|
||||
/*0711*/ 0x0f1f0f1f,
|
||||
/*0712*/ 0x00020003,
|
||||
/*0713*/ 0x02000200,
|
||||
/*0714*/ 0x00000200,
|
||||
/*0715*/ 0x00001102,
|
||||
/*0716*/ 0x00000064,
|
||||
/*0717*/ 0x00000000,
|
||||
/*0718*/ 0x00000000,
|
||||
/*0719*/ 0x00000502,
|
||||
/*071a*/ 0x027f6e00,
|
||||
/*071b*/ 0x007f007f,
|
||||
/*071c*/ 0x00007f3c,
|
||||
/*071d*/ 0x00047f6e,
|
||||
/*071e*/ 0x0003154f,
|
||||
/*071f*/ 0x0001154f,
|
||||
/*0720*/ 0x0001154f,
|
||||
/*0721*/ 0x0001154f,
|
||||
/*0722*/ 0x0001154f,
|
||||
/*0723*/ 0x00003fee,
|
||||
/*0724*/ 0x0001154f,
|
||||
/*0725*/ 0x00003fee,
|
||||
/*0726*/ 0x0001154f,
|
||||
/*0727*/ 0x00007f3c,
|
||||
/*0728*/ 0x0001154f,
|
||||
/*0729*/ 0x00000000,
|
||||
/*072a*/ 0x00000000,
|
||||
/*072b*/ 0x00000000,
|
||||
/*072c*/ 0x65000000,
|
||||
/*072d*/ 0x00000000,
|
||||
/*072e*/ 0x00000000,
|
||||
/*072f*/ 0x00000201,
|
||||
/*0730*/ 0x00000000,
|
||||
/*0731*/ 0x00000000,
|
||||
/*0732*/ 0x00000000,
|
||||
/*0733*/ 0x00000000,
|
||||
/*0734*/ 0x00000000,
|
||||
/*0735*/ 0x00000000,
|
||||
/*0736*/ 0x00000000,
|
||||
/*0737*/ 0x00000000,
|
||||
/*0738*/ 0x00000000,
|
||||
/*0739*/ 0x00000000,
|
||||
/*073a*/ 0x00000000
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PI_REGSET_H3[DDR_PI_REGSET_NUM_H3] = {
|
||||
/*0200*/ 0x00000b00,
|
||||
/*0201*/ 0x00000100,
|
||||
/*0202*/ 0x00000000,
|
||||
/*0203*/ 0x0000ffff,
|
||||
/*0204*/ 0x00000000,
|
||||
/*0205*/ 0x0000ffff,
|
||||
/*0206*/ 0x00000000,
|
||||
/*0207*/ 0x304cffff,
|
||||
/*0208*/ 0x00000200,
|
||||
/*0209*/ 0x00000200,
|
||||
/*020a*/ 0x00000200,
|
||||
/*020b*/ 0x00000200,
|
||||
/*020c*/ 0x0000304c,
|
||||
/*020d*/ 0x00000200,
|
||||
/*020e*/ 0x00000200,
|
||||
/*020f*/ 0x00000200,
|
||||
/*0210*/ 0x00000200,
|
||||
/*0211*/ 0x0000304c,
|
||||
/*0212*/ 0x00000200,
|
||||
/*0213*/ 0x00000200,
|
||||
/*0214*/ 0x00000200,
|
||||
/*0215*/ 0x00000200,
|
||||
/*0216*/ 0x00010000,
|
||||
/*0217*/ 0x00000003,
|
||||
/*0218*/ 0x01000001,
|
||||
/*0219*/ 0x00000000,
|
||||
/*021a*/ 0x00000000,
|
||||
/*021b*/ 0x00000000,
|
||||
/*021c*/ 0x00000000,
|
||||
/*021d*/ 0x00000000,
|
||||
/*021e*/ 0x00000000,
|
||||
/*021f*/ 0x00000000,
|
||||
/*0220*/ 0x00000000,
|
||||
/*0221*/ 0x00000000,
|
||||
/*0222*/ 0x00000000,
|
||||
/*0223*/ 0x00000000,
|
||||
/*0224*/ 0x00000000,
|
||||
/*0225*/ 0x00000000,
|
||||
/*0226*/ 0x00000000,
|
||||
/*0227*/ 0x00000000,
|
||||
/*0228*/ 0x00000000,
|
||||
/*0229*/ 0x0f000101,
|
||||
/*022a*/ 0x08492d25,
|
||||
/*022b*/ 0x500e0c04,
|
||||
/*022c*/ 0x0002500e,
|
||||
/*022d*/ 0x00460003,
|
||||
/*022e*/ 0x182600cf,
|
||||
/*022f*/ 0x182600cf,
|
||||
/*0230*/ 0x00000005,
|
||||
/*0231*/ 0x00000000,
|
||||
/*0232*/ 0x00000000,
|
||||
/*0233*/ 0x00000000,
|
||||
/*0234*/ 0x00000000,
|
||||
/*0235*/ 0x00000000,
|
||||
/*0236*/ 0x00000000,
|
||||
/*0237*/ 0x00000000,
|
||||
/*0238*/ 0x01000000,
|
||||
/*0239*/ 0x00040404,
|
||||
/*023a*/ 0x01280a00,
|
||||
/*023b*/ 0x00000000,
|
||||
/*023c*/ 0x000f0000,
|
||||
/*023d*/ 0x00001803,
|
||||
/*023e*/ 0x00000000,
|
||||
/*023f*/ 0x00000000,
|
||||
/*0240*/ 0x00060002,
|
||||
/*0241*/ 0x00010001,
|
||||
/*0242*/ 0x01000101,
|
||||
/*0243*/ 0x04020201,
|
||||
/*0244*/ 0x00080804,
|
||||
/*0245*/ 0x00000000,
|
||||
/*0246*/ 0x08030000,
|
||||
/*0247*/ 0x15150408,
|
||||
/*0248*/ 0x00000000,
|
||||
/*0249*/ 0x00000000,
|
||||
/*024a*/ 0x00000000,
|
||||
/*024b*/ 0x001e0f0f,
|
||||
/*024c*/ 0x00000000,
|
||||
/*024d*/ 0x01000300,
|
||||
/*024e*/ 0x00000000,
|
||||
/*024f*/ 0x00000000,
|
||||
/*0250*/ 0x01000000,
|
||||
/*0251*/ 0x00010101,
|
||||
/*0252*/ 0x000e0e0e,
|
||||
/*0253*/ 0x000c0c0c,
|
||||
/*0254*/ 0x02060601,
|
||||
/*0255*/ 0x00000000,
|
||||
/*0256*/ 0x00000003,
|
||||
/*0257*/ 0x00181703,
|
||||
/*0258*/ 0x00280006,
|
||||
/*0259*/ 0x00280016,
|
||||
/*025a*/ 0x00000016,
|
||||
/*025b*/ 0x00000000,
|
||||
/*025c*/ 0x00000000,
|
||||
/*025d*/ 0x00000000,
|
||||
/*025e*/ 0x140a0000,
|
||||
/*025f*/ 0x0005010a,
|
||||
/*0260*/ 0x03018d03,
|
||||
/*0261*/ 0x000a018d,
|
||||
/*0262*/ 0x00060100,
|
||||
/*0263*/ 0x01000006,
|
||||
/*0264*/ 0x018e018e,
|
||||
/*0265*/ 0x018e0100,
|
||||
/*0266*/ 0x1111018e,
|
||||
/*0267*/ 0x10010204,
|
||||
/*0268*/ 0x09090650,
|
||||
/*0269*/ 0x20110202,
|
||||
/*026a*/ 0x00201000,
|
||||
/*026b*/ 0x00201000,
|
||||
/*026c*/ 0x04041000,
|
||||
/*026d*/ 0x18020100,
|
||||
/*026e*/ 0x00010118,
|
||||
/*026f*/ 0x004b004a,
|
||||
/*0270*/ 0x050f0000,
|
||||
/*0271*/ 0x0c01021e,
|
||||
/*0272*/ 0x34000000,
|
||||
/*0273*/ 0x00000000,
|
||||
/*0274*/ 0x00000000,
|
||||
/*0275*/ 0x00000000,
|
||||
/*0276*/ 0x312ed400,
|
||||
/*0277*/ 0xd4111132,
|
||||
/*0278*/ 0x1132312e,
|
||||
/*0279*/ 0x312ed411,
|
||||
/*027a*/ 0x00111132,
|
||||
/*027b*/ 0x32312ed4,
|
||||
/*027c*/ 0x2ed41111,
|
||||
/*027d*/ 0x11113231,
|
||||
/*027e*/ 0x32312ed4,
|
||||
/*027f*/ 0xd4001111,
|
||||
/*0280*/ 0x1132312e,
|
||||
/*0281*/ 0x312ed411,
|
||||
/*0282*/ 0xd4111132,
|
||||
/*0283*/ 0x1132312e,
|
||||
/*0284*/ 0x2ed40011,
|
||||
/*0285*/ 0x11113231,
|
||||
/*0286*/ 0x32312ed4,
|
||||
/*0287*/ 0x2ed41111,
|
||||
/*0288*/ 0x11113231,
|
||||
/*0289*/ 0x00020000,
|
||||
/*028a*/ 0x018d018d,
|
||||
/*028b*/ 0x0c08018d,
|
||||
/*028c*/ 0x1f121d22,
|
||||
/*028d*/ 0x4301b344,
|
||||
/*028e*/ 0x10172006,
|
||||
/*028f*/ 0x121d220c,
|
||||
/*0290*/ 0x01b3441f,
|
||||
/*0291*/ 0x17200643,
|
||||
/*0292*/ 0x1d220c10,
|
||||
/*0293*/ 0x00001f12,
|
||||
/*0294*/ 0x4301b344,
|
||||
/*0295*/ 0x10172006,
|
||||
/*0296*/ 0x00020002,
|
||||
/*0297*/ 0x00020002,
|
||||
/*0298*/ 0x00020002,
|
||||
/*0299*/ 0x00020002,
|
||||
/*029a*/ 0x00020002,
|
||||
/*029b*/ 0x00000000,
|
||||
/*029c*/ 0x00000000,
|
||||
/*029d*/ 0x00000000,
|
||||
/*029e*/ 0x00000000,
|
||||
/*029f*/ 0x00000000,
|
||||
/*02a0*/ 0x00000000,
|
||||
/*02a1*/ 0x00000000,
|
||||
/*02a2*/ 0x00000000,
|
||||
/*02a3*/ 0x00000000,
|
||||
/*02a4*/ 0x00000000,
|
||||
/*02a5*/ 0x00000000,
|
||||
/*02a6*/ 0x00000000,
|
||||
/*02a7*/ 0x01000400,
|
||||
/*02a8*/ 0x00304c00,
|
||||
/*02a9*/ 0x0001e2f8,
|
||||
/*02aa*/ 0x0000304c,
|
||||
/*02ab*/ 0x0001e2f8,
|
||||
/*02ac*/ 0x0000304c,
|
||||
/*02ad*/ 0x0001e2f8,
|
||||
/*02ae*/ 0x08000000,
|
||||
/*02af*/ 0x00000100,
|
||||
/*02b0*/ 0x00000000,
|
||||
/*02b1*/ 0x00000000,
|
||||
/*02b2*/ 0x00000000,
|
||||
/*02b3*/ 0x00000000,
|
||||
/*02b4*/ 0x00000002
|
||||
};
|
||||
+538
@@ -0,0 +1,538 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_OFS_H3VER2 0x0400
|
||||
#define DDR_PHY_ADR_V_REGSET_OFS_H3VER2 0x0600
|
||||
#define DDR_PHY_ADR_I_REGSET_OFS_H3VER2 0x0640
|
||||
#define DDR_PHY_ADR_G_REGSET_OFS_H3VER2 0x0680
|
||||
#define DDR_PI_REGSET_OFS_H3VER2 0x0200
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_SIZE_H3VER2 0x80
|
||||
#define DDR_PHY_ADR_V_REGSET_SIZE_H3VER2 0x40
|
||||
#define DDR_PHY_ADR_I_REGSET_SIZE_H3VER2 0x40
|
||||
#define DDR_PHY_ADR_G_REGSET_SIZE_H3VER2 0x80
|
||||
#define DDR_PI_REGSET_SIZE_H3VER2 0x100
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_NUM_H3VER2 97
|
||||
#define DDR_PHY_ADR_V_REGSET_NUM_H3VER2 37
|
||||
#define DDR_PHY_ADR_I_REGSET_NUM_H3VER2 37
|
||||
#define DDR_PHY_ADR_G_REGSET_NUM_H3VER2 79
|
||||
#define DDR_PI_REGSET_NUM_H3VER2 245
|
||||
|
||||
static const uint32_t DDR_PHY_SLICE_REGSET_H3VER2
|
||||
[DDR_PHY_SLICE_REGSET_NUM_H3VER2] = {
|
||||
/*0400*/ 0x76543210,
|
||||
/*0401*/ 0x0004f008,
|
||||
/*0402*/ 0x00020133,
|
||||
/*0403*/ 0x00000000,
|
||||
/*0404*/ 0x00000000,
|
||||
/*0405*/ 0x00010000,
|
||||
/*0406*/ 0x016e6e0e,
|
||||
/*0407*/ 0x026e6e0e,
|
||||
/*0408*/ 0x00010300,
|
||||
/*0409*/ 0x04000100,
|
||||
/*040a*/ 0x01000000,
|
||||
/*040b*/ 0x00000000,
|
||||
/*040c*/ 0x00000000,
|
||||
/*040d*/ 0x00000100,
|
||||
/*040e*/ 0x001700c0,
|
||||
/*040f*/ 0x020100b0,
|
||||
/*0410*/ 0x00030020,
|
||||
/*0411*/ 0x00000000,
|
||||
/*0412*/ 0x00000000,
|
||||
/*0413*/ 0x00000000,
|
||||
/*0414*/ 0x00000000,
|
||||
/*0415*/ 0x00000000,
|
||||
/*0416*/ 0x00000000,
|
||||
/*0417*/ 0x00000000,
|
||||
/*0418*/ 0x09000000,
|
||||
/*0419*/ 0x04080000,
|
||||
/*041a*/ 0x04080400,
|
||||
/*041b*/ 0x08000000,
|
||||
/*041c*/ 0x0c008007,
|
||||
/*041d*/ 0x00000f00,
|
||||
/*041e*/ 0x00000100,
|
||||
/*041f*/ 0x55aa55aa,
|
||||
/*0420*/ 0x33cc33cc,
|
||||
/*0421*/ 0x0ff00ff0,
|
||||
/*0422*/ 0x0f0ff0f0,
|
||||
/*0423*/ 0x00018e38,
|
||||
/*0424*/ 0x00000000,
|
||||
/*0425*/ 0x00000000,
|
||||
/*0426*/ 0x00000000,
|
||||
/*0427*/ 0x00000000,
|
||||
/*0428*/ 0x00000000,
|
||||
/*0429*/ 0x00000000,
|
||||
/*042a*/ 0x00000000,
|
||||
/*042b*/ 0x00000000,
|
||||
/*042c*/ 0x00000000,
|
||||
/*042d*/ 0x00000000,
|
||||
/*042e*/ 0x00000000,
|
||||
/*042f*/ 0x00000000,
|
||||
/*0430*/ 0x00000000,
|
||||
/*0431*/ 0x00000000,
|
||||
/*0432*/ 0x00000000,
|
||||
/*0433*/ 0x00000000,
|
||||
/*0434*/ 0x00000000,
|
||||
/*0435*/ 0x00000000,
|
||||
/*0436*/ 0x00000000,
|
||||
/*0437*/ 0x00000000,
|
||||
/*0438*/ 0x00000104,
|
||||
/*0439*/ 0x00082020,
|
||||
/*043a*/ 0x08200820,
|
||||
/*043b*/ 0x08200820,
|
||||
/*043c*/ 0x08200820,
|
||||
/*043d*/ 0x08200820,
|
||||
/*043e*/ 0x08200820,
|
||||
/*043f*/ 0x00000000,
|
||||
/*0440*/ 0x00000000,
|
||||
/*0441*/ 0x03000300,
|
||||
/*0442*/ 0x03000300,
|
||||
/*0443*/ 0x03000300,
|
||||
/*0444*/ 0x03000300,
|
||||
/*0445*/ 0x00000300,
|
||||
/*0446*/ 0x00000000,
|
||||
/*0447*/ 0x00000000,
|
||||
/*0448*/ 0x00000000,
|
||||
/*0449*/ 0x00000000,
|
||||
/*044a*/ 0x00000000,
|
||||
/*044b*/ 0x00a000a0,
|
||||
/*044c*/ 0x00a000a0,
|
||||
/*044d*/ 0x00a000a0,
|
||||
/*044e*/ 0x00a000a0,
|
||||
/*044f*/ 0x00a000a0,
|
||||
/*0450*/ 0x00a000a0,
|
||||
/*0451*/ 0x00a000a0,
|
||||
/*0452*/ 0x00a000a0,
|
||||
/*0453*/ 0x00a000a0,
|
||||
/*0454*/ 0x01040109,
|
||||
/*0455*/ 0x00000200,
|
||||
/*0456*/ 0x01000000,
|
||||
/*0457*/ 0x00000200,
|
||||
/*0458*/ 0x00000004,
|
||||
/*0459*/ 0x4041a151,
|
||||
/*045a*/ 0xc00141a0,
|
||||
/*045b*/ 0x0e0000c0,
|
||||
/*045c*/ 0x0010000c,
|
||||
/*045d*/ 0x063e4208,
|
||||
/*045e*/ 0x0f0c180c,
|
||||
/*045f*/ 0x00e00140,
|
||||
/*0460*/ 0x00000c20
|
||||
};
|
||||
|
||||
static const uint32_t
|
||||
DDR_PHY_ADR_V_REGSET_H3VER2[DDR_PHY_ADR_V_REGSET_NUM_H3VER2] = {
|
||||
/*0600*/ 0x00000000,
|
||||
/*0601*/ 0x00000000,
|
||||
/*0602*/ 0x00000000,
|
||||
/*0603*/ 0x00000000,
|
||||
/*0604*/ 0x00000000,
|
||||
/*0605*/ 0x00000000,
|
||||
/*0606*/ 0x00000000,
|
||||
/*0607*/ 0x00010000,
|
||||
/*0608*/ 0x00000200,
|
||||
/*0609*/ 0x00000000,
|
||||
/*060a*/ 0x00000000,
|
||||
/*060b*/ 0x00000000,
|
||||
/*060c*/ 0x00400320,
|
||||
/*060d*/ 0x00000040,
|
||||
/*060e*/ 0x00dcba98,
|
||||
/*060f*/ 0x03000000,
|
||||
/*0610*/ 0x00000200,
|
||||
/*0611*/ 0x00000000,
|
||||
/*0612*/ 0x00000000,
|
||||
/*0613*/ 0x00000000,
|
||||
/*0614*/ 0x0000002a,
|
||||
/*0615*/ 0x00000015,
|
||||
/*0616*/ 0x00000015,
|
||||
/*0617*/ 0x0000002a,
|
||||
/*0618*/ 0x00000033,
|
||||
/*0619*/ 0x0000000c,
|
||||
/*061a*/ 0x0000000c,
|
||||
/*061b*/ 0x00000033,
|
||||
/*061c*/ 0x00418820,
|
||||
/*061d*/ 0x003f0000,
|
||||
/*061e*/ 0x0000003f,
|
||||
/*061f*/ 0x0002c06e,
|
||||
/*0620*/ 0x02c002c0,
|
||||
/*0621*/ 0x02c002c0,
|
||||
/*0622*/ 0x000002c0,
|
||||
/*0623*/ 0x42080010,
|
||||
/*0624*/ 0x0000033e
|
||||
};
|
||||
|
||||
static const uint32_t
|
||||
DDR_PHY_ADR_I_REGSET_H3VER2[DDR_PHY_ADR_I_REGSET_NUM_H3VER2] = {
|
||||
/*0640*/ 0x00000000,
|
||||
/*0641*/ 0x00000000,
|
||||
/*0642*/ 0x00000000,
|
||||
/*0643*/ 0x00000000,
|
||||
/*0644*/ 0x00000000,
|
||||
/*0645*/ 0x00000000,
|
||||
/*0646*/ 0x00000000,
|
||||
/*0647*/ 0x00000000,
|
||||
/*0648*/ 0x00000000,
|
||||
/*0649*/ 0x00000000,
|
||||
/*064a*/ 0x00000000,
|
||||
/*064b*/ 0x00000000,
|
||||
/*064c*/ 0x00000000,
|
||||
/*064d*/ 0x00000000,
|
||||
/*064e*/ 0x00000000,
|
||||
/*064f*/ 0x00000000,
|
||||
/*0650*/ 0x00000000,
|
||||
/*0651*/ 0x00000000,
|
||||
/*0652*/ 0x00000000,
|
||||
/*0653*/ 0x00000000,
|
||||
/*0654*/ 0x00000000,
|
||||
/*0655*/ 0x00000000,
|
||||
/*0656*/ 0x00000000,
|
||||
/*0657*/ 0x00000000,
|
||||
/*0658*/ 0x00000000,
|
||||
/*0659*/ 0x00000000,
|
||||
/*065a*/ 0x00000000,
|
||||
/*065b*/ 0x00000000,
|
||||
/*065c*/ 0x00000000,
|
||||
/*065d*/ 0x00000000,
|
||||
/*065e*/ 0x00000000,
|
||||
/*065f*/ 0x00000000,
|
||||
/*0660*/ 0x00000000,
|
||||
/*0661*/ 0x00000000,
|
||||
/*0662*/ 0x00000000,
|
||||
/*0663*/ 0x00000000,
|
||||
/*0664*/ 0x00000000
|
||||
};
|
||||
|
||||
static const uint32_t
|
||||
DDR_PHY_ADR_G_REGSET_H3VER2[DDR_PHY_ADR_G_REGSET_NUM_H3VER2] = {
|
||||
/*0680*/ 0x00000000,
|
||||
/*0681*/ 0x00000100,
|
||||
/*0682*/ 0x00000000,
|
||||
/*0683*/ 0x00050000,
|
||||
/*0684*/ 0x0f000000,
|
||||
/*0685*/ 0x00800400,
|
||||
/*0686*/ 0x00020032,
|
||||
/*0687*/ 0x00020055,
|
||||
/*0688*/ 0x00000000,
|
||||
/*0689*/ 0x00000000,
|
||||
/*068a*/ 0x00000000,
|
||||
/*068b*/ 0x00000050,
|
||||
/*068c*/ 0x00000000,
|
||||
/*068d*/ 0x01010100,
|
||||
/*068e*/ 0x01000200,
|
||||
/*068f*/ 0x00000000,
|
||||
/*0690*/ 0x00010100,
|
||||
/*0691*/ 0x00000000,
|
||||
/*0692*/ 0x00000000,
|
||||
/*0693*/ 0x00000000,
|
||||
/*0694*/ 0x00000000,
|
||||
/*0695*/ 0x00005064,
|
||||
/*0696*/ 0x01421142,
|
||||
/*0697*/ 0x00000142,
|
||||
/*0698*/ 0x00000000,
|
||||
/*0699*/ 0x000f1100,
|
||||
/*069a*/ 0x0f110f11,
|
||||
/*069b*/ 0x09000f11,
|
||||
/*069c*/ 0x00000003,
|
||||
/*069d*/ 0x0002c000,
|
||||
/*069e*/ 0x02c002c0,
|
||||
/*069f*/ 0x000002c0,
|
||||
/*06a0*/ 0x03421342,
|
||||
/*06a1*/ 0x00000342,
|
||||
/*06a2*/ 0x00000000,
|
||||
/*06a3*/ 0x00000000,
|
||||
/*06a4*/ 0x05020000,
|
||||
/*06a5*/ 0x14000000,
|
||||
/*06a6*/ 0x027f6e00,
|
||||
/*06a7*/ 0x047f027f,
|
||||
/*06a8*/ 0x00027f6e,
|
||||
/*06a9*/ 0x00047f6e,
|
||||
/*06aa*/ 0x0003554f,
|
||||
/*06ab*/ 0x0001554f,
|
||||
/*06ac*/ 0x0001554f,
|
||||
/*06ad*/ 0x0001554f,
|
||||
/*06ae*/ 0x0001554f,
|
||||
/*06af*/ 0x00003fee,
|
||||
/*06b0*/ 0x0001554f,
|
||||
/*06b1*/ 0x00003fee,
|
||||
/*06b2*/ 0x0001554f,
|
||||
/*06b3*/ 0x00027f6e,
|
||||
/*06b4*/ 0x0001554f,
|
||||
/*06b5*/ 0x00004011,
|
||||
/*06b6*/ 0x00004410,
|
||||
/*06b7*/ 0x00000000,
|
||||
/*06b8*/ 0x00000000,
|
||||
/*06b9*/ 0x00000000,
|
||||
/*06ba*/ 0x00000065,
|
||||
/*06bb*/ 0x00000000,
|
||||
/*06bc*/ 0x00020201,
|
||||
/*06bd*/ 0x00000000,
|
||||
/*06be*/ 0x03000000,
|
||||
/*06bf*/ 0x00000008,
|
||||
/*06c0*/ 0x00000000,
|
||||
/*06c1*/ 0x00000000,
|
||||
/*06c2*/ 0x00000000,
|
||||
/*06c3*/ 0x00000000,
|
||||
/*06c4*/ 0x00000001,
|
||||
/*06c5*/ 0x00000000,
|
||||
/*06c6*/ 0x00000000,
|
||||
/*06c7*/ 0x00000000,
|
||||
/*06c8*/ 0x000000e4,
|
||||
/*06c9*/ 0x00010198,
|
||||
/*06ca*/ 0x00000000,
|
||||
/*06cb*/ 0x00000000,
|
||||
/*06cc*/ 0x07010000,
|
||||
/*06cd*/ 0x00000104,
|
||||
/*06ce*/ 0x00000000
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PI_REGSET_H3VER2[DDR_PI_REGSET_NUM_H3VER2] = {
|
||||
/*0200*/ 0x00000b00,
|
||||
/*0201*/ 0x00000100,
|
||||
/*0202*/ 0x00640000,
|
||||
/*0203*/ 0x00000000,
|
||||
/*0204*/ 0x0000ffff,
|
||||
/*0205*/ 0x00000000,
|
||||
/*0206*/ 0x0000ffff,
|
||||
/*0207*/ 0x00000000,
|
||||
/*0208*/ 0x0000ffff,
|
||||
/*0209*/ 0x0000304c,
|
||||
/*020a*/ 0x00000200,
|
||||
/*020b*/ 0x00000200,
|
||||
/*020c*/ 0x00000200,
|
||||
/*020d*/ 0x00000200,
|
||||
/*020e*/ 0x0000304c,
|
||||
/*020f*/ 0x00000200,
|
||||
/*0210*/ 0x00000200,
|
||||
/*0211*/ 0x00000200,
|
||||
/*0212*/ 0x00000200,
|
||||
/*0213*/ 0x0000304c,
|
||||
/*0214*/ 0x00000200,
|
||||
/*0215*/ 0x00000200,
|
||||
/*0216*/ 0x00000200,
|
||||
/*0217*/ 0x00000200,
|
||||
/*0218*/ 0x00010000,
|
||||
/*0219*/ 0x00000003,
|
||||
/*021a*/ 0x01000001,
|
||||
/*021b*/ 0x00000000,
|
||||
/*021c*/ 0x00000000,
|
||||
/*021d*/ 0x00000000,
|
||||
/*021e*/ 0x00000000,
|
||||
/*021f*/ 0x00000000,
|
||||
/*0220*/ 0x00000000,
|
||||
/*0221*/ 0x00000000,
|
||||
/*0222*/ 0x00000000,
|
||||
/*0223*/ 0x00000000,
|
||||
/*0224*/ 0x00000000,
|
||||
/*0225*/ 0x00000000,
|
||||
/*0226*/ 0x00000000,
|
||||
/*0227*/ 0x00000000,
|
||||
/*0228*/ 0x00000000,
|
||||
/*0229*/ 0x00000000,
|
||||
/*022a*/ 0x00000000,
|
||||
/*022b*/ 0x0f000101,
|
||||
/*022c*/ 0x08492d25,
|
||||
/*022d*/ 0x500e0c04,
|
||||
/*022e*/ 0x0002500e,
|
||||
/*022f*/ 0x00000301,
|
||||
/*0230*/ 0x00000046,
|
||||
/*0231*/ 0x000000cf,
|
||||
/*0232*/ 0x00001826,
|
||||
/*0233*/ 0x000000cf,
|
||||
/*0234*/ 0x00001826,
|
||||
/*0235*/ 0x00000005,
|
||||
/*0236*/ 0x00000000,
|
||||
/*0237*/ 0x00000000,
|
||||
/*0238*/ 0x00000000,
|
||||
/*0239*/ 0x00000000,
|
||||
/*023a*/ 0x00000000,
|
||||
/*023b*/ 0x00000000,
|
||||
/*023c*/ 0x00000000,
|
||||
/*023d*/ 0x00000000,
|
||||
/*023e*/ 0x04010000,
|
||||
/*023f*/ 0x00000404,
|
||||
/*0240*/ 0x0101280a,
|
||||
/*0241*/ 0x00000000,
|
||||
/*0242*/ 0x00000000,
|
||||
/*0243*/ 0x0003000f,
|
||||
/*0244*/ 0x00000018,
|
||||
/*0245*/ 0x00000000,
|
||||
/*0246*/ 0x00000000,
|
||||
/*0247*/ 0x00060002,
|
||||
/*0248*/ 0x00010001,
|
||||
/*0249*/ 0x01000101,
|
||||
/*024a*/ 0x04020201,
|
||||
/*024b*/ 0x00080804,
|
||||
/*024c*/ 0x00000000,
|
||||
/*024d*/ 0x08030000,
|
||||
/*024e*/ 0x15150408,
|
||||
/*024f*/ 0x00000000,
|
||||
/*0250*/ 0x00000000,
|
||||
/*0251*/ 0x00000000,
|
||||
/*0252*/ 0x0f0f0000,
|
||||
/*0253*/ 0x0000001e,
|
||||
/*0254*/ 0x00000000,
|
||||
/*0255*/ 0x01000300,
|
||||
/*0256*/ 0x00000100,
|
||||
/*0257*/ 0x00000000,
|
||||
/*0258*/ 0x00000000,
|
||||
/*0259*/ 0x01000000,
|
||||
/*025a*/ 0x00000101,
|
||||
/*025b*/ 0x55555a5a,
|
||||
/*025c*/ 0x55555a5a,
|
||||
/*025d*/ 0x55555a5a,
|
||||
/*025e*/ 0x55555a5a,
|
||||
/*025f*/ 0x0e0e0001,
|
||||
/*0260*/ 0x0c0c000e,
|
||||
/*0261*/ 0x0601000c,
|
||||
/*0262*/ 0x17170106,
|
||||
/*0263*/ 0x00020202,
|
||||
/*0264*/ 0x03000000,
|
||||
/*0265*/ 0x00000000,
|
||||
/*0266*/ 0x00181703,
|
||||
/*0267*/ 0x00280006,
|
||||
/*0268*/ 0x00280016,
|
||||
/*0269*/ 0x00000016,
|
||||
/*026a*/ 0x00000000,
|
||||
/*026b*/ 0x00000000,
|
||||
/*026c*/ 0x00000000,
|
||||
/*026d*/ 0x0a000000,
|
||||
/*026e*/ 0x00010a14,
|
||||
/*026f*/ 0x00030005,
|
||||
/*0270*/ 0x0003018d,
|
||||
/*0271*/ 0x000a018d,
|
||||
/*0272*/ 0x00060100,
|
||||
/*0273*/ 0x01000006,
|
||||
/*0274*/ 0x018e018e,
|
||||
/*0275*/ 0x018e0100,
|
||||
/*0276*/ 0x1111018e,
|
||||
/*0277*/ 0x10010204,
|
||||
/*0278*/ 0x09090650,
|
||||
/*0279*/ 0xff110202,
|
||||
/*027a*/ 0x00ff1000,
|
||||
/*027b*/ 0x00ff1000,
|
||||
/*027c*/ 0x04041000,
|
||||
/*027d*/ 0x18020100,
|
||||
/*027e*/ 0x01010018,
|
||||
/*027f*/ 0x004a004a,
|
||||
/*0280*/ 0x004b004a,
|
||||
/*0281*/ 0x050f0000,
|
||||
/*0282*/ 0x0c01021e,
|
||||
/*0283*/ 0x34000000,
|
||||
/*0284*/ 0x00000000,
|
||||
/*0285*/ 0x00000000,
|
||||
/*0286*/ 0x00000000,
|
||||
/*0287*/ 0x00000000,
|
||||
/*0288*/ 0x36312ed4,
|
||||
/*0289*/ 0x2ed41111,
|
||||
/*028a*/ 0x11113631,
|
||||
/*028b*/ 0x36312ed4,
|
||||
/*028c*/ 0xd4001111,
|
||||
/*028d*/ 0x1136312e,
|
||||
/*028e*/ 0x312ed411,
|
||||
/*028f*/ 0xd4111136,
|
||||
/*0290*/ 0x1136312e,
|
||||
/*0291*/ 0x2ed40011,
|
||||
/*0292*/ 0x11113631,
|
||||
/*0293*/ 0x36312ed4,
|
||||
/*0294*/ 0x2ed41111,
|
||||
/*0295*/ 0x11113631,
|
||||
/*0296*/ 0x312ed400,
|
||||
/*0297*/ 0xd4111136,
|
||||
/*0298*/ 0x1136312e,
|
||||
/*0299*/ 0x312ed411,
|
||||
/*029a*/ 0x00111136,
|
||||
/*029b*/ 0x018d0200,
|
||||
/*029c*/ 0x018d018d,
|
||||
/*029d*/ 0x1d220c08,
|
||||
/*029e*/ 0x00001f12,
|
||||
/*029f*/ 0x4301b344,
|
||||
/*02a0*/ 0x10172006,
|
||||
/*02a1*/ 0x121d220c,
|
||||
/*02a2*/ 0x01b3441f,
|
||||
/*02a3*/ 0x17200643,
|
||||
/*02a4*/ 0x1d220c10,
|
||||
/*02a5*/ 0x00001f12,
|
||||
/*02a6*/ 0x4301b344,
|
||||
/*02a7*/ 0x10172006,
|
||||
/*02a8*/ 0x00020002,
|
||||
/*02a9*/ 0x00020002,
|
||||
/*02aa*/ 0x00020002,
|
||||
/*02ab*/ 0x00020002,
|
||||
/*02ac*/ 0x00020002,
|
||||
/*02ad*/ 0x00000000,
|
||||
/*02ae*/ 0x00000000,
|
||||
/*02af*/ 0x00000000,
|
||||
/*02b0*/ 0x00000000,
|
||||
/*02b1*/ 0x00000000,
|
||||
/*02b2*/ 0x00000000,
|
||||
/*02b3*/ 0x00000000,
|
||||
/*02b4*/ 0x00000000,
|
||||
/*02b5*/ 0x00000000,
|
||||
/*02b6*/ 0x00000000,
|
||||
/*02b7*/ 0x00000000,
|
||||
/*02b8*/ 0x00000000,
|
||||
/*02b9*/ 0x00000400,
|
||||
/*02ba*/ 0x05040302,
|
||||
/*02bb*/ 0x01000f0e,
|
||||
/*02bc*/ 0x07060504,
|
||||
/*02bd*/ 0x03020100,
|
||||
/*02be*/ 0x02010000,
|
||||
/*02bf*/ 0x00000103,
|
||||
/*02c0*/ 0x0000304c,
|
||||
/*02c1*/ 0x0001e2f8,
|
||||
/*02c2*/ 0x0000304c,
|
||||
/*02c3*/ 0x0001e2f8,
|
||||
/*02c4*/ 0x0000304c,
|
||||
/*02c5*/ 0x0001e2f8,
|
||||
/*02c6*/ 0x08000000,
|
||||
/*02c7*/ 0x00000100,
|
||||
/*02c8*/ 0x00000000,
|
||||
/*02c9*/ 0x00000000,
|
||||
/*02ca*/ 0x00000000,
|
||||
/*02cb*/ 0x00000000,
|
||||
/*02cc*/ 0x00010000,
|
||||
/*02cd*/ 0x00000000,
|
||||
/*02ce*/ 0x00000000,
|
||||
/*02cf*/ 0x00000000,
|
||||
/*02d0*/ 0x00000000,
|
||||
/*02d1*/ 0x00000000,
|
||||
/*02d2*/ 0x00000000,
|
||||
/*02d3*/ 0x00000000,
|
||||
/*02d4*/ 0x00000000,
|
||||
/*02d5*/ 0x00000000,
|
||||
/*02d6*/ 0x00000000,
|
||||
/*02d7*/ 0x00000000,
|
||||
/*02d8*/ 0x00000000,
|
||||
/*02d9*/ 0x00000000,
|
||||
/*02da*/ 0x00000000,
|
||||
/*02db*/ 0x00000000,
|
||||
/*02dc*/ 0x00000000,
|
||||
/*02dd*/ 0x00000000,
|
||||
/*02de*/ 0x00000000,
|
||||
/*02df*/ 0x00000000,
|
||||
/*02e0*/ 0x00000000,
|
||||
/*02e1*/ 0x00000000,
|
||||
/*02e2*/ 0x00000000,
|
||||
/*02e3*/ 0x00000000,
|
||||
/*02e4*/ 0x00000000,
|
||||
/*02e5*/ 0x00000000,
|
||||
/*02e6*/ 0x00000000,
|
||||
/*02e7*/ 0x00000000,
|
||||
/*02e8*/ 0x00000000,
|
||||
/*02e9*/ 0x00000000,
|
||||
/*02ea*/ 0x00000000,
|
||||
/*02eb*/ 0x00000000,
|
||||
/*02ec*/ 0x00000000,
|
||||
/*02ed*/ 0x00000000,
|
||||
/*02ee*/ 0x00000002,
|
||||
/*02ef*/ 0x00000000,
|
||||
/*02f0*/ 0x00000000,
|
||||
/*02f1*/ 0x00000000,
|
||||
/*02f2*/ 0x00000000,
|
||||
/*02f3*/ 0x00000000,
|
||||
/*02f4*/ 0x00000000
|
||||
};
|
||||
+468
@@ -0,0 +1,468 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_OFS_M3 0x0800
|
||||
#define DDR_PHY_ADR_V_REGSET_OFS_M3 0x0a00
|
||||
#define DDR_PHY_ADR_I_REGSET_OFS_M3 0x0a80
|
||||
#define DDR_PHY_ADR_G_REGSET_OFS_M3 0x0b80
|
||||
#define DDR_PI_REGSET_OFS_M3 0x0200
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_SIZE_M3 0x80
|
||||
#define DDR_PHY_ADR_V_REGSET_SIZE_M3 0x80
|
||||
#define DDR_PHY_ADR_I_REGSET_SIZE_M3 0x80
|
||||
#define DDR_PHY_ADR_G_REGSET_SIZE_M3 0x80
|
||||
#define DDR_PI_REGSET_SIZE_M3 0x100
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_NUM_M3 89
|
||||
#define DDR_PHY_ADR_V_REGSET_NUM_M3 37
|
||||
#define DDR_PHY_ADR_I_REGSET_NUM_M3 37
|
||||
#define DDR_PHY_ADR_G_REGSET_NUM_M3 64
|
||||
#define DDR_PI_REGSET_NUM_M3 202
|
||||
|
||||
static const uint32_t DDR_PHY_SLICE_REGSET_M3[DDR_PHY_SLICE_REGSET_NUM_M3] = {
|
||||
/*0800*/ 0x76543210,
|
||||
/*0801*/ 0x0004f008,
|
||||
/*0802*/ 0x00000000,
|
||||
/*0803*/ 0x00000000,
|
||||
/*0804*/ 0x00010000,
|
||||
/*0805*/ 0x036e6e0e,
|
||||
/*0806*/ 0x026e6e0e,
|
||||
/*0807*/ 0x00010300,
|
||||
/*0808*/ 0x04000100,
|
||||
/*0809*/ 0x00000300,
|
||||
/*080a*/ 0x001700c0,
|
||||
/*080b*/ 0x00b00201,
|
||||
/*080c*/ 0x00030020,
|
||||
/*080d*/ 0x00000000,
|
||||
/*080e*/ 0x00000000,
|
||||
/*080f*/ 0x00000000,
|
||||
/*0810*/ 0x00000000,
|
||||
/*0811*/ 0x00000000,
|
||||
/*0812*/ 0x00000000,
|
||||
/*0813*/ 0x00000000,
|
||||
/*0814*/ 0x09000000,
|
||||
/*0815*/ 0x04080000,
|
||||
/*0816*/ 0x04080400,
|
||||
/*0817*/ 0x00000000,
|
||||
/*0818*/ 0x32103210,
|
||||
/*0819*/ 0x00800708,
|
||||
/*081a*/ 0x000f000c,
|
||||
/*081b*/ 0x00000100,
|
||||
/*081c*/ 0x55aa55aa,
|
||||
/*081d*/ 0x33cc33cc,
|
||||
/*081e*/ 0x0ff00ff0,
|
||||
/*081f*/ 0x0f0ff0f0,
|
||||
/*0820*/ 0x00018e38,
|
||||
/*0821*/ 0x00000000,
|
||||
/*0822*/ 0x00000000,
|
||||
/*0823*/ 0x00000000,
|
||||
/*0824*/ 0x00000000,
|
||||
/*0825*/ 0x00000000,
|
||||
/*0826*/ 0x00000000,
|
||||
/*0827*/ 0x00000000,
|
||||
/*0828*/ 0x00000000,
|
||||
/*0829*/ 0x00000000,
|
||||
/*082a*/ 0x00000000,
|
||||
/*082b*/ 0x00000000,
|
||||
/*082c*/ 0x00000000,
|
||||
/*082d*/ 0x00000000,
|
||||
/*082e*/ 0x00000000,
|
||||
/*082f*/ 0x00000000,
|
||||
/*0830*/ 0x00000000,
|
||||
/*0831*/ 0x00000000,
|
||||
/*0832*/ 0x00000000,
|
||||
/*0833*/ 0x00200000,
|
||||
/*0834*/ 0x08200820,
|
||||
/*0835*/ 0x08200820,
|
||||
/*0836*/ 0x08200820,
|
||||
/*0837*/ 0x08200820,
|
||||
/*0838*/ 0x08200820,
|
||||
/*0839*/ 0x00000820,
|
||||
/*083a*/ 0x03000300,
|
||||
/*083b*/ 0x03000300,
|
||||
/*083c*/ 0x03000300,
|
||||
/*083d*/ 0x03000300,
|
||||
/*083e*/ 0x00000300,
|
||||
/*083f*/ 0x00000000,
|
||||
/*0840*/ 0x00000000,
|
||||
/*0841*/ 0x00000000,
|
||||
/*0842*/ 0x00000000,
|
||||
/*0843*/ 0x00a00000,
|
||||
/*0844*/ 0x00a000a0,
|
||||
/*0845*/ 0x00a000a0,
|
||||
/*0846*/ 0x00a000a0,
|
||||
/*0847*/ 0x00a000a0,
|
||||
/*0848*/ 0x00a000a0,
|
||||
/*0849*/ 0x00a000a0,
|
||||
/*084a*/ 0x00a000a0,
|
||||
/*084b*/ 0x00a000a0,
|
||||
/*084c*/ 0x010900a0,
|
||||
/*084d*/ 0x02000104,
|
||||
/*084e*/ 0x00000000,
|
||||
/*084f*/ 0x00010000,
|
||||
/*0850*/ 0x00000200,
|
||||
/*0851*/ 0x4041a151,
|
||||
/*0852*/ 0xc00141a0,
|
||||
/*0853*/ 0x0e0100c0,
|
||||
/*0854*/ 0x0010000c,
|
||||
/*0855*/ 0x0c064208,
|
||||
/*0856*/ 0x000f0c18,
|
||||
/*0857*/ 0x00e00140,
|
||||
/*0858*/ 0x00000c20
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_V_REGSET_M3[DDR_PHY_ADR_V_REGSET_NUM_M3] = {
|
||||
/*0a00*/ 0x00000000,
|
||||
/*0a01*/ 0x00000000,
|
||||
/*0a02*/ 0x00000000,
|
||||
/*0a03*/ 0x00000000,
|
||||
/*0a04*/ 0x00000000,
|
||||
/*0a05*/ 0x00000000,
|
||||
/*0a06*/ 0x00000002,
|
||||
/*0a07*/ 0x00000000,
|
||||
/*0a08*/ 0x00000000,
|
||||
/*0a09*/ 0x00000000,
|
||||
/*0a0a*/ 0x00400320,
|
||||
/*0a0b*/ 0x00000040,
|
||||
/*0a0c*/ 0x00dcba98,
|
||||
/*0a0d*/ 0x00000000,
|
||||
/*0a0e*/ 0x00dcba98,
|
||||
/*0a0f*/ 0x01000000,
|
||||
/*0a10*/ 0x00020003,
|
||||
/*0a11*/ 0x00000000,
|
||||
/*0a12*/ 0x00000000,
|
||||
/*0a13*/ 0x00000000,
|
||||
/*0a14*/ 0x0000002a,
|
||||
/*0a15*/ 0x00000015,
|
||||
/*0a16*/ 0x00000015,
|
||||
/*0a17*/ 0x0000002a,
|
||||
/*0a18*/ 0x00000033,
|
||||
/*0a19*/ 0x0000000c,
|
||||
/*0a1a*/ 0x0000000c,
|
||||
/*0a1b*/ 0x00000033,
|
||||
/*0a1c*/ 0x0a418820,
|
||||
/*0a1d*/ 0x003f0000,
|
||||
/*0a1e*/ 0x0000003f,
|
||||
/*0a1f*/ 0x0002c06e,
|
||||
/*0a20*/ 0x02c002c0,
|
||||
/*0a21*/ 0x02c002c0,
|
||||
/*0a22*/ 0x000002c0,
|
||||
/*0a23*/ 0x42080010,
|
||||
/*0a24*/ 0x00000003
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_I_REGSET_M3[DDR_PHY_ADR_I_REGSET_NUM_M3] = {
|
||||
/*0a80*/ 0x04040404,
|
||||
/*0a81*/ 0x00000404,
|
||||
/*0a82*/ 0x00000000,
|
||||
/*0a83*/ 0x00000000,
|
||||
/*0a84*/ 0x00000000,
|
||||
/*0a85*/ 0x00000000,
|
||||
/*0a86*/ 0x00000002,
|
||||
/*0a87*/ 0x00000000,
|
||||
/*0a88*/ 0x00000000,
|
||||
/*0a89*/ 0x00000000,
|
||||
/*0a8a*/ 0x00400320,
|
||||
/*0a8b*/ 0x00000040,
|
||||
/*0a8c*/ 0x00000000,
|
||||
/*0a8d*/ 0x00000000,
|
||||
/*0a8e*/ 0x00000000,
|
||||
/*0a8f*/ 0x01000000,
|
||||
/*0a90*/ 0x00020003,
|
||||
/*0a91*/ 0x00000000,
|
||||
/*0a92*/ 0x00000000,
|
||||
/*0a93*/ 0x00000000,
|
||||
/*0a94*/ 0x0000002a,
|
||||
/*0a95*/ 0x00000015,
|
||||
/*0a96*/ 0x00000015,
|
||||
/*0a97*/ 0x0000002a,
|
||||
/*0a98*/ 0x00000033,
|
||||
/*0a99*/ 0x0000000c,
|
||||
/*0a9a*/ 0x0000000c,
|
||||
/*0a9b*/ 0x00000033,
|
||||
/*0a9c*/ 0x00000000,
|
||||
/*0a9d*/ 0x00000000,
|
||||
/*0a9e*/ 0x00000000,
|
||||
/*0a9f*/ 0x0002c06e,
|
||||
/*0aa0*/ 0x02c002c0,
|
||||
/*0aa1*/ 0x02c002c0,
|
||||
/*0aa2*/ 0x000002c0,
|
||||
/*0aa3*/ 0x42080010,
|
||||
/*0aa4*/ 0x00000003
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = {
|
||||
/*0b80*/ 0x00000001,
|
||||
/*0b81*/ 0x00000000,
|
||||
/*0b82*/ 0x00000005,
|
||||
/*0b83*/ 0x04000f00,
|
||||
/*0b84*/ 0x00020080,
|
||||
/*0b85*/ 0x00020055,
|
||||
/*0b86*/ 0x00000000,
|
||||
/*0b87*/ 0x00000000,
|
||||
/*0b88*/ 0x00000000,
|
||||
/*0b89*/ 0x00000050,
|
||||
/*0b8a*/ 0x00000000,
|
||||
/*0b8b*/ 0x01010100,
|
||||
/*0b8c*/ 0x00000600,
|
||||
/*0b8d*/ 0x50640000,
|
||||
/*0b8e*/ 0x01421142,
|
||||
/*0b8f*/ 0x00000142,
|
||||
/*0b90*/ 0x00000000,
|
||||
/*0b91*/ 0x000f1600,
|
||||
/*0b92*/ 0x0f160f16,
|
||||
/*0b93*/ 0x0f160f16,
|
||||
/*0b94*/ 0x00000003,
|
||||
/*0b95*/ 0x0002c000,
|
||||
/*0b96*/ 0x02c002c0,
|
||||
/*0b97*/ 0x000002c0,
|
||||
/*0b98*/ 0x03421342,
|
||||
/*0b99*/ 0x00000342,
|
||||
/*0b9a*/ 0x00000000,
|
||||
/*0b9b*/ 0x00000000,
|
||||
/*0b9c*/ 0x05020000,
|
||||
/*0b9d*/ 0x00000000,
|
||||
/*0b9e*/ 0x00027f6e,
|
||||
/*0b9f*/ 0x047f027f,
|
||||
/*0ba0*/ 0x00027f6e,
|
||||
/*0ba1*/ 0x00047f6e,
|
||||
/*0ba2*/ 0x0003554f,
|
||||
/*0ba3*/ 0x0001554f,
|
||||
/*0ba4*/ 0x0001554f,
|
||||
/*0ba5*/ 0x0001554f,
|
||||
/*0ba6*/ 0x0001554f,
|
||||
/*0ba7*/ 0x00003fee,
|
||||
/*0ba8*/ 0x0001554f,
|
||||
/*0ba9*/ 0x00003fee,
|
||||
/*0baa*/ 0x0001554f,
|
||||
/*0bab*/ 0x00027f6e,
|
||||
/*0bac*/ 0x0001554f,
|
||||
/*0bad*/ 0x00000000,
|
||||
/*0bae*/ 0x00000000,
|
||||
/*0baf*/ 0x00000000,
|
||||
/*0bb0*/ 0x65000000,
|
||||
/*0bb1*/ 0x00000000,
|
||||
/*0bb2*/ 0x00000000,
|
||||
/*0bb3*/ 0x00000201,
|
||||
/*0bb4*/ 0x00000000,
|
||||
/*0bb5*/ 0x00000000,
|
||||
/*0bb6*/ 0x00000000,
|
||||
/*0bb7*/ 0x00000000,
|
||||
/*0bb8*/ 0x00000000,
|
||||
/*0bb9*/ 0x00000000,
|
||||
/*0bba*/ 0x00000000,
|
||||
/*0bbb*/ 0x00000000,
|
||||
/*0bbc*/ 0x06e40000,
|
||||
/*0bbd*/ 0x00000000,
|
||||
/*0bbe*/ 0x00000000,
|
||||
/*0bbf*/ 0x00010000
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PI_REGSET_M3[DDR_PI_REGSET_NUM_M3] = {
|
||||
/*0200*/ 0x00000b00,
|
||||
/*0201*/ 0x00000100,
|
||||
/*0202*/ 0x00000000,
|
||||
/*0203*/ 0x0000ffff,
|
||||
/*0204*/ 0x00000000,
|
||||
/*0205*/ 0x0000ffff,
|
||||
/*0206*/ 0x00000000,
|
||||
/*0207*/ 0x304cffff,
|
||||
/*0208*/ 0x00000200,
|
||||
/*0209*/ 0x00000200,
|
||||
/*020a*/ 0x00000200,
|
||||
/*020b*/ 0x00000200,
|
||||
/*020c*/ 0x0000304c,
|
||||
/*020d*/ 0x00000200,
|
||||
/*020e*/ 0x00000200,
|
||||
/*020f*/ 0x00000200,
|
||||
/*0210*/ 0x00000200,
|
||||
/*0211*/ 0x0000304c,
|
||||
/*0212*/ 0x00000200,
|
||||
/*0213*/ 0x00000200,
|
||||
/*0214*/ 0x00000200,
|
||||
/*0215*/ 0x00000200,
|
||||
/*0216*/ 0x00010000,
|
||||
/*0217*/ 0x00000003,
|
||||
/*0218*/ 0x01000001,
|
||||
/*0219*/ 0x00000000,
|
||||
/*021a*/ 0x00000000,
|
||||
/*021b*/ 0x00000000,
|
||||
/*021c*/ 0x00000000,
|
||||
/*021d*/ 0x00000000,
|
||||
/*021e*/ 0x00000000,
|
||||
/*021f*/ 0x00000000,
|
||||
/*0220*/ 0x00000000,
|
||||
/*0221*/ 0x00000000,
|
||||
/*0222*/ 0x00000000,
|
||||
/*0223*/ 0x00000000,
|
||||
/*0224*/ 0x00000000,
|
||||
/*0225*/ 0x00000000,
|
||||
/*0226*/ 0x00000000,
|
||||
/*0227*/ 0x00000000,
|
||||
/*0228*/ 0x00000000,
|
||||
/*0229*/ 0x0f000101,
|
||||
/*022a*/ 0x08492d25,
|
||||
/*022b*/ 0x0e0c0004,
|
||||
/*022c*/ 0x000e5000,
|
||||
/*022d*/ 0x00000250,
|
||||
/*022e*/ 0x00460003,
|
||||
/*022f*/ 0x182600cf,
|
||||
/*0230*/ 0x182600cf,
|
||||
/*0231*/ 0x00000005,
|
||||
/*0232*/ 0x00000000,
|
||||
/*0233*/ 0x00000000,
|
||||
/*0234*/ 0x00000000,
|
||||
/*0235*/ 0x00000000,
|
||||
/*0236*/ 0x00000000,
|
||||
/*0237*/ 0x00000000,
|
||||
/*0238*/ 0x00000000,
|
||||
/*0239*/ 0x01000000,
|
||||
/*023a*/ 0x00040404,
|
||||
/*023b*/ 0x01280a00,
|
||||
/*023c*/ 0x00000000,
|
||||
/*023d*/ 0x000f0000,
|
||||
/*023e*/ 0x00001803,
|
||||
/*023f*/ 0x00000000,
|
||||
/*0240*/ 0x00000000,
|
||||
/*0241*/ 0x00060002,
|
||||
/*0242*/ 0x00010001,
|
||||
/*0243*/ 0x01000101,
|
||||
/*0244*/ 0x04020201,
|
||||
/*0245*/ 0x00080804,
|
||||
/*0246*/ 0x00000000,
|
||||
/*0247*/ 0x08030000,
|
||||
/*0248*/ 0x15150408,
|
||||
/*0249*/ 0x00000000,
|
||||
/*024a*/ 0x00000000,
|
||||
/*024b*/ 0x00000000,
|
||||
/*024c*/ 0x000f0f00,
|
||||
/*024d*/ 0x0000001e,
|
||||
/*024e*/ 0x00000000,
|
||||
/*024f*/ 0x01000300,
|
||||
/*0250*/ 0x00000000,
|
||||
/*0251*/ 0x00000000,
|
||||
/*0252*/ 0x01000000,
|
||||
/*0253*/ 0x00010101,
|
||||
/*0254*/ 0x000e0e0e,
|
||||
/*0255*/ 0x000c0c0c,
|
||||
/*0256*/ 0x02060601,
|
||||
/*0257*/ 0x00000000,
|
||||
/*0258*/ 0x00000003,
|
||||
/*0259*/ 0x00181703,
|
||||
/*025a*/ 0x00280006,
|
||||
/*025b*/ 0x00280016,
|
||||
/*025c*/ 0x00000016,
|
||||
/*025d*/ 0x00000000,
|
||||
/*025e*/ 0x00000000,
|
||||
/*025f*/ 0x00000000,
|
||||
/*0260*/ 0x140a0000,
|
||||
/*0261*/ 0x0005010a,
|
||||
/*0262*/ 0x03018d03,
|
||||
/*0263*/ 0x000a018d,
|
||||
/*0264*/ 0x00060100,
|
||||
/*0265*/ 0x01000006,
|
||||
/*0266*/ 0x018e018e,
|
||||
/*0267*/ 0x018e0100,
|
||||
/*0268*/ 0x1111018e,
|
||||
/*0269*/ 0x10010204,
|
||||
/*026a*/ 0x09090650,
|
||||
/*026b*/ 0x20110202,
|
||||
/*026c*/ 0x00201000,
|
||||
/*026d*/ 0x00201000,
|
||||
/*026e*/ 0x04041000,
|
||||
/*026f*/ 0x18020100,
|
||||
/*0270*/ 0x00010118,
|
||||
/*0271*/ 0x004b004a,
|
||||
/*0272*/ 0x050f0000,
|
||||
/*0273*/ 0x0c01021e,
|
||||
/*0274*/ 0x34000000,
|
||||
/*0275*/ 0x00000000,
|
||||
/*0276*/ 0x00000000,
|
||||
/*0277*/ 0x00000000,
|
||||
/*0278*/ 0x0000d400,
|
||||
/*0279*/ 0x0031002e,
|
||||
/*027a*/ 0x00111136,
|
||||
/*027b*/ 0x002e00d4,
|
||||
/*027c*/ 0x11360031,
|
||||
/*027d*/ 0x0000d411,
|
||||
/*027e*/ 0x0031002e,
|
||||
/*027f*/ 0x00111136,
|
||||
/*0280*/ 0x002e00d4,
|
||||
/*0281*/ 0x11360031,
|
||||
/*0282*/ 0x0000d411,
|
||||
/*0283*/ 0x0031002e,
|
||||
/*0284*/ 0x00111136,
|
||||
/*0285*/ 0x002e00d4,
|
||||
/*0286*/ 0x11360031,
|
||||
/*0287*/ 0x00d40011,
|
||||
/*0288*/ 0x0031002e,
|
||||
/*0289*/ 0x00111136,
|
||||
/*028a*/ 0x002e00d4,
|
||||
/*028b*/ 0x11360031,
|
||||
/*028c*/ 0x0000d411,
|
||||
/*028d*/ 0x0031002e,
|
||||
/*028e*/ 0x00111136,
|
||||
/*028f*/ 0x002e00d4,
|
||||
/*0290*/ 0x11360031,
|
||||
/*0291*/ 0x0000d411,
|
||||
/*0292*/ 0x0031002e,
|
||||
/*0293*/ 0x00111136,
|
||||
/*0294*/ 0x002e00d4,
|
||||
/*0295*/ 0x11360031,
|
||||
/*0296*/ 0x02000011,
|
||||
/*0297*/ 0x018d018d,
|
||||
/*0298*/ 0x0c08018d,
|
||||
/*0299*/ 0x1f121d22,
|
||||
/*029a*/ 0x4301b344,
|
||||
/*029b*/ 0x10172006,
|
||||
/*029c*/ 0x1d220c10,
|
||||
/*029d*/ 0x00001f12,
|
||||
/*029e*/ 0x4301b344,
|
||||
/*029f*/ 0x10172006,
|
||||
/*02a0*/ 0x1d220c10,
|
||||
/*02a1*/ 0x00001f12,
|
||||
/*02a2*/ 0x4301b344,
|
||||
/*02a3*/ 0x10172006,
|
||||
/*02a4*/ 0x02000210,
|
||||
/*02a5*/ 0x02000200,
|
||||
/*02a6*/ 0x02000200,
|
||||
/*02a7*/ 0x02000200,
|
||||
/*02a8*/ 0x02000200,
|
||||
/*02a9*/ 0x00000000,
|
||||
/*02aa*/ 0x00000000,
|
||||
/*02ab*/ 0x00000000,
|
||||
/*02ac*/ 0x00000000,
|
||||
/*02ad*/ 0x00000000,
|
||||
/*02ae*/ 0x00000000,
|
||||
/*02af*/ 0x00000000,
|
||||
/*02b0*/ 0x00000000,
|
||||
/*02b1*/ 0x00000000,
|
||||
/*02b2*/ 0x00000000,
|
||||
/*02b3*/ 0x00000000,
|
||||
/*02b4*/ 0x00000000,
|
||||
/*02b5*/ 0x00000400,
|
||||
/*02b6*/ 0x15141312,
|
||||
/*02b7*/ 0x11100f0e,
|
||||
/*02b8*/ 0x080b0c0d,
|
||||
/*02b9*/ 0x05040a09,
|
||||
/*02ba*/ 0x01000706,
|
||||
/*02bb*/ 0x00000302,
|
||||
/*02bc*/ 0x01030201,
|
||||
/*02bd*/ 0x00304c00,
|
||||
/*02be*/ 0x0001e2f8,
|
||||
/*02bf*/ 0x0000304c,
|
||||
/*02c0*/ 0x0001e2f8,
|
||||
/*02c1*/ 0x0000304c,
|
||||
/*02c2*/ 0x0001e2f8,
|
||||
/*02c3*/ 0x08000000,
|
||||
/*02c4*/ 0x00000100,
|
||||
/*02c5*/ 0x00000000,
|
||||
/*02c6*/ 0x00000000,
|
||||
/*02c7*/ 0x00000000,
|
||||
/*02c8*/ 0x00000000,
|
||||
/*02c9*/ 0x00000002
|
||||
};
|
||||
+587
@@ -0,0 +1,587 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2020, Renesas Electronics Corporation.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_OFS_M3N 0x0800
|
||||
#define DDR_PHY_ADR_V_REGSET_OFS_M3N 0x0a00
|
||||
#define DDR_PHY_ADR_I_REGSET_OFS_M3N 0x0a80
|
||||
#define DDR_PHY_ADR_G_REGSET_OFS_M3N 0x0b80
|
||||
#define DDR_PI_REGSET_OFS_M3N 0x0200
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_SIZE_M3N 0x80
|
||||
#define DDR_PHY_ADR_V_REGSET_SIZE_M3N 0x80
|
||||
#define DDR_PHY_ADR_I_REGSET_SIZE_M3N 0x80
|
||||
#define DDR_PHY_ADR_G_REGSET_SIZE_M3N 0x80
|
||||
#define DDR_PI_REGSET_SIZE_M3N 0x100
|
||||
|
||||
#define DDR_PHY_SLICE_REGSET_NUM_M3N 101
|
||||
#define DDR_PHY_ADR_V_REGSET_NUM_M3N 37
|
||||
#define DDR_PHY_ADR_I_REGSET_NUM_M3N 37
|
||||
#define DDR_PHY_ADR_G_REGSET_NUM_M3N 87
|
||||
#define DDR_PI_REGSET_NUM_M3N 286
|
||||
|
||||
static const uint32_t DDR_PHY_SLICE_REGSET_M3N[DDR_PHY_SLICE_REGSET_NUM_M3N] = {
|
||||
/*0800*/ 0x76543210,
|
||||
/*0801*/ 0x0004f008,
|
||||
/*0802*/ 0x00020200,
|
||||
/*0803*/ 0x00000000,
|
||||
/*0804*/ 0x00000000,
|
||||
/*0805*/ 0x00010000,
|
||||
/*0806*/ 0x036e6e0e,
|
||||
/*0807*/ 0x026e6e0e,
|
||||
/*0808*/ 0x00000103,
|
||||
/*0809*/ 0x00040001,
|
||||
/*080a*/ 0x00000103,
|
||||
/*080b*/ 0x00000001,
|
||||
/*080c*/ 0x00000000,
|
||||
/*080d*/ 0x00000000,
|
||||
/*080e*/ 0x00000100,
|
||||
/*080f*/ 0x001800c0,
|
||||
/*0810*/ 0x020100b0,
|
||||
/*0811*/ 0x00030020,
|
||||
/*0812*/ 0x00000000,
|
||||
/*0813*/ 0x00000000,
|
||||
/*0814*/ 0x0000aaaa,
|
||||
/*0815*/ 0x00005555,
|
||||
/*0816*/ 0x0000b5b5,
|
||||
/*0817*/ 0x00004a4a,
|
||||
/*0818*/ 0x00000000,
|
||||
/*0819*/ 0x09000000,
|
||||
/*081a*/ 0x04080000,
|
||||
/*081b*/ 0x08040000,
|
||||
/*081c*/ 0x00000004,
|
||||
/*081d*/ 0x00800710,
|
||||
/*081e*/ 0x000f000c,
|
||||
/*081f*/ 0x00000100,
|
||||
/*0820*/ 0x55aa55aa,
|
||||
/*0821*/ 0x33cc33cc,
|
||||
/*0822*/ 0x0ff00ff0,
|
||||
/*0823*/ 0x0f0ff0f0,
|
||||
/*0824*/ 0x00018e38,
|
||||
/*0825*/ 0x00000000,
|
||||
/*0826*/ 0x00000000,
|
||||
/*0827*/ 0x00000000,
|
||||
/*0828*/ 0x00000000,
|
||||
/*0829*/ 0x00000000,
|
||||
/*082a*/ 0x00000000,
|
||||
/*082b*/ 0x00000000,
|
||||
/*082c*/ 0x00000000,
|
||||
/*082d*/ 0x00000000,
|
||||
/*082e*/ 0x00000000,
|
||||
/*082f*/ 0x00000000,
|
||||
/*0830*/ 0x00000000,
|
||||
/*0831*/ 0x00000000,
|
||||
/*0832*/ 0x00000000,
|
||||
/*0833*/ 0x00000000,
|
||||
/*0834*/ 0x00000000,
|
||||
/*0835*/ 0x00000000,
|
||||
/*0836*/ 0x00000000,
|
||||
/*0837*/ 0x00000000,
|
||||
/*0838*/ 0x00000000,
|
||||
/*0839*/ 0x00000000,
|
||||
/*083a*/ 0x00000104,
|
||||
/*083b*/ 0x00082020,
|
||||
/*083c*/ 0x08200820,
|
||||
/*083d*/ 0x08200820,
|
||||
/*083e*/ 0x08200820,
|
||||
/*083f*/ 0x08200820,
|
||||
/*0840*/ 0x08200820,
|
||||
/*0841*/ 0x00000000,
|
||||
/*0842*/ 0x00000000,
|
||||
/*0843*/ 0x03000300,
|
||||
/*0844*/ 0x03000300,
|
||||
/*0845*/ 0x03000300,
|
||||
/*0846*/ 0x03000300,
|
||||
/*0847*/ 0x00000300,
|
||||
/*0848*/ 0x00000000,
|
||||
/*0849*/ 0x00000000,
|
||||
/*084a*/ 0x00000000,
|
||||
/*084b*/ 0x00000000,
|
||||
/*084c*/ 0x00000000,
|
||||
/*084d*/ 0x00a000a0,
|
||||
/*084e*/ 0x00a000a0,
|
||||
/*084f*/ 0x00a000a0,
|
||||
/*0850*/ 0x00a000a0,
|
||||
/*0851*/ 0x00a000a0,
|
||||
/*0852*/ 0x00a000a0,
|
||||
/*0853*/ 0x00a000a0,
|
||||
/*0854*/ 0x00a000a0,
|
||||
/*0855*/ 0x00a000a0,
|
||||
/*0856*/ 0x01040119,
|
||||
/*0857*/ 0x00000200,
|
||||
/*0858*/ 0x01000000,
|
||||
/*0859*/ 0x00000200,
|
||||
/*085a*/ 0x00000004,
|
||||
/*085b*/ 0x4041a151,
|
||||
/*085c*/ 0x0141a0a0,
|
||||
/*085d*/ 0x0000c0c0,
|
||||
/*085e*/ 0x0e0c000e,
|
||||
/*085f*/ 0x10001000,
|
||||
/*0860*/ 0x0c073e42,
|
||||
/*0861*/ 0x000f0c28,
|
||||
/*0862*/ 0x00e00140,
|
||||
/*0863*/ 0x000c0020,
|
||||
/*0864*/ 0x00000203
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_V_REGSET_M3N[DDR_PHY_ADR_V_REGSET_NUM_M3N] = {
|
||||
/*0a00*/ 0x00000000,
|
||||
/*0a01*/ 0x00000000,
|
||||
/*0a02*/ 0x00000000,
|
||||
/*0a03*/ 0x00000000,
|
||||
/*0a04*/ 0x00000000,
|
||||
/*0a05*/ 0x00000000,
|
||||
/*0a06*/ 0x00000000,
|
||||
/*0a07*/ 0x01000000,
|
||||
/*0a08*/ 0x00020000,
|
||||
/*0a09*/ 0x00000000,
|
||||
/*0a0a*/ 0x00000000,
|
||||
/*0a0b*/ 0x00000000,
|
||||
/*0a0c*/ 0x00400000,
|
||||
/*0a0d*/ 0x00000080,
|
||||
/*0a0e*/ 0x00dcba98,
|
||||
/*0a0f*/ 0x03000000,
|
||||
/*0a10*/ 0x00000200,
|
||||
/*0a11*/ 0x00000000,
|
||||
/*0a12*/ 0x00000000,
|
||||
/*0a13*/ 0x00000000,
|
||||
/*0a14*/ 0x0000002a,
|
||||
/*0a15*/ 0x00000015,
|
||||
/*0a16*/ 0x00000015,
|
||||
/*0a17*/ 0x0000002a,
|
||||
/*0a18*/ 0x00000033,
|
||||
/*0a19*/ 0x0000000c,
|
||||
/*0a1a*/ 0x0000000c,
|
||||
/*0a1b*/ 0x00000033,
|
||||
/*0a1c*/ 0x0a418820,
|
||||
/*0a1d*/ 0x003f0000,
|
||||
/*0a1e*/ 0x0000013f,
|
||||
/*0a1f*/ 0x0002c06e,
|
||||
/*0a20*/ 0x02c002c0,
|
||||
/*0a21*/ 0x02c002c0,
|
||||
/*0a22*/ 0x000002c0,
|
||||
/*0a23*/ 0x42080010,
|
||||
/*0a24*/ 0x0000033e
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_I_REGSET_M3N[DDR_PHY_ADR_I_REGSET_NUM_M3N] = {
|
||||
/*0a80*/ 0x00000000,
|
||||
/*0a81*/ 0x00000000,
|
||||
/*0a82*/ 0x00000000,
|
||||
/*0a83*/ 0x00000000,
|
||||
/*0a84*/ 0x00000000,
|
||||
/*0a85*/ 0x00000000,
|
||||
/*0a86*/ 0x00000000,
|
||||
/*0a87*/ 0x01000000,
|
||||
/*0a88*/ 0x00020000,
|
||||
/*0a89*/ 0x00000000,
|
||||
/*0a8a*/ 0x00000000,
|
||||
/*0a8b*/ 0x00000000,
|
||||
/*0a8c*/ 0x00400000,
|
||||
/*0a8d*/ 0x00000080,
|
||||
/*0a8e*/ 0x00000000,
|
||||
/*0a8f*/ 0x03000000,
|
||||
/*0a90*/ 0x00000200,
|
||||
/*0a91*/ 0x00000000,
|
||||
/*0a92*/ 0x00000000,
|
||||
/*0a93*/ 0x00000000,
|
||||
/*0a94*/ 0x0000002a,
|
||||
/*0a95*/ 0x00000015,
|
||||
/*0a96*/ 0x00000015,
|
||||
/*0a97*/ 0x0000002a,
|
||||
/*0a98*/ 0x00000033,
|
||||
/*0a99*/ 0x0000000c,
|
||||
/*0a9a*/ 0x0000000c,
|
||||
/*0a9b*/ 0x00000033,
|
||||
/*0a9c*/ 0x00000000,
|
||||
/*0a9d*/ 0x00000000,
|
||||
/*0a9e*/ 0x00000000,
|
||||
/*0a9f*/ 0x0002c06e,
|
||||
/*0aa0*/ 0x02c002c0,
|
||||
/*0aa1*/ 0x02c002c0,
|
||||
/*0aa2*/ 0x000002c0,
|
||||
/*0aa3*/ 0x42080010,
|
||||
/*0aa4*/ 0x0000033e
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = {
|
||||
/*0b80*/ 0x00000000,
|
||||
/*0b81*/ 0x00000100,
|
||||
/*0b82*/ 0x00000000,
|
||||
/*0b83*/ 0x00050000,
|
||||
/*0b84*/ 0x00000000,
|
||||
/*0b85*/ 0x0004000f,
|
||||
/*0b86*/ 0x00280080,
|
||||
/*0b87*/ 0x02005502,
|
||||
/*0b88*/ 0x00000000,
|
||||
/*0b89*/ 0x00000000,
|
||||
/*0b8a*/ 0x00000000,
|
||||
/*0b8b*/ 0x00000050,
|
||||
/*0b8c*/ 0x00000000,
|
||||
/*0b8d*/ 0x01010100,
|
||||
/*0b8e*/ 0x00010000,
|
||||
/*0b8f*/ 0x00000000,
|
||||
/*0b90*/ 0x00000101,
|
||||
/*0b91*/ 0x00000000,
|
||||
/*0b92*/ 0x00000000,
|
||||
/*0b93*/ 0x00000000,
|
||||
/*0b94*/ 0x00000000,
|
||||
/*0b95*/ 0x00005064,
|
||||
/*0b96*/ 0x01421142,
|
||||
/*0b97*/ 0x00000142,
|
||||
/*0b98*/ 0x00000000,
|
||||
/*0b99*/ 0x000f1600,
|
||||
/*0b9a*/ 0x0f160f16,
|
||||
/*0b9b*/ 0x0f160f16,
|
||||
/*0b9c*/ 0x00000003,
|
||||
/*0b9d*/ 0x0002c000,
|
||||
/*0b9e*/ 0x02c002c0,
|
||||
/*0b9f*/ 0x000002c0,
|
||||
/*0ba0*/ 0x08040201,
|
||||
/*0ba1*/ 0x03421342,
|
||||
/*0ba2*/ 0x00000342,
|
||||
/*0ba3*/ 0x00000000,
|
||||
/*0ba4*/ 0x00000000,
|
||||
/*0ba5*/ 0x05030000,
|
||||
/*0ba6*/ 0x00010700,
|
||||
/*0ba7*/ 0x00000014,
|
||||
/*0ba8*/ 0x00027f6e,
|
||||
/*0ba9*/ 0x047f027f,
|
||||
/*0baa*/ 0x00027f6e,
|
||||
/*0bab*/ 0x00047f6e,
|
||||
/*0bac*/ 0x0003554f,
|
||||
/*0bad*/ 0x0001554f,
|
||||
/*0bae*/ 0x0001554f,
|
||||
/*0baf*/ 0x0001554f,
|
||||
/*0bb0*/ 0x0001554f,
|
||||
/*0bb1*/ 0x00003fee,
|
||||
/*0bb2*/ 0x0001554f,
|
||||
/*0bb3*/ 0x00003fee,
|
||||
/*0bb4*/ 0x0001554f,
|
||||
/*0bb5*/ 0x00027f6e,
|
||||
/*0bb6*/ 0x0001554f,
|
||||
/*0bb7*/ 0x00004011,
|
||||
/*0bb8*/ 0x00004410,
|
||||
/*0bb9*/ 0x00000000,
|
||||
/*0bba*/ 0x00000000,
|
||||
/*0bbb*/ 0x00000000,
|
||||
/*0bbc*/ 0x00000265,
|
||||
/*0bbd*/ 0x00000000,
|
||||
/*0bbe*/ 0x00040401,
|
||||
/*0bbf*/ 0x00000000,
|
||||
/*0bc0*/ 0x03000000,
|
||||
/*0bc1*/ 0x00000020,
|
||||
/*0bc2*/ 0x00000000,
|
||||
/*0bc3*/ 0x00000000,
|
||||
/*0bc4*/ 0x04102006,
|
||||
/*0bc5*/ 0x00041020,
|
||||
/*0bc6*/ 0x01c98c98,
|
||||
/*0bc7*/ 0x00400000,
|
||||
/*0bc8*/ 0x00000000,
|
||||
/*0bc9*/ 0x0001ffff,
|
||||
/*0bca*/ 0x00000000,
|
||||
/*0bcb*/ 0x00000000,
|
||||
/*0bcc*/ 0x00000001,
|
||||
/*0bcd*/ 0x00000000,
|
||||
/*0bce*/ 0x00000000,
|
||||
/*0bcf*/ 0x00000000,
|
||||
/*0bd0*/ 0x76543210,
|
||||
/*0bd1*/ 0x06010198,
|
||||
/*0bd2*/ 0x00000000,
|
||||
/*0bd3*/ 0x00000000,
|
||||
/*0bd4*/ 0x04070000,
|
||||
/*0bd5*/ 0x00000001,
|
||||
/*0bd6*/ 0x00000f00
|
||||
};
|
||||
|
||||
static const uint32_t DDR_PI_REGSET_M3N[DDR_PI_REGSET_NUM_M3N] = {
|
||||
/*0200*/ 0x00000b00,
|
||||
/*0201*/ 0x00000101,
|
||||
/*0202*/ 0x01640000,
|
||||
/*0203*/ 0x00000014,
|
||||
/*0204*/ 0x00000014,
|
||||
/*0205*/ 0x00000014,
|
||||
/*0206*/ 0x00000014,
|
||||
/*0207*/ 0x00000000,
|
||||
/*0208*/ 0x00000000,
|
||||
/*0209*/ 0x0000ffff,
|
||||
/*020a*/ 0x00000000,
|
||||
/*020b*/ 0x0000ffff,
|
||||
/*020c*/ 0x00000000,
|
||||
/*020d*/ 0x0000ffff,
|
||||
/*020e*/ 0x0000304c,
|
||||
/*020f*/ 0x00000200,
|
||||
/*0210*/ 0x00000200,
|
||||
/*0211*/ 0x00000200,
|
||||
/*0212*/ 0x00000200,
|
||||
/*0213*/ 0x0000304c,
|
||||
/*0214*/ 0x00000200,
|
||||
/*0215*/ 0x00000200,
|
||||
/*0216*/ 0x00000200,
|
||||
/*0217*/ 0x00000200,
|
||||
/*0218*/ 0x0000304c,
|
||||
/*0219*/ 0x00000200,
|
||||
/*021a*/ 0x00000200,
|
||||
/*021b*/ 0x00000200,
|
||||
/*021c*/ 0x00000200,
|
||||
/*021d*/ 0x00010000,
|
||||
/*021e*/ 0x00000003,
|
||||
/*021f*/ 0x01000001,
|
||||
/*0220*/ 0x00000000,
|
||||
/*0221*/ 0x00000000,
|
||||
/*0222*/ 0x00000000,
|
||||
/*0223*/ 0x00000000,
|
||||
/*0224*/ 0x00000000,
|
||||
/*0225*/ 0x00000000,
|
||||
/*0226*/ 0x00000000,
|
||||
/*0227*/ 0x00000000,
|
||||
/*0228*/ 0x00000000,
|
||||
/*0229*/ 0x00000000,
|
||||
/*022a*/ 0x00000000,
|
||||
/*022b*/ 0x00000000,
|
||||
/*022c*/ 0x00000000,
|
||||
/*022d*/ 0x00000000,
|
||||
/*022e*/ 0x00000000,
|
||||
/*022f*/ 0x00000000,
|
||||
/*0230*/ 0x0f000101,
|
||||
/*0231*/ 0x084d3129,
|
||||
/*0232*/ 0x0e0c0004,
|
||||
/*0233*/ 0x000e5000,
|
||||
/*0234*/ 0x01000250,
|
||||
/*0235*/ 0x00000003,
|
||||
/*0236*/ 0x00000046,
|
||||
/*0237*/ 0x000000cf,
|
||||
/*0238*/ 0x00001826,
|
||||
/*0239*/ 0x000000cf,
|
||||
/*023a*/ 0x00001826,
|
||||
/*023b*/ 0x00000000,
|
||||
/*023c*/ 0x00000000,
|
||||
/*023d*/ 0x00000000,
|
||||
/*023e*/ 0x00000000,
|
||||
/*023f*/ 0x00000000,
|
||||
/*0240*/ 0x00000000,
|
||||
/*0241*/ 0x00000000,
|
||||
/*0242*/ 0x00000000,
|
||||
/*0243*/ 0x00000000,
|
||||
/*0244*/ 0x00000000,
|
||||
/*0245*/ 0x01000000,
|
||||
/*0246*/ 0x00040404,
|
||||
/*0247*/ 0x01280a00,
|
||||
/*0248*/ 0x00000001,
|
||||
/*0249*/ 0x00000000,
|
||||
/*024a*/ 0x03000f00,
|
||||
/*024b*/ 0x00200020,
|
||||
/*024c*/ 0x00000020,
|
||||
/*024d*/ 0x00000000,
|
||||
/*024e*/ 0x00000000,
|
||||
/*024f*/ 0x00010002,
|
||||
/*0250*/ 0x01010001,
|
||||
/*0251*/ 0x02010100,
|
||||
/*0252*/ 0x08040402,
|
||||
/*0253*/ 0x00000008,
|
||||
/*0254*/ 0x00000000,
|
||||
/*0255*/ 0x04080803,
|
||||
/*0256*/ 0x00001515,
|
||||
/*0257*/ 0x00000000,
|
||||
/*0258*/ 0x000000aa,
|
||||
/*0259*/ 0x00000055,
|
||||
/*025a*/ 0x000000b5,
|
||||
/*025b*/ 0x0000004a,
|
||||
/*025c*/ 0x00000056,
|
||||
/*025d*/ 0x000000a9,
|
||||
/*025e*/ 0x000000a9,
|
||||
/*025f*/ 0x000000b5,
|
||||
/*0260*/ 0x00000000,
|
||||
/*0261*/ 0x00000000,
|
||||
/*0262*/ 0x0f000000,
|
||||
/*0263*/ 0x00001e0f,
|
||||
/*0264*/ 0x000007d0,
|
||||
/*0265*/ 0x01000300,
|
||||
/*0266*/ 0x00000100,
|
||||
/*0267*/ 0x00000000,
|
||||
/*0268*/ 0x00000000,
|
||||
/*0269*/ 0x01000000,
|
||||
/*026a*/ 0x00010101,
|
||||
/*026b*/ 0x000e0e0e,
|
||||
/*026c*/ 0x000c0c0c,
|
||||
/*026d*/ 0x01060601,
|
||||
/*026e*/ 0x04041717,
|
||||
/*026f*/ 0x00000004,
|
||||
/*0270*/ 0x00000300,
|
||||
/*0271*/ 0x17030000,
|
||||
/*0272*/ 0x00060018,
|
||||
/*0273*/ 0x00160028,
|
||||
/*0274*/ 0x00160028,
|
||||
/*0275*/ 0x00000000,
|
||||
/*0276*/ 0x00000000,
|
||||
/*0277*/ 0x00000000,
|
||||
/*0278*/ 0x0a000000,
|
||||
/*0279*/ 0x00010a14,
|
||||
/*027a*/ 0x00030005,
|
||||
/*027b*/ 0x0003018d,
|
||||
/*027c*/ 0x000a018d,
|
||||
/*027d*/ 0x00060100,
|
||||
/*027e*/ 0x01000006,
|
||||
/*027f*/ 0x018e018e,
|
||||
/*0280*/ 0x018e0100,
|
||||
/*0281*/ 0x1e1a018e,
|
||||
/*0282*/ 0x1e1a1e1a,
|
||||
/*0283*/ 0x01010204,
|
||||
/*0284*/ 0x06501001,
|
||||
/*0285*/ 0x090d0a07,
|
||||
/*0286*/ 0x090d0a07,
|
||||
/*0287*/ 0x0811180f,
|
||||
/*0288*/ 0x00ff1102,
|
||||
/*0289*/ 0x00ff1000,
|
||||
/*028a*/ 0x00ff1000,
|
||||
/*028b*/ 0x04041000,
|
||||
/*028c*/ 0x18020100,
|
||||
/*028d*/ 0x01010018,
|
||||
/*028e*/ 0x005f005f,
|
||||
/*028f*/ 0x005f005f,
|
||||
/*0290*/ 0x050f0000,
|
||||
/*0291*/ 0x051e051e,
|
||||
/*0292*/ 0x0c01021e,
|
||||
/*0293*/ 0x00000c0c,
|
||||
/*0294*/ 0x00003400,
|
||||
/*0295*/ 0x00000000,
|
||||
/*0296*/ 0x00000000,
|
||||
/*0297*/ 0x00000000,
|
||||
/*0298*/ 0x00000000,
|
||||
/*0299*/ 0x002e00d4,
|
||||
/*029a*/ 0x11360031,
|
||||
/*029b*/ 0x00d41611,
|
||||
/*029c*/ 0x0031002e,
|
||||
/*029d*/ 0x16111136,
|
||||
/*029e*/ 0x002e00d4,
|
||||
/*029f*/ 0x11360031,
|
||||
/*02a0*/ 0x00001611,
|
||||
/*02a1*/ 0x002e00d4,
|
||||
/*02a2*/ 0x11360031,
|
||||
/*02a3*/ 0x00d41611,
|
||||
/*02a4*/ 0x0031002e,
|
||||
/*02a5*/ 0x16111136,
|
||||
/*02a6*/ 0x002e00d4,
|
||||
/*02a7*/ 0x11360031,
|
||||
/*02a8*/ 0x00001611,
|
||||
/*02a9*/ 0x002e00d4,
|
||||
/*02aa*/ 0x11360031,
|
||||
/*02ab*/ 0x00d41611,
|
||||
/*02ac*/ 0x0031002e,
|
||||
/*02ad*/ 0x16111136,
|
||||
/*02ae*/ 0x002e00d4,
|
||||
/*02af*/ 0x11360031,
|
||||
/*02b0*/ 0x00001611,
|
||||
/*02b1*/ 0x002e00d4,
|
||||
/*02b2*/ 0x11360031,
|
||||
/*02b3*/ 0x00d41611,
|
||||
/*02b4*/ 0x0031002e,
|
||||
/*02b5*/ 0x16111136,
|
||||
/*02b6*/ 0x002e00d4,
|
||||
/*02b7*/ 0x11360031,
|
||||
/*02b8*/ 0x00001611,
|
||||
/*02b9*/ 0x00018d00,
|
||||
/*02ba*/ 0x018d018d,
|
||||
/*02bb*/ 0x1d220c08,
|
||||
/*02bc*/ 0x00001f12,
|
||||
/*02bd*/ 0x4301b344,
|
||||
/*02be*/ 0x17032006,
|
||||
/*02bf*/ 0x220c1010,
|
||||
/*02c0*/ 0x001f121d,
|
||||
/*02c1*/ 0x4301b344,
|
||||
/*02c2*/ 0x17062006,
|
||||
/*02c3*/ 0x220c1010,
|
||||
/*02c4*/ 0x001f121d,
|
||||
/*02c5*/ 0x4301b344,
|
||||
/*02c6*/ 0x17182006,
|
||||
/*02c7*/ 0x00021010,
|
||||
/*02c8*/ 0x00020002,
|
||||
/*02c9*/ 0x00020002,
|
||||
/*02ca*/ 0x00020002,
|
||||
/*02cb*/ 0x00020002,
|
||||
/*02cc*/ 0x00000002,
|
||||
/*02cd*/ 0x00000000,
|
||||
/*02ce*/ 0x00000000,
|
||||
/*02cf*/ 0x00000000,
|
||||
/*02d0*/ 0x00000000,
|
||||
/*02d1*/ 0x00000000,
|
||||
/*02d2*/ 0x00000000,
|
||||
/*02d3*/ 0x00000000,
|
||||
/*02d4*/ 0x00000000,
|
||||
/*02d5*/ 0x00000000,
|
||||
/*02d6*/ 0x00000000,
|
||||
/*02d7*/ 0x00000000,
|
||||
/*02d8*/ 0x00000000,
|
||||
/*02d9*/ 0x00000400,
|
||||
/*02da*/ 0x15141312,
|
||||
/*02db*/ 0x11100f0e,
|
||||
/*02dc*/ 0x080b0c0d,
|
||||
/*02dd*/ 0x05040a09,
|
||||
/*02de*/ 0x01000706,
|
||||
/*02df*/ 0x00000302,
|
||||
/*02e0*/ 0x01030201,
|
||||
/*02e1*/ 0x00304c08,
|
||||
/*02e2*/ 0x0001e2f8,
|
||||
/*02e3*/ 0x0000304c,
|
||||
/*02e4*/ 0x0001e2f8,
|
||||
/*02e5*/ 0x0000304c,
|
||||
/*02e6*/ 0x0001e2f8,
|
||||
/*02e7*/ 0x08000000,
|
||||
/*02e8*/ 0x00000100,
|
||||
/*02e9*/ 0x00000000,
|
||||
/*02ea*/ 0x00000000,
|
||||
/*02eb*/ 0x00000000,
|
||||
/*02ec*/ 0x00000000,
|
||||
/*02ed*/ 0x00010000,
|
||||
/*02ee*/ 0x00000000,
|
||||
/*02ef*/ 0x00000000,
|
||||
/*02f0*/ 0x00000000,
|
||||
/*02f1*/ 0x00000000,
|
||||
/*02f2*/ 0x00000000,
|
||||
/*02f3*/ 0x00000000,
|
||||
/*02f4*/ 0x00000000,
|
||||
/*02f5*/ 0x00000000,
|
||||
/*02f6*/ 0x00000000,
|
||||
/*02f7*/ 0x00000000,
|
||||
/*02f8*/ 0x00000000,
|
||||
/*02f9*/ 0x00000000,
|
||||
/*02fa*/ 0x00000000,
|
||||
/*02fb*/ 0x00000000,
|
||||
/*02fc*/ 0x00000000,
|
||||
/*02fd*/ 0x00000000,
|
||||
/*02fe*/ 0x00000000,
|
||||
/*02ff*/ 0x00000000,
|
||||
/*0300*/ 0x00000000,
|
||||
/*0301*/ 0x00000000,
|
||||
/*0302*/ 0x00000000,
|
||||
/*0303*/ 0x00000000,
|
||||
/*0304*/ 0x00000000,
|
||||
/*0305*/ 0x00000000,
|
||||
/*0306*/ 0x00000000,
|
||||
/*0307*/ 0x00000000,
|
||||
/*0308*/ 0x00000000,
|
||||
/*0309*/ 0x00000000,
|
||||
/*030a*/ 0x00000000,
|
||||
/*030b*/ 0x00000000,
|
||||
/*030c*/ 0x00000000,
|
||||
/*030d*/ 0x00000000,
|
||||
/*030e*/ 0x00000000,
|
||||
/*030f*/ 0x00050002,
|
||||
/*0310*/ 0x015c0057,
|
||||
/*0311*/ 0x01000100,
|
||||
/*0312*/ 0x01020001,
|
||||
/*0313*/ 0x00010300,
|
||||
/*0314*/ 0x05000104,
|
||||
/*0315*/ 0x01060001,
|
||||
/*0316*/ 0x00010700,
|
||||
/*0317*/ 0x00000000,
|
||||
/*0318*/ 0x00000000,
|
||||
/*0319*/ 0x00000001,
|
||||
/*031a*/ 0x00000000,
|
||||
/*031b*/ 0x00000000,
|
||||
/*031c*/ 0x00000000,
|
||||
/*031d*/ 0x20080101
|
||||
};
|
||||
Reference in New Issue
Block a user