GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

2026-09-06 03:52:57 +08:00
commit b1928b41c0
21813 changed files with 4413081 additions and 0 deletions
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+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "cpg_registers.h"
+#include "rcar_def.h"
+#include "rcar_private.h"
+#include "rpc_registers.h"
+
+#define MSTPSR9_RPC_BIT		(0x00020000U)
+#define RPC_CMNCR_MD_BIT	(0x80000000U)
+#define RPC_PHYCNT_CAL		BIT(31)
+#define RPC_PHYCNT_STRTIM_M3V1	(0x6 << 15UL)
+#define RPC_PHYCNT_STRTIM	(0x7 << 15UL)
+
+static void rpc_enable(void)
+{
+	/* Enable clock supply to RPC. */
+	mstpcr_write(CPG_SMSTPCR9, CPG_MSTPSR9, MSTPSR9_RPC_BIT);
+}
+
+static void rpc_setup(void)
+{
+	uint32_t product, cut, reg, phy_strtim;
+
+	if (mmio_read_32(RPC_CMNCR) & RPC_CMNCR_MD_BIT)
+		mmio_clrbits_32(RPC_CMNCR, RPC_CMNCR_MD_BIT);
+
+	product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
+	cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
+
+	if ((product ==  PRR_PRODUCT_M3) && (cut < PRR_PRODUCT_30))
+		phy_strtim = RPC_PHYCNT_STRTIM_M3V1;
+	else
+		phy_strtim = RPC_PHYCNT_STRTIM;
+
+	reg = mmio_read_32(RPC_PHYCNT);
+	reg &= ~RPC_PHYCNT_STRTIM;
+	reg |= phy_strtim;
+	mmio_write_32(RPC_PHYCNT, reg);
+	reg |= RPC_PHYCNT_CAL;
+	mmio_write_32(RPC_PHYCNT, reg);
+}
+
+void rcar_rpc_init(void)
+{
+	rpc_enable();
+	rpc_setup();
+}
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RPC_REGISTERS_H
+#define RPC_REGISTERS_H
+
+#define RPC_BASE	(0xEE200000U)
+#define RPC_CMNCR	(RPC_BASE + 0x0000U)
+#define RPC_SSLDR	(RPC_BASE + 0x0004U)
+#define RPC_DRCR	(RPC_BASE + 0x000CU)
+#define RPC_DRCMR	(RPC_BASE + 0x0010U)
+#define RPC_DRENR	(RPC_BASE + 0x001CU)
+#define RPC_SMCR	(RPC_BASE + 0x0020U)
+#define RPC_SMCMR	(RPC_BASE + 0x0024U)
+#define RPC_SMENR	(RPC_BASE + 0x0030U)
+#define RPC_CMNSR	(RPC_BASE + 0x0048U)
+#define RPC_DRDMCR	(RPC_BASE + 0x0058U)
+#define RPC_DRDRENR	(RPC_BASE + 0x005CU)
+#define RPC_PHYCNT	(RPC_BASE + 0x007CU)
+#define RPC_PHYINT	(RPC_BASE + 0x0088U)
+
+#endif /* RPC_REGISTERS_H */