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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
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source/trusted-firmware/trusted-firmware-a-2.8/drivers/st/crypto/stm32_hash.c
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/*
* Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <errno.h>
#include <stdint.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/clk.h>
#include <drivers/delay_timer.h>
#include <drivers/st/stm32_hash.h>
#include <drivers/st/stm32mp_reset.h>
#include <lib/mmio.h>
#include <lib/utils.h>
#include <libfdt.h>
#include <plat/common/platform.h>
#include <platform_def.h>
#if STM32_HASH_VER == 2
#define DT_HASH_COMPAT "st,stm32f756-hash"
#endif
#if STM32_HASH_VER == 4
#define DT_HASH_COMPAT "st,stm32mp13-hash"
#endif
#define HASH_CR 0x00U
#define HASH_DIN 0x04U
#define HASH_STR 0x08U
#define HASH_SR 0x24U
#define HASH_HREG(x) (0x310U + ((x) * 0x04U))
/* Control Register */
#define HASH_CR_INIT BIT(2)
#define HASH_CR_DATATYPE_SHIFT U(4)
#if STM32_HASH_VER == 2
#define HASH_CR_ALGO_SHA1 0x0U
#define HASH_CR_ALGO_MD5 BIT(7)
#define HASH_CR_ALGO_SHA224 BIT(18)
#define HASH_CR_ALGO_SHA256 (BIT(18) | BIT(7))
#endif
#if STM32_HASH_VER == 4
#define HASH_CR_ALGO_SHIFT U(17)
#define HASH_CR_ALGO_SHA1 (0x0U << HASH_CR_ALGO_SHIFT)
#define HASH_CR_ALGO_SHA224 (0x2U << HASH_CR_ALGO_SHIFT)
#define HASH_CR_ALGO_SHA256 (0x3U << HASH_CR_ALGO_SHIFT)
#define HASH_CR_ALGO_SHA384 (0xCU << HASH_CR_ALGO_SHIFT)
#define HASH_CR_ALGO_SHA512_224 (0xDU << HASH_CR_ALGO_SHIFT)
#define HASH_CR_ALGO_SHA512_256 (0xEU << HASH_CR_ALGO_SHIFT)
#define HASH_CR_ALGO_SHA512 (0xFU << HASH_CR_ALGO_SHIFT)
#endif
/* Status Flags */
#define HASH_SR_DCIS BIT(1)
#define HASH_SR_BUSY BIT(3)
/* STR Register */
#define HASH_STR_NBLW_MASK GENMASK(4, 0)
#define HASH_STR_DCAL BIT(8)
#define MD5_DIGEST_SIZE 16U
#define SHA1_DIGEST_SIZE 20U
#define SHA224_DIGEST_SIZE 28U
#define SHA256_DIGEST_SIZE 32U
#define SHA384_DIGEST_SIZE 48U
#define SHA512_224_DIGEST_SIZE 28U
#define SHA512_256_DIGEST_SIZE 32U
#define SHA512_DIGEST_SIZE 64U
#define RESET_TIMEOUT_US_1MS 1000U
#define HASH_TIMEOUT_US 10000U
enum stm32_hash_data_format {
HASH_DATA_32_BITS,
HASH_DATA_16_BITS,
HASH_DATA_8_BITS,
HASH_DATA_1_BIT
};
struct stm32_hash_instance {
uintptr_t base;
unsigned int clock;
size_t digest_size;
};
struct stm32_hash_remain {
uint32_t buffer;
size_t length;
};
/* Expect a single HASH peripheral */
static struct stm32_hash_instance stm32_hash;
static struct stm32_hash_remain stm32_remain;
static uintptr_t hash_base(void)
{
return stm32_hash.base;
}
static int hash_wait_busy(void)
{
uint64_t timeout = timeout_init_us(HASH_TIMEOUT_US);
while ((mmio_read_32(hash_base() + HASH_SR) & HASH_SR_BUSY) != 0U) {
if (timeout_elapsed(timeout)) {
ERROR("%s: busy timeout\n", __func__);
return -ETIMEDOUT;
}
}
return 0;
}
static int hash_wait_computation(void)
{
uint64_t timeout = timeout_init_us(HASH_TIMEOUT_US);
while ((mmio_read_32(hash_base() + HASH_SR) & HASH_SR_DCIS) == 0U) {
if (timeout_elapsed(timeout)) {
ERROR("%s: busy timeout\n", __func__);
return -ETIMEDOUT;
}
}
return 0;
}
static int hash_write_data(uint32_t data)
{
int ret;
ret = hash_wait_busy();
if (ret != 0) {
return ret;
}
mmio_write_32(hash_base() + HASH_DIN, data);
return 0;
}
static void hash_hw_init(enum stm32_hash_algo_mode mode)
{
uint32_t reg;
reg = HASH_CR_INIT | (HASH_DATA_8_BITS << HASH_CR_DATATYPE_SHIFT);
switch (mode) {
#if STM32_HASH_VER == 2
case HASH_MD5SUM:
reg |= HASH_CR_ALGO_MD5;
stm32_hash.digest_size = MD5_DIGEST_SIZE;
break;
#endif
case HASH_SHA1:
reg |= HASH_CR_ALGO_SHA1;
stm32_hash.digest_size = SHA1_DIGEST_SIZE;
break;
case HASH_SHA224:
reg |= HASH_CR_ALGO_SHA224;
stm32_hash.digest_size = SHA224_DIGEST_SIZE;
break;
#if STM32_HASH_VER == 4
case HASH_SHA384:
reg |= HASH_CR_ALGO_SHA384;
stm32_hash.digest_size = SHA384_DIGEST_SIZE;
break;
case HASH_SHA512:
reg |= HASH_CR_ALGO_SHA512;
stm32_hash.digest_size = SHA512_DIGEST_SIZE;
break;
#endif
/* Default selected algo is SHA256 */
case HASH_SHA256:
default:
reg |= HASH_CR_ALGO_SHA256;
stm32_hash.digest_size = SHA256_DIGEST_SIZE;
break;
}
mmio_write_32(hash_base() + HASH_CR, reg);
}
static int hash_get_digest(uint8_t *digest)
{
int ret;
uint32_t i;
uint32_t dsg;
ret = hash_wait_computation();
if (ret != 0) {
return ret;
}
for (i = 0U; i < (stm32_hash.digest_size / sizeof(uint32_t)); i++) {
dsg = __builtin_bswap32(mmio_read_32(hash_base() +
HASH_HREG(i)));
memcpy(digest + (i * sizeof(uint32_t)), &dsg, sizeof(uint32_t));
}
/*
* Clean hardware context as HASH could be used later
* by non-secure software
*/
hash_hw_init(HASH_SHA256);
return 0;
}
int stm32_hash_update(const uint8_t *buffer, size_t length)
{
size_t remain_length = length;
int ret = 0;
if ((length == 0U) || (buffer == NULL)) {
return 0;
}
clk_enable(stm32_hash.clock);
if (stm32_remain.length != 0U) {
uint32_t copysize;
copysize = MIN((sizeof(uint32_t) - stm32_remain.length),
length);
memcpy(((uint8_t *)&stm32_remain.buffer) + stm32_remain.length,
buffer, copysize);
remain_length -= copysize;
buffer += copysize;
if (stm32_remain.length == sizeof(uint32_t)) {
ret = hash_write_data(stm32_remain.buffer);
if (ret != 0) {
goto exit;
}
zeromem(&stm32_remain, sizeof(stm32_remain));
}
}
while (remain_length / sizeof(uint32_t) != 0U) {
uint32_t tmp_buf;
memcpy(&tmp_buf, buffer, sizeof(uint32_t));
ret = hash_write_data(tmp_buf);
if (ret != 0) {
goto exit;
}
buffer += sizeof(uint32_t);
remain_length -= sizeof(uint32_t);
}
if (remain_length != 0U) {
assert(stm32_remain.length == 0U);
memcpy((uint8_t *)&stm32_remain.buffer, buffer, remain_length);
stm32_remain.length = remain_length;
}
exit:
clk_disable(stm32_hash.clock);
return ret;
}
int stm32_hash_final(uint8_t *digest)
{
int ret;
clk_enable(stm32_hash.clock);
if (stm32_remain.length != 0U) {
ret = hash_write_data(stm32_remain.buffer);
if (ret != 0) {
clk_disable(stm32_hash.clock);
return ret;
}
mmio_clrsetbits_32(hash_base() + HASH_STR, HASH_STR_NBLW_MASK,
8U * stm32_remain.length);
zeromem(&stm32_remain, sizeof(stm32_remain));
} else {
mmio_clrbits_32(hash_base() + HASH_STR, HASH_STR_NBLW_MASK);
}
mmio_setbits_32(hash_base() + HASH_STR, HASH_STR_DCAL);
ret = hash_get_digest(digest);
clk_disable(stm32_hash.clock);
return ret;
}
int stm32_hash_final_update(const uint8_t *buffer, uint32_t length,
uint8_t *digest)
{
int ret;
ret = stm32_hash_update(buffer, length);
if (ret != 0) {
return ret;
}
return stm32_hash_final(digest);
}
void stm32_hash_init(enum stm32_hash_algo_mode mode)
{
clk_enable(stm32_hash.clock);
hash_hw_init(mode);
clk_disable(stm32_hash.clock);
zeromem(&stm32_remain, sizeof(stm32_remain));
}
int stm32_hash_register(void)
{
struct dt_node_info hash_info;
int node;
for (node = dt_get_node(&hash_info, -1, DT_HASH_COMPAT);
node != -FDT_ERR_NOTFOUND;
node = dt_get_node(&hash_info, node, DT_HASH_COMPAT)) {
if (hash_info.status != DT_DISABLED) {
break;
}
}
if (node == -FDT_ERR_NOTFOUND) {
return -ENODEV;
}
if (hash_info.clock < 0) {
return -EINVAL;
}
stm32_hash.base = hash_info.base;
stm32_hash.clock = hash_info.clock;
clk_enable(stm32_hash.clock);
if (hash_info.reset >= 0) {
uint32_t id = (uint32_t)hash_info.reset;
if (stm32mp_reset_assert(id, RESET_TIMEOUT_US_1MS) != 0) {
panic();
}
udelay(20);
if (stm32mp_reset_deassert(id, RESET_TIMEOUT_US_1MS) != 0) {
panic();
}
}
clk_disable(stm32_hash.clock);
return 0;
}
source/trusted-firmware/trusted-firmware-a-2.8/drivers/st/crypto/stm32_pka.c
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/*
* Copyright (c) 2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <errno.h>
#include <stdint.h>
#include <drivers/clk.h>
#include <drivers/delay_timer.h>
#include <drivers/st/stm32_pka.h>
#include <drivers/st/stm32mp_reset.h>
#include <lib/mmio.h>
#include <lib/utils.h>
#include <libfdt.h>
#include <plat/common/platform.h>
#include <platform_def.h>
/*
* For our comprehension in this file
* _len are in BITs
* _size are in BYTEs
* _nbw are in number of PKA_word (PKA_word = u64)
*/
#define UINT8_LEN 8U
#define UINT64_LEN (UINT8_LEN * sizeof(uint64_t))
#define WORD_SIZE (sizeof(uint64_t))
#define OP_NBW_FROM_LEN(len) (DIV_ROUND_UP_2EVAL((len), UINT64_LEN) + 1)
#define OP_NBW_FROM_SIZE(s) OP_NBW_FROM_LEN((s) * UINT8_LEN)
#define OP_SIZE_FROM_SIZE(s) (OP_NBW_FROM_SIZE(s) * WORD_SIZE)
#define DT_PKA_COMPAT "st,stm32-pka64"
#define MAX_ECC_SIZE_LEN 640U
#define MAX_EO_NBW OP_NBW_FROM_LEN(MAX_ECC_SIZE_LEN)
/* PKA registers */
/* PKA control register */
#define _PKA_CR 0x0U
/* PKA status register */
#define _PKA_SR 0x4U
/* PKA clear flag register */
#define _PKA_CLRFR 0x8U
/* PKA version register */
#define _PKA_VERR 0x1FF4U
/* PKA identification register */
#define _PKA_IPIDR 0x1FF8U
/* PKA control register fields */
#define _PKA_CR_MODE_MASK GENMASK(13, 8)
#define _PKA_CR_MODE_SHIFT 8U
#define _PKA_CR_MODE_ADD 0x9U
#define _PKA_CR_MODE_ECDSA_VERIF 0x26U
#define _PKA_CR_START BIT(1)
#define _PKA_CR_EN BIT(0)
/* PKA status register fields */
#define _PKA_SR_BUSY BIT(16)
#define _PKA_SR_LMF BIT(1)
#define _PKA_SR_INITOK BIT(0)
/* PKA it flag fields (used in CR, SR and CLRFR) */
#define _PKA_IT_MASK (GENMASK(21, 19) | BIT(17))
#define _PKA_IT_SHIFT 17U
#define _PKA_IT_OPERR BIT(21)
#define _PKA_IT_ADDRERR BIT(20)
#define _PKA_IT_RAMERR BIT(19)
#define _PKA_IT_PROCEND BIT(17)
/* PKA version register fields */
#define _PKA_VERR_MAJREV_MASK GENMASK(7, 4)
#define _PKA_VERR_MAJREV_SHIFT 4U
#define _PKA_VERR_MINREV_MASK GENMASK(3, 0)
#define _PKA_VERR_MINREV_SHIFT 0U
/* RAM magic offset */
#define _PKA_RAM_START 0x400U
#define _PKA_RAM_SIZE 5336U
/* ECDSA verification */
#define _PKA_RAM_N_LEN 0x408U /* 64 */
#define _PKA_RAM_P_LEN 0x4C8U /* 64 */
#define _PKA_RAM_A_SIGN 0x468U /* 64 */
#define _PKA_RAM_A 0x470U /* EOS */
#define _PKA_RAM_P 0x4D0U /* EOS */
#define _PKA_RAM_XG 0x678U /* EOS */
#define _PKA_RAM_YG 0x6D0U /* EOS */
#define _PKA_RAM_XQ 0x12F8U /* EOS */
#define _PKA_RAM_YQ 0x1350U /* EOS */
#define _PKA_RAM_SIGN_R 0x10E0U /* EOS */
#define _PKA_RAM_SIGN_S 0xC68U /* EOS */
#define _PKA_RAM_HASH_Z 0x13A8U /* EOS */
#define _PKA_RAM_PRIME_N 0x1088U /* EOS */
#define _PKA_RAM_ECDSA_VERIFY 0x5D0U /* 64 */
#define _PKA_RAM_ECDSA_VERIFY_VALID 0xD60DULL
#define _PKA_RAM_ECDSA_VERIFY_INVALID 0xA3B7ULL
#define PKA_TIMEOUT_US 1000000U
#define TIMEOUT_US_1MS 1000U
#define PKA_RESET_DELAY 20U
struct curve_parameters {
uint32_t a_sign; /* 0 positive, 1 negative */
uint8_t *a; /* Curve coefficient |a| */
size_t a_size;
uint8_t *p; /* Curve modulus value */
uint32_t p_len;
uint8_t *xg; /* Curve base point G coordinate x */
size_t xg_size;
uint8_t *yg; /* Curve base point G coordinate y */
size_t yg_size;
uint8_t *n; /* Curve prime order n */
uint32_t n_len;
};
static const struct curve_parameters curve_def[] = {
#if PKA_USE_NIST_P256
[PKA_NIST_P256] = {
.p_len = 256U,
.n_len = 256U,
.p = (uint8_t[]){0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x01,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF},
.n = (uint8_t[]){0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xBC, 0xE6, 0xFA, 0xAD, 0xA7, 0x17, 0x9E, 0x84,
0xF3, 0xB9, 0xCA, 0xC2, 0xFC, 0x63, 0x25, 0x51},
.a_sign = 1U,
.a = (uint8_t[]){0x03},
.a_size = 1U,
.xg = (uint8_t[]){0x6B, 0x17, 0xD1, 0xF2, 0xE1, 0x2C, 0x42, 0x47,
0xF8, 0xBC, 0xE6, 0xE5, 0x63, 0xA4, 0x40, 0xF2,
0x77, 0x03, 0x7D, 0x81, 0x2D, 0xEB, 0x33, 0xA0,
0xF4, 0xA1, 0x39, 0x45, 0xD8, 0x98, 0xC2, 0x96},
.xg_size = 32U,
.yg = (uint8_t[]){0x4F, 0xE3, 0x42, 0xE2, 0xFE, 0x1A, 0x7F, 0x9B,
0x8E, 0xE7, 0xEB, 0x4A, 0x7C, 0x0F, 0x9E, 0x16,
0x2B, 0xCE, 0x33, 0x57, 0x6B, 0x31, 0x5E, 0xCE,
0xCB, 0xB6, 0x40, 0x68, 0x37, 0xBF, 0x51, 0xF5},
.yg_size = 32U,
},
#endif
#if PKA_USE_BRAINPOOL_P256R1
[PKA_BRAINPOOL_P256R1] = {
.p_len = 256,
.n_len = 256,
.p = (uint8_t[]){0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC,
0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x72,
0x6E, 0x3B, 0xF6, 0x23, 0xD5, 0x26, 0x20, 0x28,
0x20, 0x13, 0x48, 0x1D, 0x1F, 0x6E, 0x53, 0x77},
.n = (uint8_t[]){0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC,
0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x71,
0x8C, 0x39, 0x7A, 0xA3, 0xB5, 0x61, 0xA6, 0xF7,
0x90, 0x1E, 0x0E, 0x82, 0x97, 0x48, 0x56, 0xA7},
.a = (uint8_t[]){0x7D, 0x5A, 0x09, 0x75, 0xFC, 0x2C, 0x30, 0x57,
0xEE, 0xF6, 0x75, 0x30, 0x41, 0x7A, 0xFF, 0xE7,
0xFB, 0x80, 0x55, 0xC1, 0x26, 0xDC, 0x5C, 0x6C,
0xE9, 0x4A, 0x4B, 0x44, 0xF3, 0x30, 0xB5, 0xD9},
.a_size = 32U,
.xg = (uint8_t[]){0x8B, 0xD2, 0xAE, 0xB9, 0xCB, 0x7E, 0x57, 0xCB,
0x2C, 0x4B, 0x48, 0x2F, 0xFC, 0x81, 0xB7, 0xAF,
0xB9, 0xDE, 0x27, 0xE1, 0xE3, 0xBD, 0x23, 0xC2,
0x3A, 0x44, 0x53, 0xBD, 0x9A, 0xCE, 0x32, 0x62},
.xg_size = 32U,
.yg = (uint8_t[]){0x54, 0x7E, 0xF8, 0x35, 0xC3, 0xDA, 0xC4, 0xFD,
0x97, 0xF8, 0x46, 0x1A, 0x14, 0x61, 0x1D, 0xC9,
0xC2, 0x77, 0x45, 0x13, 0x2D, 0xED, 0x8E, 0x54,
0x5C, 0x1D, 0x54, 0xC7, 0x2F, 0x04, 0x69, 0x97},
.yg_size = 32U,
},
#endif
#if PKA_USE_BRAINPOOL_P256T1
[PKA_BRAINPOOL_P256T1] = {
.p_len = 256,
.n_len = 256,
.p = (uint8_t[]){0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC,
0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x72,
0x6E, 0x3B, 0xF6, 0x23, 0xD5, 0x26, 0x20, 0x28,
0x20, 0x13, 0x48, 0x1D, 0x1F, 0x6E, 0x53, 0x77},
.n = (uint8_t[]){0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC,
0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x71,
0x8C, 0x39, 0x7A, 0xA3, 0xB5, 0x61, 0xA6, 0xF7,
0x90, 0x1E, 0x0E, 0x82, 0x97, 0x48, 0x56, 0xA7},
.a = (uint8_t[]){0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC,
0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x72,
0x6E, 0x3B, 0xF6, 0x23, 0xD5, 0x26, 0x20, 0x28,
0x20, 0x13, 0x48, 0x1D, 0x1F, 0x6E, 0x53, 0x74},
.a_size = 32U,
.xg = (uint8_t[]){0xA3, 0xE8, 0xEB, 0x3C, 0xC1, 0xCF, 0xE7, 0xB7,
0x73, 0x22, 0x13, 0xB2, 0x3A, 0x65, 0x61, 0x49,
0xAF, 0xA1, 0x42, 0xC4, 0x7A, 0xAF, 0xBC, 0x2B,
0x79, 0xA1, 0x91, 0x56, 0x2E, 0x13, 0x05, 0xF4},
.xg_size = 32U,
.yg = (uint8_t[]){0x2D, 0x99, 0x6C, 0x82, 0x34, 0x39, 0xC5, 0x6D,
0x7F, 0x7B, 0x22, 0xE1, 0x46, 0x44, 0x41, 0x7E,
0x69, 0xBC, 0xB6, 0xDE, 0x39, 0xD0, 0x27, 0x00,
0x1D, 0xAB, 0xE8, 0xF3, 0x5B, 0x25, 0xC9, 0xBE},
.yg_size = 32U,
},
#endif
#if PKA_USE_NIST_P521
[PKA_NIST_P521] = {
.p_len = 521,
.n_len = 521,
.p = (uint8_t[]){ 0x01, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
.n = (uint8_t[]){ 0x01, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa,
0x51, 0x86, 0x87, 0x83, 0xbf, 0x2f, 0x96, 0x6b,
0x7f, 0xcc, 0x01, 0x48, 0xf7, 0x09, 0xa5, 0xd0,
0x3b, 0xb5, 0xc9, 0xb8, 0x89, 0x9c, 0x47, 0xae,
0xbb, 0x6f, 0xb7, 0x1e, 0x91, 0x38, 0x64, 0x09},
.a_sign = 1,
.a = (uint8_t[]){0x03},
.a_size = 1U,
.xg = (uint8_t[]){ 0xc6,
0x85, 0x8e, 0x06, 0xb7, 0x04, 0x04, 0xe9, 0xcd,
0x9e, 0x3e, 0xcb, 0x66, 0x23, 0x95, 0xb4, 0x42,
0x9c, 0x64, 0x81, 0x39, 0x05, 0x3f, 0xb5, 0x21,
0xf8, 0x28, 0xaf, 0x60, 0x6b, 0x4d, 0x3d, 0xba,
0xa1, 0x4b, 0x5e, 0x77, 0xef, 0xe7, 0x59, 0x28,
0xfe, 0x1d, 0xc1, 0x27, 0xa2, 0xff, 0xa8, 0xde,
0x33, 0x48, 0xb3, 0xc1, 0x85, 0x6a, 0x42, 0x9b,
0xf9, 0x7e, 0x7e, 0x31, 0xc2, 0xe5, 0xbd, 0x66},
.xg_size = 65U,
.yg = (uint8_t[]){ 0x01, 0x18,
0x39, 0x29, 0x6a, 0x78, 0x9a, 0x3b, 0xc0, 0x04,
0x5c, 0x8a, 0x5f, 0xb4, 0x2c, 0x7d, 0x1b, 0xd9,
0x98, 0xf5, 0x44, 0x49, 0x57, 0x9b, 0x44, 0x68,
0x17, 0xaf, 0xbd, 0x17, 0x27, 0x3e, 0x66, 0x2c,
0x97, 0xee, 0x72, 0x99, 0x5e, 0xf4, 0x26, 0x40,
0xc5, 0x50, 0xb9, 0x01, 0x3f, 0xad, 0x07, 0x61,
0x35, 0x3c, 0x70, 0x86, 0xa2, 0x72, 0xc2, 0x40,
0x88, 0xbe, 0x94, 0x76, 0x9f, 0xd1, 0x66, 0x50},
.yg_size = 66U,
},
#endif
};
static struct stm32_pka_platdata pka_pdata;
#pragma weak stm32_pka_get_platdata
int stm32_pka_get_platdata(struct stm32_pka_platdata *pdata)
{
return -ENODEV;
}
static int stm32_pka_parse_fdt(void)
{
int node;
struct dt_node_info info;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return -FDT_ERR_NOTFOUND;
}
node = dt_get_node(&info, -1, DT_PKA_COMPAT);
if (node < 0) {
ERROR("No PKA entry in DT\n");
return -FDT_ERR_NOTFOUND;
}
if (info.status == DT_DISABLED) {
return -FDT_ERR_NOTFOUND;
}
if ((info.base == 0) || (info.clock < 0) || (info.reset < 0)) {
return -FDT_ERR_BADVALUE;
}
pka_pdata.base = (uintptr_t)info.base;
pka_pdata.clock_id = (unsigned long)info.clock;
pka_pdata.reset_id = (unsigned int)info.reset;
return 0;
}
static int pka_wait_bit(uintptr_t base, uint32_t bit)
{
uint64_t timeout = timeout_init_us(PKA_TIMEOUT_US);
while ((mmio_read_32(base + _PKA_SR) & bit) != bit) {
if (timeout_elapsed(timeout)) {
WARN("timeout waiting %x\n", bit);
return -ETIMEDOUT;
}
}
return 0;
}
static void pka_disable(uintptr_t base)
{
mmio_clrbits_32(base + _PKA_CR, _PKA_CR_EN);
}
static int pka_enable(uintptr_t base, uint32_t mode)
{
/* Set mode and disable interrupts */
mmio_clrsetbits_32(base + _PKA_CR, _PKA_IT_MASK | _PKA_CR_MODE_MASK,
_PKA_CR_MODE_MASK & (mode << _PKA_CR_MODE_SHIFT));
mmio_setbits_32(base + _PKA_CR, _PKA_CR_EN);
return pka_wait_bit(base, _PKA_SR_INITOK);
}
/*
* Data are already loaded in PKA internal RAM
* MODE is set
* We start process, and wait for its end.
*/
static int stm32_pka_process(uintptr_t base)
{
mmio_setbits_32(base + _PKA_CR, _PKA_CR_START);
return pka_wait_bit(base, _PKA_IT_PROCEND);
}
/**
* @brief Write ECC operand to PKA RAM.
* @note PKA expect to write u64 word, each u64 are: the least significant bit is
* bit 0; the most significant bit is bit 63.
* We write eo_nbw (ECC operand Size) u64, value that depends of the chosen
* prime modulus length in bits.
* First less signicant u64 is written to low address
* Most significant u64 to higher address.
* And at last address we write a u64(0x0)
* @note This function doesn't only manage endianness (as bswap64 do), but also
* complete most significant incomplete u64 with 0 (if data is not a u64
* multiple), and fill u64 last address with 0.
* @param addr: PKA_RAM address to write the buffer 'data'
* @param data: is a BYTE list with most significant bytes first
* @param data_size: nb of byte in data
* @param eo_nbw: is ECC Operand size in 64bits word (including the extra 0)
* (note it depends of the prime modulus length, not the data size)
* @retval 0 if OK.
* -EINVAL if data_size and eo_nbw are inconsistent, ie data doesn't
* fit in defined eo_nbw, or eo_nbw bigger than hardware limit.
*/
static int write_eo_data(uintptr_t addr, uint8_t *data, unsigned int data_size,
unsigned int eo_nbw)
{
uint32_t word_index;
int data_index;
if ((eo_nbw < OP_NBW_FROM_SIZE(data_size)) || (eo_nbw > MAX_EO_NBW)) {
return -EINVAL;
}
/* Fill value */
data_index = (int)data_size - 1;
for (word_index = 0U; word_index < eo_nbw; word_index++) {
uint64_t tmp = 0ULL;
unsigned int i = 0U; /* index in the tmp U64 word */
/* Stop if end of tmp or end of data */
while ((i < sizeof(tmp)) && (data_index >= 0)) {
tmp |= (uint64_t)(data[data_index]) << (UINT8_LEN * i);
i++; /* Move byte index in current (u64)tmp */
data_index--; /* Move to just next most significat byte */
}
mmio_write_64(addr + word_index * sizeof(tmp), tmp);
}
return 0;
}
static unsigned int get_ecc_op_nbword(enum stm32_pka_ecdsa_curve_id cid)
{
if (cid >= ARRAY_SIZE(curve_def)) {
ERROR("CID %u is out of boundaries\n", cid);
panic();
}
return OP_NBW_FROM_LEN(curve_def[cid].n_len);
}
static int stm32_pka_ecdsa_verif_configure_curve(uintptr_t base, enum stm32_pka_ecdsa_curve_id cid)
{
int ret;
unsigned int eo_nbw = get_ecc_op_nbword(cid);
mmio_write_64(base + _PKA_RAM_N_LEN, curve_def[cid].n_len);
mmio_write_64(base + _PKA_RAM_P_LEN, curve_def[cid].p_len);
mmio_write_64(base + _PKA_RAM_A_SIGN, curve_def[cid].a_sign);
ret = write_eo_data(base + _PKA_RAM_A, curve_def[cid].a, curve_def[cid].a_size, eo_nbw);
if (ret < 0) {
return ret;
}
ret = write_eo_data(base + _PKA_RAM_PRIME_N,
curve_def[cid].n, div_round_up(curve_def[cid].n_len, UINT8_LEN),
eo_nbw);
if (ret < 0) {
return ret;
}
ret = write_eo_data(base + _PKA_RAM_P, curve_def[cid].p,
div_round_up(curve_def[cid].p_len, UINT8_LEN), eo_nbw);
if (ret < 0) {
return ret;
}
ret = write_eo_data(base + _PKA_RAM_XG, curve_def[cid].xg, curve_def[cid].xg_size, eo_nbw);
if (ret < 0) {
return ret;
}
ret = write_eo_data(base + _PKA_RAM_YG, curve_def[cid].yg, curve_def[cid].yg_size, eo_nbw);
if (ret < 0) {
return ret;
}
return 0;
}
static int stm32_pka_ecdsa_verif_check_return(uintptr_t base)
{
uint64_t value;
uint32_t sr;
sr = mmio_read_32(base + _PKA_SR);
if ((sr & (_PKA_IT_OPERR | _PKA_IT_ADDRERR | _PKA_IT_RAMERR)) != 0) {
WARN("Detected error(s): %s%s%s\n",
(sr & _PKA_IT_OPERR) ? "Operation " : "",
(sr & _PKA_IT_ADDRERR) ? "Address " : "",
(sr & _PKA_IT_RAMERR) ? "RAM" : "");
return -EINVAL;
}
value = mmio_read_64(base + _PKA_RAM_ECDSA_VERIFY);
if (value == _PKA_RAM_ECDSA_VERIFY_VALID) {
return 0;
}
if (value == _PKA_RAM_ECDSA_VERIFY_INVALID) {
return -EAUTH;
}
return -EINVAL;
}
/**
* @brief Check if BigInt stored in data is 0
*
* @param data: a BYTE array with most significant bytes first
* @param size: data size
*
* @retval: true: if data represents a 0 value (ie all bytes == 0)
* false: if data represents a non-zero value.
*/
static bool is_zero(uint8_t *data, unsigned int size)
{
unsigned int i;
for (i = 0U; i < size; i++) {
if (data[i] != 0U) {
return false;
}
}
return true;
}
/**
* @brief Compare two BigInt:
* @param xdata_a: a BYTE array with most significant bytes first
* @param size_a: nb of Byte of 'a'
* @param data_b: a BYTE array with most significant bytes first
* @param size_b: nb of Byte of 'b'
*
* @retval: true if data_a < data_b
* false if data_a >= data_b
*/
static bool is_smaller(uint8_t *data_a, unsigned int size_a,
uint8_t *data_b, unsigned int size_b)
{
unsigned int i;
i = MAX(size_a, size_b) + 1U;
do {
uint8_t a, b;
i--;
if (size_a < i) {
a = 0U;
} else {
a = data_a[size_a - i];
}
if (size_b < i) {
b = 0U;
} else {
b = data_b[size_b - i];
}
if (a < b) {
return true;
}
if (a > b) {
return false;
}
} while (i != 0U);
return false;
}
static int stm32_pka_ecdsa_check_param(void *sig_r_ptr, unsigned int sig_r_size,
void *sig_s_ptr, unsigned int sig_s_size,
void *pk_x_ptr, unsigned int pk_x_size,
void *pk_y_ptr, unsigned int pk_y_size,
enum stm32_pka_ecdsa_curve_id cid)
{
/* Public Key check */
/* Check Xq < p */
if (!is_smaller(pk_x_ptr, pk_x_size,
curve_def[cid].p, div_round_up(curve_def[cid].p_len, UINT8_LEN))) {
WARN("%s Xq < p inval\n", __func__);
return -EINVAL;
}
/* Check Yq < p */
if (!is_smaller(pk_y_ptr, pk_y_size,
curve_def[cid].p, div_round_up(curve_def[cid].p_len, UINT8_LEN))) {
WARN("%s Yq < p inval\n", __func__);
return -EINVAL;
}
/* Signature check */
/* Check 0 < r < n */
if (!is_smaller(sig_r_ptr, sig_r_size,
curve_def[cid].n, div_round_up(curve_def[cid].n_len, UINT8_LEN)) &&
!is_zero(sig_r_ptr, sig_r_size)) {
WARN("%s 0< r < n inval\n", __func__);
return -EINVAL;
}
/* Check 0 < s < n */
if (!is_smaller(sig_s_ptr, sig_s_size,
curve_def[cid].n, div_round_up(curve_def[cid].n_len, UINT8_LEN)) &&
!is_zero(sig_s_ptr, sig_s_size)) {
WARN("%s 0< s < n inval\n", __func__);
return -EINVAL;
}
return 0;
}
/*
* @brief Initialize the PKA driver.
* @param None.
* @retval 0 if OK, negative value else.
*/
int stm32_pka_init(void)
{
int err;
#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
uint32_t ver;
uint32_t id;
#endif
err = stm32_pka_parse_fdt();
if (err != 0) {
err = stm32_pka_get_platdata(&pka_pdata);
if (err != 0) {
return err;
}
}
clk_enable(pka_pdata.clock_id);
if (stm32mp_reset_assert((unsigned long)pka_pdata.reset_id, TIMEOUT_US_1MS) != 0) {
panic();
}
udelay(PKA_RESET_DELAY);
if (stm32mp_reset_deassert((unsigned long)pka_pdata.reset_id, TIMEOUT_US_1MS) != 0) {
panic();
}
#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
id = mmio_read_32(pka_pdata.base + _PKA_IPIDR);
ver = mmio_read_32(pka_pdata.base + _PKA_VERR);
VERBOSE("STM32 PKA[%x] V%u.%u\n", id,
(ver & _PKA_VERR_MAJREV_MASK) >> _PKA_VERR_MAJREV_SHIFT,
(ver & _PKA_VERR_MINREV_MASK) >> _PKA_VERR_MINREV_SHIFT);
#endif
return 0;
}
int stm32_pka_ecdsa_verif(void *hash, unsigned int hash_size,
void *sig_r_ptr, unsigned int sig_r_size,
void *sig_s_ptr, unsigned int sig_s_size,
void *pk_x_ptr, unsigned int pk_x_size,
void *pk_y_ptr, unsigned int pk_y_size,
enum stm32_pka_ecdsa_curve_id cid)
{
int ret;
uintptr_t base = pka_pdata.base;
unsigned int eo_nbw = get_ecc_op_nbword(cid);
if ((hash == NULL) || (sig_r_ptr == NULL) || (sig_s_ptr == NULL) ||
(pk_x_ptr == NULL) || (pk_y_ptr == NULL)) {
INFO("%s invalid input param\n", __func__);
return -EINVAL;
}
ret = stm32_pka_ecdsa_check_param(sig_r_ptr, sig_r_size,
sig_s_ptr, sig_s_size,
pk_x_ptr, pk_x_size,
pk_y_ptr, pk_y_size,
cid);
if (ret < 0) {
INFO("%s check param error %d\n", __func__, ret);
goto out;
}
if ((mmio_read_32(base + _PKA_SR) & _PKA_SR_BUSY) == _PKA_SR_BUSY) {
INFO("%s busy\n", __func__);
ret = -EBUSY;
goto out;
}
/* Fill PKA RAM */
/* With curve id values */
ret = stm32_pka_ecdsa_verif_configure_curve(base, cid);
if (ret < 0) {
goto out;
}
/* With pubkey */
ret = write_eo_data(base + _PKA_RAM_XQ, pk_x_ptr, pk_x_size, eo_nbw);
if (ret < 0) {
goto out;
}
ret = write_eo_data(base + _PKA_RAM_YQ, pk_y_ptr, pk_y_size, eo_nbw);
if (ret < 0) {
goto out;
}
/* With hash */
ret = write_eo_data(base + _PKA_RAM_HASH_Z, hash, hash_size, eo_nbw);
if (ret < 0) {
goto out;
}
/* With signature */
ret = write_eo_data(base + _PKA_RAM_SIGN_R, sig_r_ptr, sig_r_size, eo_nbw);
if (ret < 0) {
goto out;
}
ret = write_eo_data(base + _PKA_RAM_SIGN_S, sig_s_ptr, sig_s_size, eo_nbw);
if (ret < 0) {
goto out;
}
/* Set mode to ecdsa signature verification */
ret = pka_enable(base, _PKA_CR_MODE_ECDSA_VERIF);
if (ret < 0) {
WARN("%s set mode pka error %d\n", __func__, ret);
goto out;
}
/* Start processing and wait end */
ret = stm32_pka_process(base);
if (ret < 0) {
WARN("%s process error %d\n", __func__, ret);
goto out;
}
/* Check return status */
ret = stm32_pka_ecdsa_verif_check_return(base);
/* Unset end proc */
mmio_setbits_32(base + _PKA_CLRFR, _PKA_IT_PROCEND);
out:
/* Disable PKA (will stop all pending proccess and reset RAM) */
pka_disable(base);
return ret;
}
source/trusted-firmware/trusted-firmware-a-2.8/drivers/st/crypto/stm32_rng.c
+269
View File
@@ -0,0 +1,269 @@
/*
* Copyright (c) 2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <errno.h>
#include <stdbool.h>
#include <arch_helpers.h>
#include <drivers/clk.h>
#include <drivers/delay_timer.h>
#include <drivers/st/stm32_rng.h>
#include <drivers/st/stm32mp_reset.h>
#include <lib/mmio.h>
#include <libfdt.h>
#include <platform_def.h>
#if STM32_RNG_VER == 2
#define DT_RNG_COMPAT "st,stm32-rng"
#endif
#if STM32_RNG_VER == 4
#define DT_RNG_COMPAT "st,stm32mp13-rng"
#endif
#define RNG_CR 0x00U
#define RNG_SR 0x04U
#define RNG_DR 0x08U
#define RNG_CR_RNGEN BIT(2)
#define RNG_CR_IE BIT(3)
#define RNG_CR_CED BIT(5)
#define RNG_CR_CLKDIV GENMASK(19, 16)
#define RNG_CR_CLKDIV_SHIFT 16U
#define RNG_CR_CONDRST BIT(30)
#define RNG_SR_DRDY BIT(0)
#define RNG_SR_CECS BIT(1)
#define RNG_SR_SECS BIT(2)
#define RNG_SR_CEIS BIT(5)
#define RNG_SR_SEIS BIT(6)
#define RNG_TIMEOUT_US 100000U
#define RNG_TIMEOUT_STEP_US 10U
#define TIMEOUT_US_1MS 1000U
#define RNG_NIST_CONFIG_A 0x00F40F00U
#define RNG_NIST_CONFIG_B 0x01801000U
#define RNG_NIST_CONFIG_C 0x00F00D00U
#define RNG_NIST_CONFIG_MASK GENMASK(25, 8)
#define RNG_MAX_NOISE_CLK_FREQ 48000000U
struct stm32_rng_instance {
uintptr_t base;
unsigned long clock;
};
static struct stm32_rng_instance stm32_rng;
static void seed_error_recovery(void)
{
uint8_t i __maybe_unused;
/* Recommended by the SoC reference manual */
mmio_clrbits_32(stm32_rng.base + RNG_SR, RNG_SR_SEIS);
dmbsy();
#if STM32_RNG_VER == 2
/* No Auto-reset on version 2, need to clean FIFO */
for (i = 12U; i != 0U; i--) {
(void)mmio_read_32(stm32_rng.base + RNG_DR);
}
dmbsy();
#endif
if ((mmio_read_32(stm32_rng.base + RNG_SR) & RNG_SR_SEIS) != 0U) {
ERROR("RNG noise\n");
panic();
}
}
static uint32_t stm32_rng_clock_freq_restrain(void)
{
unsigned long clock_rate;
uint32_t clock_div = 0U;
clock_rate = clk_get_rate(stm32_rng.clock);
/*
* Get the exponent to apply on the CLKDIV field in RNG_CR register
* No need to handle the case when clock-div > 0xF as it is physically
* impossible
*/
while ((clock_rate >> clock_div) > RNG_MAX_NOISE_CLK_FREQ) {
clock_div++;
}
VERBOSE("RNG clk rate : %lu\n", clk_get_rate(stm32_rng.clock) >> clock_div);
return clock_div;
}
static int stm32_rng_enable(void)
{
uint32_t sr;
uint64_t timeout;
uint32_t clock_div __maybe_unused;
#if STM32_RNG_VER == 2
mmio_write_32(stm32_rng.base + RNG_CR, RNG_CR_RNGEN | RNG_CR_CED);
#endif
#if STM32_RNG_VER == 4
/* Reset internal block and disable CED bit */
clock_div = stm32_rng_clock_freq_restrain();
/* Update configuration fields */
mmio_clrsetbits_32(stm32_rng.base + RNG_CR, RNG_NIST_CONFIG_MASK,
RNG_NIST_CONFIG_A | RNG_CR_CONDRST | RNG_CR_CED);
mmio_clrsetbits_32(stm32_rng.base + RNG_CR, RNG_CR_CLKDIV,
(clock_div << RNG_CR_CLKDIV_SHIFT));
mmio_clrsetbits_32(stm32_rng.base + RNG_CR, RNG_CR_CONDRST, RNG_CR_RNGEN);
#endif
timeout = timeout_init_us(RNG_TIMEOUT_US);
sr = mmio_read_32(stm32_rng.base + RNG_SR);
while ((sr & RNG_SR_DRDY) == 0U) {
if (timeout_elapsed(timeout)) {
WARN("Timeout waiting\n");
return -ETIMEDOUT;
}
if ((sr & (RNG_SR_SECS | RNG_SR_SEIS)) != 0U) {
seed_error_recovery();
timeout = timeout_init_us(RNG_TIMEOUT_US);
}
udelay(RNG_TIMEOUT_STEP_US);
sr = mmio_read_32(stm32_rng.base + RNG_SR);
}
VERBOSE("Init RNG done\n");
return 0;
}
/*
* stm32_rng_read - Read a number of random bytes from RNG
* out: pointer to the output buffer
* size: number of bytes to be read
* Return 0 on success, non-0 on failure
*/
int stm32_rng_read(uint8_t *out, uint32_t size)
{
uint8_t *buf = out;
size_t len = size;
int nb_tries;
uint32_t data32;
int rc = 0;
unsigned int count;
if (stm32_rng.base == 0U) {
return -EPERM;
}
while (len != 0U) {
nb_tries = RNG_TIMEOUT_US / RNG_TIMEOUT_STEP_US;
do {
uint32_t status = mmio_read_32(stm32_rng.base + RNG_SR);
if ((status & (RNG_SR_SECS | RNG_SR_SEIS)) != 0U) {
seed_error_recovery();
}
udelay(RNG_TIMEOUT_STEP_US);
nb_tries--;
if (nb_tries == 0) {
rc = -ETIMEDOUT;
goto bail;
}
} while ((mmio_read_32(stm32_rng.base + RNG_SR) &
RNG_SR_DRDY) == 0U);
count = 4U;
while (len != 0U) {
data32 = mmio_read_32(stm32_rng.base + RNG_DR);
count--;
memcpy(buf, &data32, MIN(len, sizeof(uint32_t)));
buf += MIN(len, sizeof(uint32_t));
len -= MIN(len, sizeof(uint32_t));
if (count == 0U) {
break;
}
}
}
bail:
if (rc != 0) {
memset(out, 0, buf - out);
}
return rc;
}
/*
* stm32_rng_init: Initialize rng from DT
* return 0 on success, negative value on failure
*/
int stm32_rng_init(void)
{
void *fdt;
struct dt_node_info dt_rng;
int node;
if (stm32_rng.base != 0U) {
/* Driver is already initialized */
return 0;
}
if (fdt_get_address(&fdt) == 0) {
panic();
}
node = dt_get_node(&dt_rng, -1, DT_RNG_COMPAT);
if (node < 0) {
return 0;
}
if (dt_rng.status == DT_DISABLED) {
return 0;
}
assert(dt_rng.base != 0U);
stm32_rng.base = dt_rng.base;
if (dt_rng.clock < 0) {
panic();
}
stm32_rng.clock = (unsigned long)dt_rng.clock;
clk_enable(stm32_rng.clock);
if (dt_rng.reset >= 0) {
int ret;
ret = stm32mp_reset_assert((unsigned long)dt_rng.reset,
TIMEOUT_US_1MS);
if (ret != 0) {
panic();
}
udelay(20);
ret = stm32mp_reset_deassert((unsigned long)dt_rng.reset,
TIMEOUT_US_1MS);
if (ret != 0) {
panic();
}
}
return stm32_rng_enable();
}
source/trusted-firmware/trusted-firmware-a-2.8/drivers/st/crypto/stm32_saes.c
+913
View File
@@ -0,0 +1,913 @@
/*
* Copyright (c) 2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <endian.h>
#include <errno.h>
#include <stdint.h>
#include <drivers/clk.h>
#include <drivers/delay_timer.h>
#include <drivers/st/stm32_saes.h>
#include <drivers/st/stm32mp_reset.h>
#include <lib/mmio.h>
#include <lib/utils_def.h>
#include <libfdt.h>
#include <platform_def.h>
#define UINT8_BIT 8U
#define AES_BLOCK_SIZE_BIT 128U
#define AES_BLOCK_SIZE (AES_BLOCK_SIZE_BIT / UINT8_BIT)
#define AES_KEYSIZE_128 16U
#define AES_KEYSIZE_256 32U
#define AES_IVSIZE 16U
/* SAES control register */
#define _SAES_CR 0x0U
/* SAES status register */
#define _SAES_SR 0x04U
/* SAES data input register */
#define _SAES_DINR 0x08U
/* SAES data output register */
#define _SAES_DOUTR 0x0CU
/* SAES key registers [0-3] */
#define _SAES_KEYR0 0x10U
#define _SAES_KEYR1 0x14U
#define _SAES_KEYR2 0x18U
#define _SAES_KEYR3 0x1CU
/* SAES initialization vector registers [0-3] */
#define _SAES_IVR0 0x20U
#define _SAES_IVR1 0x24U
#define _SAES_IVR2 0x28U
#define _SAES_IVR3 0x2CU
/* SAES key registers [4-7] */
#define _SAES_KEYR4 0x30U
#define _SAES_KEYR5 0x34U
#define _SAES_KEYR6 0x38U
#define _SAES_KEYR7 0x3CU
/* SAES suspend registers [0-7] */
#define _SAES_SUSPR0 0x40U
#define _SAES_SUSPR1 0x44U
#define _SAES_SUSPR2 0x48U
#define _SAES_SUSPR3 0x4CU
#define _SAES_SUSPR4 0x50U
#define _SAES_SUSPR5 0x54U
#define _SAES_SUSPR6 0x58U
#define _SAES_SUSPR7 0x5CU
/* SAES Interrupt Enable Register */
#define _SAES_IER 0x300U
/* SAES Interrupt Status Register */
#define _SAES_ISR 0x304U
/* SAES Interrupt Clear Register */
#define _SAES_ICR 0x308U
/* SAES control register fields */
#define _SAES_CR_RESET_VALUE 0x0U
#define _SAES_CR_IPRST BIT(31)
#define _SAES_CR_KEYSEL_MASK GENMASK(30, 28)
#define _SAES_CR_KEYSEL_SHIFT 28U
#define _SAES_CR_KEYSEL_SOFT 0x0U
#define _SAES_CR_KEYSEL_DHUK 0x1U
#define _SAES_CR_KEYSEL_BHK 0x2U
#define _SAES_CR_KEYSEL_BHU_XOR_BH_K 0x4U
#define _SAES_CR_KEYSEL_TEST 0x7U
#define _SAES_CR_KSHAREID_MASK GENMASK(27, 26)
#define _SAES_CR_KSHAREID_SHIFT 26U
#define _SAES_CR_KSHAREID_CRYP 0x0U
#define _SAES_CR_KEYMOD_MASK GENMASK(25, 24)
#define _SAES_CR_KEYMOD_SHIFT 24U
#define _SAES_CR_KEYMOD_NORMAL 0x0U
#define _SAES_CR_KEYMOD_WRAPPED 0x1U
#define _SAES_CR_KEYMOD_SHARED 0x2U
#define _SAES_CR_NPBLB_MASK GENMASK(23, 20)
#define _SAES_CR_NPBLB_SHIFT 20U
#define _SAES_CR_KEYPROT BIT(19)
#define _SAES_CR_KEYSIZE BIT(18)
#define _SAES_CR_GCMPH_MASK GENMASK(14, 13)
#define _SAES_CR_GCMPH_SHIFT 13U
#define _SAES_CR_GCMPH_INIT 0U
#define _SAES_CR_GCMPH_HEADER 1U
#define _SAES_CR_GCMPH_PAYLOAD 2U
#define _SAES_CR_GCMPH_FINAL 3U
#define _SAES_CR_DMAOUTEN BIT(12)
#define _SAES_CR_DMAINEN BIT(11)
#define _SAES_CR_CHMOD_MASK (BIT(16) | GENMASK(6, 5))
#define _SAES_CR_CHMOD_SHIFT 5U
#define _SAES_CR_CHMOD_ECB 0x0U
#define _SAES_CR_CHMOD_CBC 0x1U
#define _SAES_CR_CHMOD_CTR 0x2U
#define _SAES_CR_CHMOD_GCM 0x3U
#define _SAES_CR_CHMOD_GMAC 0x3U
#define _SAES_CR_CHMOD_CCM 0x800U
#define _SAES_CR_MODE_MASK GENMASK(4, 3)
#define _SAES_CR_MODE_SHIFT 3U
#define _SAES_CR_MODE_ENC 0U
#define _SAES_CR_MODE_KEYPREP 1U
#define _SAES_CR_MODE_DEC 2U
#define _SAES_CR_DATATYPE_MASK GENMASK(2, 1)
#define _SAES_CR_DATATYPE_SHIFT 1U
#define _SAES_CR_DATATYPE_NONE 0U
#define _SAES_CR_DATATYPE_HALF_WORD 1U
#define _SAES_CR_DATATYPE_BYTE 2U
#define _SAES_CR_DATATYPE_BIT 3U
#define _SAES_CR_EN BIT(0)
/* SAES status register fields */
#define _SAES_SR_KEYVALID BIT(7)
#define _SAES_SR_BUSY BIT(3)
#define _SAES_SR_WRERR BIT(2)
#define _SAES_SR_RDERR BIT(1)
#define _SAES_SR_CCF BIT(0)
/* SAES interrupt registers fields */
#define _SAES_I_RNG_ERR BIT(3)
#define _SAES_I_KEY_ERR BIT(2)
#define _SAES_I_RW_ERR BIT(1)
#define _SAES_I_CC BIT(0)
#define SAES_TIMEOUT_US 100000U
#define TIMEOUT_US_1MS 1000U
#define SAES_RESET_DELAY 20U
#define IS_CHAINING_MODE(mod, cr) \
(((cr) & _SAES_CR_CHMOD_MASK) == (_SAES_CR_CHMOD_##mod << _SAES_CR_CHMOD_SHIFT))
#define SET_CHAINING_MODE(mod, cr) \
mmio_clrsetbits_32((cr), _SAES_CR_CHMOD_MASK, _SAES_CR_CHMOD_##mod << _SAES_CR_CHMOD_SHIFT)
#define pragma weak stm32_saes_get_platdata
static struct stm32_saes_platdata saes_pdata;
int stm32_saes_get_platdata(struct stm32_saes_platdata *pdata)
{
return -ENODEV;
}
static int stm32_saes_parse_fdt(struct stm32_saes_platdata *pdata)
{
int node;
struct dt_node_info info;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return -FDT_ERR_NOTFOUND;
}
node = dt_get_node(&info, -1, DT_SAES_COMPAT);
if (node < 0) {
ERROR("No SAES entry in DT\n");
return -FDT_ERR_NOTFOUND;
}
if (info.status == DT_DISABLED) {
return -FDT_ERR_NOTFOUND;
}
if ((info.base == 0U) || (info.clock < 0) || (info.reset < 0)) {
return -FDT_ERR_BADVALUE;
}
pdata->base = (uintptr_t)info.base;
pdata->clock_id = (unsigned long)info.clock;
pdata->reset_id = (unsigned int)info.reset;
return 0;
}
static bool does_chaining_mode_need_iv(uint32_t cr)
{
return !(IS_CHAINING_MODE(ECB, cr));
}
static bool is_encrypt(uint32_t cr)
{
return (cr & _SAES_CR_MODE_MASK) == (_SAES_CR_MODE_ENC << _SAES_CR_MODE_SHIFT);
}
static bool is_decrypt(uint32_t cr)
{
return (cr & _SAES_CR_MODE_MASK) == (_SAES_CR_MODE_DEC << _SAES_CR_MODE_SHIFT);
}
static int wait_computation_completed(uintptr_t base)
{
uint64_t timeout = timeout_init_us(SAES_TIMEOUT_US);
while ((mmio_read_32(base + _SAES_SR) & _SAES_SR_CCF) != _SAES_SR_CCF) {
if (timeout_elapsed(timeout)) {
WARN("%s: timeout\n", __func__);
return -ETIMEDOUT;
}
}
return 0;
}
static void clear_computation_completed(uintptr_t base)
{
mmio_setbits_32(base + _SAES_ICR, _SAES_I_CC);
}
static int saes_start(struct stm32_saes_context *ctx)
{
uint64_t timeout;
/* Reset IP */
mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
udelay(SAES_RESET_DELAY);
mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
timeout = timeout_init_us(SAES_TIMEOUT_US);
while ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_BUSY) == _SAES_SR_BUSY) {
if (timeout_elapsed(timeout)) {
WARN("%s: timeout\n", __func__);
return -ETIMEDOUT;
}
}
return 0;
}
static void saes_end(struct stm32_saes_context *ctx, int prev_error)
{
if (prev_error != 0) {
/* Reset IP */
mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
udelay(SAES_RESET_DELAY);
mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
}
/* Disable the SAES peripheral */
mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
}
static void saes_write_iv(struct stm32_saes_context *ctx)
{
/* If chaining mode need to restore IV */
if (does_chaining_mode_need_iv(ctx->cr)) {
uint8_t i;
/* Restore the _SAES_IVRx */
for (i = 0U; i < AES_IVSIZE / sizeof(uint32_t); i++) {
mmio_write_32(ctx->base + _SAES_IVR0 + i * sizeof(uint32_t), ctx->iv[i]);
}
}
}
static void saes_write_key(struct stm32_saes_context *ctx)
{
/* Restore the _SAES_KEYRx if SOFTWARE key */
if ((ctx->cr & _SAES_CR_KEYSEL_MASK) == (_SAES_CR_KEYSEL_SOFT << _SAES_CR_KEYSEL_SHIFT)) {
uint8_t i;
for (i = 0U; i < AES_KEYSIZE_128 / sizeof(uint32_t); i++) {
mmio_write_32(ctx->base + _SAES_KEYR0 + i * sizeof(uint32_t), ctx->key[i]);
}
if ((ctx->cr & _SAES_CR_KEYSIZE) == _SAES_CR_KEYSIZE) {
for (i = 0U; i < (AES_KEYSIZE_256 / 2U) / sizeof(uint32_t); i++) {
mmio_write_32(ctx->base + _SAES_KEYR4 + i * sizeof(uint32_t),
ctx->key[i + 4U]);
}
}
}
}
static int saes_prepare_key(struct stm32_saes_context *ctx)
{
/* Disable the SAES peripheral */
mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
/* Set key size */
if ((ctx->cr & _SAES_CR_KEYSIZE) != 0U) {
mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_KEYSIZE);
} else {
mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_KEYSIZE);
}
saes_write_key(ctx);
/* For ECB/CBC decryption, key preparation mode must be selected to populate the key */
if ((IS_CHAINING_MODE(ECB, ctx->cr) || IS_CHAINING_MODE(CBC, ctx->cr)) &&
is_decrypt(ctx->cr)) {
int ret;
/* Select Mode 2 */
mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_MODE_MASK,
_SAES_CR_MODE_KEYPREP << _SAES_CR_MODE_SHIFT);
/* Enable SAES */
mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
/* Wait Computation completed */
ret = wait_computation_completed(ctx->base);
if (ret != 0) {
return ret;
}
clear_computation_completed(ctx->base);
/* Set Mode 3 */
mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_MODE_MASK,
_SAES_CR_MODE_DEC << _SAES_CR_MODE_SHIFT);
}
return 0;
}
static int save_context(struct stm32_saes_context *ctx)
{
if ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_CCF) != 0U) {
/* Device should not be in a processing phase */
return -EINVAL;
}
/* Save CR */
ctx->cr = mmio_read_32(ctx->base + _SAES_CR);
/* If chaining mode need to save current IV */
if (does_chaining_mode_need_iv(ctx->cr)) {
uint8_t i;
/* Save IV */
for (i = 0U; i < AES_IVSIZE / sizeof(uint32_t); i++) {
ctx->iv[i] = mmio_read_32(ctx->base + _SAES_IVR0 + i * sizeof(uint32_t));
}
}
/* Disable the SAES peripheral */
mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
return 0;
}
/* To resume the processing of a message */
static int restore_context(struct stm32_saes_context *ctx)
{
int ret;
/* IP should be disabled */
if ((mmio_read_32(ctx->base + _SAES_CR) & _SAES_CR_EN) != 0U) {
VERBOSE("%s: Device is still enabled\n", __func__);
return -EINVAL;
}
/* Reset internal state */
mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
/* Restore the _SAES_CR */
mmio_write_32(ctx->base + _SAES_CR, ctx->cr);
/* Preparation decrypt key */
ret = saes_prepare_key(ctx);
if (ret != 0) {
return ret;
}
saes_write_iv(ctx);
/* Enable the SAES peripheral */
mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
return 0;
}
/**
* @brief Initialize SAES driver.
* @param None.
* @retval 0 if OK; negative value else.
*/
int stm32_saes_driver_init(void)
{
int err;
err = stm32_saes_parse_fdt(&saes_pdata);
if (err != 0) {
err = stm32_saes_get_platdata(&saes_pdata);
if (err != 0) {
return err;
}
}
clk_enable(saes_pdata.clock_id);
if (stm32mp_reset_assert(saes_pdata.reset_id, TIMEOUT_US_1MS) != 0) {
panic();
}
udelay(SAES_RESET_DELAY);
if (stm32mp_reset_deassert(saes_pdata.reset_id, TIMEOUT_US_1MS) != 0) {
panic();
}
return 0;
}
/**
* @brief Start a AES computation.
* @param ctx: SAES process context
* @param is_dec: true if decryption, false if encryption
* @param ch_mode: define the chaining mode
* @param key_select: define where the key comes from.
* @param key: pointer to key (if key_select is KEY_SOFT, else unused)
* @param key_size: key size
* @param iv: pointer to initialization vectore (unsed if ch_mode is ECB)
* @param iv_size: iv size
* @note this function doesn't access to hardware but store in ctx the values
*
* @retval 0 if OK; negative value else.
*/
int stm32_saes_init(struct stm32_saes_context *ctx, bool is_dec,
enum stm32_saes_chaining_mode ch_mode, enum stm32_saes_key_selection key_select,
const void *key, size_t key_size, const void *iv, size_t iv_size)
{
unsigned int i;
const uint32_t *iv_u32;
const uint32_t *key_u32;
ctx->assoc_len = 0U;
ctx->load_len = 0U;
ctx->base = saes_pdata.base;
ctx->cr = _SAES_CR_RESET_VALUE;
/* We want buffer to be u32 aligned */
assert((uintptr_t)key % __alignof__(uint32_t) == 0);
assert((uintptr_t)iv % __alignof__(uint32_t) == 0);
iv_u32 = iv;
key_u32 = key;
if (is_dec) {
/* Save Mode 3 = decrypt */
mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_MODE_MASK,
_SAES_CR_MODE_DEC << _SAES_CR_MODE_SHIFT);
} else {
/* Save Mode 1 = crypt */
mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_MODE_MASK,
_SAES_CR_MODE_ENC << _SAES_CR_MODE_SHIFT);
}
/* Save chaining mode */
switch (ch_mode) {
case STM32_SAES_MODE_ECB:
SET_CHAINING_MODE(ECB, (uintptr_t)&(ctx->cr));
break;
case STM32_SAES_MODE_CBC:
SET_CHAINING_MODE(CBC, (uintptr_t)&(ctx->cr));
break;
case STM32_SAES_MODE_CTR:
SET_CHAINING_MODE(CTR, (uintptr_t)&(ctx->cr));
break;
case STM32_SAES_MODE_GCM:
SET_CHAINING_MODE(GCM, (uintptr_t)&(ctx->cr));
break;
case STM32_SAES_MODE_CCM:
SET_CHAINING_MODE(CCM, (uintptr_t)&(ctx->cr));
break;
default:
return -EINVAL;
}
/* We will use HW Byte swap (_SAES_CR_DATATYPE_BYTE) for data.
* so we won't need to
* htobe32(data) before write to DINR
* nor
* be32toh after reading from DOUTR
*
* But note that wrap key only accept _SAES_CR_DATATYPE_NONE
*/
mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_DATATYPE_MASK,
_SAES_CR_DATATYPE_BYTE << _SAES_CR_DATATYPE_SHIFT);
/* Configure keysize */
switch (key_size) {
case AES_KEYSIZE_128:
mmio_clrbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSIZE);
break;
case AES_KEYSIZE_256:
mmio_setbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSIZE);
break;
default:
return -EINVAL;
}
/* Configure key */
switch (key_select) {
case STM32_SAES_KEY_SOFT:
mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK,
_SAES_CR_KEYSEL_SOFT << _SAES_CR_KEYSEL_SHIFT);
/* Save key */
switch (key_size) {
case AES_KEYSIZE_128:
/* First 16 bytes == 4 u32 */
for (i = 0U; i < AES_KEYSIZE_128 / sizeof(uint32_t); i++) {
mmio_write_32((uintptr_t)(ctx->key + i), htobe32(key_u32[3 - i]));
/* /!\ we save the key in HW byte order
* and word order : key[i] is for _SAES_KEYRi
*/
}
break;
case AES_KEYSIZE_256:
for (i = 0U; i < AES_KEYSIZE_256 / sizeof(uint32_t); i++) {
mmio_write_32((uintptr_t)(ctx->key + i), htobe32(key_u32[7 - i]));
/* /!\ we save the key in HW byte order
* and word order : key[i] is for _SAES_KEYRi
*/
}
break;
default:
return -EINVAL;
}
break;
case STM32_SAES_KEY_DHU:
mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK,
_SAES_CR_KEYSEL_DHUK << _SAES_CR_KEYSEL_SHIFT);
break;
case STM32_SAES_KEY_BH:
mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK,
_SAES_CR_KEYSEL_BHK << _SAES_CR_KEYSEL_SHIFT);
break;
case STM32_SAES_KEY_BHU_XOR_BH:
mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK,
_SAES_CR_KEYSEL_BHU_XOR_BH_K << _SAES_CR_KEYSEL_SHIFT);
break;
case STM32_SAES_KEY_WRAPPED:
mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK,
_SAES_CR_KEYSEL_SOFT << _SAES_CR_KEYSEL_SHIFT);
break;
default:
return -EINVAL;
}
/* Save IV */
if (ch_mode != STM32_SAES_MODE_ECB) {
if ((iv == NULL) || (iv_size != AES_IVSIZE)) {
return -EINVAL;
}
for (i = 0U; i < AES_IVSIZE / sizeof(uint32_t); i++) {
mmio_write_32((uintptr_t)(ctx->iv + i), htobe32(iv_u32[3 - i]));
/* /!\ We save the iv in HW byte order */
}
}
return saes_start(ctx);
}
/**
* @brief Update (or start) a AES authentificate process of associated data (CCM or GCM).
* @param ctx: SAES process context
* @param last_block: true if last assoc data block
* @param data: pointer to associated data
* @param data_size: data size
*
* @retval 0 if OK; negative value else.
*/
int stm32_saes_update_assodata(struct stm32_saes_context *ctx, bool last_block,
uint8_t *data, size_t data_size)
{
int ret;
uint32_t *data_u32;
unsigned int i = 0U;
/* We want buffers to be u32 aligned */
assert((uintptr_t)data % __alignof__(uint32_t) == 0);
data_u32 = (uint32_t *)data;
/* Init phase */
ret = restore_context(ctx);
if (ret != 0) {
goto out;
}
ret = wait_computation_completed(ctx->base);
if (ret != 0) {
return ret;
}
clear_computation_completed(ctx->base);
if ((data == NULL) || (data_size == 0U)) {
/* No associated data */
/* ret already = 0 */
goto out;
}
/* There is an header/associated data phase */
mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_GCMPH_MASK,
_SAES_CR_GCMPH_HEADER << _SAES_CR_GCMPH_SHIFT);
/* Enable the SAES peripheral */
mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
while (i < round_down(data_size, AES_BLOCK_SIZE)) {
unsigned int w; /* Word index */
w = i / sizeof(uint32_t);
/* No need to htobe() as we configure the HW to swap bytes */
mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 0U]);
mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 1U]);
mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 2U]);
mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 3U]);
ret = wait_computation_completed(ctx->base);
if (ret != 0) {
goto out;
}
clear_computation_completed(ctx->base);
/* Process next block */
i += AES_BLOCK_SIZE;
ctx->assoc_len += AES_BLOCK_SIZE_BIT;
}
/* Manage last block if not a block size multiple */
if ((last_block) && (i < data_size)) {
/* We don't manage unaligned last block yet */
ret = -ENODEV;
goto out;
}
out:
if (ret != 0) {
saes_end(ctx, ret);
}
return ret;
}
/**
* @brief Update (or start) a AES authenticate and de/encrypt with payload data (CCM or GCM).
* @param ctx: SAES process context
* @param last_block: true if last payload data block
* @param data_in: pointer to payload
* @param data_out: pointer where to save de/encrypted payload
* @param data_size: payload size
*
* @retval 0 if OK; negative value else.
*/
int stm32_saes_update_load(struct stm32_saes_context *ctx, bool last_block,
uint8_t *data_in, uint8_t *data_out, size_t data_size)
{
int ret = 0;
uint32_t *data_in_u32;
uint32_t *data_out_u32;
unsigned int i = 0U;
uint32_t prev_cr;
/* We want buffers to be u32 aligned */
assert((uintptr_t)data_in % __alignof__(uint32_t) == 0);
assert((uintptr_t)data_out % __alignof__(uint32_t) == 0);
data_in_u32 = (uint32_t *)data_in;
data_out_u32 = (uint32_t *)data_out;
prev_cr = mmio_read_32(ctx->base + _SAES_CR);
if ((data_in == NULL) || (data_size == 0U)) {
/* there is no data */
goto out;
}
/* There is a load phase */
mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_GCMPH_MASK,
_SAES_CR_GCMPH_PAYLOAD << _SAES_CR_GCMPH_SHIFT);
if ((prev_cr & _SAES_CR_GCMPH_MASK) ==
(_SAES_CR_GCMPH_INIT << _SAES_CR_GCMPH_SHIFT)) {
/* Still in initialization phase, no header
* We need to enable the SAES peripheral
*/
mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
}
while (i < round_down(data_size, AES_BLOCK_SIZE)) {
unsigned int w; /* Word index */
w = i / sizeof(uint32_t);
/* No need to htobe() as we configure the HW to swap bytes */
mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 0U]);
mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 1U]);
mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 2U]);
mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 3U]);
ret = wait_computation_completed(ctx->base);
if (ret != 0) {
goto out;
}
/* No need to htobe() as we configure the HW to swap bytes */
data_out_u32[w + 0U] = mmio_read_32(ctx->base + _SAES_DOUTR);
data_out_u32[w + 1U] = mmio_read_32(ctx->base + _SAES_DOUTR);
data_out_u32[w + 2U] = mmio_read_32(ctx->base + _SAES_DOUTR);
data_out_u32[w + 3U] = mmio_read_32(ctx->base + _SAES_DOUTR);
clear_computation_completed(ctx->base);
/* Process next block */
i += AES_BLOCK_SIZE;
ctx->load_len += AES_BLOCK_SIZE_BIT;
}
/* Manage last block if not a block size multiple */
if ((last_block) && (i < data_size)) {
uint32_t block_in[AES_BLOCK_SIZE / sizeof(uint32_t)] = {0};
uint32_t block_out[AES_BLOCK_SIZE / sizeof(uint32_t)] = {0};
memcpy(block_in, data_in + i, data_size - i);
/* No need to htobe() as we configure the HW to swap bytes */
mmio_write_32(ctx->base + _SAES_DINR, block_in[0U]);
mmio_write_32(ctx->base + _SAES_DINR, block_in[1U]);
mmio_write_32(ctx->base + _SAES_DINR, block_in[2U]);
mmio_write_32(ctx->base + _SAES_DINR, block_in[3U]);
ret = wait_computation_completed(ctx->base);
if (ret != 0) {
VERBOSE("%s %d\n", __func__, __LINE__);
goto out;
}
/* No need to htobe() as we configure the HW to swap bytes */
block_out[0U] = mmio_read_32(ctx->base + _SAES_DOUTR);
block_out[1U] = mmio_read_32(ctx->base + _SAES_DOUTR);
block_out[2U] = mmio_read_32(ctx->base + _SAES_DOUTR);
block_out[3U] = mmio_read_32(ctx->base + _SAES_DOUTR);
clear_computation_completed(ctx->base);
memcpy(data_out + i, block_out, data_size - i);
ctx->load_len += (data_size - i) * UINT8_BIT;
}
out:
if (ret != 0) {
saes_end(ctx, ret);
}
return ret;
}
/**
* @brief Get authentication tag for AES authenticated algorithms (CCM or GCM).
* @param ctx: SAES process context
* @param tag: pointer where to save the tag
* @param data_size: tag size
*
* @retval 0 if OK; negative value else.
*/
int stm32_saes_final(struct stm32_saes_context *ctx, uint8_t *tag,
size_t tag_size)
{
int ret;
uint32_t tag_u32[4];
uint32_t prev_cr;
prev_cr = mmio_read_32(ctx->base + _SAES_CR);
mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_GCMPH_MASK,
_SAES_CR_GCMPH_FINAL << _SAES_CR_GCMPH_SHIFT);
if ((prev_cr & _SAES_CR_GCMPH_MASK) == (_SAES_CR_GCMPH_INIT << _SAES_CR_GCMPH_SHIFT)) {
/* Still in initialization phase, no header
* We need to enable the SAES peripheral
*/
mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
}
/* No need to htobe() as we configure the HW to swap bytes */
mmio_write_32(ctx->base + _SAES_DINR, 0);
mmio_write_32(ctx->base + _SAES_DINR, ctx->assoc_len);
mmio_write_32(ctx->base + _SAES_DINR, 0);
mmio_write_32(ctx->base + _SAES_DINR, ctx->load_len);
ret = wait_computation_completed(ctx->base);
if (ret != 0) {
goto out;
}
/* No need to htobe() as we configure the HW to swap bytes */
tag_u32[0] = mmio_read_32(ctx->base + _SAES_DOUTR);
tag_u32[1] = mmio_read_32(ctx->base + _SAES_DOUTR);
tag_u32[2] = mmio_read_32(ctx->base + _SAES_DOUTR);
tag_u32[3] = mmio_read_32(ctx->base + _SAES_DOUTR);
clear_computation_completed(ctx->base);
memcpy(tag, tag_u32, MIN(sizeof(tag_u32), tag_size));
out:
saes_end(ctx, ret);
return ret;
}
/**
* @brief Update (or start) a AES de/encrypt process (ECB, CBC or CTR).
* @param ctx: SAES process context
* @param last_block: true if last payload data block
* @param data_in: pointer to payload
* @param data_out: pointer where to save de/encrypted payload
* @param data_size: payload size
*
* @retval 0 if OK; negative value else.
*/
int stm32_saes_update(struct stm32_saes_context *ctx, bool last_block,
uint8_t *data_in, uint8_t *data_out, size_t data_size)
{
int ret;
uint32_t *data_in_u32;
uint32_t *data_out_u32;
unsigned int i = 0U;
/* We want buffers to be u32 aligned */
assert((uintptr_t)data_in % __alignof__(uint32_t) == 0);
assert((uintptr_t)data_out % __alignof__(uint32_t) == 0);
data_in_u32 = (uint32_t *)data_in;
data_out_u32 = (uint32_t *)data_out;
if ((!last_block) &&
(round_down(data_size, AES_BLOCK_SIZE) != data_size)) {
ERROR("%s: non last block must be multiple of 128 bits\n",
__func__);
ret = -EINVAL;
goto out;
}
/* In CBC encryption we need to manage specifically last 2 128bits
* blocks if total size in not a block size aligned
* work TODO. Currently return ENODEV.
* Morevoer as we need to know last 2 block, if unaligned and
* call with less than two block, return -EINVAL.
*/
if (last_block && IS_CHAINING_MODE(CBC, ctx->cr) && is_encrypt(ctx->cr) &&
(round_down(data_size, AES_BLOCK_SIZE) != data_size)) {
if (data_size < AES_BLOCK_SIZE * 2U) {
ERROR("if CBC, last part size should be at least 2 * AES_BLOCK_SIZE\n");
ret = -EINVAL;
goto out;
}
/* Moreover the CBC specific padding for encrypt is not yet implemented */
ret = -ENODEV;
goto out;
}
ret = restore_context(ctx);
if (ret != 0) {
goto out;
}
while (i < round_down(data_size, AES_BLOCK_SIZE)) {
unsigned int w; /* Word index */
w = i / sizeof(uint32_t);
/* No need to htobe() as we configure the HW to swap bytes */
mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 0U]);
mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 1U]);
mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 2U]);
mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 3U]);
ret = wait_computation_completed(ctx->base);
if (ret != 0) {
goto out;
}
/* No need to htobe() as we configure the HW to swap bytes */
data_out_u32[w + 0U] = mmio_read_32(ctx->base + _SAES_DOUTR);
data_out_u32[w + 1U] = mmio_read_32(ctx->base + _SAES_DOUTR);
data_out_u32[w + 2U] = mmio_read_32(ctx->base + _SAES_DOUTR);
data_out_u32[w + 3U] = mmio_read_32(ctx->base + _SAES_DOUTR);
clear_computation_completed(ctx->base);
/* Process next block */
i += AES_BLOCK_SIZE;
}
/* Manage last block if not a block size multiple */
if ((last_block) && (i < data_size)) {
/* In and out buffer have same size so should be AES_BLOCK_SIZE multiple */
ret = -ENODEV;
goto out;
}
if (!last_block) {
ret = save_context(ctx);
}
out:
/* If last block or error, end of SAES process */
if (last_block || (ret != 0)) {
saes_end(ctx, ret);
}
return ret;
}