GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <console_macros.S>
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#include <drivers/st/stm32_console.h>
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#include <drivers/st/stm32_uart_regs.h>
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#define USART_TIMEOUT 0x1000
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/*
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* "core" functions are low-level implementations that don't require
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* writeable memory and are thus safe to call in BL1 crash context.
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*/
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.globl console_stm32_core_init
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.globl console_stm32_core_putc
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.globl console_stm32_core_getc
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.globl console_stm32_core_flush
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.globl console_stm32_putc
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.globl console_stm32_flush
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/* -----------------------------------------------------------------
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* int console_core_init(uintptr_t base_addr,
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* unsigned int uart_clk,
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* unsigned int baud_rate)
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*
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* Function to initialize the console without a C Runtime to print
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* debug information. This function will be accessed by console_init
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* and crash reporting.
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*
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* In: r0 - console base address
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* r1 - Uart clock in Hz
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* r2 - Baud rate
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* Out: return 1 on success else 0 on error
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* Clobber list : r1, r2, r3
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* -----------------------------------------------------------------
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*/
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func console_stm32_core_init
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/* Check the input base address */
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cmp r0, #0
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beq core_init_fail
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#if !defined(IMAGE_BL2)
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#if STM32MP_RECONFIGURE_CONSOLE
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/* UART clock rate is set to 0 in BL32, skip init in that case */
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cmp r1, #0
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beq 1f
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#else /* STM32MP_RECONFIGURE_CONSOLE */
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/* Skip UART initialization if it is already enabled */
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ldr r3, [r0, #USART_CR1]
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ands r3, r3, #USART_CR1_UE
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bne 1f
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#endif /* STM32MP_RECONFIGURE_CONSOLE */
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#endif /* IMAGE_BL2 */
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/* Check baud rate and uart clock for sanity */
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cmp r1, #0
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beq core_init_fail
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cmp r2, #0
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beq core_init_fail
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/* Disable UART */
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ldr r3, [r0, #USART_CR1]
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bic r3, r3, #USART_CR1_UE
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str r3, [r0, #USART_CR1]
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/* Configure UART */
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orr r3, r3, #(USART_CR1_TE | USART_CR1_FIFOEN)
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str r3, [r0, #USART_CR1]
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ldr r3, [r0, #USART_CR2]
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bic r3, r3, #USART_CR2_STOP
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str r3, [r0, #USART_CR2]
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/* Divisor = (Uart clock + (baudrate / 2)) / baudrate */
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lsr r3, r2, #1
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add r3, r1, r3
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udiv r3, r3, r2
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cmp r3, #16
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bhi 2f
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/* Oversampling 8 */
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/* Divisor = (2 * Uart clock + (baudrate / 2)) / baudrate */
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lsr r3, r2, #1
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add r3, r3, r1, lsl #1
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udiv r3, r3, r2
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and r1, r3, #USART_BRR_DIV_FRACTION
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lsr r1, r1, #1
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bic r3, r3, #USART_BRR_DIV_FRACTION
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orr r3, r3, r1
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ldr r1, [r0, #USART_CR1]
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orr r1, r1, #USART_CR1_OVER8
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str r1, [r0, #USART_CR1]
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2:
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str r3, [r0, #USART_BRR]
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/* Enable UART */
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ldr r3, [r0, #USART_CR1]
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orr r3, r3, #USART_CR1_UE
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str r3, [r0, #USART_CR1]
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/* Check TEACK bit */
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mov r2, #USART_TIMEOUT
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teack_loop:
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subs r2, r2, #1
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beq core_init_fail
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ldr r3, [r0, #USART_ISR]
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tst r3, #USART_ISR_TEACK
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beq teack_loop
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1:
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mov r0, #1
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bx lr
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core_init_fail:
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mov r0, #0
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bx lr
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endfunc console_stm32_core_init
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.globl console_stm32_register
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/* -------------------------------------------------------
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* int console_stm32_register(uintptr_t baseaddr,
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* uint32_t clock, uint32_t baud,
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* console_t *console);
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* Function to initialize and register a new STM32
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* console. Storage passed in for the console struct
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* *must* be persistent (i.e. not from the stack).
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* In: r0 - UART register base address
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* r1 - UART clock in Hz
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* r2 - Baud rate
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* r3 - pointer to empty console_t struct
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* Out: return 1 on success, 0 on error
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* Clobber list : r0, r1, r2
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* -------------------------------------------------------
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*/
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func console_stm32_register
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push {r4, lr}
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mov r4, r3
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cmp r4, #0
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beq register_fail
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str r0, [r4, #CONSOLE_T_BASE]
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bl console_stm32_core_init
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cmp r0, #0
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beq register_fail
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mov r0, r4
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pop {r4, lr}
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finish_console_register stm32 putc=1, getc=0, flush=1
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register_fail:
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pop {r4, pc}
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endfunc console_stm32_register
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/* ---------------------------------------------------------------
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* int console_core_putc(int c, uintptr_t base_addr)
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*
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* Function to output a character over the console. It returns the
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* character printed on success or -1 on error.
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*
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* In : r0 - character to be printed
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* r1 - console base address
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* Out : return -1 on error else return character.
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* Clobber list : r2
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* ---------------------------------------------------------------
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*/
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func console_stm32_core_putc
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/* Check the input parameter */
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cmp r1, #0
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beq putc_error
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/* Check Transmit Data Register Empty */
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txe_loop:
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ldr r2, [r1, #USART_ISR]
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tst r2, #USART_ISR_TXE
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beq txe_loop
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str r0, [r1, #USART_TDR]
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/* Check transmit complete flag */
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tc_loop:
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ldr r2, [r1, #USART_ISR]
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tst r2, #USART_ISR_TC
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beq tc_loop
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bx lr
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putc_error:
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mov r0, #-1
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bx lr
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endfunc console_stm32_core_putc
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/* ------------------------------------------------------------
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* int console_stm32_putc(int c, console_t *console)
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* Function to output a character over the console. It
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* returns the character printed on success or -1 on error.
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* In: r0 - character to be printed
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* r1 - pointer to console_t structure
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* Out : return -1 on error else return character.
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* Clobber list: r2
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* ------------------------------------------------------------
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*/
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func console_stm32_putc
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#if ENABLE_ASSERTIONS
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cmp r1, #0
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ASM_ASSERT(ne)
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#endif /* ENABLE_ASSERTIONS */
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ldr r1, [r1, #CONSOLE_T_BASE]
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b console_stm32_core_putc
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endfunc console_stm32_putc
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/* -----------------------------------------------------------
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* int console_core_getc(uintptr_t base_addr)
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*
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* Function to get a character from the console.
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* It returns the character grabbed on success or -1 on error.
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*
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* In : r0 - console base address
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* Out : return -1.
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* Clobber list : r0, r1
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* -----------------------------------------------------------
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*/
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func console_stm32_core_getc
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/* Not supported */
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mov r0, #-1
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bx lr
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endfunc console_stm32_core_getc
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/* ---------------------------------------------------------------
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* void console_core_flush(uintptr_t base_addr)
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*
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* Function to force a write of all buffered data that hasn't been
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* output.
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*
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* In : r0 - console base address
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* Out : void.
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* Clobber list : r0, r1
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* ---------------------------------------------------------------
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*/
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func console_stm32_core_flush
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#if ENABLE_ASSERTIONS
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cmp r0, #0
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ASM_ASSERT(ne)
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#endif /* ENABLE_ASSERTIONS */
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/* Check Transmit Data Register Empty */
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txe_loop_3:
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ldr r1, [r0, #USART_ISR]
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tst r1, #USART_ISR_TXE
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beq txe_loop_3
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bx lr
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endfunc console_stm32_core_flush
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/* ------------------------------------------------------
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* void console_stm32_flush(console_t *console)
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* Function to force a write of all buffered
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* data that hasn't been output.
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* In : r0 - pointer to console_t structure
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* Out : void.
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* Clobber list: r0, r1
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* ------------------------------------------------------
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*/
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func console_stm32_flush
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#if ENABLE_ASSERTIONS
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cmp r0, #0
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ASM_ASSERT(ne)
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#endif /* ENABLE_ASSERTIONS */
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ldr r0, [r0, #CONSOLE_T_BASE]
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b console_stm32_core_flush
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endfunc console_stm32_flush
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@@ -0,0 +1,439 @@
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/*
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* Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <string.h>
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#include <common/bl_common.h>
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#include <drivers/clk.h>
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#include <drivers/delay_timer.h>
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#include <drivers/st/stm32_gpio.h>
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#include <drivers/st/stm32_uart.h>
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#include <drivers/st/stm32_uart_regs.h>
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#include <drivers/st/stm32mp_clkfunc.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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/* UART time-out value */
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#define STM32_UART_TIMEOUT_US 20000U
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/* Mask to clear ALL the configuration registers */
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#define STM32_UART_CR1_FIELDS \
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(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
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USART_CR1_RE | USART_CR1_OVER8 | USART_CR1_FIFOEN)
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#define STM32_UART_CR2_FIELDS \
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(USART_CR2_SLVEN | USART_CR2_DIS_NSS | USART_CR2_ADDM7 | \
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USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \
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USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \
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USART_CR2_STOP | USART_CR2_LINEN | USART_CR2_SWAP | \
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USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV | \
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USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMODE | \
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USART_CR2_RTOEN | USART_CR2_ADD)
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#define STM32_UART_CR3_FIELDS \
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(USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | \
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USART_CR3_HDSEL | USART_CR3_NACK | USART_CR3_SCEN | \
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USART_CR3_DMAR | USART_CR3_DMAT | USART_CR3_RTSE | \
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USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \
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USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | \
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USART_CR3_DEP | USART_CR3_SCARCNT | USART_CR3_WUS | \
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USART_CR3_WUFIE | USART_CR3_TXFTIE | USART_CR3_TCBGTIE | \
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USART_CR3_RXFTCFG | USART_CR3_RXFTIE | USART_CR3_TXFTCFG)
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#define STM32_UART_ISR_ERRORS \
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(USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE | USART_ISR_PE)
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static const uint16_t presc_table[STM32_UART_PRESCALER_NB] = {
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1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U
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};
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/* @brief BRR division operation to set BRR register in 8-bit oversampling
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* mode.
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* @param clockfreq: UART clock.
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* @param baud_rate: Baud rate set by the user.
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* @param prescaler: UART prescaler value.
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* @retval Division result.
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*/
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static uint32_t uart_div_sampling8(unsigned long clockfreq,
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uint32_t baud_rate,
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uint32_t prescaler)
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{
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uint32_t scaled_freq = clockfreq / presc_table[prescaler];
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return ((scaled_freq * 2) + (baud_rate / 2)) / baud_rate;
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}
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/* @brief BRR division operation to set BRR register in 16-bit oversampling
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* mode.
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* @param clockfreq: UART clock.
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* @param baud_rate: Baud rate set by the user.
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* @param prescaler: UART prescaler value.
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* @retval Division result.
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*/
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static uint32_t uart_div_sampling16(unsigned long clockfreq,
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uint32_t baud_rate,
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uint32_t prescaler)
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{
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uint32_t scaled_freq = clockfreq / presc_table[prescaler];
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return (scaled_freq + (baud_rate / 2)) / baud_rate;
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}
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/*
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* @brief Return the UART clock frequency.
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* @param huart: UART handle.
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* @retval Frequency value in Hz.
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*/
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static unsigned long uart_get_clock_freq(struct stm32_uart_handle_s *huart)
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{
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return fdt_get_uart_clock_freq((uintptr_t)huart->base);
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}
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/*
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* @brief Configure the UART peripheral.
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* @param huart: UART handle.
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* @retval UART status.
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*/
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static int uart_set_config(struct stm32_uart_handle_s *huart,
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const struct stm32_uart_init_s *init)
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{
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uint32_t tmpreg;
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unsigned long clockfreq;
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unsigned long int_div;
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uint32_t brrtemp;
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uint32_t over_sampling;
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/*---------------------- USART BRR configuration --------------------*/
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clockfreq = uart_get_clock_freq(huart);
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if (clockfreq == 0UL) {
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return -ENODEV;
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}
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int_div = clockfreq / init->baud_rate;
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if (int_div < 16U) {
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uint32_t usartdiv = uart_div_sampling8(clockfreq,
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init->baud_rate,
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init->prescaler);
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brrtemp = (usartdiv & USART_BRR_DIV_MANTISSA) |
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((usartdiv & USART_BRR_DIV_FRACTION) >> 1);
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over_sampling = USART_CR1_OVER8;
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} else {
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brrtemp = uart_div_sampling16(clockfreq,
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init->baud_rate,
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init->prescaler) &
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(USART_BRR_DIV_FRACTION | USART_BRR_DIV_MANTISSA);
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over_sampling = 0x0U;
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}
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mmio_write_32(huart->base + USART_BRR, brrtemp);
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/*
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* ---------------------- USART CR1 Configuration --------------------
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* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
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* the UART word length, parity, mode and oversampling:
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* - set the M bits according to init->word_length value,
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* - set PCE and PS bits according to init->parity value,
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* - set TE and RE bits according to init->mode value,
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* - set OVER8 bit according baudrate and clock.
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*/
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tmpreg = init->word_length |
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init->parity |
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init->mode |
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over_sampling |
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init->fifo_mode;
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mmio_clrsetbits_32(huart->base + USART_CR1, STM32_UART_CR1_FIELDS, tmpreg);
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/*
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* --------------------- USART CR2 Configuration ---------------------
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* Configure the UART Stop Bits: Set STOP[13:12] bits according
|
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* to init->stop_bits value.
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*/
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mmio_clrsetbits_32(huart->base + USART_CR2, STM32_UART_CR2_FIELDS,
|
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init->stop_bits);
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/*
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* --------------------- USART CR3 Configuration ---------------------
|
||||
* Configure:
|
||||
* - UART HardWare Flow Control: set CTSE and RTSE bits according
|
||||
* to init->hw_flow_control value,
|
||||
* - one-bit sampling method versus three samples' majority rule
|
||||
* according to init->one_bit_sampling (not applicable to
|
||||
* LPUART),
|
||||
* - set TXFTCFG bit according to init->tx_fifo_threshold value,
|
||||
* - set RXFTCFG bit according to init->rx_fifo_threshold value.
|
||||
*/
|
||||
tmpreg = init->hw_flow_control | init->one_bit_sampling;
|
||||
|
||||
if (init->fifo_mode == USART_CR1_FIFOEN) {
|
||||
tmpreg |= init->tx_fifo_threshold |
|
||||
init->rx_fifo_threshold;
|
||||
}
|
||||
|
||||
mmio_clrsetbits_32(huart->base + USART_CR3, STM32_UART_CR3_FIELDS, tmpreg);
|
||||
|
||||
/*
|
||||
* --------------------- USART PRESC Configuration -------------------
|
||||
* Configure UART Clock Prescaler : set PRESCALER according to
|
||||
* init->prescaler value.
|
||||
*/
|
||||
assert(init->prescaler < STM32_UART_PRESCALER_NB);
|
||||
mmio_clrsetbits_32(huart->base + USART_PRESC, USART_PRESC_PRESCALER,
|
||||
init->prescaler);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief Handle UART communication timeout.
|
||||
* @param huart: UART handle.
|
||||
* @param flag: Specifies the UART flag to check.
|
||||
* @retval UART status.
|
||||
*/
|
||||
static int stm32_uart_wait_flag(struct stm32_uart_handle_s *huart, uint32_t flag)
|
||||
{
|
||||
uint64_t timeout_ref = timeout_init_us(STM32_UART_TIMEOUT_US);
|
||||
|
||||
while ((mmio_read_32(huart->base + USART_ISR) & flag) == 0U) {
|
||||
if (timeout_elapsed(timeout_ref)) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief Check the UART idle State.
|
||||
* @param huart: UART handle.
|
||||
* @retval UART status.
|
||||
*/
|
||||
static int stm32_uart_check_idle(struct stm32_uart_handle_s *huart)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Check if the transmitter is enabled */
|
||||
if ((mmio_read_32(huart->base + USART_CR1) & USART_CR1_TE) == USART_CR1_TE) {
|
||||
ret = stm32_uart_wait_flag(huart, USART_ISR_TEACK);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if the receiver is enabled */
|
||||
if ((mmio_read_32(huart->base + USART_CR1) & USART_CR1_RE) == USART_CR1_RE) {
|
||||
ret = stm32_uart_wait_flag(huart, USART_ISR_REACK);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief Compute RDR register mask depending on word length.
|
||||
* @param huart: UART handle.
|
||||
* @retval Mask value.
|
||||
*/
|
||||
static unsigned int stm32_uart_rdr_mask(const struct stm32_uart_init_s *init)
|
||||
{
|
||||
unsigned int mask = 0U;
|
||||
|
||||
switch (init->word_length) {
|
||||
case STM32_UART_WORDLENGTH_9B:
|
||||
mask = GENMASK(8, 0);
|
||||
break;
|
||||
case STM32_UART_WORDLENGTH_8B:
|
||||
mask = GENMASK(7, 0);
|
||||
break;
|
||||
case STM32_UART_WORDLENGTH_7B:
|
||||
mask = GENMASK(6, 0);
|
||||
break;
|
||||
default:
|
||||
break; /* not reached */
|
||||
}
|
||||
|
||||
if (init->parity != STM32_UART_PARITY_NONE) {
|
||||
mask >>= 1;
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief Check interrupt and status errors.
|
||||
* @retval True if error detected, false otherwise.
|
||||
*/
|
||||
static bool stm32_uart_error_detected(struct stm32_uart_handle_s *huart)
|
||||
{
|
||||
return (mmio_read_32(huart->base + USART_ISR) & STM32_UART_ISR_ERRORS) != 0U;
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief Clear status errors.
|
||||
*/
|
||||
static void stm32_uart_error_clear(struct stm32_uart_handle_s *huart)
|
||||
{
|
||||
mmio_write_32(huart->base + USART_ICR, STM32_UART_ISR_ERRORS);
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief Stop the UART.
|
||||
* @param base: UART base address.
|
||||
*/
|
||||
void stm32_uart_stop(uintptr_t base)
|
||||
{
|
||||
mmio_clrbits_32(base + USART_CR1, USART_CR1_UE);
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief Initialize UART.
|
||||
* @param huart: UART handle.
|
||||
* @param base_addr: base address of UART.
|
||||
* @param init: UART initialization parameter.
|
||||
* @retval UART status.
|
||||
*/
|
||||
int stm32_uart_init(struct stm32_uart_handle_s *huart,
|
||||
uintptr_t base_addr,
|
||||
const struct stm32_uart_init_s *init)
|
||||
{
|
||||
int ret;
|
||||
int uart_node;
|
||||
int clk;
|
||||
void *fdt = NULL;
|
||||
|
||||
if (huart == NULL || init == NULL || base_addr == 0U) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
huart->base = base_addr;
|
||||
|
||||
/* Search UART instance in DT */
|
||||
if (fdt_get_address(&fdt) == 0) {
|
||||
return -FDT_ERR_NOTFOUND;
|
||||
}
|
||||
|
||||
if (fdt == NULL) {
|
||||
return -FDT_ERR_NOTFOUND;
|
||||
}
|
||||
|
||||
uart_node = dt_match_instance_by_compatible(DT_UART_COMPAT, base_addr);
|
||||
if (uart_node == -FDT_ERR_NOTFOUND) {
|
||||
return -FDT_ERR_NOTFOUND;
|
||||
}
|
||||
|
||||
/* Pinctrl initialization */
|
||||
if (dt_set_pinctrl_config(uart_node) != 0) {
|
||||
return -FDT_ERR_BADVALUE;
|
||||
}
|
||||
|
||||
/* Clock initialization */
|
||||
clk = fdt_get_clock_id(uart_node);
|
||||
if (clk < 0) {
|
||||
return -FDT_ERR_NOTFOUND;
|
||||
}
|
||||
clk_enable(clk);
|
||||
|
||||
/* Disable the peripheral */
|
||||
stm32_uart_stop(huart->base);
|
||||
|
||||
/* Computation of UART mask to apply to RDR register */
|
||||
huart->rdr_mask = stm32_uart_rdr_mask(init);
|
||||
|
||||
/* Init the peripheral */
|
||||
ret = uart_set_config(huart, init);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Enable the peripheral */
|
||||
mmio_setbits_32(huart->base + USART_CR1, USART_CR1_UE);
|
||||
|
||||
/* TEACK and/or REACK to check */
|
||||
return stm32_uart_check_idle(huart);
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief Transmit one data in no blocking mode.
|
||||
* @param huart: UART handle.
|
||||
* @param c: data to sent.
|
||||
* @retval UART status.
|
||||
*/
|
||||
int stm32_uart_putc(struct stm32_uart_handle_s *huart, int c)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (huart == NULL) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = stm32_uart_wait_flag(huart, USART_ISR_TXE);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
mmio_write_32(huart->base + USART_TDR, c);
|
||||
if (stm32_uart_error_detected(huart)) {
|
||||
stm32_uart_error_clear(huart);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief Flush TX Transmit fifo
|
||||
* @param huart: UART handle.
|
||||
* @retval UART status.
|
||||
*/
|
||||
int stm32_uart_flush(struct stm32_uart_handle_s *huart)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (huart == NULL) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = stm32_uart_wait_flag(huart, USART_ISR_TXE);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
return stm32_uart_wait_flag(huart, USART_ISR_TC);
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief Receive a data in no blocking mode.
|
||||
* @retval value if >0 or UART status.
|
||||
*/
|
||||
int stm32_uart_getc(struct stm32_uart_handle_s *huart)
|
||||
{
|
||||
uint32_t data;
|
||||
|
||||
if (huart == NULL) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Check if data is available */
|
||||
if ((mmio_read_32(huart->base + USART_ISR) & USART_ISR_RXNE) == 0U) {
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
data = mmio_read_32(huart->base + USART_RDR) & huart->rdr_mask;
|
||||
|
||||
if (stm32_uart_error_detected(huart)) {
|
||||
stm32_uart_error_clear(huart);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
return (int)data;
|
||||
}
|
||||
Reference in New Issue
Block a user