GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,911 @@
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/*
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* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <endian.h>
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#include <errno.h>
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#include <stdint.h>
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#include <string.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <drivers/ufs.h>
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#include <lib/mmio.h>
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#define CDB_ADDR_MASK 127
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#define ALIGN_CDB(x) (((x) + CDB_ADDR_MASK) & ~CDB_ADDR_MASK)
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#define ALIGN_8(x) (((x) + 7) & ~7)
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#define UFS_DESC_SIZE 0x400
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#define MAX_UFS_DESC_SIZE 0x8000 /* 32 descriptors */
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#define MAX_PRDT_SIZE 0x40000 /* 256KB */
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static ufs_params_t ufs_params;
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static int nutrs; /* Number of UTP Transfer Request Slots */
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int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd)
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{
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unsigned int data;
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if (base == 0 || cmd == NULL)
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return -EINVAL;
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data = mmio_read_32(base + HCS);
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if ((data & HCS_UCRDY) == 0)
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return -EBUSY;
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mmio_write_32(base + IS, ~0);
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mmio_write_32(base + UCMDARG1, cmd->arg1);
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mmio_write_32(base + UCMDARG2, cmd->arg2);
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mmio_write_32(base + UCMDARG3, cmd->arg3);
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mmio_write_32(base + UICCMD, cmd->op);
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do {
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data = mmio_read_32(base + IS);
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} while ((data & UFS_INT_UCCS) == 0);
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mmio_write_32(base + IS, UFS_INT_UCCS);
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return mmio_read_32(base + UCMDARG2) & CONFIG_RESULT_CODE_MASK;
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}
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int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val)
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{
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uintptr_t base;
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unsigned int data;
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int result, retries;
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uic_cmd_t cmd;
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assert(ufs_params.reg_base != 0);
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if (val == NULL)
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return -EINVAL;
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base = ufs_params.reg_base;
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for (retries = 0; retries < 100; retries++) {
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data = mmio_read_32(base + HCS);
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if ((data & HCS_UCRDY) != 0)
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break;
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mdelay(1);
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}
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if (retries >= 100)
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return -EBUSY;
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cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx);
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cmd.arg2 = 0;
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cmd.arg3 = 0;
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cmd.op = DME_GET;
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for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) {
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result = ufshc_send_uic_cmd(base, &cmd);
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if (result == 0)
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break;
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data = mmio_read_32(base + IS);
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if (data & UFS_INT_UE)
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return -EINVAL;
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}
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if (retries >= UFS_UIC_COMMAND_RETRIES)
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return -EIO;
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*val = mmio_read_32(base + UCMDARG3);
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return 0;
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}
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int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val)
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{
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uintptr_t base;
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unsigned int data;
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int result, retries;
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uic_cmd_t cmd;
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assert((ufs_params.reg_base != 0));
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base = ufs_params.reg_base;
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cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx);
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cmd.arg2 = 0;
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cmd.arg3 = val;
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cmd.op = DME_SET;
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for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) {
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result = ufshc_send_uic_cmd(base, &cmd);
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if (result == 0)
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break;
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data = mmio_read_32(base + IS);
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if (data & UFS_INT_UE)
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return -EINVAL;
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}
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if (retries >= UFS_UIC_COMMAND_RETRIES)
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return -EIO;
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return 0;
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}
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static int ufshc_hce_enable(uintptr_t base)
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{
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unsigned int data;
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int retries;
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/* Enable Host Controller */
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mmio_write_32(base + HCE, HCE_ENABLE);
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/* Wait until basic initialization sequence completed */
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for (retries = 0; retries < HCE_ENABLE_INNER_RETRIES; ++retries) {
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data = mmio_read_32(base + HCE);
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if (data & HCE_ENABLE) {
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break;
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}
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udelay(HCE_ENABLE_TIMEOUT_US);
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}
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if (retries >= HCE_ENABLE_INNER_RETRIES) {
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int ufshc_hce_disable(uintptr_t base)
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{
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unsigned int data;
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int timeout;
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/* Disable Host Controller */
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mmio_write_32(base + HCE, HCE_DISABLE);
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timeout = HCE_DISABLE_TIMEOUT_US;
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do {
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data = mmio_read_32(base + HCE);
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if ((data & HCE_ENABLE) == HCE_DISABLE) {
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break;
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}
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udelay(1);
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} while (--timeout > 0);
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if (timeout <= 0) {
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int ufshc_reset(uintptr_t base)
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{
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unsigned int data;
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int retries, result;
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/* disable controller if enabled */
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if (mmio_read_32(base + HCE) & HCE_ENABLE) {
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result = ufshc_hce_disable(base);
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if (result != 0) {
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return -EIO;
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}
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}
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for (retries = 0; retries < HCE_ENABLE_OUTER_RETRIES; ++retries) {
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result = ufshc_hce_enable(base);
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if (result == 0) {
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break;
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}
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}
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if (retries >= HCE_ENABLE_OUTER_RETRIES) {
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return -EIO;
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}
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/* Enable Interrupts */
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data = UFS_INT_UCCS | UFS_INT_ULSS | UFS_INT_UE | UFS_INT_UTPES |
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UFS_INT_DFES | UFS_INT_HCFES | UFS_INT_SBFES;
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mmio_write_32(base + IE, data);
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return 0;
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}
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static int ufshc_dme_link_startup(uintptr_t base)
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{
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uic_cmd_t cmd;
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memset(&cmd, 0, sizeof(cmd));
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cmd.op = DME_LINKSTARTUP;
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return ufshc_send_uic_cmd(base, &cmd);
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}
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static int ufshc_link_startup(uintptr_t base)
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{
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int data, result;
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int retries;
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for (retries = DME_LINKSTARTUP_RETRIES; retries > 0; retries--) {
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result = ufshc_dme_link_startup(base);
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if (result != 0) {
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/* Reset controller before trying again */
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result = ufshc_reset(base);
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if (result != 0) {
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return result;
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}
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continue;
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}
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assert((mmio_read_32(base + HCS) & HCS_DP) == 0);
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data = mmio_read_32(base + IS);
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if (data & UFS_INT_ULSS)
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mmio_write_32(base + IS, UFS_INT_ULSS);
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return 0;
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}
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return -EIO;
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}
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/* Check Door Bell register to get an empty slot */
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static int get_empty_slot(int *slot)
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{
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unsigned int data;
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int i;
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data = mmio_read_32(ufs_params.reg_base + UTRLDBR);
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for (i = 0; i < nutrs; i++) {
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if ((data & 1) == 0)
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break;
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data = data >> 1;
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}
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if (i >= nutrs)
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return -EBUSY;
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*slot = i;
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return 0;
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}
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static void get_utrd(utp_utrd_t *utrd)
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{
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uintptr_t base;
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int slot = 0, result;
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utrd_header_t *hd;
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assert(utrd != NULL);
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result = get_empty_slot(&slot);
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assert(result == 0);
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/* clear utrd */
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memset((void *)utrd, 0, sizeof(utp_utrd_t));
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base = ufs_params.desc_base + (slot * sizeof(utrd_header_t));
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/* clear the descriptor */
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memset((void *)base, 0, UFS_DESC_SIZE);
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utrd->header = base;
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utrd->task_tag = slot + 1;
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/* CDB address should be aligned with 128 bytes */
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utrd->upiu = ALIGN_CDB(utrd->header + sizeof(utrd_header_t));
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utrd->resp_upiu = ALIGN_8(utrd->upiu + sizeof(cmd_upiu_t));
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utrd->size_upiu = utrd->resp_upiu - utrd->upiu;
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utrd->size_resp_upiu = ALIGN_8(sizeof(resp_upiu_t));
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utrd->prdt = utrd->resp_upiu + utrd->size_resp_upiu;
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hd = (utrd_header_t *)utrd->header;
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hd->ucdba = utrd->upiu & UINT32_MAX;
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hd->ucdbau = (utrd->upiu >> 32) & UINT32_MAX;
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/* Both RUL and RUO is based on DWORD */
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hd->rul = utrd->size_resp_upiu >> 2;
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hd->ruo = utrd->size_upiu >> 2;
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(void)result;
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}
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/*
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* Prepare UTRD, Command UPIU, Response UPIU.
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*/
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static int ufs_prepare_cmd(utp_utrd_t *utrd, uint8_t op, uint8_t lun,
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int lba, uintptr_t buf, size_t length)
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{
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utrd_header_t *hd;
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cmd_upiu_t *upiu;
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prdt_t *prdt;
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unsigned int ulba;
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unsigned int lba_cnt;
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int prdt_size;
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hd = (utrd_header_t *)utrd->header;
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upiu = (cmd_upiu_t *)utrd->upiu;
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hd->i = 1;
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hd->ct = CT_UFS_STORAGE;
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hd->ocs = OCS_MASK;
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upiu->trans_type = CMD_UPIU;
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upiu->task_tag = utrd->task_tag;
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upiu->cdb[0] = op;
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ulba = (unsigned int)lba;
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lba_cnt = (unsigned int)(length >> UFS_BLOCK_SHIFT);
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switch (op) {
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case CDBCMD_TEST_UNIT_READY:
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break;
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case CDBCMD_READ_CAPACITY_10:
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hd->dd = DD_OUT;
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upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S;
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upiu->lun = lun;
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break;
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case CDBCMD_READ_10:
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hd->dd = DD_OUT;
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upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S;
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upiu->lun = lun;
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upiu->cdb[1] = RW_WITHOUT_CACHE;
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/* set logical block address */
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upiu->cdb[2] = (ulba >> 24) & 0xff;
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upiu->cdb[3] = (ulba >> 16) & 0xff;
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upiu->cdb[4] = (ulba >> 8) & 0xff;
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upiu->cdb[5] = ulba & 0xff;
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/* set transfer length */
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upiu->cdb[7] = (lba_cnt >> 8) & 0xff;
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upiu->cdb[8] = lba_cnt & 0xff;
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break;
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case CDBCMD_WRITE_10:
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hd->dd = DD_IN;
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upiu->flags = UPIU_FLAGS_W | UPIU_FLAGS_ATTR_S;
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upiu->lun = lun;
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upiu->cdb[1] = RW_WITHOUT_CACHE;
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/* set logical block address */
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upiu->cdb[2] = (ulba >> 24) & 0xff;
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upiu->cdb[3] = (ulba >> 16) & 0xff;
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upiu->cdb[4] = (ulba >> 8) & 0xff;
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upiu->cdb[5] = ulba & 0xff;
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/* set transfer length */
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upiu->cdb[7] = (lba_cnt >> 8) & 0xff;
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upiu->cdb[8] = lba_cnt & 0xff;
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break;
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default:
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assert(0);
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break;
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}
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if (hd->dd == DD_IN)
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flush_dcache_range(buf, length);
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else if (hd->dd == DD_OUT)
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inv_dcache_range(buf, length);
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if (length) {
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upiu->exp_data_trans_len = htobe32(length);
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assert(lba_cnt <= UINT16_MAX);
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prdt = (prdt_t *)utrd->prdt;
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prdt_size = 0;
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while (length > 0) {
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prdt->dba = (unsigned int)(buf & UINT32_MAX);
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prdt->dbau = (unsigned int)((buf >> 32) & UINT32_MAX);
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/* prdt->dbc counts from 0 */
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if (length > MAX_PRDT_SIZE) {
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prdt->dbc = MAX_PRDT_SIZE - 1;
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length = length - MAX_PRDT_SIZE;
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} else {
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prdt->dbc = length - 1;
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length = 0;
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}
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buf += MAX_PRDT_SIZE;
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prdt++;
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prdt_size += sizeof(prdt_t);
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}
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utrd->size_prdt = ALIGN_8(prdt_size);
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hd->prdtl = utrd->size_prdt >> 2;
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hd->prdto = (utrd->size_upiu + utrd->size_resp_upiu) >> 2;
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}
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flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE);
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return 0;
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}
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static int ufs_prepare_query(utp_utrd_t *utrd, uint8_t op, uint8_t idn,
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uint8_t index, uint8_t sel,
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uintptr_t buf, size_t length)
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{
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utrd_header_t *hd;
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query_upiu_t *query_upiu;
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hd = (utrd_header_t *)utrd->header;
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query_upiu = (query_upiu_t *)utrd->upiu;
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hd->i = 1;
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hd->ct = CT_UFS_STORAGE;
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hd->ocs = OCS_MASK;
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query_upiu->trans_type = QUERY_REQUEST_UPIU;
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query_upiu->task_tag = utrd->task_tag;
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query_upiu->ts.desc.opcode = op;
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query_upiu->ts.desc.idn = idn;
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query_upiu->ts.desc.index = index;
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query_upiu->ts.desc.selector = sel;
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switch (op) {
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case QUERY_READ_DESC:
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query_upiu->query_func = QUERY_FUNC_STD_READ;
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query_upiu->ts.desc.length = htobe16(length);
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break;
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case QUERY_WRITE_DESC:
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query_upiu->query_func = QUERY_FUNC_STD_WRITE;
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query_upiu->ts.desc.length = htobe16(length);
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memcpy((void *)(utrd->upiu + sizeof(query_upiu_t)),
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(void *)buf, length);
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break;
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case QUERY_READ_ATTR:
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case QUERY_READ_FLAG:
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query_upiu->query_func = QUERY_FUNC_STD_READ;
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break;
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case QUERY_CLEAR_FLAG:
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case QUERY_SET_FLAG:
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query_upiu->query_func = QUERY_FUNC_STD_WRITE;
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break;
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case QUERY_WRITE_ATTR:
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query_upiu->query_func = QUERY_FUNC_STD_WRITE;
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query_upiu->ts.attr.value = htobe32(*((uint32_t *)buf));
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break;
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default:
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assert(0);
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break;
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}
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flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE);
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return 0;
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}
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static void ufs_prepare_nop_out(utp_utrd_t *utrd)
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{
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utrd_header_t *hd;
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nop_out_upiu_t *nop_out;
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hd = (utrd_header_t *)utrd->header;
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nop_out = (nop_out_upiu_t *)utrd->upiu;
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hd->i = 1;
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hd->ct = CT_UFS_STORAGE;
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hd->ocs = OCS_MASK;
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nop_out->trans_type = 0;
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nop_out->task_tag = utrd->task_tag;
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flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE);
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}
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static void ufs_send_request(int task_tag)
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||||
{
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||||
unsigned int data;
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||||
int slot;
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||||
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slot = task_tag - 1;
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||||
/* clear all interrupts */
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||||
mmio_write_32(ufs_params.reg_base + IS, ~0);
|
||||
|
||||
mmio_write_32(ufs_params.reg_base + UTRLRSR, 1);
|
||||
assert(mmio_read_32(ufs_params.reg_base + UTRLRSR) == 1);
|
||||
|
||||
data = UTRIACR_IAEN | UTRIACR_CTR | UTRIACR_IACTH(0x1F) |
|
||||
UTRIACR_IATOVAL(0xFF);
|
||||
mmio_write_32(ufs_params.reg_base + UTRIACR, data);
|
||||
/* send request */
|
||||
mmio_setbits_32(ufs_params.reg_base + UTRLDBR, 1 << slot);
|
||||
}
|
||||
|
||||
static int ufs_check_resp(utp_utrd_t *utrd, int trans_type)
|
||||
{
|
||||
utrd_header_t *hd;
|
||||
resp_upiu_t *resp;
|
||||
sense_data_t *sense;
|
||||
unsigned int data;
|
||||
int slot;
|
||||
|
||||
hd = (utrd_header_t *)utrd->header;
|
||||
resp = (resp_upiu_t *)utrd->resp_upiu;
|
||||
do {
|
||||
data = mmio_read_32(ufs_params.reg_base + IS);
|
||||
if ((data & ~(UFS_INT_UCCS | UFS_INT_UTRCS)) != 0)
|
||||
return -EIO;
|
||||
} while ((data & UFS_INT_UTRCS) == 0);
|
||||
slot = utrd->task_tag - 1;
|
||||
|
||||
data = mmio_read_32(ufs_params.reg_base + UTRLDBR);
|
||||
assert((data & (1 << slot)) == 0);
|
||||
/*
|
||||
* Invalidate the header after DMA read operation has
|
||||
* completed to avoid cpu referring to the prefetched
|
||||
* data brought in before DMA completion.
|
||||
*/
|
||||
inv_dcache_range((uintptr_t)hd, UFS_DESC_SIZE);
|
||||
assert(hd->ocs == OCS_SUCCESS);
|
||||
assert((resp->trans_type & TRANS_TYPE_CODE_MASK) == trans_type);
|
||||
|
||||
sense = &resp->sd.sense;
|
||||
if (sense->resp_code == SENSE_DATA_VALID &&
|
||||
sense->sense_key == SENSE_KEY_UNIT_ATTENTION && sense->asc == 0x29 &&
|
||||
sense->ascq == 0) {
|
||||
WARN("Unit Attention Condition\n");
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
(void)resp;
|
||||
(void)slot;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ufs_send_cmd(utp_utrd_t *utrd, uint8_t cmd_op, uint8_t lun, int lba, uintptr_t buf,
|
||||
size_t length)
|
||||
{
|
||||
int result, i;
|
||||
|
||||
for (i = 0; i < UFS_CMD_RETRIES; ++i) {
|
||||
get_utrd(utrd);
|
||||
result = ufs_prepare_cmd(utrd, cmd_op, lun, lba, buf, length);
|
||||
assert(result == 0);
|
||||
ufs_send_request(utrd->task_tag);
|
||||
result = ufs_check_resp(utrd, RESPONSE_UPIU);
|
||||
if (result == 0 || result == -EIO) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
assert(result == 0);
|
||||
(void)result;
|
||||
}
|
||||
|
||||
#ifdef UFS_RESP_DEBUG
|
||||
static void dump_upiu(utp_utrd_t *utrd)
|
||||
{
|
||||
utrd_header_t *hd;
|
||||
int i;
|
||||
|
||||
hd = (utrd_header_t *)utrd->header;
|
||||
INFO("utrd:0x%x, ruo:0x%x, rul:0x%x, ocs:0x%x, UTRLDBR:0x%x\n",
|
||||
(unsigned int)(uintptr_t)utrd, hd->ruo, hd->rul, hd->ocs,
|
||||
mmio_read_32(ufs_params.reg_base + UTRLDBR));
|
||||
for (i = 0; i < sizeof(utrd_header_t); i += 4) {
|
||||
INFO("[%lx]:0x%x\n",
|
||||
(uintptr_t)utrd->header + i,
|
||||
*(unsigned int *)((uintptr_t)utrd->header + i));
|
||||
}
|
||||
|
||||
for (i = 0; i < sizeof(cmd_upiu_t); i += 4) {
|
||||
INFO("cmd[%lx]:0x%x\n",
|
||||
utrd->upiu + i,
|
||||
*(unsigned int *)(utrd->upiu + i));
|
||||
}
|
||||
for (i = 0; i < sizeof(resp_upiu_t); i += 4) {
|
||||
INFO("resp[%lx]:0x%x\n",
|
||||
utrd->resp_upiu + i,
|
||||
*(unsigned int *)(utrd->resp_upiu + i));
|
||||
}
|
||||
for (i = 0; i < sizeof(prdt_t); i += 4) {
|
||||
INFO("prdt[%lx]:0x%x\n",
|
||||
utrd->prdt + i,
|
||||
*(unsigned int *)(utrd->prdt + i));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static void ufs_verify_init(void)
|
||||
{
|
||||
utp_utrd_t utrd;
|
||||
int result;
|
||||
|
||||
get_utrd(&utrd);
|
||||
ufs_prepare_nop_out(&utrd);
|
||||
ufs_send_request(utrd.task_tag);
|
||||
result = ufs_check_resp(&utrd, NOP_IN_UPIU);
|
||||
assert(result == 0);
|
||||
(void)result;
|
||||
}
|
||||
|
||||
static void ufs_verify_ready(void)
|
||||
{
|
||||
utp_utrd_t utrd;
|
||||
ufs_send_cmd(&utrd, CDBCMD_TEST_UNIT_READY, 0, 0, 0, 0);
|
||||
}
|
||||
|
||||
static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel,
|
||||
uintptr_t buf, size_t size)
|
||||
{
|
||||
utp_utrd_t utrd;
|
||||
query_resp_upiu_t *resp;
|
||||
int result;
|
||||
|
||||
switch (op) {
|
||||
case QUERY_READ_FLAG:
|
||||
case QUERY_READ_ATTR:
|
||||
case QUERY_READ_DESC:
|
||||
case QUERY_WRITE_DESC:
|
||||
case QUERY_WRITE_ATTR:
|
||||
assert(((buf & 3) == 0) && (size != 0));
|
||||
break;
|
||||
default:
|
||||
/* Do nothing in default case */
|
||||
break;
|
||||
}
|
||||
get_utrd(&utrd);
|
||||
ufs_prepare_query(&utrd, op, idn, index, sel, buf, size);
|
||||
ufs_send_request(utrd.task_tag);
|
||||
result = ufs_check_resp(&utrd, QUERY_RESPONSE_UPIU);
|
||||
assert(result == 0);
|
||||
resp = (query_resp_upiu_t *)utrd.resp_upiu;
|
||||
#ifdef UFS_RESP_DEBUG
|
||||
dump_upiu(&utrd);
|
||||
#endif
|
||||
assert(resp->query_resp == QUERY_RESP_SUCCESS);
|
||||
|
||||
switch (op) {
|
||||
case QUERY_READ_FLAG:
|
||||
*(uint32_t *)buf = (uint32_t)resp->ts.flag.value;
|
||||
break;
|
||||
case QUERY_READ_DESC:
|
||||
memcpy((void *)buf,
|
||||
(void *)(utrd.resp_upiu + sizeof(query_resp_upiu_t)),
|
||||
size);
|
||||
break;
|
||||
case QUERY_READ_ATTR:
|
||||
*(uint32_t *)buf = htobe32(resp->ts.attr.value);
|
||||
break;
|
||||
default:
|
||||
/* Do nothing in default case */
|
||||
break;
|
||||
}
|
||||
(void)result;
|
||||
}
|
||||
|
||||
unsigned int ufs_read_attr(int idn)
|
||||
{
|
||||
unsigned int value;
|
||||
|
||||
ufs_query(QUERY_READ_ATTR, idn, 0, 0,
|
||||
(uintptr_t)&value, sizeof(value));
|
||||
return value;
|
||||
}
|
||||
|
||||
void ufs_write_attr(int idn, unsigned int value)
|
||||
{
|
||||
ufs_query(QUERY_WRITE_ATTR, idn, 0, 0,
|
||||
(uintptr_t)&value, sizeof(value));
|
||||
}
|
||||
|
||||
unsigned int ufs_read_flag(int idn)
|
||||
{
|
||||
unsigned int value;
|
||||
|
||||
ufs_query(QUERY_READ_FLAG, idn, 0, 0,
|
||||
(uintptr_t)&value, sizeof(value));
|
||||
return value;
|
||||
}
|
||||
|
||||
void ufs_set_flag(int idn)
|
||||
{
|
||||
ufs_query(QUERY_SET_FLAG, idn, 0, 0, 0, 0);
|
||||
}
|
||||
|
||||
void ufs_clear_flag(int idn)
|
||||
{
|
||||
ufs_query(QUERY_CLEAR_FLAG, idn, 0, 0, 0, 0);
|
||||
}
|
||||
|
||||
void ufs_read_desc(int idn, int index, uintptr_t buf, size_t size)
|
||||
{
|
||||
ufs_query(QUERY_READ_DESC, idn, index, 0, buf, size);
|
||||
}
|
||||
|
||||
void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size)
|
||||
{
|
||||
ufs_query(QUERY_WRITE_DESC, idn, index, 0, buf, size);
|
||||
}
|
||||
|
||||
static int ufs_read_capacity(int lun, unsigned int *num, unsigned int *size)
|
||||
{
|
||||
utp_utrd_t utrd;
|
||||
resp_upiu_t *resp;
|
||||
sense_data_t *sense;
|
||||
unsigned char data[CACHE_WRITEBACK_GRANULE << 1];
|
||||
uintptr_t buf;
|
||||
int retries = UFS_READ_CAPACITY_RETRIES;
|
||||
|
||||
assert((ufs_params.reg_base != 0) &&
|
||||
(ufs_params.desc_base != 0) &&
|
||||
(ufs_params.desc_size >= UFS_DESC_SIZE) &&
|
||||
(num != NULL) && (size != NULL));
|
||||
|
||||
/* align buf address */
|
||||
buf = (uintptr_t)data;
|
||||
buf = (buf + CACHE_WRITEBACK_GRANULE - 1) &
|
||||
~(CACHE_WRITEBACK_GRANULE - 1);
|
||||
do {
|
||||
ufs_send_cmd(&utrd, CDBCMD_READ_CAPACITY_10, lun, 0,
|
||||
buf, READ_CAPACITY_LENGTH);
|
||||
#ifdef UFS_RESP_DEBUG
|
||||
dump_upiu(&utrd);
|
||||
#endif
|
||||
resp = (resp_upiu_t *)utrd.resp_upiu;
|
||||
sense = &resp->sd.sense;
|
||||
if (!((sense->resp_code == SENSE_DATA_VALID) &&
|
||||
(sense->sense_key == SENSE_KEY_UNIT_ATTENTION) &&
|
||||
(sense->asc == 0x29) && (sense->ascq == 0))) {
|
||||
inv_dcache_range(buf, CACHE_WRITEBACK_GRANULE);
|
||||
/* last logical block address */
|
||||
*num = be32toh(*(unsigned int *)buf);
|
||||
if (*num)
|
||||
*num += 1;
|
||||
/* logical block length in bytes */
|
||||
*size = be32toh(*(unsigned int *)(buf + 4));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
} while (retries-- > 0);
|
||||
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size)
|
||||
{
|
||||
utp_utrd_t utrd;
|
||||
resp_upiu_t *resp;
|
||||
|
||||
assert((ufs_params.reg_base != 0) &&
|
||||
(ufs_params.desc_base != 0) &&
|
||||
(ufs_params.desc_size >= UFS_DESC_SIZE));
|
||||
|
||||
ufs_send_cmd(&utrd, CDBCMD_READ_10, lun, lba, buf, size);
|
||||
#ifdef UFS_RESP_DEBUG
|
||||
dump_upiu(&utrd);
|
||||
#endif
|
||||
/*
|
||||
* Invalidate prefetched cache contents before cpu
|
||||
* accesses the buf.
|
||||
*/
|
||||
inv_dcache_range(buf, size);
|
||||
resp = (resp_upiu_t *)utrd.resp_upiu;
|
||||
return size - resp->res_trans_cnt;
|
||||
}
|
||||
|
||||
size_t ufs_write_blocks(int lun, int lba, const uintptr_t buf, size_t size)
|
||||
{
|
||||
utp_utrd_t utrd;
|
||||
resp_upiu_t *resp;
|
||||
|
||||
assert((ufs_params.reg_base != 0) &&
|
||||
(ufs_params.desc_base != 0) &&
|
||||
(ufs_params.desc_size >= UFS_DESC_SIZE));
|
||||
|
||||
ufs_send_cmd(&utrd, CDBCMD_WRITE_10, lun, lba, buf, size);
|
||||
#ifdef UFS_RESP_DEBUG
|
||||
dump_upiu(&utrd);
|
||||
#endif
|
||||
resp = (resp_upiu_t *)utrd.resp_upiu;
|
||||
return size - resp->res_trans_cnt;
|
||||
}
|
||||
|
||||
static int ufs_set_fdevice_init(void)
|
||||
{
|
||||
unsigned int result;
|
||||
int timeout;
|
||||
|
||||
ufs_set_flag(FLAG_DEVICE_INIT);
|
||||
|
||||
timeout = FDEVICEINIT_TIMEOUT_MS;
|
||||
do {
|
||||
result = ufs_read_flag(FLAG_DEVICE_INIT);
|
||||
if (!result) {
|
||||
break;
|
||||
}
|
||||
mdelay(5);
|
||||
timeout -= 5;
|
||||
} while (timeout > 0);
|
||||
|
||||
if (result != 0U) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ufs_enum(void)
|
||||
{
|
||||
unsigned int blk_num, blk_size;
|
||||
int i, result;
|
||||
|
||||
mmio_write_32(ufs_params.reg_base + UTRLBA,
|
||||
ufs_params.desc_base & UINT32_MAX);
|
||||
mmio_write_32(ufs_params.reg_base + UTRLBAU,
|
||||
(ufs_params.desc_base >> 32) & UINT32_MAX);
|
||||
|
||||
ufs_verify_init();
|
||||
ufs_verify_ready();
|
||||
|
||||
result = ufs_set_fdevice_init();
|
||||
assert(result == 0);
|
||||
|
||||
blk_num = 0;
|
||||
blk_size = 0;
|
||||
|
||||
/* dump available LUNs */
|
||||
for (i = 0; i < UFS_MAX_LUNS; i++) {
|
||||
result = ufs_read_capacity(i, &blk_num, &blk_size);
|
||||
if (result != 0) {
|
||||
WARN("UFS LUN%d dump failed\n", i);
|
||||
}
|
||||
if (blk_num && blk_size) {
|
||||
INFO("UFS LUN%d contains %d blocks with %d-byte size\n",
|
||||
i, blk_num, blk_size);
|
||||
}
|
||||
}
|
||||
|
||||
(void)result;
|
||||
}
|
||||
|
||||
static void ufs_get_device_info(struct ufs_dev_desc *card_data)
|
||||
{
|
||||
uint8_t desc_buf[DESC_DEVICE_MAX_SIZE];
|
||||
|
||||
ufs_query(QUERY_READ_DESC, DESC_TYPE_DEVICE, 0, 0,
|
||||
(uintptr_t)desc_buf, DESC_DEVICE_MAX_SIZE);
|
||||
|
||||
/*
|
||||
* getting vendor (manufacturerID) and Bank Index in big endian
|
||||
* format
|
||||
*/
|
||||
card_data->wmanufacturerid = (uint16_t)((desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8) |
|
||||
(desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]));
|
||||
}
|
||||
|
||||
int ufs_init(const ufs_ops_t *ops, ufs_params_t *params)
|
||||
{
|
||||
int result;
|
||||
unsigned int data;
|
||||
uic_cmd_t cmd;
|
||||
struct ufs_dev_desc card = {0};
|
||||
|
||||
assert((params != NULL) &&
|
||||
(params->reg_base != 0) &&
|
||||
(params->desc_base != 0) &&
|
||||
(params->desc_size >= UFS_DESC_SIZE));
|
||||
|
||||
memcpy(&ufs_params, params, sizeof(ufs_params_t));
|
||||
|
||||
/* 0 means 1 slot */
|
||||
nutrs = (mmio_read_32(ufs_params.reg_base + CAP) & CAP_NUTRS_MASK) + 1;
|
||||
if (nutrs > (ufs_params.desc_size / UFS_DESC_SIZE)) {
|
||||
nutrs = ufs_params.desc_size / UFS_DESC_SIZE;
|
||||
}
|
||||
|
||||
|
||||
if (ufs_params.flags & UFS_FLAGS_SKIPINIT) {
|
||||
mmio_write_32(ufs_params.reg_base + UTRLBA,
|
||||
ufs_params.desc_base & UINT32_MAX);
|
||||
mmio_write_32(ufs_params.reg_base + UTRLBAU,
|
||||
(ufs_params.desc_base >> 32) & UINT32_MAX);
|
||||
|
||||
result = ufshc_dme_get(0x1571, 0, &data);
|
||||
assert(result == 0);
|
||||
result = ufshc_dme_get(0x41, 0, &data);
|
||||
assert(result == 0);
|
||||
if (data == 1) {
|
||||
/* prepare to exit hibernate mode */
|
||||
memset(&cmd, 0, sizeof(uic_cmd_t));
|
||||
cmd.op = DME_HIBERNATE_EXIT;
|
||||
result = ufshc_send_uic_cmd(ufs_params.reg_base,
|
||||
&cmd);
|
||||
assert(result == 0);
|
||||
data = mmio_read_32(ufs_params.reg_base + UCMDARG2);
|
||||
assert(data == 0);
|
||||
do {
|
||||
data = mmio_read_32(ufs_params.reg_base + IS);
|
||||
} while ((data & UFS_INT_UHXS) == 0);
|
||||
mmio_write_32(ufs_params.reg_base + IS, UFS_INT_UHXS);
|
||||
data = mmio_read_32(ufs_params.reg_base + HCS);
|
||||
assert((data & HCS_UPMCRS_MASK) == HCS_PWR_LOCAL);
|
||||
}
|
||||
result = ufshc_dme_get(0x1568, 0, &data);
|
||||
assert(result == 0);
|
||||
assert((data > 0) && (data <= 3));
|
||||
} else {
|
||||
assert((ops != NULL) && (ops->phy_init != NULL) &&
|
||||
(ops->phy_set_pwr_mode != NULL));
|
||||
|
||||
result = ufshc_reset(ufs_params.reg_base);
|
||||
assert(result == 0);
|
||||
ops->phy_init(&ufs_params);
|
||||
result = ufshc_link_startup(ufs_params.reg_base);
|
||||
assert(result == 0);
|
||||
|
||||
ufs_enum();
|
||||
|
||||
ufs_get_device_info(&card);
|
||||
if (card.wmanufacturerid == UFS_VENDOR_SKHYNIX) {
|
||||
ufs_params.flags |= UFS_FLAGS_VENDOR_SKHYNIX;
|
||||
}
|
||||
|
||||
ops->phy_set_pwr_mode(&ufs_params);
|
||||
}
|
||||
|
||||
(void)result;
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user