GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CSS_MHU_H
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#define CSS_MHU_H
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#include <stdint.h>
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void mhu_secure_message_start(unsigned int slot_id);
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void mhu_secure_message_send(unsigned int slot_id);
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uint32_t mhu_secure_message_wait(void);
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void mhu_secure_message_end(unsigned int slot_id);
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void mhu_secure_init(void);
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#endif /* CSS_MHU_H */
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+44
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/*
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* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CSS_MHU_DOORBELL_H
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#define CSS_MHU_DOORBELL_H
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#include <stdint.h>
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#include <lib/mmio.h>
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/* MHUv2 Frame Base Mask */
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#define MHU_V2_FRAME_BASE_MASK UL(~0xFFF)
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/* MHUv2 Control Registers Offsets */
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#define MHU_V2_MSG_NO_CAP_OFFSET UL(0xF80)
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#define MHU_V2_ACCESS_REQ_OFFSET UL(0xF88)
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#define MHU_V2_ACCESS_READY_OFFSET UL(0xF8C)
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#define SENDER_REG_STAT(_channel) (0x20 * (_channel))
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#define SENDER_REG_SET(_channel) ((0x20 * (_channel)) + 0xC)
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/* Helper macro to ring doorbell */
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#define MHU_RING_DOORBELL(addr, modify_mask, preserve_mask) do { \
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uint32_t db = mmio_read_32(addr) & (preserve_mask); \
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mmio_write_32(addr, db | (modify_mask)); \
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} while (0)
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#define MHU_V2_ACCESS_REQUEST(addr) \
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mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x1)
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#define MHU_V2_CLEAR_REQUEST(addr) \
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mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x0)
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#define MHU_V2_IS_ACCESS_READY(addr) \
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(mmio_read_32((addr) + MHU_V2_ACCESS_READY_OFFSET) & 0x1)
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struct scmi_channel_plat_info;
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void mhu_ring_doorbell(struct scmi_channel_plat_info *plat_info);
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void mhuv2_ring_doorbell(struct scmi_channel_plat_info *plat_info);
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#endif /* CSS_MHU_DOORBELL_H */
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@@ -0,0 +1,52 @@
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/*
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* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CSS_SCP_H
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#define CSS_SCP_H
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#include <stdint.h>
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#include <platform_def.h>
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#include <lib/cassert.h>
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/* Forward declarations */
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struct psci_power_state;
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/* API for power management by SCP */
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int css_system_reset2(int is_vendor, int reset_type, u_register_t cookie);
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void css_scp_suspend(const struct psci_power_state *target_state);
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void css_scp_off(const struct psci_power_state *target_state);
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void css_scp_on(u_register_t mpidr);
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int css_scp_get_power_state(u_register_t mpidr, unsigned int power_level);
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void __dead2 css_scp_sys_shutdown(void);
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void __dead2 css_scp_sys_reboot(void);
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void __dead2 css_scp_system_off(int state);
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/* API for SCP Boot Image transfer. Return 0 on success, -1 on error */
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int css_scp_boot_image_xfer(void *image, unsigned int image_size);
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/*
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* API to wait for SCP to signal till it's ready after booting the transferred
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* image.
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*/
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int css_scp_boot_ready(void);
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#if CSS_LOAD_SCP_IMAGES
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/*
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* All CSS platforms load SCP_BL2/SCP_BL2U just below BL2 (this is where BL31
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* usually resides except when ARM_BL31_IN_DRAM is
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* set). Ensure that SCP_BL2/SCP_BL2U do not overflow into fw_config.
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*/
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CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
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CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
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CASSERT(SCP_BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2_overflow);
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CASSERT(SCP_BL2U_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2u_overflow);
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#endif
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#endif /* CSS_SCP_H */
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@@ -0,0 +1,109 @@
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/*
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* Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CSS_SCPI_H
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#define CSS_SCPI_H
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#include <stddef.h>
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#include <stdint.h>
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/*
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* An SCPI command consists of a header and a payload.
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* The following structure describes the header. It is 64-bit long.
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*/
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typedef struct {
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/* Command ID */
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uint32_t id : 7;
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/* Set ID. Identifies whether this is a standard or extended command. */
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uint32_t set : 1;
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/* Sender ID to match a reply. The value is sender specific. */
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uint32_t sender : 8;
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/* Size of the payload in bytes (0 - 511) */
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uint32_t size : 9;
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uint32_t reserved : 7;
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/*
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* Status indicating the success of a command.
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* See the enum below.
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*/
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uint32_t status;
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} scpi_cmd_t;
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typedef enum {
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SCPI_SET_NORMAL = 0, /* Normal SCPI commands */
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SCPI_SET_EXTENDED /* Extended SCPI commands */
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} scpi_set_t;
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enum {
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SCP_OK = 0, /* Success */
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SCP_E_PARAM, /* Invalid parameter(s) */
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SCP_E_ALIGN, /* Invalid alignment */
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SCP_E_SIZE, /* Invalid size */
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SCP_E_HANDLER, /* Invalid handler or callback */
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SCP_E_ACCESS, /* Invalid access or permission denied */
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SCP_E_RANGE, /* Value out of range */
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SCP_E_TIMEOUT, /* Time out has ocurred */
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SCP_E_NOMEM, /* Invalid memory area or pointer */
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SCP_E_PWRSTATE, /* Invalid power state */
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SCP_E_SUPPORT, /* Feature not supported or disabled */
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SCPI_E_DEVICE, /* Device error */
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SCPI_E_BUSY, /* Device is busy */
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};
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typedef uint32_t scpi_status_t;
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typedef enum {
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SCPI_CMD_SCP_READY = 0x01,
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SCPI_CMD_SET_CSS_POWER_STATE = 0x03,
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SCPI_CMD_GET_CSS_POWER_STATE = 0x04,
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SCPI_CMD_SYS_POWER_STATE = 0x05
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} scpi_command_t;
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/*
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* Macros to parse SCP response to GET_CSS_POWER_STATE command
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*
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* [3:0] : cluster ID
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* [7:4] : cluster state: 0 = on; 3 = off; rest are reserved
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* [15:8]: on/off state for individual CPUs in the cluster
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*
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* Payload is in little-endian
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*/
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#define CLUSTER_ID(_resp) ((_resp) & 0xf)
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#define CLUSTER_POWER_STATE(_resp) (((_resp) >> 4) & 0xf)
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/* Result is a bit mask of CPU on/off states in the cluster */
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#define CPU_POWER_STATE(_resp) (((_resp) >> 8) & 0xff)
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/*
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* For GET_CSS_POWER_STATE, SCP returns the power states of every cluster. The
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* size of response depends on the number of clusters in the system. The
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* SCP-to-AP payload contains 2 bytes per cluster. Make sure the response is
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* large enough to contain power states of a given cluster
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*/
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#define CHECK_RESPONSE(_resp, _clus) \
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(_resp.size >= (((_clus) + 1) * 2))
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typedef enum {
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scpi_power_on = 0,
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scpi_power_retention = 1,
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scpi_power_off = 3,
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} scpi_power_state_t;
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typedef enum {
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scpi_system_shutdown = 0,
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scpi_system_reboot = 1,
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scpi_system_reset = 2
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} scpi_system_state_t;
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int scpi_wait_ready(void);
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void scpi_set_css_power_state(unsigned int mpidr,
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scpi_power_state_t cpu_state,
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scpi_power_state_t cluster_state,
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scpi_power_state_t css_state);
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int scpi_get_css_power_state(unsigned int mpidr, unsigned int *cpu_state_p,
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unsigned int *cluster_state_p);
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uint32_t scpi_sys_power_state(scpi_system_state_t system_state);
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#endif /* CSS_SCPI_H */
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@@ -0,0 +1,176 @@
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/*
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* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SCMI_H
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#define SCMI_H
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#include <stddef.h>
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#include <stdint.h>
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#include <lib/bakery_lock.h>
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#include <lib/psci/psci.h>
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#include <lib/spinlock.h>
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/* Supported SCMI Protocol Versions */
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#define SCMI_AP_CORE_PROTO_VER MAKE_SCMI_VERSION(1, 0)
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#define SCMI_PWR_DMN_PROTO_VER MAKE_SCMI_VERSION(2, 0)
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#define SCMI_SYS_PWR_PROTO_VER MAKE_SCMI_VERSION(1, 0)
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#define GET_SCMI_MAJOR_VER(ver) (((ver) >> 16) & 0xffff)
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#define GET_SCMI_MINOR_VER(ver) ((ver) & 0xffff)
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#define MAKE_SCMI_VERSION(maj, min) \
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((((maj) & 0xffff) << 16) | ((min) & 0xffff))
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/*
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* Check that the driver's version is same or higher than the reported SCMI
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* version. We accept lower major version numbers, as all affected protocols
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* so far stay backwards compatible. This might need to be revisited in the
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* future.
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*/
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#define is_scmi_version_compatible(drv, scmi) \
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((GET_SCMI_MAJOR_VER(drv) > GET_SCMI_MAJOR_VER(scmi)) || \
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((GET_SCMI_MAJOR_VER(drv) == GET_SCMI_MAJOR_VER(scmi)) && \
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(GET_SCMI_MINOR_VER(drv) <= GET_SCMI_MINOR_VER(scmi))))
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/* SCMI Protocol identifiers */
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#define SCMI_PWR_DMN_PROTO_ID 0x11
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#define SCMI_SYS_PWR_PROTO_ID 0x12
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/* The AP core protocol is a CSS platform-specific extension */
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#define SCMI_AP_CORE_PROTO_ID 0x90
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/* Mandatory messages IDs for all SCMI protocols */
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#define SCMI_PROTO_VERSION_MSG 0x0
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#define SCMI_PROTO_ATTR_MSG 0x1
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#define SCMI_PROTO_MSG_ATTR_MSG 0x2
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/* SCMI power domain management protocol message IDs */
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#define SCMI_PWR_STATE_SET_MSG 0x4
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#define SCMI_PWR_STATE_GET_MSG 0x5
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/* SCMI system power management protocol message IDs */
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#define SCMI_SYS_PWR_STATE_SET_MSG 0x3
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#define SCMI_SYS_PWR_STATE_GET_MSG 0x4
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/* SCMI AP core protocol message IDs */
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#define SCMI_AP_CORE_RESET_ADDR_SET_MSG 0x3
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#define SCMI_AP_CORE_RESET_ADDR_GET_MSG 0x4
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/* Helper macros for system power management protocol commands */
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/*
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* Macros to describe the bit-fields of the `attribute` of system power domain
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* protocol PROTOCOL_MSG_ATTRIBUTE message.
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*/
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#define SYS_PWR_ATTR_WARM_RESET_SHIFT 31
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#define SCMI_SYS_PWR_WARM_RESET_SUPPORTED (1U << SYS_PWR_ATTR_WARM_RESET_SHIFT)
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#define SYS_PWR_ATTR_SUSPEND_SHIFT 30
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#define SCMI_SYS_PWR_SUSPEND_SUPPORTED (1 << SYS_PWR_ATTR_SUSPEND_SHIFT)
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/*
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* Macros to describe the bit-fields of the `flags` parameter of system power
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* domain protocol SYSTEM_POWER_STATE_SET message.
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*/
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#define SYS_PWR_SET_GRACEFUL_REQ_SHIFT 0
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#define SCMI_SYS_PWR_GRACEFUL_REQ (1 << SYS_PWR_SET_GRACEFUL_REQ_SHIFT)
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#define SCMI_SYS_PWR_FORCEFUL_REQ (0 << SYS_PWR_SET_GRACEFUL_REQ_SHIFT)
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/*
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* Macros to describe the `system_state` parameter of system power
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* domain protocol SYSTEM_POWER_STATE_SET message.
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*/
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#define SCMI_SYS_PWR_SHUTDOWN 0x0
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#define SCMI_SYS_PWR_COLD_RESET 0x1
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#define SCMI_SYS_PWR_WARM_RESET 0x2
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#define SCMI_SYS_PWR_POWER_UP 0x3
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#define SCMI_SYS_PWR_SUSPEND 0x4
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/*
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* Macros to describe the bit-fields of the `attribute` of AP core protocol
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* AP_CORE_RESET_ADDR set/get messages.
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*/
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#define SCMI_AP_CORE_LOCK_ATTR_SHIFT 0x0
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#define SCMI_AP_CORE_LOCK_ATTR (1U << SCMI_AP_CORE_LOCK_ATTR_SHIFT)
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/* SCMI Error code definitions */
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#define SCMI_E_QUEUED 1
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#define SCMI_E_SUCCESS 0
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#define SCMI_E_NOT_SUPPORTED -1
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#define SCMI_E_INVALID_PARAM -2
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#define SCMI_E_DENIED -3
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#define SCMI_E_NOT_FOUND -4
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#define SCMI_E_OUT_OF_RANGE -5
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#define SCMI_E_BUSY -6
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/*
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* SCMI driver platform information. The details of the doorbell mechanism
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* can be found in the SCMI specification.
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*/
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typedef struct scmi_channel_plat_info {
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/* SCMI mailbox memory */
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uintptr_t scmi_mbx_mem;
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/* The door bell register address */
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uintptr_t db_reg_addr;
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/* The bit mask that need to be preserved when ringing doorbell */
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uint32_t db_preserve_mask;
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/* The bit mask that need to be set to ring doorbell */
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uint32_t db_modify_mask;
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/* The handler for ringing doorbell */
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void (*ring_doorbell)(struct scmi_channel_plat_info *plat_info);
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/* cookie is unused now. But added for future enhancements. */
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void *cookie;
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} scmi_channel_plat_info_t;
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#if HW_ASSISTED_COHERENCY
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typedef spinlock_t scmi_lock_t;
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#else
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typedef bakery_lock_t scmi_lock_t;
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#endif
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/*
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* Structure to represent an SCMI channel.
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*/
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typedef struct scmi_channel {
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scmi_channel_plat_info_t *info;
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/* The lock for channel access */
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scmi_lock_t *lock;
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/* Indicate whether the channel is initialized */
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int is_initialized;
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} scmi_channel_t;
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/* External Common API */
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void *scmi_init(scmi_channel_t *ch);
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int scmi_proto_msg_attr(void *p, uint32_t proto_id, uint32_t command_id,
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uint32_t *attr);
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int scmi_proto_version(void *p, uint32_t proto_id, uint32_t *version);
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/*
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* Power domain protocol commands. Refer to the SCMI specification for more
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* details on these commands.
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*/
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int scmi_pwr_state_set(void *p, uint32_t domain_id, uint32_t scmi_pwr_state);
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int scmi_pwr_state_get(void *p, uint32_t domain_id, uint32_t *scmi_pwr_state);
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/*
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* System power management protocol commands. Refer SCMI specification for more
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* details on these commands.
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*/
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int scmi_sys_pwr_state_set(void *p, uint32_t flags, uint32_t system_state);
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int scmi_sys_pwr_state_get(void *p, uint32_t *system_state);
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/* SCMI AP core configuration protocol commands. */
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int scmi_ap_core_set_reset_addr(void *p, uint64_t reset_addr, uint32_t attr);
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int scmi_ap_core_get_reset_addr(void *p, uint64_t *reset_addr, uint32_t *attr);
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/* API to get the platform specific SCMI channel information. */
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scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id);
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/* API to override default PSCI callbacks for platforms that support SCMI. */
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const plat_psci_ops_t *css_scmi_override_pm_ops(plat_psci_ops_t *ops);
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#endif /* SCMI_H */
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@@ -0,0 +1,90 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
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||||
#ifndef SDS_H
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#define SDS_H
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||||
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||||
/* SDS Structure Identifier defines */
|
||||
/* AP CPU INFO defines */
|
||||
#define SDS_AP_CPU_INFO_STRUCT_ID 1
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#define SDS_AP_CPU_INFO_PRIMARY_CPUID_OFFSET 0x0
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||||
#define SDS_AP_CPU_INFO_PRIMARY_CPUID_SIZE 0x4
|
||||
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||||
/* ROM Firmware Version defines */
|
||||
#define SDS_ROM_VERSION_STRUCT_ID 2
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||||
#define SDS_ROM_VERSION_OFFSET 0x0
|
||||
#define SDS_ROM_VERSION_SIZE 0x4
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||||
|
||||
/* RAM Firmware version defines */
|
||||
#define SDS_RAM_VERSION_STRUCT_ID 3
|
||||
#define SDS_RAM_VERSION_OFFSET 0x0
|
||||
#define SDS_RAM_VERSION_SIZE 0x4
|
||||
|
||||
/* Platform Identity defines */
|
||||
#define SDS_PLATFORM_IDENTITY_STRUCT_ID 4
|
||||
#define SDS_PLATFORM_IDENTITY_ID_OFFSET 0x0
|
||||
#define SDS_PLATFORM_IDENTITY_ID_SIZE 0x4
|
||||
#define SDS_PLATFORM_IDENTITY_ID_CONFIG_SHIFT 28
|
||||
#define SDS_PLATFORM_IDENTITY_ID_CONFIG_WIDTH 4
|
||||
#define SDS_PLATFORM_IDENTITY_ID_CONFIG_MASK \
|
||||
((1 << SDS_PLATFORM_IDENTITY_ID_CONFIG_WIDTH) - 1)
|
||||
|
||||
#define SDS_PLATFORM_IDENTITY_PLAT_TYPE_OFFSET 0x4
|
||||
#define SDS_PLATFORM_IDENTITY_PLAT_TYPE_SIZE 0x4
|
||||
|
||||
/* Reset Syndrome defines */
|
||||
#define SDS_RESET_SYNDROME_STRUCT_ID 5
|
||||
#define SDS_RESET_SYNDROME_OFFSET 0
|
||||
#define SDS_RESET_SYNDROME_SIZE 4
|
||||
#define SDS_RESET_SYNDROME_POW_ON_RESET_BIT (1 << 0)
|
||||
#define SDS_RESET_SYNDROME_SCP_WD_RESET_BIT (1 << 1)
|
||||
#define SDS_RESET_SYNDROME_AP_WD_RESET_BIT (1 << 2)
|
||||
#define SDS_RESET_SYNDROME_SYS_RESET_REQ_BIT (1 << 3)
|
||||
#define SDS_RESET_SYNDROME_M3_LOCKUP_BIT (1 << 4)
|
||||
|
||||
/* SCP Firmware Feature Availability defines */
|
||||
#define SDS_FEATURE_AVAIL_STRUCT_ID 6
|
||||
#define SDS_FEATURE_AVAIL_OFFSET 0
|
||||
#define SDS_FEATURE_AVAIL_SIZE 4
|
||||
#define SDS_FEATURE_AVAIL_SCP_RAM_READY_BIT (1 << 0)
|
||||
#define SDS_FEATURE_AVAIL_DMC_READY_BIT (1 << 1)
|
||||
#define SDS_FEATURE_AVAIL_MSG_IF_READY_BIT (1 << 2)
|
||||
|
||||
/* SCP BL2 Image Metadata defines */
|
||||
#define SDS_SCP_IMG_STRUCT_ID 9
|
||||
#define SDS_SCP_IMG_FLAG_OFFSET 0
|
||||
#define SDS_SCP_IMG_FLAG_SIZE 4
|
||||
#define SDS_SCP_IMG_VALID_FLAG_BIT (1 << 0)
|
||||
#define SDS_SCP_IMG_ADDR_OFFSET 4
|
||||
#define SDS_SCP_IMG_ADDR_SIZE 4
|
||||
#define SDS_SCP_IMG_SIZE_OFFSET 8
|
||||
#define SDS_SCP_IMG_SIZE_SIZE 4
|
||||
|
||||
/* SDS Driver Error Codes */
|
||||
#define SDS_OK 0
|
||||
#define SDS_ERR_FAIL -1
|
||||
#define SDS_ERR_INVALID_PARAMS -2
|
||||
#define SDS_ERR_STRUCT_NOT_FOUND -3
|
||||
#define SDS_ERR_STRUCT_NOT_FINALIZED -4
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
typedef enum {
|
||||
SDS_ACCESS_MODE_NON_CACHED,
|
||||
SDS_ACCESS_MODE_CACHED,
|
||||
} sds_access_mode_t;
|
||||
|
||||
int sds_init(void);
|
||||
int sds_struct_exists(unsigned int structure_id);
|
||||
int sds_struct_read(uint32_t structure_id, unsigned int fld_off, void *data,
|
||||
size_t size, sds_access_mode_t mode);
|
||||
int sds_struct_write(uint32_t structure_id, unsigned int fld_off, void *data,
|
||||
size_t size, sds_access_mode_t mode);
|
||||
#endif /*__ASSEMBLER__ */
|
||||
|
||||
#endif /* SDS_H */
|
||||
Reference in New Issue
Block a user