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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
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source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/chimp.h
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/*
* Copyright (c) 2016 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SR_CHIMP_H
#define SR_CHIMP_H
#include <common/bl_common.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <platform_def.h>
#define CHIMP_WINDOW_SIZE 0x400000
#define CHIMP_ERROR_OFFSET 28
#define CHIMP_ERROR_MASK 0xf0000000
#ifndef EMULATION_SETUP
#define CHIMP_HANDSHAKE_TIMEOUT_MS 10000
#else
/*
* 1hr timeout for test in emulator
* By doing this ChiMP is given a chance to boot
* fully from the QSPI
* (on Palladium this takes upto 50 min depending on QSPI clk)
*/
#define CHIMP_HANDSHAKE_TIMEOUT_MS 3600000
#endif
#define CHIMP_BPE_MODE_ID_PATTERN (0x25000000)
#define CHIMP_BPE_MODE_ID_MASK (0x7f000000)
#define NIC_RESET_RELEASE_TIMEOUT_US (10)
/* written by M0, used by ChiMP ROM */
#define SR_IN_SMARTNIC_MODE_BIT 0
/* written by M0, used by ChiMP ROM */
#define SR_CHIMP_SECURE_BOOT_BIT 1
/* cleared by AP, set by ChiMP BC2 code */
#define SR_FLASH_ACCESS_DONE_BIT 2
#ifdef USE_CHIMP
void bcm_chimp_write(uintptr_t addr, uint32_t value);
uint32_t bcm_chimp_read(uintptr_t addr);
uint32_t bcm_chimp_read_ctrl(uint32_t offset);
void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits);
void bcm_chimp_setbits(uintptr_t addr, uint32_t bits);
int bcm_chimp_is_nic_mode(void);
void bcm_chimp_fru_prog_done(bool status);
int bcm_chimp_handshake_done(void);
int bcm_chimp_wait_handshake(void);
/* Fastboot-related*/
int bcm_chimp_initiate_fastboot(int fastboot_type);
#else
static inline void bcm_chimp_write(uintptr_t addr, uint32_t value)
{
}
static inline uint32_t bcm_chimp_read(uintptr_t addr)
{
return 0;
}
static inline uint32_t bcm_chimp_read_ctrl(uint32_t offset)
{
return 0;
}
static inline void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits)
{
}
static inline void bcm_chimp_setbits(uintptr_t addr, uint32_t bits)
{
}
static inline int bcm_chimp_is_nic_mode(void)
{
return 0;
}
static inline void bcm_chimp_fru_prog_done(bool status)
{
}
static inline int bcm_chimp_handshake_done(void)
{
return 0;
}
static inline int bcm_chimp_wait_handshake(void)
{
return 0;
}
static inline int bcm_chimp_initiate_fastboot(int fastboot_type)
{
return 0;
}
#endif /* USE_CHIMP */
#endif
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/chimp_nv_defs.h
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/*
* Copyright (c) 2016 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BNXNVM_DEFS_H
#define BNXNVM_DEFS_H
#if defined(__GNUC__)
#define PACKED_STRUCT __packed
#else /* non-GCC compiler */
#ifndef DOS_DRIVERS
#pragma pack(push)
#pragma pack(1)
#endif
#define PACKED_STRUCT
#endif
typedef uint32_t u32_t;
typedef uint8_t u8_t;
typedef uint16_t u16_t;
#define BNXNVM_DEFAULT_BLOCK_SIZE 4096
#define BNXNVM_UNUSED_BYTE_VALUE 0xff
#define NV_MAX_BLOCK_SIZE 16384
#define BITS_PER_BYTE (8)
#define SIZEOF_IN_BITS(x) (sizeof(x)*BITS_PER_BYTE)
/************************/
/* byte-swapping macros */
/************************/
#define BYTE_SWAP_16(x) \
((((u16_t)(x) & 0xff00) >> 8) | \
(((u16_t)(x) & 0x00ff) << 8))
#define BYTE_SWAP_32(x) \
((((u32_t)(x) & 0xff000000) >> 24) | \
(((u32_t)(x) & 0x00ff0000) >> 8) | \
(((u32_t)(x) & 0x0000ff00) << 8) | \
(((u32_t)(x) & 0x000000ff) << 24))
/* auto-detect integer size */
#define BYTE_SWAP_INT(x) \
(SIZEOF_IN_BITS(x) == 16 ? BYTE_SWAP_16(x) : \
SIZEOF_IN_BITS(x) == 32 ? BYTE_SWAP_32(x) : (x))
/********************************/
/* Architecture-specific macros */
/********************************/
#ifdef __BIG_ENDIAN__ /* e.g. Motorola */
#define BE_INT16(x) (x)
#define BE_INT32(x) (x)
#define BE_INT(x) (x)
#define LE_INT16(x) BYTE_SWAP_16(x)
#define LE_INT32(x) BYTE_SWAP_32(x)
#define LE_INT(x) BYTE_SWAP_INT(x)
#else /* Little Endian (e.g. Intel) */
#define LE_INT16(x) (x)
#define LE_INT32(x) (x)
#define LE_INT(x) (x)
#define BE_INT16(x) BYTE_SWAP_16(x)
#define BE_INT32(x) BYTE_SWAP_32(x)
#define BE_INT(x) BYTE_SWAP_INT(x)
#endif
enum {
NV_OK = 0,
NV_NOT_NVRAM,
NV_BAD_MB,
NV_BAD_DIR_HEADER,
NV_BAD_DIR_ENTRY,
NV_FW_NOT_FOUND,
};
typedef struct {
#define BNXNVM_MASTER_BLOCK_SIG BE_INT32(0x424E5834) /*"BNX4"*/
/* Signature*/
u32_t sig;
/* Length of Master Block Header, in bytes [32] */
u32_t length;
/* Block size, in bytes [4096] */
u32_t block_size;
/* Byte-offset to Directory Block (translated) */
u32_t directory_offset;
/* Byte-offset to Block Redirection Table (non-translated) */
u32_t redirect_offset;
/* Size, in bytes of Reserved Blocks region (at end of NVRAM) */
u32_t reserved_size;
/*
* Size of NVRAM (in bytes) - may be used to
* override auto-detected size
*/
u32_t nvram_size;
/* CRC-32 (IEEE 802.3 compatible) of the above */
u32_t chksum;
} PACKED_STRUCT bnxnvm_master_block_header_t;
typedef struct {
#define BNXNVM_DIRECTORY_BLOCK_SIG BE_INT32(0x44697230) /* "Dir0" */
/* Signature */
u32_t sig;
/* Length of Directory Header, in bytes [16] */
u32_t length;
/* Number of Directory Entries */
u32_t entries;
/* Length of each Directory Entry, in bytes [24] */
u32_t entry_length;
} PACKED_STRUCT bnxnvm_directory_block_header_t;
typedef struct {
/* Directory Entry Type (see enum bnxnvm_directory_type) */
u16_t type;
/* Instance of this Directory Entry type (0-based) */
u16_t ordinal;
/*
* Directory Entry Extension flags used to identify
* secondary instances of a type:ordinal combinations
*/
u16_t ext;
/* Directory Entry Attribute flags used to describe the item contents */
u16_t attr;
/* Item location in NVRAM specified as offset (in bytes) */
u32_t item_location;
/*
* Length of NVRAM item in bytes
* (including padding - multiple of block size)
*/
u32_t item_length;
/* Length of item data in bytes (excluding padding) */
u32_t data_length;
/*
* CRC-32 (IEEE 802.3 compatible) of item data
* (excluding padding) (optional)
*/
u32_t data_chksum;
} PACKED_STRUCT bnxnvm_directory_entry_t;
enum bnxnvm_version_format {
/* US-ASCII string (not necessarily null-terminated) */
BNX_VERSION_FMT_ASCII = 0,
/* Each field 16-bits, displayed as unpadded decimal (e.g. "1.2.3.4") */
BNX_VERSION_FMT_DEC = 1,
/* A single hexadecimal value, up to 64-bits (no dots) */
BNX_VERSION_FMT_HEX = 2,
/* Multiple version values (three 8-bit version fields) */
BNX_VERSION_FMT_MULTI = 3
};
/* This structure definition must not change: */
typedef struct {
u16_t flags; /* bit-flags (defaults to 0x0000) */
u8_t version_format; /* enum bnxnvm_version_format */
u8_t version_length; /* in bytes */
u8_t version[16]; /* version value */
u16_t dir_type; /* enum bnxnvm_directory_type */
/* size of the entire trailer (to locate end of component data) */
u16_t trailer_length;
#define BNXNVM_COMPONENT_TRAILER_SIG BE_INT32(0x54726c72) /* "Trlr" */
u32_t sig;
u32_t chksum; /* CRC-32 of all bytes to this point */
} PACKED_STRUCT bnxnvm_component_trailer_base_t;
typedef struct {
/*
* new trailer members (e.g. digital signature)
* go here (insert at top):
*/
u8_t rsa_sig[256]; /* 2048-bit RSA-encrypted SHA-256 hash */
bnxnvm_component_trailer_base_t base;
} PACKED_STRUCT bnxnvm_component_trailer_t;
#define BNX_MAX_LEN_DIR_NAME 12
#define BNX_MAX_LEN_DIR_DESC 50
/*********************************************************
* NVRAM Directory Entry/Item Types, Names, and Descriptions
*
* If you see a name or description that needs improvement,
* please correct it or raise for discussion.
* When adding a new directory type, it would be appreciated
* if you also updated ../../libs/nvm/bnxt_nvm_str.c.
* DIR_NAME macros may contain up to 12 alpha-numeric
* US-ASCII characters only, camelCase is preferred for clarity.
* DIR_DESC macros may contain up to 50 US-ASCII characters
* providing a verbose description of the directory type.
*/
enum bnxnvm_directory_type {
/* 0x00 Unused directory entry, available for use */
BNX_DIR_TYPE_UNUSED = 0,
#define BNX_DIR_NAME_UNUSED "unused"
#define BNX_DIR_DESC_UNUSED "Deleted directory entry, available for reuse"
/* 0x01 Package installation log */
BNX_DIR_TYPE_PKG_LOG = 1,
#define BNX_DIR_NAME_PKG_LOG "pkgLog"
#define BNX_DIR_DESC_PKG_LOG "Package Installation Log"
BNX_DIR_TYPE_CHIMP_PATCH = 3,
#define BNX_DIR_NAME_CHIMP_PATCH "chimpPatch"
#define BNX_DIR_DESC_CHIMP_PATCH "ChiMP Patch Firmware"
/* 0x04 ChiMP firmware: Boot Code phase 1 */
BNX_DIR_TYPE_BOOTCODE = 4,
#define BNX_DIR_NAME_BOOTCODE "chimpBoot"
#define BNX_DIR_DESC_BOOTCODE "Chip Management Processor Boot Firmware"
/* 0x05 VPD data block */
BNX_DIR_TYPE_VPD = 5,
#define BNX_DIR_NAME_VPD "VPD"
#define BNX_DIR_DESC_VPD "Vital Product Data"
/* 0x06 Exp ROM MBA */
BNX_DIR_TYPE_EXP_ROM_MBA = 6,
#define BNX_DIR_NAME_EXP_ROM_MBA "MBA"
#define BNX_DIR_DESC_EXP_ROM_MBA "Multiple Boot Agent Expansion ROM"
BNX_DIR_TYPE_AVS = 7, /* 0x07 AVS FW */
#define BNX_DIR_NAME_AVS "AVS"
#define BNX_DIR_DESC_AVS "Adaptive Voltage Scaling Firmware"
BNX_DIR_TYPE_PCIE = 8, /* 0x08 PCIE FW */
#define BNX_DIR_NAME_PCIE "PCIEucode"
#define BNX_DIR_DESC_PCIE "PCIe Microcode"
BNX_DIR_TYPE_PORT_MACRO = 9, /* 0x09 PORT MACRO FW */
#define BNX_DIR_NAME_PORT_MACRO "portMacro"
#define BNX_DIR_DESC_PORT_MACRO "Port Macro Firmware"
BNX_DIR_TYPE_APE_FW = 10, /* 0x0A APE Firmware */
#define BNX_DIR_NAME_APE_FW "apeFW"
#define BNX_DIR_DESC_APE_FW "Application Processing Engine Firmware"
/* 0x0B Patch firmware executed by APE ROM */
BNX_DIR_TYPE_APE_PATCH = 11,
#define BNX_DIR_NAME_APE_PATCH "apePatch"
#define BNX_DIR_DESC_APE_PATCH "APE Patch Firmware"
BNX_DIR_TYPE_KONG_FW = 12, /* 0x0C Kong Firmware */
#define BNX_DIR_NAME_KONG_FW "kongFW"
#define BNX_DIR_DESC_KONG_FW "Kong Firmware"
/* 0x0D Patch firmware executed by Kong ROM */
BNX_DIR_TYPE_KONG_PATCH = 13,
#define BNX_DIR_NAME_KONG_PATCH "kongPatch"
#define BNX_DIR_DESC_KONG_PATCH "Kong Patch Firmware"
BNX_DIR_TYPE_BONO_FW = 14, /* 0x0E Bono Firmware */
#define BNX_DIR_NAME_BONO_FW "bonoFW"
#define BNX_DIR_DESC_BONO_FW "Bono Firmware"
/* 0x0F Patch firmware executed by Bono ROM */
BNX_DIR_TYPE_BONO_PATCH = 15,
#define BNX_DIR_NAME_BONO_PATCH "bonoPatch"
#define BNX_DIR_DESC_BONO_PATCH "Bono Patch Firmware"
BNX_DIR_TYPE_TANG_FW = 16, /* 0x10 Tang firmware */
#define BNX_DIR_NAME_TANG_FW "tangFW"
#define BNX_DIR_DESC_TANG_FW "Tang Firmware"
/* 0x11 Patch firmware executed by Tang ROM */
BNX_DIR_TYPE_TANG_PATCH = 17,
#define BNX_DIR_NAME_TANG_PATCH "tangPatch"
#define BNX_DIR_DESC_TANG_PATCH "Tang Patch Firmware"
/* 0x12 ChiMP firmware: Boot Code phase 2 (loaded by phase 1) */
BNX_DIR_TYPE_BOOTCODE_2 = 18,
#define BNX_DIR_NAME_BOOTCODE_2 "chimpHWRM"
#define BNX_DIR_DESC_BOOTCODE_2 "ChiMP Hardware Resource Manager Firmware"
BNX_DIR_TYPE_CCM = 19, /* 0x13 CCM ROM binary */
#define BNX_DIR_NAME_CCM "CCM"
#define BNX_DIR_DESC_CCM "Comprehensive Configuration Management"
/* 0x14 PCI-IDs, PCI-related configuration properties */
BNX_DIR_TYPE_PCI_CFG = 20,
#define BNX_DIR_NAME_PCI_CFG "pciCFG"
#define BNX_DIR_DESC_PCI_CFG "PCIe Configuration Data"
BNX_DIR_TYPE_TSCF_UCODE = 21, /* 0x15 TSCF micro-code */
#define BNX_DIR_NAME_TSCF_UCODE "PHYucode"
#define BNX_DIR_DESC_TSCF_UCODE "Falcon PHY Microcode"
BNX_DIR_TYPE_ISCSI_BOOT = 22, /* 0x16 iSCSI Boot */
#define BNX_DIR_NAME_ISCSI_BOOT "iSCSIboot"
#define BNX_DIR_DESC_ISCSI_BOOT "iSCSI Boot Software Initiator"
/* 0x18 iSCSI Boot IPV6 - ***DEPRECATED*** */
BNX_DIR_TYPE_ISCSI_BOOT_IPV6 = 24,
/* 0x19 iSCSI Boot IPV4N6 - ***DEPRECATED*** */
BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6 = 25,
BNX_DIR_TYPE_ISCSI_BOOT_CFG = 26, /* 0x1a iSCSI Boot CFG v6 */
#define BNX_DIR_NAME_ISCSI_BOOT_CFG "iSCSIcfg"
#define BNX_DIR_DESC_ISCSI_BOOT_CFG "iSCSI Boot Configuration Data"
BNX_DIR_TYPE_EXT_PHY = 27, /* 0x1b External PHY FW */
#define BNX_DIR_NAME_EXT_PHY "extPHYfw"
#define BNX_DIR_DESC_EXT_PHY "External PHY Firmware"
BNX_DIR_TYPE_MODULES_PN = 28, /* 0x1c Modules PartNum list */
#define BNX_DIR_NAME_MODULES_PN "modPartNums"
#define BNX_DIR_DESC_MODULES_PN "Optical Modules Part Number List"
BNX_DIR_TYPE_SHARED_CFG = 40, /* 0x28 shared configuration block */
#define BNX_DIR_NAME_SHARED_CFG "sharedCFG"
#define BNX_DIR_DESC_SHARED_CFG "Shared Configuration Data"
BNX_DIR_TYPE_PORT_CFG = 41, /* 0x29 port configuration block */
#define BNX_DIR_NAME_PORT_CFG "portCFG"
#define BNX_DIR_DESC_PORT_CFG "Port Configuration Data"
BNX_DIR_TYPE_FUNC_CFG = 42, /* 0x2A func configuration block */
#define BNX_DIR_NAME_FUNC_CFG "funcCFG"
#define BNX_DIR_DESC_FUNC_CFG "Function Configuration Data"
/* Management Firmware (TruManage) related dir entries*/
/* 0x30 Management firmware configuration (see BMCFG library)*/
BNX_DIR_TYPE_MGMT_CFG = 48,
#define BNX_DIR_NAME_MGMT_CFG "mgmtCFG"
#define BNX_DIR_DESC_MGMT_CFG "Out-of-band Management Configuration Data"
BNX_DIR_TYPE_MGMT_DATA = 49, /* 0x31 "Opaque Management Data" */
#define BNX_DIR_NAME_MGMT_DATA "mgmtData"
#define BNX_DIR_DESC_MGMT_DATA "Out-of-band Management Data"
BNX_DIR_TYPE_MGMT_WEB_DATA = 50, /* 0x32 "Web GUI" file data */
#define BNX_DIR_NAME_MGMT_WEB_DATA "webData"
#define BNX_DIR_DESC_MGMT_WEB_DATA "Out-of-band Management Web Data"
/* 0x33 "Web GUI" file metadata */
BNX_DIR_TYPE_MGMT_WEB_META = 51,
#define BNX_DIR_NAME_MGMT_WEB_META "webMeta"
#define BNX_DIR_DESC_MGMT_WEB_META "Out-of-band Management Web Metadata"
/* 0x34 Management firmware Event Log (a.k.a. "SEL") */
BNX_DIR_TYPE_MGMT_EVENT_LOG = 52,
#define BNX_DIR_NAME_MGMT_EVENT_LOG "eventLog"
#define BNX_DIR_DESC_MGMT_EVENT_LOG "Out-of-band Management Event Log"
/* 0x35 Management firmware Audit Log */
BNX_DIR_TYPE_MGMT_AUDIT_LOG = 53
#define BNX_DIR_NAME_MGMT_AUDIT_LOG "auditLog"
#define BNX_DIR_DESC_MGMT_AUDIT_LOG "Out-of-band Management Audit Log"
};
/* For backwards compatibility only, may be removed later */
#define BNX_DIR_TYPE_ISCSI_BOOT_CFG6 BNX_DIR_TYPE_ISCSI_BOOT_CFG
/* Firmware NVM items of "APE BIN" format are identified with
* the following macro:
*/
#define BNX_DIR_TYPE_IS_APE_BIN_FMT(type)\
((type) == BNX_DIR_TYPE_CHIMP_PATCH \
|| (type) == BNX_DIR_TYPE_BOOTCODE \
|| (type) == BNX_DIR_TYPE_BOOTCODE_2 \
|| (type) == BNX_DIR_TYPE_APE_FW \
|| (type) == BNX_DIR_TYPE_APE_PATCH \
|| (type) == BNX_DIR_TYPE_TANG_FW \
|| (type) == BNX_DIR_TYPE_TANG_PATCH \
|| (type) == BNX_DIR_TYPE_KONG_FW \
|| (type) == BNX_DIR_TYPE_KONG_PATCH \
|| (type) == BNX_DIR_TYPE_BONO_FW \
|| (type) == BNX_DIR_TYPE_BONO_PATCH \
)
/* Other (non APE BIN) executable NVM items are identified with
* the following macro:
*/
#define BNX_DIR_TYPE_IS_OTHER_EXEC(type)\
((type) == BNX_DIR_TYPE_AVS \
|| (type) == BNX_DIR_TYPE_EXP_ROM_MBA \
|| (type) == BNX_DIR_TYPE_PCIE \
|| (type) == BNX_DIR_TYPE_TSCF_UCODE \
|| (type) == BNX_DIR_TYPE_EXT_PHY \
|| (type) == BNX_DIR_TYPE_CCM \
|| (type) == BNX_DIR_TYPE_ISCSI_BOOT \
)
/* Executable NVM items (e.g. microcode, firmware, software) identified
* with the following macro
*/
#define BNX_DIR_TYPE_IS_EXECUTABLE(type) \
(BNX_DIR_TYPE_IS_APE_BIN_FMT(type) \
|| BNX_DIR_TYPE_IS_OTHER_EXEC(type))
#define BNX_DIR_ORDINAL_FIRST 0 /* Ordinals are 0-based */
/* No extension flags for this directory entry */
#define BNX_DIR_EXT_NONE 0
/* Directory entry is inactive (not used, not hidden,
* not available for reuse)
*/
#define BNX_DIR_EXT_INACTIVE (1 << 0)
/* Directory content is a temporary staging location for
* updating the primary (non-update) directory entry contents
* (e.g. performing a secure firmware update)
*/
#define BNX_DIR_EXT_UPDATE (1 << 1)
/* No attribute flags set for this directory entry */
#define BNX_DIR_ATTR_NONE 0
/* Directory entry checksum of contents is purposely incorrect */
#define BNX_DIR_ATTR_NO_CHKSUM (1 << 0)
/* Directory contents are in the form of a property-stream
* (e.g. configuration properties)
*/
#define BNX_DIR_ATTR_PROP_STREAM (1 << 1)
/* Directory content (e.g. iSCSI boot) supports IPv4 */
#define BNX_DIR_ATTR_IPv4 (1 << 2)
/* Directory content (e.g. iSCSI boot) supports IPv6 */
#define BNX_DIR_ATTR_IPv6 (1 << 3)
/* Directory content includes standard NVM component trailer
* (bnxnvm_component_trailer_t)
*/
#define BNX_DIR_ATTR_TRAILER (1 << 4)
/* Index of tab-delimited fields in each package log
* (BNX_DIR_TYPE_PKG_LOG) record (\n-terminated line):
*/
enum bnxnvm_pkglog_field_index {
/* Package installation date/time in ISO-8601 format */
BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP = 0,
/* Installed package description (from package header) or "N/A" */
BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION = 1,
/* Installed package version string (from package header) or "N/A" */
BNX_PKG_LOG_FIELD_IDX_PKG_VERSION = 2,
/* Installed package creation/modification timestamp (ISO-8601) */
BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP = 3,
/* Installed package checksum in hexadecimal (CRC-32) or "N/A" */
BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM = 4,
/* Total number of packaged items applied in this installation */
BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5,
/* Hexadecimal bit-mask identifying which items were installed */
BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6
};
#if !defined(__GNUC__)
#ifndef DOS_DRIVERS
#pragma pack(pop) /* original packing */
#endif
#endif
#endif /* Don't add anything after this line */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/dmu.h
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/*
* Copyright (c) 2015 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef DMU_H
#define DMU_H
/* Clock field should be 2 bits only */
#define CLKCONFIG_MASK 0x3
/* argument */
struct DmuBlockEnable {
uint32_t sotp:1;
uint32_t pka_rng:1;
uint32_t crypto:1;
uint32_t spl:1;
uint32_t cdru_vgm:1;
uint32_t apbs_s0_idm:1;
uint32_t smau_s0_idm:1;
};
/* prototype */
uint32_t bcm_dmu_block_enable(struct DmuBlockEnable dbe);
uint32_t bcm_dmu_block_disable(struct DmuBlockEnable dbe);
uint32_t bcm_set_ihost_pll_freq(uint32_t cluster_num, int ihost_pll_freq_sel);
uint32_t bcm_get_ihost_pll_freq(uint32_t cluster_num);
#define PLL_FREQ_BYPASS 0x0
#define PLL_FREQ_FULL 0x1
#define PLL_FREQ_HALF 0x2
#define PLL_FREQ_QRTR 0x3
#endif
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/emmc/bcm_emmc.h
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/*
* Copyright (c) 2016 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef EMMC_H
#define EMMC_H
#include <stdint.h>
#include <common/debug.h>
#include <platform_def.h>
#include "emmc_chal_types.h"
#include "emmc_chal_sd.h"
#include "emmc_csl_sdprot.h"
#include "emmc_csl_sdcmd.h"
#include "emmc_pboot_hal_memory_drv.h"
/* ------------------------------------------------------------------- */
#define EXT_CSD_SIZE 512
#ifdef PLAT_SD_MAX_READ_LENGTH
#define SD_MAX_READ_LENGTH PLAT_SD_MAX_READ_LENGTH
#ifdef USE_EMMC_LARGE_BLK_TRANSFER_LENGTH
#define SD_MAX_BLK_TRANSFER_LENGTH 0x10000000
#else
#define SD_MAX_BLK_TRANSFER_LENGTH 0x1000
#endif
#else
#define SD_MAX_READ_LENGTH EMMC_BLOCK_SIZE
#define SD_MAX_BLK_TRANSFER_LENGTH EMMC_BLOCK_SIZE
#endif
struct emmc_global_buffer {
union {
uint8_t Ext_CSD_storage[EXT_CSD_SIZE];
uint8_t tempbuf[SD_MAX_READ_LENGTH];
} u;
};
struct emmc_global_vars {
struct sd_card_data cardData;
struct sd_handle sdHandle;
struct sd_dev sdDevice;
struct sd_card_info sdCard;
unsigned int init_done;
};
#define ICFG_SDIO0_CAP0__SLOT_TYPE_R 27
#define ICFG_SDIO0_CAP0__INT_MODE_R 26
#define ICFG_SDIO0_CAP0__SYS_BUS_64BIT_R 25
#define ICFG_SDIO0_CAP0__VOLTAGE_1P8V_R 24
#define ICFG_SDIO0_CAP0__VOLTAGE_3P0V_R 23
#define ICFG_SDIO0_CAP0__VOLTAGE_3P3V_R 22
#define ICFG_SDIO0_CAP0__SUSPEND_RESUME_R 21
#define ICFG_SDIO0_CAP0__SDMA_R 20
#define ICFG_SDIO0_CAP0__HIGH_SPEED_R 19
#define ICFG_SDIO0_CAP0__ADMA2_R 18
#define ICFG_SDIO0_CAP0__EXTENDED_MEDIA_R 17
#define ICFG_SDIO0_CAP0__MAX_BLOCK_LEN_R 15
#define ICFG_SDIO0_CAP0__BASE_CLK_FREQ_R 7
#define ICFG_SDIO0_CAP0__TIMEOUT_UNIT_R 6
#define ICFG_SDIO0_CAP0__TIMEOUT_CLK_FREQ_R 0
#define ICFG_SDIO0_CAP1__SPI_BLOCK_MODE_R 22
#define ICFG_SDIO0_CAP1__SPI_MODE_R 21
#define ICFG_SDIO0_CAP1__CLK_MULT_R 13
#define ICFG_SDIO0_CAP1__RETUNING_MODE_R 11
#define ICFG_SDIO0_CAP1__TUNE_SDR50_R 10
#define ICFG_SDIO0_CAP1__TIME_RETUNE_R 6
#define ICFG_SDIO0_CAP1__DRIVER_D_R 5
#define ICFG_SDIO0_CAP1__DRIVER_C_R 4
#define ICFG_SDIO0_CAP1__DRIVER_A_R 3
#define ICFG_SDIO0_CAP1__DDR50_R 2
#define ICFG_SDIO0_CAP1__SDR104_R 1
#define ICFG_SDIO0_CAP1__SDR50_R 0
#define SDIO0_CTRL_REGS_BASE_ADDR (SDIO0_EMMCSDXC_SYSADDR)
#define SDIO0_IDM_RESET_CTRL_ADDR (SDIO_IDM0_IDM_RESET_CONTROL)
#define EMMC_CTRL_REGS_BASE_ADDR SDIO0_CTRL_REGS_BASE_ADDR
#define EMMC_IDM_RESET_CTRL_ADDR SDIO0_IDM_RESET_CTRL_ADDR
#define EMMC_IDM_IO_CTRL_DIRECT_ADDR SDIO_IDM0_IO_CONTROL_DIRECT
extern struct emmc_global_buffer *emmc_global_buf_ptr;
extern struct emmc_global_vars *emmc_global_vars_ptr;
#define EMMC_CARD_DETECT_TIMEOUT_MS 1200
#define EMMC_CMD_TIMEOUT_MS 200
#define EMMC_BUSY_CMD_TIMEOUT_MS 200
#define EMMC_CLOCK_SETTING_TIMEOUT_MS 100
#define EMMC_WFE_RETRY 40000
#define EMMC_WFE_RETRY_DELAY_US 10
#ifdef EMMC_DEBUG
#define EMMC_TRACE INFO
#else
#define EMMC_TRACE(...)
#endif
#endif /* EMMC_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/emmc/emmc_api.h
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/*
* Copyright (c) 2016 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef EMMC_API_H
#define EMMC_API_H
#include "bcm_emmc.h"
#include "emmc_pboot_hal_memory_drv.h"
#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE
/*
* The erasable unit of the eMMC is the Erase Group
* Erase group is measured in write blocks which
* are the basic writable units of the Device
* EMMC_ERASE_GROUP_SIZE is the number of writeable
* units (each unit is 512 bytes)
*/
/* Start address (sector) */
#define EMMC_ERASE_START_BLOCK 0x0
/* Number of blocks to be erased */
#define EMMC_ERASE_BLOCK_COUNT 0x1
#define EMMC_ERASE_USER_AREA 0
#define EMMC_ERASE_BOOT_PARTITION1 1
#define EMMC_ERASE_BOOT_PARTITION2 2
/* eMMC partition to be erased */
#define EMMC_ERASE_PARTITION EMMC_ERASE_USER_AREA
#endif
uint32_t bcm_emmc_init(bool card_rdy_only);
void emmc_deinit(void);
#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE
int emmc_erase(uintptr_t mem_addr, size_t num_of_blocks, uint32_t partition);
#endif
uint32_t emmc_partition_select(uint32_t partition);
uint32_t emmc_read(uintptr_t mem_addr, uintptr_t storage_addr,
size_t storage_size, size_t bytes_to_read);
uint32_t emmc_write(uintptr_t mem_addr, uintptr_t data_addr,
size_t bytes_to_write);
#endif /* EMMC_API_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/emmc/emmc_brcm_rdb_sd4_top.h
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source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/emmc/emmc_chal_sd.h
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/*
* Copyright (c) 2016 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CHAL_SD_H
#define CHAL_SD_H
#include <stddef.h>
#define BASE_CLK_FREQ (200 * 1000 * 1000)
#define INIT_CLK_FREQ (400 * 1000)
#define SD_ERROR_RECOVERABLE 0
#define SD_ERROR_NON_RECOVERABLE 1
#define SD_OK 0
#define SD_FAIL (-1)
#define SD_INVALID_HANDLE (-2)
#define SD_CEATA_INIT_ERROR (-3)
#define SD_RESET_ERROR (-4)
#define SD_CARD_INIT_ERROR (-5)
#define SD_INV_DATA_WIDTH (-6)
#define SD_SET_BUS_WIDTH_ERROR (-7)
#define SD_DMA_NOT_SUPPORT (-8)
#define SD_SDIO_READ_ERROR (-9)
#define SD_SDIO_WRITE_ERROR (-10)
#define SD_WRITE_ERROR (-11)
#define SD_READ_ERROR (-12)
#define SD_READ_SIZE_ERROR (-13)
#define SD_RW_ADDRESS_ERROR (-14)
#define SD_XFER_ADDRESS_ERROR (-15)
#define SD_DATA_XFER_ADDR_ERROR (-16)
#define SD_DATA_XFER_ERROR (-17)
#define SD_WRITE_SIZE_ERROR (-18)
#define SD_CMD_STATUS_UPDATE_ERR (-19)
#define SD_CMD12_ERROR (-20)
#define SD_CMD_DATA_ERROR (-21)
#define SD_CMD_TIMEOUT (-22)
#define SD_CMD_NO_RESPONSE (-22)
#define SD_CMD_ABORT_ERROR (-23)
#define SD_CMD_INVALID (-24)
#define SD_CMD_RESUME_ERROR (-25)
#define SD_CMD_ERR_INVALID_RESPONSE (-26)
#define SD_WAIT_TIMEOUT (-27)
#define SD_READ_TIMEOUT (-28)
#define SD_CEATA_REST_ERROR (-29)
#define SD_INIT_CAED_FAILED (-30)
#define SD_ERROR_CLOCK_OFFLIMIT (-31)
#define SD_INV_SLOT (-32)
#define SD_NOR_INTERRUPTS 0x000000FF
#define SD_ERR_INTERRUPTS 0x03FF0000
#define SD_CMD_ERROR_INT 0x010F0000
#define SD_DAT_ERROR_INT 0x02F00000
#define SD_DAT_TIMEOUT 0x00100000
/* Operation modes */
#define SD_PIO_MODE 0
#define SD_INT_MODE 1
/* Support both ADMA and SDMA (for version 2.0 and above) */
#define SD_DMA_OFF 0
#define SD_DMA_SDMA 1
#define SD_DMA_ADMA 2
#define SD_NORMAL_SPEED 0
#define SD_HIGH_SPEED 1
#define SD_XFER_CARD_TO_HOST 3
#define SD_XFER_HOST_TO_CARD 4
#define SD_CARD_DETECT_AUTO 0
#define SD_CARD_DETECT_SD 1
#define SD_CARD_DETECT_SDIO 2
#define SD_CARD_DETECT_MMC 3
#define SD_CARD_DETECT_CEATA 4
#define SD_ABORT_SYNC_MODE 0
#define SD_ABORT_ASYNC_MODE 1
#define SD_CMD_ERROR_FLAGS (0x18F << 16)
#define SD_DATA_ERROR_FLAGS (0x70 << 16)
#define SD_AUTO_CMD12_ERROR_FLAGS (0x9F)
#define SD_CARD_STATUS_ERROR 0x10000000
#define SD_CMD_MISSING 0x80000000
#define SD_ERROR_INT 0x8000
#define SD_TRAN_HIGH_SPEED 0x32
#define SD_CARD_HIGH_CAPACITY 0x40000000
#define SD_CARD_POWER_UP_STATUS 0x80000000
#define SD_HOST_CORE_TIMEOUT 0x0E
/* SD CARD and Host Controllers bus width */
#define SD_BUS_DATA_WIDTH_1BIT 0x00
#define SD_BUS_DATA_WIDTH_4BIT 0x02
#define SD_BUS_DATA_WIDTH_8BIT 0x20
/* dma boundary settings */
#define SD_DMA_BOUNDARY_4K 0
#define SD_DMA_BOUNDARY_8K (1 << 12)
#define SD_DMA_BOUNDARY_16K (2 << 12)
#define SD_DMA_BOUNDARY_32K (3 << 12)
#define SD_DMA_BOUNDARY_64K (4 << 12)
#define SD_DMA_BOUNDARY_128K (5 << 12)
#define SD_DMA_BOUNDARY_256K (6 << 12)
#define SD_DMA_BOUNDARY_512K (7 << 12)
#define SD_CMDR_CMD_NORMAL 0x00000000
#define SD_CMDR_CMD_SUSPEND 0x00400000
#define SD_CMDR_CMD_RESUME 0x00800000
#define SD_CMDR_CMD_ABORT 0x00c00000
#define SD_CMDR_RSP_TYPE_NONE 0x0
#define SD_CMDR_RSP_TYPE_R2 0x1
#define SD_CMDR_RSP_TYPE_R3_4 0x2
#define SD_CMDR_RSP_TYPE_R1_5_6 0x2
#define SD_CMDR_RSP_TYPE_R1b_5b 0x3
#define SD_CMDR_RSP_TYPE_S 16
struct sd_ctrl_info {
uint32_t blkReg; /* current block register cache value */
uint32_t cmdReg; /* current command register cache value */
uint32_t argReg; /* current argument register cache value */
uint32_t cmdIndex; /* current command index */
uint32_t cmdStatus; /* current command status, cmd/data compelete */
uint16_t rca; /* relative card address */
uint32_t ocr; /* operation codition */
uint32_t eventList; /* events list */
uint32_t blkGapEnable;
uint32_t capability; /* controller's capbilities */
uint32_t maxCurrent; /* maximum current supported */
uint32_t present; /* if card is inserted or removed */
uint32_t version; /* SD spec version 1.0 or 2.0 */
uint32_t vendor; /* vendor number */
uintptr_t sdRegBaseAddr; /* sdio control registers */
uintptr_t hostRegBaseAddr; /* SD Host control registers */
};
struct sd_cfg {
uint32_t mode; /* interrupt or polling */
uint32_t dma; /* dma enabled or disabled */
uint32_t retryLimit; /* command retry limit */
uint32_t speedMode; /* speed mode, 0 standard, 1 high speed */
uint32_t voltage; /* voltage level */
uint32_t blockSize; /* access block size (512 for HC card) */
uint32_t dmaBoundary; /* dma address boundary */
uint32_t detSignal; /* card det signal src, for test purpose only */
uint32_t rdWaiting;
uint32_t wakeupOut;
uint32_t wakeupIn;
uint32_t wakeupInt;
uint32_t wfe_retry;
uint32_t gapInt;
uint32_t readWait;
uint32_t led;
};
struct sd_dev {
struct sd_cfg cfg; /* SD configuration */
struct sd_ctrl_info ctrl; /* SD info */
};
int32_t chal_sd_start(CHAL_HANDLE *sdHandle, uint32_t mode,
uint32_t sdBase, uint32_t hostBase);
int32_t chal_sd_config(CHAL_HANDLE *sdHandle, uint32_t speed,
uint32_t retry, uint32_t boundary,
uint32_t blkSize, uint32_t dma);
int32_t chal_sd_stop(void);
int32_t chal_sd_set_dma(CHAL_HANDLE *sdHandle, uint32_t mode);
uintptr_t chal_sd_get_dma_addr(CHAL_HANDLE *handle);
int32_t chal_sd_config_bus_width(CHAL_HANDLE *sdHandle, int32_t width);
int32_t chal_sd_send_cmd(CHAL_HANDLE *sdHandle, uint32_t cmdIndex,
uint32_t arg, uint32_t options);
int32_t chal_sd_set_dma_addr(CHAL_HANDLE *sdHandle, uintptr_t address);
int32_t chal_sd_set_clock(CHAL_HANDLE *sdHandle,
uint32_t div_ctrl_setting, uint32_t on);
uint32_t chal_sd_freq_2_div_ctrl_setting(uint32_t desired_freq);
int32_t chal_sd_setup_xfer(CHAL_HANDLE *sdHandle, uint8_t *data,
uint32_t length, int32_t dir);
int32_t chal_sd_write_buffer(CHAL_HANDLE *sdHandle, uint32_t length,
uint8_t *data);
int32_t chal_sd_read_buffer(CHAL_HANDLE *sdHandle, uint32_t length,
uint8_t *data);
int32_t chal_sd_reset_line(CHAL_HANDLE *sdHandle, uint32_t line);
int32_t chal_sd_get_response(CHAL_HANDLE *sdHandle, uint32_t *resp);
int32_t chal_sd_clear_pending_irq(CHAL_HANDLE *sdHandle);
int32_t chal_sd_get_irq_status(CHAL_HANDLE *sdHandle);
int32_t chal_sd_clear_irq(CHAL_HANDLE *sdHandle, uint32_t mask);
uint32_t chal_sd_get_present_status(CHAL_HANDLE *sdHandle);
int32_t chal_sd_get_atuo12_error(CHAL_HANDLE *sdHandle);
void chal_sd_set_speed(CHAL_HANDLE *sdHandle, uint32_t speed);
int32_t chal_sd_check_cap(CHAL_HANDLE *sdHandle, uint32_t cap);
void chal_sd_set_irq_signal(CHAL_HANDLE *sdHandle, uint32_t mask,
uint32_t state);
void chal_sd_dump_fifo(CHAL_HANDLE *sdHandle);
#endif /* CHAL_SD_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/emmc/emmc_chal_types.h
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/*
* Copyright (c) 2016 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CHAL_TYPES_H
#define CHAL_TYPES_H
#include <stdint.h>
//
// Generic cHAL handler
//
#ifndef CHAL_HANDLE
typedef void *CHAL_HANDLE; ///< void pointer (32 bits wide)
#endif
#endif /* _CHAL_TYPES_H_ */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/emmc/emmc_csl_sd.h
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/*
* Copyright (c) 2016 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CSL_SD_H
#define CSL_SD_H
#define SD_CLOCK_BASE 104000000
#define SD_CLOCK_52MHZ 52000000
#define SD_CLOCK_26MHZ 26000000
#define SD_CLOCK_17MHZ 17330000
#define SD_CLOCK_13MHZ 13000000
#define SD_CLOCK_10MHZ 10000000
#define SD_CLOCK_9MHZ 9000000
#define SD_CLOCK_7MHZ 7000000
#define SD_CLOCK_5MHZ 5000000
#define SD_CLOCK_1MHZ 1000000
#define SD_CLOCK_400KHZ 400000
#define SD_DRIVE_STRENGTH_MASK 0x38000000
#if defined(_BCM213x1_) || defined(_BCM21551_) || defined(_ATHENA_)
#define SD_DRIVE_STRENGTH 0x28000000
#elif defined(_BCM2153_)
#define SD_DRIVE_STRENGTH 0x38000000
#else
#define SD_DRIVE_STRENGTH 0x00000000
#endif
#define SD_NUM_HOST 2
#define SD_CARD_UNLOCK 0
#define SD_CARD_LOCK 0x4
#define SD_CARD_CLEAR_PWD 0x2
#define SD_CARD_SET_PWD 0x1
#define SD_CARD_ERASE_PWD 0x8
#define SD_CARD_LOCK_STATUS 0x02000000
#define SD_CARD_UNLOCK_STATUS 0x01000000
#define SD_CMD_ERROR_FLAGS (0x18F << 16)
#define SD_DATA_ERROR_FLAGS (0x70 << 16)
#define SD_AUTO_CMD12_ERROR_FLAGS (0x9F)
#define SD_CARD_STATUS_ERROR 0x10000000
#define SD_CMD_MISSING 0x80000000
#define SD_TRAN_HIGH_SPEED 0x32
#define SD_CARD_HIGH_CAPACITY 0x40000000
#define SD_CARD_POWER_UP_STATUS 0x80000000
struct sd_dev_info {
uint32_t mode; /* interrupt or polling */
uint32_t dma; /* dma enabled or disabled */
uint32_t voltage; /* voltage level */
uint32_t slot; /* if the HC is locatd at slot 0 or slot 1 */
uint32_t version; /* 1.0 or 2.0 */
uint32_t curSystemAddr; /* system address */
uint32_t dataWidth; /* data width for the controller */
uint32_t clock; /* clock rate */
uint32_t status; /* if device is active on transfer or not */
};
void data_xfer_setup(struct sd_handle *handle, uint8_t *data,
uint32_t length, int dir);
int reset_card(struct sd_handle *handle);
int reset_host_ctrl(struct sd_handle *handle);
int init_card(struct sd_handle *handle, int detection);
int init_mmc_card(struct sd_handle *handle);
int write_buffer(struct sd_handle *handle, uint32_t len, uint8_t *buffer);
int read_buffer(struct sd_handle *handle, uint32_t len, uint8_t *buffer);
int select_blk_sz(struct sd_handle *handle, uint16_t size);
int check_error(struct sd_handle *handle, uint32_t ints);
int process_data_xfer(struct sd_handle *handle, uint8_t *buffer,
uint32_t addr, uint32_t length, int dir);
int read_block(struct sd_handle *handle, uint8_t *dst, uint32_t addr,
uint32_t len);
#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE
int erase_card(struct sd_handle *handle, uint32_t addr, uint32_t blocks);
#endif
int write_block(struct sd_handle *handle, uint8_t *src, uint32_t addr,
uint32_t len);
int process_cmd_response(struct sd_handle *handle, uint32_t cmdIndex,
uint32_t rsp0, uint32_t rsp1, uint32_t rsp2,
uint32_t rsp3, struct sd_resp *resp);
int32_t set_config(struct sd_handle *handle, uint32_t speed,
uint32_t retry, uint32_t dma, uint32_t dmaBound,
uint32_t blkSize, uint32_t wfe_retry);
uint32_t wait_for_event(struct sd_handle *handle, uint32_t mask,
uint32_t retry);
int set_boot_config(struct sd_handle *handle, uint32_t config);
int mmc_cmd1(struct sd_handle *handle);
#endif /* CSL_SD_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/emmc/emmc_csl_sdcmd.h
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/*
* Copyright (c) 2016 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CSL_SD_CMD_H
#define CSL_SD_CMD_H
#define SD_CMD_OK 0
#define SD_CMD_ERROR -1
#define SD_CMD_ERR_NO_IO_FUNC 5
#define SD_CMD_ERR_INVALID_PARAMETER 6
#define SD_CMD_ERR_R1_ILLEGAL_COMMAND 7
#define SD_CMD_ERR_R1_COM_CRC_ERROR 8
#define SD_CMD_ERR_R1_FUNC_NUM_ERROR 9
#define SD_CMD_ERR_R1_ADDRESS_ERROR 10
#define SD_CMD_ERR_R1_PARAMETER_ERROR 11
#define SD_CMD_ERR_DATA_ERROR_TOKEN 12
#define SD_CMD_ERR_DATA_NOT_ACCEPTED 13
#define SD_CMD7_ARG_RCA_SHIFT 16
#define SD_CARD_STATUS_PENDING 0x01
#define SD_CARD_STATUS_BUFFER_OVERFLOW 0x01
#define SD_CARD_STATUS_DEVICE_BUSY 0x02
#define SD_CARD_STATUS_UNSUCCESSFUL 0x03
#define SD_CARD_STATUS_NOT_IMPLEMENTED 0x04
#define SD_CARD_STATUS_ACCESS_VIOLATION 0x05
#define SD_CARD_STATUS_INVALID_HANDLE 0x06
#define SD_CARD_STATUS_INVALID_PARAMETER 0x07
#define SD_CARD_STATUS_NO_SUCH_DEVICE 0x08
#define SD_CARD_STATUS_INVALID_DEVICE_REQUEST 0x09
#define SD_CARD_STATUS_NO_MEMORY 0x0A
#define SD_CARD_STATUS_BUS_DRIVER_NOT_READY 0x0B
#define SD_CARD_STATUS_DATA_ERROR 0x0C
#define SD_CARD_STATUS_CRC_ERROR 0x0D
#define SD_CARD_STATUS_INSUFFICIENT_RESOURCES 0x0E
#define SD_CARD_STATUS_DEVICE_NOT_CONNECTED 0x10
#define SD_CARD_STATUS_DEVICE_REMOVED 0x11
#define SD_CARD_STATUS_DEVICE_NOT_RESPONDING 0x12
#define SD_CARD_STATUS_CANCELED 0x13
#define SD_CARD_STATUS_RESPONSE_TIMEOUT 0x14
#define SD_CARD_STATUS_DATA_TIMEOUT 0x15
#define SD_CARD_STATUS_DEVICE_RESPONSE_ERROR 0x16
#define SD_CARD_STATUS_DEVICE_UNSUPPORTED 0x17
/* Response structure */
struct sd_r2_resp {
uint32_t rsp4; /* 127:96 */
uint32_t rsp3; /* 95:64 */
uint32_t rsp2; /* 63:32 */
uint32_t rsp1; /* 31:0 */
};
struct sd_r3_resp {
uint32_t ocr;
};
struct sd_r4_resp {
uint8_t cardReady;
uint8_t funcs;
uint8_t memPresent;
uint32_t ocr;
};
struct sd_r5_resp {
uint8_t data;
};
struct sd_r6_resp {
uint16_t rca;
uint16_t cardStatus;
};
struct sd_r7_resp {
uint16_t rca;
};
struct sd_resp {
uint8_t r1;
uint32_t cardStatus;
uint32_t rawData[4];
union {
struct sd_r2_resp r2;
struct sd_r3_resp r3;
struct sd_r4_resp r4;
struct sd_r5_resp r5;
struct sd_r6_resp r6;
struct sd_r7_resp r7;
} data;
};
struct sd_card_info {
uint32_t type; /* card type SD, MMC or SDIO */
uint64_t size; /* card size */
uint32_t speed; /* card speed */
uint32_t voltage; /* voltage supported */
uint32_t mId; /* manufacturer ID */
uint32_t oId; /* OEM ID */
uint32_t classes; /* card class */
uint32_t name1; /* product name part 1 */
uint32_t name2; /* product name part 2 */
uint32_t revision; /* revison */
uint32_t sn; /* serial number */
uint32_t numIoFuns; /* total I/O function number */
uint32_t maxRdBlkLen; /* max read block length */
uint32_t maxWtBlkLen; /* max write block length */
uint32_t blkMode; /* sdio card block mode support */
uint32_t f0Cis; /* sdio card block mode support */
uint32_t f1Cis; /* sdio card block mode support */
uint8_t partRead; /* partial block read allowed */
uint8_t partWrite; /* partial block write allowed */
uint8_t dsr; /* card DSR */
uint8_t rdCurMin; /* min current for read */
uint8_t rdCurMax; /* max current for read */
uint8_t wtCurMin; /* min current for write */
uint8_t wtCurMax; /* max current for write */
uint8_t erase; /* erase enable */
uint8_t eraseSecSize; /* erase sector size */
uint8_t proGrpSize; /* write protection group size */
uint8_t protect; /* permanent write protection or not */
uint8_t tmpProt; /* temp write protection or not */
uint8_t wtSpeed; /* write speed relatively to read */
uint8_t version; /* card version 0:1.0 - 1.01, 1:1.10, 2:2.0 */
uint8_t eraseState; /* if the data will be 0 or 1 after erase */
uint8_t bus; /* data with supported */
uint8_t security; /* security support 0, 2:1.01 3:2.0 */
uint8_t format; /* file format */
uint8_t fileGrp; /* file group */
char pwd[20]; /* password */
};
struct sd_handle {
struct sd_dev *device;
struct sd_card_info *card;
};
int sd_cmd0(struct sd_handle *handle);
int sd_cmd1(struct sd_handle *handle, uint32_t initOcr, uint32_t *ocr);
int sd_cmd2(struct sd_handle *handle);
int sd_cmd3(struct sd_handle *handle);
int sd_cmd7(struct sd_handle *handle, uint32_t rca);
int sd_cmd9(struct sd_handle *handle, struct sd_card_data *card);
int sd_cmd13(struct sd_handle *handle, uint32_t *status);
int sd_cmd16(struct sd_handle *handle, uint32_t blockLen);
int sd_cmd17(struct sd_handle *handle,
uint32_t addr, uint32_t len, uint8_t *buffer);
int sd_cmd18(struct sd_handle *handle,
uint32_t addr, uint32_t len, uint8_t *buffer);
#ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
int sd_cmd24(struct sd_handle *handle,
uint32_t addr, uint32_t len, uint8_t *buffer);
int sd_cmd25(struct sd_handle *handle,
uint32_t addr, uint32_t len, uint8_t *buffer);
#endif
#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE
int sd_cmd35(struct sd_handle *handle, uint32_t start);
int sd_cmd36(struct sd_handle *handle, uint32_t end);
int sd_cmd38(struct sd_handle *handle);
#endif
int mmc_cmd6(struct sd_handle *handle, uint32_t argument);
int mmc_cmd8(struct sd_handle *handle, uint8_t *extCsdReg);
int send_cmd(struct sd_handle *handle, uint32_t cmdIndex,
uint32_t argument, uint32_t options, struct sd_resp *resp);
#endif /* CSL_SD_CMD_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/emmc/emmc_csl_sdprot.h
+435
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/*
* Copyright (c) 2016 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CSL_SD_PROT_H
#define CSL_SD_PROT_H
#define SD_CARD_UNKNOWN 0 /* bad type or unrecognized */
#define SD_CARD_SD 1 /* IO only card */
#define SD_CARD_SDIO 2 /* memory only card */
#define SD_CARD_COMBO 3 /* IO and memory combo card */
#define SD_CARD_MMC 4 /* memory only card */
#define SD_CARD_CEATA 5 /* IO and memory combo card */
#define SD_IO_FIXED_ADDRESS 0 /* fix Address */
#define SD_IO_INCREMENT_ADDRESS 1
#define SD_HIGH_CAPACITY_CARD 0x40000000
#define MMC_CMD_IDLE_RESET_ARG 0xF0F0F0F0
/* Supported operating voltages are 3.2-3.3 and 3.3-3.4 */
#define MMC_OCR_OP_VOLT 0x00300000
/* Enable sector access mode */
#define MMC_OCR_SECTOR_ACCESS_MODE 0x40000000
/* command index */
#define SD_CMD_GO_IDLE_STATE 0 /* mandatory for SDIO */
#define SD_CMD_SEND_OPCOND 1
#define SD_CMD_ALL_SEND_CID 2
#define SD_CMD_MMC_SET_RCA 3
#define SD_CMD_MMC_SET_DSR 4
#define SD_CMD_IO_SEND_OP_COND 5 /* mandatory for SDIO */
#define SD_ACMD_SET_BUS_WIDTH 6
#define SD_CMD_SWITCH_FUNC 6
#define SD_CMD_SELECT_DESELECT_CARD 7
#define SD_CMD_READ_EXT_CSD 8
#define SD_CMD_SEND_CSD 9
#define SD_CMD_SEND_CID 10
#define SD_CMD_STOP_TRANSMISSION 12
#define SD_CMD_SEND_STATUS 13
#define SD_ACMD_SD_STATUS 13
#define SD_CMD_GO_INACTIVE_STATE 15
#define SD_CMD_SET_BLOCKLEN 16
#define SD_CMD_READ_SINGLE_BLOCK 17
#define SD_CMD_READ_MULTIPLE_BLOCK 18
#define SD_CMD_WRITE_BLOCK 24
#define SD_CMD_WRITE_MULTIPLE_BLOCK 25
#define SD_CMD_PROGRAM_CSD 27
#define SD_CMD_SET_WRITE_PROT 28
#define SD_CMD_CLR_WRITE_PROT 29
#define SD_CMD_SEND_WRITE_PROT 30
#define SD_CMD_ERASE_WR_BLK_START 32
#define SD_CMD_ERASE_WR_BLK_END 33
#define SD_CMD_ERASE_GROUP_START 35
#define SD_CMD_ERASE_GROUP_END 36
#define SD_CMD_ERASE 38
#define SD_CMD_LOCK_UNLOCK 42
#define SD_CMD_IO_RW_DIRECT 52 /* mandatory for SDIO */
#define SD_CMD_IO_RW_EXTENDED 53 /* mandatory for SDIO */
#define SD_CMD_APP_CMD 55
#define SD_CMD_GEN_CMD 56
#define SD_CMD_READ_OCR 58
#define SD_CMD_CRC_ON_OFF 59 /* mandatory for SDIO */
#define SD_ACMD_SEND_NUM_WR_BLOCKS 22
#define SD_ACMD_SET_WR_BLOCK_ERASE_CNT 23
#define SD_ACMD_SD_SEND_OP_COND 41
#define SD_ACMD_SET_CLR_CARD_DETECT 42
#define SD_ACMD_SEND_SCR 51
/* response parameters */
#define SD_RSP_NO_NONE 0
#define SD_RSP_NO_1 1
#define SD_RSP_NO_2 2
#define SD_RSP_NO_3 3
#define SD_RSP_NO_4 4
#define SD_RSP_NO_5 5
#define SD_RSP_NO_6 6
/* Modified R6 response (to CMD3) */
#define SD_RSP_MR6_COM_CRC_ERROR 0x8000
#define SD_RSP_MR6_ILLEGAL_COMMAND 0x4000
#define SD_RSP_MR6_ERROR 0x2000
/* Modified R1 in R4 Response (to CMD5) */
#define SD_RSP_MR1_SBIT 0x80
#define SD_RSP_MR1_PARAMETER_ERROR 0x40
#define SD_RSP_MR1_RFU5 0x20
#define SD_RSP_MR1_FUNC_NUM_ERROR 0x10
#define SD_RSP_MR1_COM_CRC_ERROR 0x80
#define SD_RSP_MR1_ILLEGAL_COMMAND 0x40
#define SD_RSP_MR1_RFU1 0x20
#define SD_RSP_MR1_IDLE_STATE 0x01
/* R5 response (to CMD52 and CMD53) */
#define SD_RSP_R5_COM_CRC_ERROR 0x80
#define SD_RSP_R5_ILLEGAL_COMMAND 0x40
#define SD_RSP_R5_IO_CURRENTSTATE1 0x20
#define SD_RSP_R5_IO_CURRENTSTATE0 0x10
#define SD_RSP_R5_ERROR 0x80
#define SD_RSP_R5_RFU 0x40
#define SD_RSP_R5_FUNC_NUM_ERROR 0x20
#define SD_RSP_R5_OUT_OF_RANGE 0x01
/* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */
#define SD_OP_READ 0 /* Read_Write */
#define SD_OP_WRITE 1 /* Read_Write */
#define SD_RW_NORMAL 0 /* no RAW */
#define SD_RW_RAW 1 /* RAW */
#define SD_BYTE_MODE 0 /* Byte Mode */
#define SD_BLOCK_MODE 1 /* BlockMode */
#define SD_FIXED_ADDRESS 0 /* fix Address */
#define SD_INCREMENT_ADDRESS 1 /* IncrementAddress */
#define SD_CMD5_ARG_IO_OCR_MASK 0x00FFFFFF
#define SD_CMD5_ARG_IO_OCR_SHIFT 0
#define SD_CMD55_ARG_RCA_SHIFT 16
#define SD_CMD59_ARG_CRC_OPTION_MASK 0x01
#define SD_CMD59_ARG_CRC_OPTION_SHIFT 0
/* SD_CMD_IO_RW_DIRECT Argument */
#define SdioIoRWDirectArg(rw, raw, func, addr, data) \
(((rw & 1) << 31) | ((func & 0x7) << 28) | \
((raw & 1) << 27) | ((addr & 0x1FFFF) << 9) | \
(data & 0xFF))
/* build SD_CMD_IO_RW_EXTENDED Argument */
#define SdioIoRWExtArg(rw, blk, func, addr, inc_addr, count) \
(((rw & 1) << 31) | ((func & 0x7) << 28) | \
((blk & 1) << 27) | ((inc_addr & 1) << 26) | \
((addr & 0x1FFFF) << 9) | (count & 0x1FF))
/*
* The Common I/O area shall be implemented on all SDIO cards and
* is accessed the the host via I/O reads and writes to function 0,
* the registers within the CIA are provided to enable/disable
* the operationo fthe i/o funciton.
*/
/* cccr_sdio_rev */
#define SDIO_REV_SDIOID_MASK 0xf0 /* SDIO spec revision number */
#define SDIO_REV_CCCRID_MASK 0x0f /* CCCR format version number */
/* sd_rev */
#define SDIO_REV_PHY_MASK 0x0f /* SD format version number */
#define SDIO_FUNC_ENABLE_1 0x02 /* function 1 I/O enable */
#define SDIO_FUNC_READY_1 0x02 /* function 1 I/O ready */
#define SDIO_INTR_CTL_FUNC1_EN 0x2 /* interrupt enable for function 1 */
#define SDIO_INTR_CTL_MASTER_EN 0x1 /* interrupt enable master */
#define SDIO_INTR_STATUS_FUNC1 0x2 /* interrupt pending for function 1 */
#define SDIO_IO_ABORT_RESET_ALL 0x08 /* I/O card reset */
#define SDIO_IO_ABORT_FUNC_MASK 0x07 /* abort selection: function x */
#define SDIO_BUS_CARD_DETECT_DIS 0x80 /* Card Detect disable */
#define SDIO_BUS_SPI_CONT_INTR_CAP 0x40 /* support continuous SPI interrupt */
#define SDIO_BUS_SPI_CONT_INTR_EN 0x20 /* continuous SPI interrupt enable */
#define SDIO_BUS_DATA_WIDTH_MASK 0x03 /* bus width mask */
#define SDIO_BUS_DATA_WIDTH_4BIT 0x02 /* bus width 4-bit mode */
#define SDIO_BUS_DATA_WIDTH_1BIT 0x00 /* bus width 1-bit mode */
/* capability */
#define SDIO_CAP_4BLS 0x80 /* 4-bit support for low speed card */
#define SDIO_CAP_LSC 0x40 /* low speed card */
#define SDIO_CAP_E4MI 0x20 /* enable int between block in 4-bit mode */
#define SDIO_CAP_S4MI 0x10 /* support int between block in 4-bit mode */
#define SDIO_CAP_SBS 0x08 /* support suspend/resume */
#define SDIO_CAP_SRW 0x04 /* support read wait */
#define SDIO_CAP_SMB 0x02 /* support multi-block transfer */
#define SDIO_CAP_SDC 0x01 /* Support Direct cmd during multi-uint8 transfer */
/* CIA FBR1 registers */
#define SDIO_FUNC1_INFO 0x100 /* basic info for function 1 */
#define SDIO_FUNC1_EXT 0x101 /* extension of standard I/O device */
#define SDIO_CIS_FUNC1_BASE_LOW 0x109 /* function 1 cis address bit 0-7 */
#define SDIO_CIS_FUNC1_BASE_MID 0x10A /* function 1 cis address bit 8-15 */
#define SDIO_CIS_FUNC1_BASE_HIGH 0x10B /* function 1 cis address bit 16 */
#define SDIO_CSA_BASE_LOW 0x10C /* CSA base address uint8_t 0 */
#define SDIO_CSA_BASE_MID 0x10D /* CSA base address uint8_t 1 */
#define SDIO_CSA_BASE_HIGH 0x10E /* CSA base address uint8_t 2 */
#define SDIO_CSA_DATA_OFFSET 0x10F /* CSA data register */
#define SDIO_IO_BLK_SIZE_LOW 0x110 /* I/O block size uint8_t 0 */
#define SDIO_IO_BLK_SIZE_HIGH 0x111 /* I/O block size uint8_t 1 */
/* SD_SDIO_FUNC1_INFO bits */
#define SDIO_FUNC1_INFO_DIC 0x0f /* device interface code */
#define SDIO_FUNC1_INFO_CSA 0x40 /* CSA support flag */
#define SDIO_FUNC1_INFO_CSA_EN 0x80 /* CSA enabled */
/* SD_SDIO_FUNC1_EXT bits */
#define SDIO_FUNC1_EXT_SHP 0x03 /* support high power */
#define SDIO_FUNC1_EXT_EHP 0x04 /* enable high power */
/* devctr */
/* I/O device interface code */
#define SDIO_DEVCTR_DEVINTER 0x0f
/* support CSA */
#define SDIO_DEVCTR_CSA_SUP 0x40
/* enable CSA */
#define SDIO_DEVCTR_CSA_EN 0x80
/* ext_dev */
/* supports high-power mask */
#define SDIO_HIGHPWR_SUPPORT_M 0x3
/* enable high power */
#define SDIO_HIGHPWR_EN 0x4
/* standard power function(up to 200mA */
#define SDIO_HP_STD 0
/* need high power to operate */
#define SDIO_HP_REQUIRED 0x2
/* can work with standard power, but prefer high power */
#define SDIO_HP_DESIRED 0x3
/* misc define */
/* macro to calculate fbr register base */
#define FBR_REG_BASE(n) (n*0x100)
#define SDIO_FUNC_0 0
#define SDIO_FUNC_1 1
#define SDIO_FUNC_2 2
#define SDIO_FUNC_3 3
#define SDIO_FUNC_4 4
#define SDIO_FUNC_5 5
#define SDIO_FUNC_6 6
#define SDIO_FUNC_7 7
/* maximum block size for block mode operation */
#define SDIO_MAX_BLOCK_SIZE 2048
/* minimum block size for block mode operation */
#define SDIO_MIN_BLOCK_SIZE 1
/* Card registers: status bit position */
#define SDIO_STATUS_OUTOFRANGE 31
#define SDIO_STATUS_COMCRCERROR 23
#define SDIO_STATUS_ILLEGALCOMMAND 22
#define SDIO_STATUS_ERROR 19
#define SDIO_STATUS_IOCURRENTSTATE3 12
#define SDIO_STATUS_IOCURRENTSTATE2 11
#define SDIO_STATUS_IOCURRENTSTATE1 10
#define SDIO_STATUS_IOCURRENTSTATE0 9
#define SDIO_STATUS_FUN_NUM_ERROR 4
#define GET_SDIOCARD_STATUS(x) ((x >> 9) & 0x0f)
#define SDIO_STATUS_STATE_IDLE 0
#define SDIO_STATUS_STATE_READY 1
#define SDIO_STATUS_STATE_IDENT 2
#define SDIO_STATUS_STATE_STBY 3
#define SDIO_STATUS_STATE_TRAN 4
#define SDIO_STATUS_STATE_DATA 5
#define SDIO_STATUS_STATE_RCV 6
#define SDIO_STATUS_STATE_PRG 7
#define SDIO_STATUS_STATE_DIS 8
/* sprom */
#define SBSDIO_SPROM_CS 0x10000 /* command and status */
#define SBSDIO_SPROM_INFO 0x10001 /* info register */
#define SBSDIO_SPROM_DATA_LOW 0x10002 /* indirect access data uint8_t 0 */
#define SBSDIO_SPROM_DATA_HIGH 0x10003 /* indirect access data uint8_t 1 */
#define SBSDIO_SPROM_ADDR_LOW 0x10004 /* indirect access addr uint8_t 0 */
#define SBSDIO_SPROM_ADDR_HIGH 0x10005 /* indirect access addr uint8_t 0 */
#define SBSDIO_CHIP_CTRL_DATA 0x10006 /* xtal_pu data output */
#define SBSDIO_CHIP_CTRL_EN 0x10007 /* xtal_pu enable */
#define SBSDIO_WATERMARK 0x10008 /* retired in rev 7 */
#define SBSDIO_DEVICE_CTL 0x10009 /* control busy signal generation */
#define SBSDIO_SPROM_IDLE 0
#define SBSDIO_SPROM_WRITE 1
#define SBSDIO_SPROM_READ 2
#define SBSDIO_SPROM_WEN 4
#define SBSDIO_SPROM_WDS 7
#define SBSDIO_SPROM_DONE 8
/* SBSDIO_SPROM_INFO */
#define SBSDIO_SROM_SZ_MASK 0x03 /* SROM size, 1: 4k, 2: 16k */
#define SBSDIO_SROM_BLANK 0x04 /* depreciated in corerev 6 */
#define SBSDIO_SROM_OTP 0x80 /* OTP present */
/* SBSDIO_CHIP_CTRL */
/* or'd with onchip xtal_pu, 1: power on oscillator */
#define SBSDIO_CHIP_CTRL_XTAL 0x01
/* SBSDIO_WATERMARK */
/* number of bytes minus 1 for sd device to wait before sending data to host */
#define SBSDIO_WATERMARK_MASK 0x3f
/* SBSDIO_DEVICE_CTL */
/* 1: device will assert busy signal when receiving CMD53 */
#define SBSDIO_DEVCTL_SETBUSY 0x01
/* 1: assertion of sdio interrupt is synchronous to the sdio clock */
#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
/* function 1 OCP space */
/* sb offset addr is <= 15 bits, 32k */
#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF
#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
/* sdsdio function 1 OCP space has 16/32 bit section */
#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000
/* direct(mapped) cis space */
/* MAPPED common CIS address */
#define SBSDIO_CIS_BASE_COMMON 0x1000
/* function 0(common) cis size in bytes */
#define SBSDIO_CIS_FUNC0_LIMIT 0x020
/* funciton 1 cis size in bytes */
#define SBSDIO_CIS_SIZE_LIMIT 0x200
/* cis offset addr is < 17 bits */
#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
/* manfid tuple length, include tuple, link bytes */
#define SBSDIO_CIS_MANFID_TUPLE_LEN 6
/* indirect cis access (in sprom) */
/* 8 control bytes first, CIS starts from 8th uint8_t */
#define SBSDIO_SPROM_CIS_OFFSET 0x8
/* sdio uint8_t mode: maximum length of one data comamnd */
#define SBSDIO_BYTEMODE_DATALEN_MAX 64
/* 4317 supports less */
#define SBSDIO_BYTEMODE_DATALEN_MAX_4317 52
/* sdio core function one address mask */
#define SBSDIO_CORE_ADDR_MASK 0x1FFFF
/* CEATA defines */
#define CEATA_EXT_CSDBLOCK_SIZE 512
#define CEATA_FAST_IO 39
#define CEATA_MULTIPLE_REGISTER_RW 60
#define CEATA_MULTIPLE_BLOCK_RW 61
/* defines CE ATA task file registers */
#define CEATA_SCT_CNT_EXP_REG 0x02
#define CEATA_LBA_LOW_EXP_REG 0x03
#define CEATA_LBA_MID_EXP_REG 0x04
#define CEATA_LBA_HIGH_EXP_REG 0x05
#define CEATA_CNTRL_REG 0x06
#define CEATA_FEATURE_REG 0x09 /* write */
#define CEATA_ERROR_REG 0x09 /* read */
#define CEATA_SCT_CNT_REG 0x0A
#define CEATA_LBA_LOW_REG 0x0B
#define CEATA_LBA_MID_REG 0x0C
#define CEATA_LBA_HIGH_REG 0x0D
#define CEATA_DEV_HEAD_REG 0x0E
#define CEATA_STA_REG 0x0F /* read */
#define CEATA_CMD_REG 0x0F /* write */
/* defines CEATA control and status registers for ce ata client driver */
#define CEATA_SCR_TEMPC_REG 0x80
#define CEATA_SCR_TEMPMAXP_REG 0x84
#define CEATA_TEMPMINP_REG 0x88
#define CEATA_SCR_STATUS_REG 0x8C
#define CEATA_SCR_REALLOCSA_REG 0x90
#define CEATA_SCR_ERETRACTSA_REG 0x94
#define CEATA_SCR_CAPABILITIES_REG 0x98
#define CEATA_SCR_CONTROL_REG 0xC0
/* defines for SCR capabilities register bits for ce ata client driver */
#define CEATA_SCR_CAP_512 0x00000001
#define CEATA_SCR_CAP_1K 0x00000002
#define CEATA_SCR_CAP_4K 0x00000004
/* defines CE ATA Control reg bits for ce ata client driver */
#define CEATA_CNTRL_ENABLE_INTR 0x00
#define CEATA_CNTRL_DISABLE_INTR 0x02
#define CEATA_CNTRL_SRST 0x04
#define CEATA_CNTRL_RSRST 0x00
/* define CE ATA Status reg bits for ce ata client driver */
#define CEATA_STA_ERROR_BIT 0x01
#define CEATA_STA_OVR_BIT 0x02
#define CEATA_STA_SPT_BIT 0x04
#define CEATA_STA_DRQ_BIT 0x08
#define CEATA_STA_DRDY_BIT 0x40
#define CEATA_STA_BSY_BIT 0x80
/* define CE ATA Error reg bits for ce ata client driver */
#define CEATA_ERROR_ABORTED_BIT 0x04
#define CEATA_ERROR_IDNF_BIT 0x10
#define CEATA_ERROR_UNCORRECTABLE_BIT 0x40
#define CEATA_ERROR_ICRC_BIT 0x80
/* define CE ATA Commands for ce ata client driver */
#define CEATA_CMD_IDENTIFY_DEVICE 0xEC
#define CEATA_CMD_READ_DMA_EXT 0x25
#define CEATA_CMD_WRITE_DMA_EXT 0x35
#define CEATA_CMD_STANDBY_IMMEDIATE 0xE0
#define CEATA_CMD_FLUSH_CACHE_EXT 0xEA
struct csd_mmc {
uint32_t padding:8;
uint32_t structure:2;
uint32_t csdSpecVer:4;
uint32_t reserved1:2;
uint32_t taac:8;
uint32_t nsac:8;
uint32_t speed:8;
uint32_t classes:12;
uint32_t rdBlkLen:4;
uint32_t rdBlkPartial:1;
uint32_t wrBlkMisalign:1;
uint32_t rdBlkMisalign:1;
uint32_t dsr:1;
uint32_t reserved2:2;
uint32_t size:12;
uint32_t vddRdCurrMin:3;
uint32_t vddRdCurrMax:3;
uint32_t vddWrCurrMin:3;
uint32_t vddWrCurrMax:3;
uint32_t devSizeMulti:3;
uint32_t eraseGrpSize:5;
uint32_t eraseGrpSizeMulti:5;
uint32_t wrProtGroupSize:5;
uint32_t wrProtGroupEnable:1;
uint32_t manuDefEcc:2;
uint32_t wrSpeedFactor:3;
uint32_t wrBlkLen:4;
uint32_t wrBlkPartial:1;
uint32_t reserved5:4;
uint32_t protAppl:1;
uint32_t fileFormatGrp:1;
uint32_t copyFlag:1;
uint32_t permWrProt:1;
uint32_t tmpWrProt:1;
uint32_t fileFormat:2;
uint32_t eccCode:2;
};
/* CSD register*/
union sd_csd {
uint32_t csd[4];
struct csd_mmc mmc;
};
struct sd_card_data {
union sd_csd csd;
};
#endif /* CSL_SD_PROT_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.h
+94
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/*
* Copyright (c) 2016 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PBOOT_HAL_MEMORY_EMMC_DRV_H
#define PBOOT_HAL_MEMORY_EMMC_DRV_H
#include <drivers/delay_timer.h>
#include "emmc_chal_types.h"
#include "emmc_chal_sd.h"
#include "emmc_csl_sdprot.h"
#include "emmc_csl_sdcmd.h"
#include "emmc_csl_sd.h"
#include "emmc_brcm_rdb_sd4_top.h"
#define CLK_SDIO_DIV_52MHZ 0x0
#define SYSCFG_IOCR4_PAD_10MA 0x38000000
#define SDCLK_CNT_PER_MS 52000
#define BOOT_ACK_TIMEOUT (50 * SDCLK_CNT_PER_MS)
#define BOOT_DATA_TIMEOUT (1000 * SDCLK_CNT_PER_MS)
#define EMMC_BOOT_OK 0
#define EMMC_BOOT_ERROR 1
#define EMMC_BOOT_TIMEOUT 2
#define EMMC_BOOT_INVALIDIMAGE 3
#define EMMC_BOOT_NO_CARD 4
#define EMMC_USER_AREA 0
#define EMMC_BOOT_PARTITION1 1
#define EMMC_BOOT_PARTITION2 2
#define EMMC_USE_CURRENT_PARTITION 3
#define EMMC_BOOT_PARTITION_SIZE (128*1024)
#define EMMC_BLOCK_SIZE 512
#define EMMC_DMA_SIZE (4*1024)
/*
* EMMC4.3 definitions
* Table 6 EXT_CSD access mode
* Access
* Bits Access Name Operation
* 00 Command Set The command set is changed according to the Cmd Set field of
* the argument
* 01 Set Bits The bits in the pointed uint8_t are set,
* according to the 1 bits in the Value field.
* 10 Clear Bits The bits in the pointed uint8_t are cleared,
* according to the 1 bits in the Value field.
* 11 Write Byte The Value field is written into the pointed uint8_t.
*/
#define SDIO_HW_EMMC_EXT_CSD_WRITE_BYTE 0X03000000
/* Boot bus width1 BOOT_BUS_WIDTH 1 R/W [177] */
#define SDIO_HW_EMMC_EXT_CSD_BOOT_BUS_WIDTH_OFFSET 0X00B10000
/* Boot configuration BOOT_CONFIG 1 R/W [179] */
#define SDIO_HW_EMMC_EXT_CSD_BOOT_CONFIG_OFFSET 0X00B30000
/* Bus width mode BUS_WIDTH 1 WO [183] */
#define SDIO_HW_EMMC_EXT_CSD_BUS_WIDTH_OFFSET 0X00B70000
/*
* Bit 6: BOOT_ACK (non-volatile)
* 0x0 : No boot acknowledge sent (default)
* 0x1 : Boot acknowledge sent during boot operation
* Bit[5:3] : BOOT_PARTITION_ENABLE (non-volatile)
* User selects boot data that will be sent to master
* 0x0 : Device not boot enabled (default)
* 0x1 : Boot partition 1 enabled for boot
* 0x2 : Boot partition 2 enabled for boot
* 0x3-0x6 : Reserved
* 0x7 : User area enabled for boot
* Bit[2:0] : BOOT_PARTITION_ACCESS
* User selects boot partition for read and write operation
* 0x0 : No access to boot partition (default)
* 0x1 : R/W boot partition 1
* 0x2 : R/W boot partition 2
* 0x3-0x7 : Reserved
*/
#define SDIO_HW_EMMC_EXT_CSD_BOOT_ACC_BOOT1 0X00000100
#define SDIO_HW_EMMC_EXT_CSD_BOOT_ACC_BOOT2 0X00000200
#define SDIO_HW_EMMC_EXT_CSD_BOOT_ACC_USER 0X00000000
#define SDIO_HW_EMMC_EXT_CSD_BOOT_EN_BOOT1 0X00004800
#define SDIO_HW_EMMC_EXT_CSD_BOOT_EN_BOOT2 0X00005000
#define SDIO_HW_EMMC_EXT_CSD_BOOT_EN_USER 0X00007800
#define SD_US_DELAY(x) udelay(x)
#endif
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/fru.h
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/*
* Copyright (c) 2019-2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef FRU_H
#define FRU_H
#include <stdbool.h>
#include <stdint.h>
/* max string length */
#define FRU_MAX_STR_LEN 32
/* max number of DDR channels */
#define BCM_MAX_NR_DDR 3
/* max supported FRU table size */
#define BCM_MAX_FRU_LEN 512
/* FRU table starting offset */
#define BCM_FRU_TBL_OFFSET 0x300000
/* FRU time constants */
#define MINS_PER_DAY 1440
#define MINS_PER_HOUR 60
#define FRU_YEAR_START 1996
#define FRU_MONTH_START 1
#define FRU_DAY_START 1
#define MONTHS_PER_YEAR 12
/*
* FRU areas based on the spec
*/
enum fru_area_name {
FRU_AREA_INTERNAL = 0,
FRU_AREA_CHASSIS_INFO,
FRU_AREA_BOARD_INFO,
FRU_AREA_PRODUCT_INFO,
FRU_AREA_MRECORD_INFO,
FRU_MAX_NR_AREAS
};
/*
* FRU area information
*
* @use: indicate this area is being used
* @version: format version
* @offset: offset of this area from the beginning of the FRU table
* @len: total length of the area
*/
struct fru_area_info {
bool use;
uint8_t version;
unsigned int offset;
unsigned int len;
};
/*
* DDR MCB information
*
* @idx: DDR channel index
* @size_mb: DDR size of this channel in MB
* @ref_id: DDR MCB reference ID
*/
struct ddr_mcb {
unsigned int idx;
unsigned int size_mb;
uint32_t ref_id;
};
/*
* DDR information
*
* @ddr_info: array that contains MCB related info for each channel
*/
struct ddr_info {
struct ddr_mcb mcb[BCM_MAX_NR_DDR];
};
/*
* FRU board area information
*
* @lang: Language code
* @mfg_date: Manufacturing date
* @manufacturer: Manufacturer
* @product_name: Product name
* @serial_number: Serial number
* @part_number: Part number
* @file_id: FRU file ID
*/
struct fru_board_info {
unsigned char lang;
unsigned int mfg_date;
unsigned char manufacturer[FRU_MAX_STR_LEN];
unsigned char product_name[FRU_MAX_STR_LEN];
unsigned char serial_number[FRU_MAX_STR_LEN];
unsigned char part_number[FRU_MAX_STR_LEN];
unsigned char file_id[FRU_MAX_STR_LEN];
};
/*
* FRU manufacture date in human readable format
*/
struct fru_time {
unsigned int min;
unsigned int hour;
unsigned int day;
unsigned int month;
unsigned int year;
};
#ifdef USE_FRU
int fru_validate(uint8_t *data, struct fru_area_info *fru_area);
int fru_parse_ddr(uint8_t *data, struct fru_area_info *area,
struct ddr_info *ddr);
int fru_parse_board(uint8_t *data, struct fru_area_info *area,
struct fru_board_info *board);
void fru_format_time(unsigned int min, struct fru_time *tm);
#else
static inline int fru_validate(uint8_t *data, struct fru_area_info *fru_area)
{
return -1;
}
static inline int fru_parse_ddr(uint8_t *data, struct fru_area_info *area,
struct ddr_info *ddr)
{
return -1;
}
static inline int fru_parse_board(uint8_t *data, struct fru_area_info *area,
struct fru_board_info *board)
{
return -1;
}
static inline void fru_format_time(unsigned int min, struct fru_time *tm)
{
}
#endif /* USE_FRU */
#endif /* FRU_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/i2c/i2c.h
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/*
* Copyright (c) 2016 - 2021, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef I2C_H
#define I2C_H
#include <stdint.h>
#define I2C_SPEED_100KHz 100000
#define I2C_SPEED_400KHz 400000
#define I2C_SPEED_DEFAULT I2C_SPEED_100KHz
/*
* Function Name: i2c_probe
*
* Description:
* This function probes the I2C bus for the existence of the specified
* device.
*
* Parameters:
* bus_id - I2C bus ID
* devaddr - Device Address
*
* Return:
* 0 on success, or -1 on failure.
*/
int i2c_probe(uint32_t bus_id, uint8_t devaddr);
/*
* Function Name: i2c_init
*
* Description:
* This function initializes the SMBUS.
*
* Parameters:
* bus_id - I2C bus ID
* speed - I2C bus speed in Hz
*
* Return:
* 0 on success, or -1 on failure.
*/
int i2c_init(uint32_t bus_id, int speed);
/*
* Function Name: i2c_set_bus_speed
*
* Description:
* This function configures the SMBUS speed
*
* Parameters:
* bus_id - I2C bus ID
* speed - I2C bus speed in Hz
*
* Return:
* 0 on success, or -1 on failure.
*/
int i2c_set_bus_speed(uint32_t bus_id, uint32_t speed);
/*
* Function Name: i2c_get_bus_speed
*
* Description:
* This function returns the SMBUS speed.
*
* Parameters:
* bus_id - I2C bus ID
*
* Return:
* Bus speed in Hz, 0 on failure
*/
uint32_t i2c_get_bus_speed(uint32_t bus_id);
/*
* Function Name: i2c_recv_byte
*
* Description:
* This function reads I2C data from a device without specifying
* a command regsiter.
*
* Parameters:
* bus_id - I2C bus ID
* devaddr - Device Address
* value - Data Read
*
* Return:
* 0 on success, or -1 on failure.
*/
int i2c_recv_byte(uint32_t bus_id, uint8_t devaddr, uint8_t *value);
/*
* Function Name: i2c_send_byte
*
* Description:
* This function send I2C data to a device without specifying
* a command regsiter.
*
* Parameters:
* bus_id - I2C bus ID
* devaddr - Device Address
* value - Data Send
*
* Return:
* 0 on success, or -1 on failure.
*/
int i2c_send_byte(uint32_t bus_id, uint8_t devaddr, uint8_t value);
/*
* Function Name: i2c_read
*
* Description:
* This function reads I2C data from a device with a designated
* command register
*
* Parameters:
* bus_id - I2C bus ID
* devaddr - Device Address
* addr - Register Offset
* alen - Address Length, 1 for byte, 2 for word (not supported)
* buffer - Data Buffer
* len - Data Length in bytes
*
* Return:
* 0 on success, or -1 on failure.
*/
int i2c_read(uint32_t bus_id,
uint8_t devaddr,
uint32_t addr,
int alen,
uint8_t *buffer,
int len);
/*
* Function Name: i2c_write
*
* Description:
* This function write I2C data to a device with a designated
* command register
*
* Parameters:
* bus_id - I2C bus ID
* devaddr - Device Address
* addr - Register Offset
* alen - Address Length, 1 for byte, 2 for word (not supported)
* buffer - Data Buffer
* len - Data Length in bytes
*
* Return:
* 0 on success, or -1 on failure.
*/
int i2c_write(uint32_t bus_id,
uint8_t devaddr,
uint32_t addr,
int alen,
uint8_t *buffer,
int len);
#endif /* I2C_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/i2c/i2c_regs.h
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/*
* Copyright (c) 2016 - 2021, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef I2C_REGS
#define I2C_REGS
/* SMBUS Config register */
#define SMB_CFG_REG 0x0U
#define SMB_CFG_RST_MASK 0x80000000U
#define SMB_CFG_RST_SHIFT 31U
#define SMB_CFG_SMBEN_MASK 0x40000000U
#define SMB_CFG_SMBEN_SHIFT 30U
#define SMB_CFG_BITBANGEN_MASK 0x20000000U
#define SMB_CFG_BITBANGEN_SHIFT 29U
#define SMB_CFG_EN_NIC_SMBADDR0_MASK 0x10000000U
#define SMB_CFG_EN_NIC_SMBADDR0_SHIFT 28U
#define SMB_CFG_PROMISCMODE_MASK 0x08000000U
#define SMB_CFG_PROMISCMODE_SHIFT 27U
#define SMB_CFG_TSTMPCNTEN_MASK 0x04000000U
#define SMB_CFG_TSTMPCNTEN_SHIFT 26U
#define SMB_CFG_MSTRRTRYCNT_MASK 0x000F0000U
#define SMB_CFG_MSTRRTRYCNT_SHIFT 16U
/* SMBUS Timing config register */
#define SMB_TIMGCFG_REG 0x4U
#define SMB_TIMGCFG_MODE400_MASK 0x80000000U
#define SMB_TIMGCFG_MODE400_SHIFT 31U
#define SMB_TIMGCFG_RNDSLVSTR_MASK 0x7F000000U
#define SMB_TIMGCFG_RNDSLVSTR_SHIFT 24U
#define SMB_TIMGCFG_PERSLVSTR_MASK 0x00FF0000U
#define SMB_TIMGCFG_PERSLVSTR_SHIFT 16U
#define SMB_TIMGCFG_IDLTIME_MASK 0x0000FF00U
#define SMB_TIMGCFG_IDLTIME_SHIFT 8U
/* SMBUS Slave address register */
#define SMB_ADDR_REG 0x8U
#define SMB_EN_NIC_SMBADDR3_MASK 0x80000000U
#define SMB_EN_NIC_SMBADDR3_SHIFT 31U
#define SMB_NIC_SMBADDR3_MASK 0x7F000000U
#define SMB_NIC_SMBADDR3_SHIFT 24U
#define SMB_EN_NIC_SMBADDR2_MASK 0x00800000U
#define SMB_EN_NIC_SMBADDR2_SHIFT 23U
#define SMB_NIC_SMBADDR2_MASK 0x007F0000U
#define SMB_NIC_SMBADDR2_SHIFT 16U
#define SMB_EN_NIC_SMBADDR1_MASK 0x00008000U
#define SMB_EN_NIC_SMBADDR1_SHIFT 15U
#define SMB_NIC_SMBADDR1_MASK 0x00007F00U
#define SMB_NIC_SMBADDR1_SHIFT 8U
#define SMB_EN_NIC_SMBADDR0_MASK 0x00000080U
#define SMB_EN_NIC_SMBADDR0_SHIFT 7U
#define SMB_NIC_SMBADDR0_MASK 0x0000007FU
#define SMB_NIC_SMBADDR0_SHIFT 0U
/* SMBUS Master FIFO control register */
#define SMB_MSTRFIFOCTL_REG 0xCU
#define SMB_MSTRRXFIFOFLSH_MASK 0x80000000U
#define SMB_MSTRRXFIFOFLSH_SHIFT 31U
#define SMB_MSTRTXFIFOFLSH_MASK 0x40000000U
#define SMB_MSTRTXFIFOFLSH_SHIFT 30U
#define SMB_MSTRRXPKTCNT_MASK 0x007F0000U
#define SMB_MSTRRXPKTCNT_SHIFT 16U
#define SMB_MSTRRXFIFOTHR_MASK 0x00003F00U
#define SMB_MSTRRXFIFOTHR_SHIFT 8U
/* SMBUS Slave FIFO control register */
#define SMB_SLVFIFOCTL_REG 0x10U
#define SMB_SLVRXFIFOFLSH_MASK 0x80000000U
#define SMB_SLVRXFIFOFLSH_SHIFT 31U
#define SMB_SLVTXFIFOFLSH_MASK 0x40000000U
#define SMB_SLVTXFIFOFLSH_SHIFT 30U
#define SMB_SLVRXPKTCNT_MASK 0x007F0000U
#define SMB_SLVRXPKTCNT_SHIFT 16U
#define SMB_SLVRXFIFOTHR_MASK 0x00003F00U
#define SMB_SLVRXFIFOTHR_SHIFT 8U
/* SMBUS Bit-bang mode control register */
#define SMB_BITBANGCTL_REG 0x14U
#define SMB_SMBCLKIN_MASK 0x80000000U
#define SMB_SMBCLKIN_SHIFT 31U
#define SMB_SMBCLKOUTEN_MASK 0x40000000U
#define SMB_SMBCLKOUTEN_SHIFT 30U
#define SMB_SMBDATAIN_MASK 0x20000000U
#define SMB_SMBDATAIN_SHIFT 29U
#define SMB_SMBDATAOUTEN_MASK 0x10000000U
#define SMB_SMBDATAOUTEN_SHIFT 28U
/* SMBUS Master command register */
#define SMB_MSTRCMD_REG 0x30U
#define SMB_MSTRSTARTBUSYCMD_MASK 0x80000000U
#define SMB_MSTRSTARTBUSYCMD_SHIFT 31U
#define SMB_MSTRABORT_MASK 0x40000000U
#define SMB_MSTRABORT_SHIFT 30U
#define SMB_MSTRSTS_MASK 0x0E000000U
#define SMB_MSTRSTS_SHIFT 25U
#define SMB_MSTRSMBUSPROTO_MASK 0x00001E00U
#define SMB_MSTRSMBUSPROTO_SHIFT 9U
#define SMB_MSTRPEC_MASK 0x00000100U
#define SMB_MSTRPEC_SHIFT 8U
#define SMB_MSTRRDBYTECNT_MASK 0x000000FFU
#define SMB_MSTRRDBYTECNT_SHIFT 0U
/* SMBUS Slave command register */
#define SMB_SLVCMD_REG 0x34U
#define SMB_SLVSTARTBUSYCMD_MASK 0x80000000U
#define SMB_SLVSTARTBUSYCMD_SHIFT 31U
#define SMB_SLVABORT_MASK 0x40000000U
#define SMB_SLVABORT_SHIFT 30U
#define SMB_SLVSTS_MASK 0x03800000U
#define SMB_SLVSTS_SHIFT 23U
#define SMB_SLVPEC_MASK 0x00000100U
#define SMB_SLVPEC_SHIFT 8U
/* SMBUS Event enable register */
#define SMB_EVTEN_REG 0x38U
#define SMB_MSTRRXFIFOFULLEN_MASK 0x80000000U
#define SMB_MSTRRXFIFOFULLEN_SHIFT 31U
#define SMB_MSTRRXFIFOTHRHITEN_MASK 0x40000000U
#define SMB_MSTRRXFIFOTHRHITEN_SHIFT 30U
#define SMB_MSTRRXEVTEN_MASK 0x20000000U
#define SMB_MSTRRXEVTEN_SHIFT 29U
#define SMB_MSTRSTARTBUSYEN_MASK 0x10000000U
#define SMB_MSTRSTARTBUSYEN_SHIFT 28U
#define SMB_MSTRTXUNDEN_MASK 0x08000000U
#define SMB_MSTRTXUNDEN_SHIFT 27U
#define SMB_SLVRXFIFOFULLEN_MASK 0x04000000U
#define SMB_SLVRXFIFOFULLEN_SHIFT 26U
#define SMB_SLVRXFIFOTHRHITEN_MASK 0x02000000U
#define SMB_SLVRXFIFOTHRHITEN_SHIFT 25U
#define SMB_SLVRXEVTEN_MASK 0x01000000U
#define SMB_SLVRXEVTEN_SHIFT 24U
#define SMB_SLVSTARTBUSYEN_MASK 0x00800000U
#define SMB_SLVSTARTBUSYEN_SHIFT 23U
#define SMB_SLVTXUNDEN_MASK 0x00400000U
#define SMB_SLVTXUNDEN_SHIFT 22U
#define SMB_SLVRDEVTEN_MASK 0x00200000U
#define SMB_SLVRDEVTEN_SHIFT 21U
/* SMBUS Event status register */
#define SMB_EVTSTS_REG 0x3CU
#define SMB_MSTRRXFIFOFULLSTS_MASK 0x80000000U
#define SMB_MSTRRXFIFOFULLSTS_SHIFT 31U
#define SMB_MSTRRXFIFOTHRHITSTS_MASK 0x40000000U
#define SMB_MSTRRXFIFOTHRHITSTS_SHIFT 30U
#define SMB_MSTRRXEVTSTS_MASK 0x20000000U
#define SMB_MSTRRXEVTSTS_SHIFT 29U
#define SMB_MSTRSTARTBUSYSTS_MASK 0x10000000U
#define SMB_MSTRSTARTBUSYSTS_SHIFT 28U
#define SMB_MSTRTXUNDSTS_MASK 0x08000000U
#define SMB_MSTRTXUNDSTS_SHIFT 27U
#define SMB_SLVRXFIFOFULLSTS_MASK 0x04000000U
#define SMB_SLVRXFIFOFULLSTS_SHIFT 26U
#define SMB_SLVRXFIFOTHRHITSTS_MASK 0x02000000U
#define SMB_SLVRXFIFOTHRHITSTS_SHIFT 25U
#define SMB_SLVRXEVTSTS_MASK 0x01000000U
#define SMB_SLVRXEVTSTS_SHIFT 24U
#define SMB_SLVSTARTBUSYSTS_MASK 0x00800000U
#define SMB_SLVSTARTBUSYSTS_SHIFT 23U
#define SMB_SLVTXUNDSTS_MASK 0x00400000U
#define SMB_SLVTXUNDSTS_SHIFT 22U
#define SMB_SLVRDEVTSTS_MASK 0x00200000U
#define SMB_SLVRDEVTSTS_SHIFT 21U
/* SMBUS Master data write register */
#define SMB_MSTRDATAWR_REG 0x40U
#define SMB_MSTRWRSTS_MASK 0x80000000U
#define SMB_MSTRWRSTS_SHIFT 31U
#define SMB_MSTRWRDATA_MASK 0x000000FFU
#define SMB_MSTRWRDATA_SHIFT 0U
/* SMBUS Master data read register */
#define SMB_MSTRDATARD_REG 0x44U
#define SMB_MSTRRDSTS_MASK 0xC0000000U
#define SMB_MSTRRDSTS_SHIFT 30U
#define SMB_MSTRRDPECERR_MASK 0x20000000U
#define SMB_MSTRRDPECERR_SHIFT 29U
#define SMB_MSTRRDDATA_MASK 0x000000FFU
#define SMB_MSTRRDDATA_SHIFT 0U
/* SMBUS Slave data write register */
#define SMB_SLVDATAWR_REG 0x48U
#define SMB_SLVWRSTS_MASK 0x80000000U
#define SMB_SLVWRSTS_SHIFT 31U
#define SMB_SLVWRDATA_MASK 0x000000FFU
#define SMB_SLVWRDATA_SHIFT 0U
/* SMBUS Slave data read register */
#define SMB_SLVDATARD_REG 0x4CU
#define SMB_SLVRDSTS_MASK 0xC0000000U
#define SMB_SLVRDSTS_SHIFT 30U
#define SMB_SLVRDERRSTS_MASK 0x30000000U
#define SMB_SLVRDERRSTS_SHIFT 28U
#define SMB_SLVRDDATA_MASK 0x000000FFU
#define SMB_SLVRDDATA_SHIFT 0U
#endif /* I2C_REGS */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/iproc_gpio.h
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/*
* Copyright (c) 2019-2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef IPROC_GPIO_H
#define IPROC_GPIO_H
#ifdef USE_GPIO
void iproc_gpio_init(uintptr_t base, int nr_gpios, uintptr_t pinmux_base,
uintptr_t pinconf_base);
#else
static void iproc_gpio_init(uintptr_t base, int nr_gpios, uintptr_t pinmux_base,
uintptr_t pinconf_base)
{
}
#endif /* IPROC_GPIO */
#endif /* IPROC_GPIO_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/mdio/mdio.h
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/*
* Copyright (c) 2016 - 2021, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MDIO_H
#define MDIO_H
#define CMIC_MIIM_PARAM (PLAT_CMIC_MIIM_BASE + 0x23cU)
#define MDIO_PARAM_MIIM_CYCLE 29U
#define MDIO_PARAM_INTERNAL_SEL 25U
#define MDIO_PARAM_BUSID 22U
#define MDIO_PARAM_BUSID_MASK 0x7U
#define MDIO_PARAM_C45_SEL 21U
#define MDIO_PARAM_PHYID 16U
#define MDIO_PARAM_PHYID_MASK 0x1FU
#define MDIO_PARAM_DATA 0U
#define MDIO_PARAM_DATA_MASK 0xFFFFU
#define CMIC_MIIM_READ_DATA (PLAT_CMIC_MIIM_BASE + 0x240U)
#define MDIO_READ_DATA_MASK 0xffffU
#define CMIC_MIIM_ADDRESS (PLAT_CMIC_MIIM_BASE + 0x244U)
#define CMIC_MIIM_CTRL (PLAT_CMIC_MIIM_BASE + 0x248U)
#define MDIO_CTRL_WRITE_OP 0x1U
#define MDIO_CTRL_READ_OP 0x2U
#define CMIC_MIIM_STAT (PLAT_CMIC_MIIM_BASE + 0x24cU)
#define MDIO_STAT_DONE 1U
int mdio_write(uint16_t busid, uint16_t phyid, uint32_t reg, uint16_t val);
int mdio_read(uint16_t busid, uint16_t phyid, uint32_t reg);
#endif /* MDIO_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/ocotp.h
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/*
* Copyright (c) 2016 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef OCOTP_H
#define OCOTP_H
#include <stdint.h>
struct otpc_map {
/* in words. */
uint32_t otpc_row_size;
/* 128 bit row / 4 words support. */
uint16_t data_r_offset[4];
/* 128 bit row / 4 words support. */
uint16_t data_w_offset[4];
int word_size;
int stride;
};
int bcm_otpc_init(struct otpc_map *map);
int bcm_otpc_read(unsigned int offset, void *val, uint32_t bytes,
uint32_t ecc_flag);
#endif /* OCOTP_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/scp.h
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/*
* Copyright (c) 2017 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SCP_H
#define SCP_H
#include <stdint.h>
int download_scp_patch(void *image, unsigned int image_size);
#endif /* SCP_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/sf.h
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/*
* Copyright (c) 2019-2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SF_H
#define SF_H
#include <stdint.h>
#include <stddef.h>
#ifdef SPI_DEBUG
#define SPI_DEBUG(fmt, ...) INFO(fmt, ##__VA_ARGS__)
#else
#define SPI_DEBUG(fmt, ...)
#endif
#define SPI_FLASH_MAX_ID_LEN 6
#define CMD_WRSR 0x01 /* Write status register */
#define CMD_PAGE_PROGRAM 0x02
#define CMD_READ_NORMAL 0x03
#define CMD_RDSR 0x05
#define CMD_WRITE_ENABLE 0x06
#define CMD_RDFSR 0x70
#define CMD_READ_ID 0x9f
#define CMD_ERASE_4K 0x20
#define CMD_ERASE_64K 0xd8
#define ERASE_SIZE_64K (64 * 1024)
/* Common status */
#define STATUS_WIP BIT(0)
struct spi_flash {
struct spi_slave *spi;
uint32_t size;
uint32_t page_size;
uint32_t sector_size;
uint32_t erase_size;
uint8_t erase_cmd;
uint8_t read_cmd;
uint8_t write_cmd;
uint8_t flags;
};
struct spi_flash_info {
const char *name;
/*
* This array stores the ID bytes.
* The first three bytes are the JEDIC ID.
* JEDEC ID zero means "no ID" (mostly older chips).
*/
uint8_t id[SPI_FLASH_MAX_ID_LEN];
uint8_t id_len;
uint32_t sector_size;
uint32_t n_sectors;
uint16_t page_size;
uint8_t flags;
};
/* Enum list - Full read commands */
enum spi_read_cmds {
ARRAY_SLOW = BIT(0),
ARRAY_FAST = BIT(1),
DUAL_OUTPUT_FAST = BIT(2),
DUAL_IO_FAST = BIT(3),
QUAD_OUTPUT_FAST = BIT(4),
QUAD_IO_FAST = BIT(5),
};
/* sf param flags */
enum spi_param_flag {
SECT_4K = BIT(0),
SECT_32K = BIT(1),
E_FSR = BIT(2),
SST_BP = BIT(3),
SST_WP = BIT(4),
WR_QPP = BIT(5),
};
int spi_flash_cmd_read(const uint8_t *cmd, size_t cmd_len,
void *data, size_t data_len);
int spi_flash_cmd(uint8_t cmd, void *response, size_t len);
int spi_flash_cmd_write(const uint8_t *cmd, size_t cmd_len,
const void *data, size_t data_len);
#endif
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/sotp.h
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/*
* Copyright (c) 2016-2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SOTP_H
#define SOTP_H
#include <stddef.h>
#include <stdint.h>
#include <platform_sotp.h>
#define SOTP_ROW_NO_ECC 0
#define SOTP_ROW_ECC 1
#define SOTP_STATUS_1 (SOTP_REGS_OTP_BASE + 0x001c)
#define SOTP_FAIL_BITS 0x18000000000
#define SOTP_ECC_ERR_DETECT 0x8000000000000000
#define SOTP_REGS_SOTP_CHIP_STATES (SOTP_REGS_OTP_BASE + 0x0028)
#define SOTP_REGS_OTP_WR_LOCK (SOTP_REGS_OTP_BASE + 0x0038)
#define SOTP_CHIP_STATES_MANU_DEBUG_MASK (1 << 8)
#define SOTP_DEVICE_SECURE_CFG0_OTP_ERASED_MASK (3 << 16)
#define SOTP_REGS_SOTP_CHIP_STATES_OTP_ERASED_MASK (1 << 16)
#define SOTP_DEVICE_SECURE_CFG0_CID_MASK (3 << 2)
#define SOTP_DEVICE_SECURE_CFG0_AB_MASK (3 << 6)
#define SOTP_DEVICE_SECURE_CFG0_DEV_MASK (3 << 8)
#define SOTP_BOOT_SOURCE_SHIFT 8
/* bits 14 and 15 */
#define SOTP_BOOT_SOURCE_ENABLE_MASK (0xC0 << SOTP_BOOT_SOURCE_SHIFT)
/* bits 8 to 13 */
#define SOTP_BOOT_SOURCE_BITS0 (0x03 << SOTP_BOOT_SOURCE_SHIFT)
#define SOTP_BOOT_SOURCE_BITS1 (0x0C << SOTP_BOOT_SOURCE_SHIFT)
#define SOTP_BOOT_SOURCE_BITS2 (0x30 << SOTP_BOOT_SOURCE_SHIFT)
#define SOTP_BOOT_SOURCE_MASK (0x3F << SOTP_BOOT_SOURCE_SHIFT)
#define SOTP_ATF_CFG_ROW_ID SOTP_DEVICE_SECURE_CFG2_ROW
/* bits 28 and 29 */
#define SOTP_SBL_MASK (3 << 28)
/* bits 30 and 31 */
#define SOTP_ATF_NVCOUNTER_ENABLE_MASK ((uint64_t)3 << 30)
/* bits 32 and 33 */
#define SOTP_ATF_WATCHDOG_ENABLE_MASK ((uint64_t)3 << 32)
/* bits 34 and 35 */
#define SOTP_ATF_PLL_ON ((uint64_t)3 << 34)
/* bits 36 and 37 */
#define SOTP_ATF_RESET_RETRY ((uint64_t)3 << 36)
/* bits 38 to 40 */
#define SOTP_ATF_LOG_LEVEL_SHIFT 38
#define SOTP_ATF_LOG_LEVEL ((uint64_t)7 << SOTP_ATF_LOG_LEVEL_SHIFT)
#define SOTP_ATF2_CFG_ROW_ID SOTP_DEVICE_SECURE_CFG3_ROW
/* bits 16 and 17 */
#define SOTP_ROMKEY_MASK (3 << 16)
/* bits 18 and 19 */
#define SOTP_EC_EN_MASK (3 << 18)
#define SOTP_ENC_DEV_TYPE_AB_DEV ((uint64_t)0x19999800000)
#define SOTP_ENC_DEV_TYPE_MASK ((uint64_t)0x1ffff800000)
uint64_t sotp_mem_read(uint32_t offset, uint32_t sotp_add_ecc);
void sotp_mem_write(uint32_t addr, uint32_t sotp_add_ecc, uint64_t wdata);
int sotp_read_key(uint8_t *key, size_t keysize, int start_row, int end_row);
int sotp_key_erased(void);
uint32_t sotp_redundancy_reduction(uint32_t sotp_row_data);
#endif
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/spi.h
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/*
* Copyright (c) 2017 - 2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPI_H
#define SPI_H
#include <stdint.h>
#define SPI_XFER_BEGIN (1 << 0) /* Assert CS before transfer */
#define SPI_XFER_END (1 << 1) /* De-assert CS after transfer */
#define SPI_XFER_QUAD (1 << 2)
int spi_init(void);
int spi_claim_bus(void);
void spi_release_bus(void);
int spi_xfer(uint32_t bitlen, const void *dout, void *din, uint32_t flags);
#endif /* _SPI_H_ */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/spi_flash.h
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/*
* Copyright (c) 2019-2020, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPI_FLASH_H
#define SPI_FLASH_H
#include <sf.h>
int spi_flash_probe(struct spi_flash *flash);
int spi_flash_erase(struct spi_flash *flash, uint32_t offset, uint32_t len);
int spi_flash_write(struct spi_flash *flash, uint32_t offset,
uint32_t len, void *buf);
int spi_flash_read(struct spi_flash *flash, uint32_t offset,
uint32_t len, void *data);
#endif /* _SPI_FLASH_H_ */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/brcm/usbh_xhci_regs.h
+4809
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