GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
/* Address map types for Marvell address translation unit drivers */
|
||||
|
||||
#ifndef ADDR_MAP_H
|
||||
#define ADDR_MAP_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
struct addr_map_win {
|
||||
uint64_t base_addr;
|
||||
uint64_t win_size;
|
||||
uint32_t target_id;
|
||||
};
|
||||
|
||||
#endif /* ADDR_MAP_H */
|
||||
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
/* AXI to M-Bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs */
|
||||
|
||||
#ifndef AMB_ADEC_H
|
||||
#define AMB_ADEC_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
enum amb_attribute_ids {
|
||||
AMB_SPI0_CS0_ID = 0x1E,
|
||||
AMB_SPI0_CS1_ID = 0x5E,
|
||||
AMB_SPI0_CS2_ID = 0x9E,
|
||||
AMB_SPI0_CS3_ID = 0xDE,
|
||||
AMB_SPI1_CS0_ID = 0x1A,
|
||||
AMB_SPI1_CS1_ID = 0x5A,
|
||||
AMB_SPI1_CS2_ID = 0x9A,
|
||||
AMB_SPI1_CS3_ID = 0xDA,
|
||||
AMB_DEV_CS0_ID = 0x3E,
|
||||
AMB_DEV_CS1_ID = 0x3D,
|
||||
AMB_DEV_CS2_ID = 0x3B,
|
||||
AMB_DEV_CS3_ID = 0x37,
|
||||
AMB_BOOT_CS_ID = 0x2f,
|
||||
AMB_BOOT_ROM_ID = 0x1D,
|
||||
};
|
||||
|
||||
#define AMB_MAX_WIN_ID 7
|
||||
|
||||
int init_amb_adec(uintptr_t base);
|
||||
|
||||
#endif /* AMB_ADEC_H */
|
||||
+14
@@ -0,0 +1,14 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef AP807_INIT_CLOCKS_H
|
||||
#define AP807_INIT_CLOCKS_H
|
||||
|
||||
void ap807_clocks_init(unsigned int freq_option);
|
||||
|
||||
#endif /* AP807_INIT_CLOCKS_H */
|
||||
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
#ifndef ARO_H
|
||||
#define ARO_H
|
||||
|
||||
enum hws_freq {
|
||||
CPU_FREQ_2000,
|
||||
CPU_FREQ_1800,
|
||||
CPU_FREQ_1600,
|
||||
CPU_FREQ_1400,
|
||||
CPU_FREQ_1300,
|
||||
CPU_FREQ_1200,
|
||||
CPU_FREQ_1000,
|
||||
CPU_FREQ_600,
|
||||
CPU_FREQ_800,
|
||||
DDR_FREQ_LAST,
|
||||
DDR_FREQ_SAR
|
||||
};
|
||||
|
||||
#include <mvebu_def.h>
|
||||
|
||||
enum cpu_clock_freq_mode {
|
||||
CPU_2000_DDR_1200_RCLK_1200 = 0x0,
|
||||
CPU_2000_DDR_1050_RCLK_1050 = 0x1,
|
||||
CPU_1600_DDR_800_RCLK_800 = 0x4,
|
||||
CPU_2200_DDR_1200_RCLK_1200 = 0x6,
|
||||
CPU_1800_DDR_1050_RCLK_1050 = 0x7,
|
||||
CPU_1600_DDR_900_RCLK_900 = 0x0B,
|
||||
CPU_1600_DDR_1050_RCLK_1050 = 0x0D,
|
||||
CPU_1600_DDR_1200_RCLK_1200 = 0x0D,
|
||||
CPU_1600_DDR_900_RCLK_900_2 = 0x0E,
|
||||
CPU_1000_DDR_650_RCLK_650 = 0x13,
|
||||
CPU_1300_DDR_800_RCLK_800 = 0x14,
|
||||
CPU_1300_DDR_650_RCLK_650 = 0x17,
|
||||
CPU_1200_DDR_800_RCLK_800 = 0x19,
|
||||
CPU_1400_DDR_800_RCLK_800 = 0x1a,
|
||||
CPU_600_DDR_800_RCLK_800 = 0x1B,
|
||||
CPU_800_DDR_800_RCLK_800 = 0x1C,
|
||||
CPU_1000_DDR_800_RCLK_800 = 0x1D,
|
||||
CPU_DDR_RCLK_INVALID
|
||||
};
|
||||
|
||||
int init_aro(void);
|
||||
|
||||
#endif /* ARO_H */
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright (C) 2018-2020 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
/* LLC driver is the Last Level Cache (L3C) driver
|
||||
* for Marvell SoCs in AP806, AP807, and AP810
|
||||
*/
|
||||
|
||||
#ifndef CACHE_LLC_H
|
||||
#define CACHE_LLC_H
|
||||
|
||||
#define LLC_CTRL(ap) (MVEBU_LLC_BASE(ap) + 0x100)
|
||||
#define LLC_SECURE_CTRL(ap) (MVEBU_LLC_BASE(ap) + 0x10C)
|
||||
#define LLC_SYNC(ap) (MVEBU_LLC_BASE(ap) + 0x700)
|
||||
#define LLC_BANKED_MNT_AHR(ap) (MVEBU_LLC_BASE(ap) + 0x724)
|
||||
#define LLC_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x77C)
|
||||
#define LLC_BLK_ALOC(ap) (MVEBU_LLC_BASE(ap) + 0x78c)
|
||||
#define LLC_CLEAN_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7BC)
|
||||
#define LLC_CLEAN_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7FC)
|
||||
#define LLC_TCN_LOCK(ap, tc) (MVEBU_LLC_BASE(ap) + 0x920 + 4 * (tc))
|
||||
|
||||
#define MASTER_LLC_CTRL LLC_CTRL(MVEBU_AP0)
|
||||
#define MASTER_LLC_INV_WAY LLC_INV_WAY(MVEBU_AP0)
|
||||
#define MASTER_LLC_TC0_LOCK LLC_TCN_LOCK(MVEBU_AP0, 0)
|
||||
|
||||
#define LLC_CTRL_EN 1
|
||||
#define LLC_EXCLUSIVE_EN 0x100
|
||||
#define LLC_ALL_WAYS_MASK 0xFFFFFFFF
|
||||
|
||||
/* AP806/AP807 - 1MB 8-ways LLC */
|
||||
#define LLC_WAYS 8
|
||||
#define LLC_WAY_MASK ((1 << LLC_WAYS) - 1)
|
||||
#define LLC_SIZE (1024 * 1024)
|
||||
#define LLC_WAY_SIZE (LLC_SIZE / LLC_WAYS)
|
||||
#define LLC_TC_NUM 15
|
||||
|
||||
#define LLC_BLK_ALOC_WAY_ID(way) ((way) & 0x1f)
|
||||
#define LLC_BLK_ALOC_WAY_DATA_DSBL (0x0 << 6)
|
||||
#define LLC_BLK_ALOC_WAY_DATA_CLR (0x1 << 6)
|
||||
#define LLC_BLK_ALOC_WAY_DATA_SET (0x3 << 6)
|
||||
#define LLC_BLK_ALOC_BASE_ADDR(addr) ((addr) & ~(LLC_WAY_SIZE - 1))
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
void llc_cache_sync(int ap_index);
|
||||
void llc_flush_all(int ap_index);
|
||||
void llc_clean_all(int ap_index);
|
||||
void llc_inv_all(int ap_index);
|
||||
void llc_disable(int ap_index);
|
||||
void llc_enable(int ap_index, int excl_mode);
|
||||
int llc_is_exclusive(int ap_index);
|
||||
void llc_runtime_enable(int ap_index);
|
||||
#if LLC_SRAM
|
||||
int llc_sram_enable(int ap_index, int size);
|
||||
void llc_sram_disable(int ap_index);
|
||||
int llc_sram_test(int ap_index, int size, char *msg);
|
||||
#endif /* LLC_SRAM */
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* CACHE_LLC_H */
|
||||
@@ -0,0 +1,53 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
/* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */
|
||||
|
||||
#ifndef CCU_H
|
||||
#define CCU_H
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <drivers/marvell/addr_map.h>
|
||||
#endif
|
||||
|
||||
/* CCU registers definitions */
|
||||
#define CCU_WIN_CR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x0 + \
|
||||
(0x10 * win))
|
||||
#define CCU_TARGET_ID_OFFSET (8)
|
||||
#define CCU_TARGET_ID_MASK (0x7F)
|
||||
|
||||
#define CCU_WIN_SCR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x4 + \
|
||||
(0x10 * win))
|
||||
#define CCU_WIN_ENA_WRITE_SECURE (0x1)
|
||||
#define CCU_WIN_ENA_READ_SECURE (0x2)
|
||||
|
||||
#define CCU_WIN_ALR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x8 + \
|
||||
(0x10 * win))
|
||||
#define CCU_WIN_AHR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0xC + \
|
||||
(0x10 * win))
|
||||
|
||||
#define CCU_WIN_GCR_OFFSET(ap) (MVEBU_CCU_BASE(ap) + 0xD0)
|
||||
#define CCU_GCR_TARGET_OFFSET (8)
|
||||
#define CCU_GCR_TARGET_MASK (0xFF)
|
||||
|
||||
#define CCU_SRAM_WIN_CR CCU_WIN_CR_OFFSET(MVEBU_AP0, 1)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
int init_ccu(int);
|
||||
void ccu_win_check(struct addr_map_win *win);
|
||||
void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id);
|
||||
void ccu_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
|
||||
void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
|
||||
void ccu_dram_win_config(int ap_index, struct addr_map_win *win);
|
||||
void ccu_dram_target_set(int ap_index, uint32_t target);
|
||||
void ccu_save_win_all(int ap_id);
|
||||
void ccu_restore_win_all(int ap_id);
|
||||
int ccu_is_win_enabled(int ap_index, uint32_t win_id);
|
||||
void errata_wa_init(void);
|
||||
#endif
|
||||
|
||||
#endif /* CCU_H */
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
/* GWIN unit device driver for Marvell AP810 SoC */
|
||||
|
||||
#ifndef GWIN_H
|
||||
#define GWIN_H
|
||||
|
||||
#include <drivers/marvell/addr_map.h>
|
||||
|
||||
int init_gwin(int ap_index);
|
||||
void gwin_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
|
||||
void gwin_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
|
||||
|
||||
#endif /* GWIN_H */
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef I2C_H
|
||||
#define I2C_H
|
||||
|
||||
|
||||
void i2c_init(void);
|
||||
|
||||
int i2c_read(uint8_t chip,
|
||||
unsigned int addr, int alen, uint8_t *buffer, int len);
|
||||
|
||||
int i2c_write(uint8_t chip,
|
||||
unsigned int addr, int alen, uint8_t *buffer, int len);
|
||||
|
||||
#endif /* I2C_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
/* IO Window unit device driver for Marvell AP807, AP807 and AP810 SoCs */
|
||||
|
||||
#ifndef IO_WIN_H
|
||||
#define IO_WIN_H
|
||||
|
||||
#include <drivers/marvell/addr_map.h>
|
||||
|
||||
int init_io_win(int ap_index);
|
||||
void iow_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
|
||||
void iow_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
|
||||
void iow_save_win_all(int ap_id);
|
||||
void iow_restore_win_all(int ap_id);
|
||||
|
||||
#endif /* IO_WIN_H */
|
||||
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
/* IOW unit device driver for Marvell CP110 and CP115 SoCs */
|
||||
|
||||
#ifndef IOB_H
|
||||
#define IOB_H
|
||||
|
||||
#include <drivers/marvell/addr_map.h>
|
||||
|
||||
enum target_ids_iob {
|
||||
INTERNAL_TID = 0x0,
|
||||
MCI0_TID = 0x1,
|
||||
PEX1_TID = 0x2,
|
||||
PEX2_TID = 0x3,
|
||||
PEX0_TID = 0x4,
|
||||
NAND_TID = 0x5,
|
||||
RUNIT_TID = 0x6,
|
||||
MCI1_TID = 0x7,
|
||||
IOB_MAX_TID
|
||||
};
|
||||
|
||||
int init_iob(uintptr_t base);
|
||||
void iob_cfg_space_update(int ap_idx, int cp_idx,
|
||||
uintptr_t base, uintptr_t new_base);
|
||||
|
||||
#endif /* IOB_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
/* MCI bus driver for Marvell ARMADA 8K and 8K+ SoCs */
|
||||
|
||||
#ifndef MCI_H
|
||||
#define MCI_H
|
||||
|
||||
int mci_link_tune(int mci_index);
|
||||
void mci_turn_link_down(void);
|
||||
void mci_turn_link_on(void);
|
||||
int mci_get_link_status(void);
|
||||
|
||||
#endif /* MCI_H */
|
||||
+18
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
/* AP8xx Marvell SoC driver */
|
||||
|
||||
#ifndef AP_SETUP_H
|
||||
#define AP_SETUP_H
|
||||
|
||||
void ap_init(void);
|
||||
void ap_ble_init(void);
|
||||
int ap_get_count(void);
|
||||
void update_cp110_default_win(int cp_id);
|
||||
|
||||
#endif /* AP_SETUP_H */
|
||||
+66
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
/* CP110 Marvell SoC driver */
|
||||
|
||||
#ifndef CP110_SETUP_H
|
||||
#define CP110_SETUP_H
|
||||
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <mvebu_def.h>
|
||||
|
||||
#define MVEBU_DEVICE_ID_REG (MVEBU_CP_DFX_OFFSET + 0x40)
|
||||
#define MVEBU_DEVICE_ID_OFFSET (0)
|
||||
#define MVEBU_DEVICE_ID_MASK (0xffff << MVEBU_DEVICE_ID_OFFSET)
|
||||
#define MVEBU_DEVICE_REV_OFFSET (16)
|
||||
#define MVEBU_DEVICE_REV_MASK (0xf << MVEBU_DEVICE_REV_OFFSET)
|
||||
#define MVEBU_70X0_DEV_ID (0x7040)
|
||||
#define MVEBU_70X0_CP115_DEV_ID (0x7045)
|
||||
#define MVEBU_3900_DEV_ID (0x6025)
|
||||
#define MVEBU_80X0_DEV_ID (0x8040)
|
||||
#define MVEBU_80X0_CP115_DEV_ID (0x8045)
|
||||
#define MVEBU_CN9130_DEV_ID (0x7025)
|
||||
#define MVEBU_CP110_SA_DEV_ID (0x110)
|
||||
#define MVEBU_CP110_REF_ID_A1 1
|
||||
#define MVEBU_CP110_REF_ID_A2 2
|
||||
#define MAX_STREAM_ID_PER_CP (0x10)
|
||||
#define STREAM_ID_BASE (0x40)
|
||||
|
||||
#define MVEBU_SECUREBOOT_CTRL_REG (MVEBU_RFU_BASE + 0x4730)
|
||||
#define MVEBU_SECUREBOOT_EN_MASK BIT(0)
|
||||
|
||||
static inline uint32_t cp110_device_id_get(uintptr_t base)
|
||||
{
|
||||
/* Returns:
|
||||
* - MVEBU_70X0_DEV_ID for A70X0 family
|
||||
* - MVEBU_80X0_DEV_ID for A80X0 family
|
||||
* - MVEBU_CP110_SA_DEV_ID for CP that connected stand alone
|
||||
*/
|
||||
return (mmio_read_32(base + MVEBU_DEVICE_ID_REG) >>
|
||||
MVEBU_DEVICE_ID_OFFSET) &
|
||||
MVEBU_DEVICE_ID_MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t cp110_rev_id_get(uintptr_t base)
|
||||
{
|
||||
return (mmio_read_32(base + MVEBU_DEVICE_ID_REG) &
|
||||
MVEBU_DEVICE_REV_MASK) >>
|
||||
MVEBU_DEVICE_REV_OFFSET;
|
||||
}
|
||||
|
||||
static inline uint32_t is_secure(void)
|
||||
{
|
||||
return !!(mmio_read_32(MVEBU_SECUREBOOT_CTRL_REG) &
|
||||
MVEBU_SECUREBOOT_EN_MASK);
|
||||
}
|
||||
|
||||
void cp110_init(uintptr_t cp110_base, uint32_t stream_id);
|
||||
void cp110_ble_init(uintptr_t cp110_base);
|
||||
void cp110_amb_init(uintptr_t base);
|
||||
|
||||
#endif /* CP110_SETUP_H */
|
||||
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
/* Driver for thermal unit located in Marvell ARMADA 8K and compatible SoCs */
|
||||
|
||||
#ifndef THERMAL_H
|
||||
#define THERMAL_H
|
||||
|
||||
struct tsen_config {
|
||||
/* thermal temperature parameters */
|
||||
int tsen_offset;
|
||||
int tsen_gain;
|
||||
int tsen_divisor;
|
||||
/* thermal data */
|
||||
int tsen_ready;
|
||||
void *regs_base;
|
||||
/* thermal functionality */
|
||||
int (*ptr_tsen_probe)(struct tsen_config *cfg);
|
||||
int (*ptr_tsen_read)(struct tsen_config *cfg, int *temp);
|
||||
};
|
||||
|
||||
/* Thermal driver APIs */
|
||||
int marvell_thermal_init(struct tsen_config *tsen_cfg);
|
||||
int marvell_thermal_read(struct tsen_config *tsen_cfg, int *temp);
|
||||
struct tsen_config *marvell_thermal_config_get(void);
|
||||
|
||||
#endif /* THERMAL_H */
|
||||
+74
@@ -0,0 +1,74 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef A3700_CONSOLE_H
|
||||
#define A3700_CONSOLE_H
|
||||
|
||||
#include <drivers/console.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
/* MVEBU UART Registers */
|
||||
#define UART_RX_REG 0x00
|
||||
#define UART_TX_REG 0x04
|
||||
#define UART_CTRL_REG 0x08
|
||||
#define UART_STATUS_REG 0x0c
|
||||
#define UART_BAUD_REG 0x10
|
||||
#define UART_POSSR_REG 0x14
|
||||
|
||||
/* FIFO Control Register bits */
|
||||
#define UARTFCR_FIFOMD_16450 (0 << 6)
|
||||
#define UARTFCR_FIFOMD_16550 (1 << 6)
|
||||
#define UARTFCR_RXTRIG_1 (0 << 6)
|
||||
#define UARTFCR_RXTRIG_4 (1 << 6)
|
||||
#define UARTFCR_RXTRIG_8 (2 << 6)
|
||||
#define UARTFCR_RXTRIG_16 (3 << 6)
|
||||
#define UARTFCR_TXTRIG_1 (0 << 4)
|
||||
#define UARTFCR_TXTRIG_4 (1 << 4)
|
||||
#define UARTFCR_TXTRIG_8 (2 << 4)
|
||||
#define UARTFCR_TXTRIG_16 (3 << 4)
|
||||
#define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */
|
||||
#define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */
|
||||
#define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */
|
||||
#define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */
|
||||
|
||||
/* Line Control Register bits */
|
||||
#define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */
|
||||
#define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */
|
||||
#define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */
|
||||
#define UARTLCR_EVEN (1 << 4) /* Even Parity Format */
|
||||
#define UARTLCR_PAR (1 << 3) /* Parity */
|
||||
#define UARTLCR_STOP (1 << 2) /* Stop Bit */
|
||||
#define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */
|
||||
#define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */
|
||||
#define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */
|
||||
#define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */
|
||||
|
||||
/* Line Status Register bits */
|
||||
#define UARTLSR_TXFIFOFULL (1 << 11) /* Tx Fifo Full */
|
||||
#define UARTLSR_TXEMPTY (1 << 6) /* Tx Empty */
|
||||
#define UARTLSR_RXRDY (1 << 4) /* Rx Ready */
|
||||
|
||||
/* UART Control Register bits */
|
||||
#define UART_CTRL_RXFIFO_RESET (1 << 14)
|
||||
#define UART_CTRL_TXFIFO_RESET (1 << 15)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Initialize a new a3700 console instance and register it with the console
|
||||
* framework. The |console| pointer must point to storage that will be valid
|
||||
* for the lifetime of the console, such as a global or static local variable.
|
||||
* Its contents will be reinitialized from scratch.
|
||||
*/
|
||||
int console_a3700_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
|
||||
console_t *console);
|
||||
|
||||
#endif /*__ASSEMBLER__*/
|
||||
|
||||
#endif /* A3700_CONSOLE_H */
|
||||
Reference in New Issue
Block a user