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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
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source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/auth/csf_hdr_parser/csf_hdr.h
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/*
* Copyright 2017-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef CSF_HDR_H
#define CSF_HDR_H
#include "caam.h"
#include "hash.h"
#include "rsa.h"
/* Barker code size in bytes */
#define CSF_BARKER_LEN 4 /* barker code length in ESBC uboot client */
/* header */
#ifdef CSF_HDR_CH3
struct csf_hdr {
uint8_t barker[CSF_BARKER_LEN]; /* 0x00 Barker code */
uint32_t srk_tbl_off; /* 0x04 SRK Table Offset */
struct {
uint8_t num_srk; /* 0x08 No. of keys */
uint8_t srk_sel; /* Key no. to be used */
uint8_t reserve; /* 0x0a rseerved */
} len_kr;
uint8_t ie_flag;
uint32_t uid_flag;
uint32_t psign; /* 0x10 signature offset */
uint32_t sign_len; /* 0x14 length of signature */
union {
struct {
uint32_t sg_table_offset; /* 0x18 SG Table Offset */
uint32_t sg_entries; /* 0x1c no of entries in SG */
} sg_isbc;
uint64_t img_addr; /* 64 bit pointer to ESBC Image */
};
union {
struct {
uint32_t img_size; /* ESBC client img size in bytes */
uint32_t ie_key_sel;
} img;
uint64_t entry_point; /* 0x20-0x24 ESBC entry point */
};
uint32_t fsl_uid_0; /* 0x28 Freescale unique id 0 */
uint32_t fsl_uid_1; /* 0x2c Freescale unique id 1 */
uint32_t oem_uid_0; /* 0x30 OEM unique id 0 */
uint32_t oem_uid_1; /* 0x34 OEM unique id 1 */
uint32_t oem_uid_2; /* 0x38 OEM unique id 2 */
uint32_t oem_uid_3; /* 0x3c OEM unique id 3 */
uint32_t oem_uid_4; /* 0x40 OEM unique id 4 */
uint32_t reserved[3]; /* 0x44 - 0x4f */
};
/* Srk table and key revocation check */
#define UNREVOCABLE_KEY 8
#define REVOC_KEY_ALIGN 7
#define MAX_KEY_ENTRIES 8
#else
/* CSF header for Chassis 2 */
struct csf_hdr {
uint8_t barker[CSF_BARKER_LEN]; /* barker code */
union {
uint32_t pkey; /* public key offset */
uint32_t srk_tbl_off;
};
union {
uint32_t key_len; /* pub key length in bytes */
struct {
uint32_t srk_table_flag:8;
uint32_t srk_sel:8;
uint32_t num_srk:16;
} len_kr;
};
uint32_t psign; /* signature offset */
uint32_t sign_len; /* length of the signature in bytes */
/* SG Table used by ISBC header */
union {
struct {
uint32_t sg_table_offset; /* 0x14 SG Table Offset */
uint32_t sg_entries; /* no of entries in SG table */
} sg_isbc;
struct {
uint32_t reserved1; /* Reserved field */
uint32_t img_size; /* ESBC img size in bytes */
} img;
};
uint32_t entry_point; /* ESBC client entry point */
uint32_t reserved2; /* Scatter gather flag */
uint32_t uid_flag;
uint32_t fsl_uid_0;
uint32_t oem_uid_0;
uint32_t reserved3[2];
uint32_t fsl_uid_1;
uint32_t oem_uid_1;
/* The entries below aren't present in ISBC header */
uint64_t img_addr; /* 64 bit pointer to ESBC Image */
uint32_t ie_flag;
uint32_t ie_key_sel;
};
/* Srk table and key revocation check */
#define UNREVOCABLE_KEY 4
#define REVOC_KEY_ALIGN 3
#define MAX_KEY_ENTRIES 4
#endif
struct srk_table {
uint32_t key_len;
uint8_t pkey[2 * RSA_4K_KEY_SZ_BYTES];
};
/*
* This struct contains the following fields
* length of the segment
* Destination Target ID
* source address
* destination address
*/
struct sg_table {
uint32_t len; /* Length of Image */
uint32_t res1;
union {
uint64_t src_addr; /* SRC Address of Image */
struct {
uint32_t src_addr;
uint32_t dst_addr;
} img;
};
};
int validate_esbc_header(void *img_hdr, void **img_key, uint32_t *key_len,
void **img_sign, uint32_t *sign_len,
enum sig_alg *algo);
int calc_img_hash(struct csf_hdr *hdr, void *img_addr, uint32_t img_size,
uint8_t *img_hash, uint32_t *hash_len);
#endif
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/console/plat_console.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef PLAT_CONSOLE_H
#define PLAT_CONSOLE_H
#include <stdint.h>
#include <drivers/console.h>
#if (NXP_CONSOLE == NS16550)
/*
* NXP specific UART - 16550 configuration
*
* Initialize a NXP 16550 console instance and register it with the console
* framework. The |console| pointer must point to storage that will be valid
* for the lifetime of the console, such as a global or static local variable.
* Its contents will be reinitialized from scratch.
* When |clock| has a value of 0, the UART will *not* be initialised. This
* means the UART should already be enabled and the baudrate and clock setup
* should have been done already, either by platform specific code or by
* previous firmware stages. The |baud| parameter will be ignored in this
* case as well.
*/
int nxp_console_16550_register(uintptr_t baseaddr, uint32_t clock,
uint32_t baud, console_t *console);
#endif
/*
* Function to initialize platform's console
* and register with console framework
*/
void plat_console_init(uintptr_t nxp_console_addr, uint32_t uart_clk_div,
uint32_t baud);
#endif
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/crypto/caam/caam.h
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/*
* Copyright 2017-2022 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef CAAM_H
#define CAAM_H
#include "caam_io.h"
#include "sec_jr_driver.h"
/* Job ring 3 is reserved for usage by sec firmware */
#define DEFAULT_JR 3
#if defined(CONFIG_CHASSIS_3_2) || defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_2)
#define CAAM_JR0_OFFSET 0x10000
#define CAAM_JR1_OFFSET 0x20000
#define CAAM_JR2_OFFSET 0x30000
#define CAAM_JR3_OFFSET 0x40000
#endif
enum sig_alg {
RSA,
ECC
};
/* This function does basic SEC Initialization */
int sec_init(uintptr_t nxp_caam_addr);
int config_sec_block(void);
uintptr_t get_caam_addr(void);
/* This function is used to submit jobs to JR */
int run_descriptor_jr(struct job_descriptor *desc);
/* This function is used to instatiate the HW RNG is already not instantiated */
int hw_rng_instantiate(void);
/* This function is used to return random bytes of byte_len from HW RNG */
int get_rand_bytes_hw(uint8_t *bytes, int byte_len);
/* This function is used to set the hw unique key from HW CAAM */
int get_hw_unq_key_blob_hw(uint8_t *hw_key, int size);
/* This function is used to fetch random number from
* CAAM of length either of 4 bytes or 8 bytes depending
* rngWidth value.
*/
unsigned long long get_random(int rngWidth);
#endif /* CAAM_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/crypto/caam/caam_io.h
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/*
* Copyright 2018-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef CAAM_IO_H
#define CAAM_IO_H
#include <endian.h>
#include <lib/mmio.h>
typedef unsigned long long phys_addr_t;
typedef unsigned long long phys_size_t;
/* Return higher 32 bits of physical address */
#define PHYS_ADDR_HI(phys_addr) \
(uint32_t)(((uint64_t)phys_addr) >> 32)
/* Return lower 32 bits of physical address */
#define PHYS_ADDR_LO(phys_addr) \
(uint32_t)(((uint64_t)phys_addr) & 0xFFFFFFFF)
#ifdef NXP_SEC_BE
#define sec_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
#define sec_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
#define sec_in64(addr) ( \
((uint64_t)sec_in32((uintptr_t)(addr)) << 32) | \
(sec_in32(((uintptr_t)(addr)) + 4)))
#define sec_out64(addr, val) ({ \
sec_out32(((uintptr_t)(addr)), (uint32_t)((val) >> 32)); \
sec_out32(((uintptr_t)(addr)) + 4, (uint32_t)(val)); })
#elif defined(NXP_SEC_LE)
#define sec_in32(a) mmio_read_32((uintptr_t)(a))
#define sec_out32(a, v) mmio_write_32((uintptr_t)(a), (v))
#define sec_in64(addr) ( \
((uint64_t)sec_in32((uintptr_t)(addr) + 4) << 32) | \
(sec_in32((uintptr_t)(addr))))
#define sec_out64(addr, val) ({ \
sec_out32(((uintptr_t)(addr)) + 4, (uint32_t)((val) >> 32)); \
sec_out32(((uintptr_t)(addr)), (uint32_t)(val)); })
#else
#error Please define CCSR SEC register endianness
#endif
static inline void *ptov(phys_addr_t *ptr)
{
return (void *)ptr;
}
static inline phys_addr_t *vtop(void *ptr)
{
return (phys_addr_t *)ptr;
}
#endif /* CAAM_IO_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/crypto/caam/hash.h
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/*
* Copyright 2017-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef __HASH_H__
#define __HASH_H__
#include <stdbool.h>
/* List of hash algorithms */
enum hash_algo {
SHA1 = 0,
SHA256
};
/* number of bytes in the SHA256-256 digest */
#define SHA256_DIGEST_SIZE 32
/*
* number of words in the digest - Digest is kept internally
* as 8 32-bit words
*/
#define _SHA256_DIGEST_LENGTH 8
/*
* block length - A block, treated as a sequence of
* 32-bit words
*/
#define SHA256_BLOCK_LENGTH 16
/* number of bytes in the block */
#define SHA256_DATA_SIZE 64
#define MAX_SG 12
struct sg_entry {
#if defined(NXP_SEC_LE)
uint32_t addr_lo; /* Memory Address - lo */
uint32_t addr_hi; /* Memory Address of start of buffer - hi */
#else
uint32_t addr_hi; /* Memory Address of start of buffer - hi */
uint32_t addr_lo; /* Memory Address - lo */
#endif
uint32_t len_flag; /* Length of the data in the frame */
#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
#define SG_ENTRY_EXTENSION_BIT 0x80000000
#define SG_ENTRY_FINAL_BIT 0x40000000
uint32_t bpid_offset;
#define SG_ENTRY_BPID_MASK 0x00FF0000
#define SG_ENTRY_BPID_SHIFT 16
#define SG_ENTRY_OFFSET_MASK 0x00001FFF
#define SG_ENTRY_OFFSET_SHIFT 0
};
/*
* SHA256-256 context
* contain the following fields
* State
* count low
* count high
* block data buffer
* index to the buffer
*/
struct hash_ctx {
struct sg_entry sg_tbl[MAX_SG];
uint32_t hash_desc[64];
uint8_t hash[SHA256_DIGEST_SIZE];
uint32_t sg_num;
uint32_t len;
uint8_t *data;
enum hash_algo algo;
bool active;
};
int hash_init(enum hash_algo algo, void **ctx);
int hash_update(enum hash_algo algo, void *context, void *data_ptr,
unsigned int data_len);
int hash_final(enum hash_algo algo, void *context, void *hash_ptr,
unsigned int hash_len);
#endif
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/crypto/caam/jobdesc.h
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/*
* Copyright 2017-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef __JOBDESC_H
#define __JOBDESC_H
#include <rsa.h>
#define DESC_LEN_MASK 0x7f
#define DESC_START_SHIFT 16
#define KEY_BLOB_SIZE 32
#define MAC_SIZE 16
#define KEY_IDNFR_SZ_BYTES 16
#define CLASS_SHIFT 25
#define CLASS_2 (0x02 << CLASS_SHIFT)
#define CMD_SHIFT 27
#define CMD_OPERATION (U(0x10) << CMD_SHIFT)
#define OP_TYPE_SHIFT 24
#define OP_TYPE_ENCAP_PROTOCOL (0x07 << OP_TYPE_SHIFT)
/* Assuming OP_TYPE = OP_TYPE_UNI_PROTOCOL */
#define OP_PCLID_SHIFT 16
#define OP_PCLID_BLOB (0x0d << OP_PCLID_SHIFT)
#define BLOB_PROTO_INFO 0x00000002
uint32_t desc_length(uint32_t *desc);
int cnstr_rng_jobdesc(uint32_t *desc, uint32_t state_handle,
uint32_t *add_inp, uint32_t add_ip_len,
uint8_t *out_data, uint32_t len);
int cnstr_rng_instantiate_jobdesc(uint32_t *desc);
/* Construct descriptor to generate hw key blob */
int cnstr_hw_encap_blob_jobdesc(uint32_t *desc,
uint8_t *key_idnfr, uint32_t key_sz,
uint32_t key_class, uint8_t *plain_txt,
uint32_t in_sz, uint8_t *enc_blob,
uint32_t out_sz, uint32_t operation);
void cnstr_hash_jobdesc(uint32_t *desc, uint8_t *msg, uint32_t msgsz,
uint8_t *digest);
void cnstr_jobdesc_pkha_rsaexp(uint32_t *desc,
struct pk_in_params *pkin, uint8_t *out,
uint32_t out_siz);
#endif
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/crypto/caam/jr_driver_config.h
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/*
* Copyright 2017-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef _JR_DRIVER_CONFIG_H_
#define _JR_DRIVER_CONFIG_H_
/* Helper defines */
/* Define used for setting a flag on */
#define ON 1
/* Define used for setting a flag off */
#define OFF 0
/* SEC is configured to start work in polling mode, */
#define SEC_STARTUP_POLLING_MODE 0
/*
* SEC is configured to start work in interrupt mode,
* when configured for NAPI notification style.
*/
#define SEC_STARTUP_INTERRUPT_MODE 1
/*
* SEC driver will use ONLY interrupts to receive notifications
* for processed packets from SEC engine hardware.
*/
#define SEC_NOTIFICATION_TYPE_IRQ 1
/*
* SEC driver will use ONLY polling to receive notifications
* for processed packets from SEC engine hardware.
*/
#define SEC_NOTIFICATION_TYPE_POLL 2
/*
* Determines how SEC user space driver will receive notifications
* for processed packets from SEC engine.
* Valid values are: #SEC_NOTIFICATION_TYPE_POLL, #SEC_NOTIFICATION_TYPE_IRQ
*/
#define SEC_NOTIFICATION_TYPE SEC_NOTIFICATION_TYPE_POLL
/* Maximum number of job rings supported by SEC hardware */
#define MAX_SEC_JOB_RINGS 1
/*
* Size of cryptographic context that is used directly in communicating
* with SEC device.
* SEC device works only with physical addresses. This is the maximum size
* for a SEC descriptor ( = 64 words).
*/
#define SEC_CRYPTO_DESCRIPTOR_SIZE 256
/*
* Size of job descriptor submitted to SEC device for each packet to be
* processed.
* Job descriptor contains 3 DMA address pointers:
* - to shared descriptor, to input buffer and to output buffer.
* The job descriptor contains other SEC specific commands as well:
* - HEADER command, SEQ IN PTR command SEQ OUT PTR command and opaque
* data, each measuring 4 bytes.
* Job descriptor size, depending on physical address representation:
* - 32 bit - size is 28 bytes - cacheline-aligned size is 64 bytes
* - 36 bit - size is 40 bytes - cacheline-aligned size is 64 bytes
* @note: Job descriptor must be cacheline-aligned to ensure efficient memory
* access.
* @note: If other format is used for job descriptor, then the size must be
* revised.
*/
#define SEC_JOB_DESCRIPTOR_SIZE 64
/*
* Size of one entry in the input ring of a job ring.
* Input ring contains pointers to job descriptors.
* The memory used for an input ring and output ring must be physically
* contiguous.
*/
#define SEC_JOB_INPUT_RING_ENTRY_SIZE sizeof(phys_addr_t)
/*
* Size of one entry in the output ring of a job ring.
* Output ring entry is a pointer to a job descriptor followed by a 4 byte
* status word.
* The memory used for an input ring and output ring must be physically
* contiguous.
* @note If desired to use also the optional SEQ OUT indication in output
* ring entries, then 4 more bytes must be added to the size.
*/
#define SEC_JOB_OUTPUT_RING_ENTRY_SIZE (SEC_JOB_INPUT_RING_ENTRY_SIZE + 4)
/* DMA memory required for an input ring of a job ring. */
#define SEC_DMA_MEM_INPUT_RING_SIZE \
((SEC_JOB_INPUT_RING_ENTRY_SIZE) * (SEC_JOB_RING_SIZE))
/*
* DMA memory required for an output ring of a job ring.
* Required extra 4 byte for status word per each entry.
*/
#define SEC_DMA_MEM_OUTPUT_RING_SIZE \
((SEC_JOB_OUTPUT_RING_ENTRY_SIZE) * (SEC_JOB_RING_SIZE))
/* DMA memory required for descriptors of a job ring. */
#define SEC_DMA_MEM_DESCRIPTORS \
((SEC_CRYPTO_DESCRIPTOR_SIZE)*(SEC_JOB_RING_SIZE))
/* DMA memory required for a job ring, including both input output rings. */
#define SEC_DMA_MEM_JOB_RING_SIZE \
((SEC_DMA_MEM_INPUT_RING_SIZE) + \
(SEC_DMA_MEM_OUTPUT_RING_SIZE))
/*
* When calling sec_init() UA will provide an area of virtual memory
* of size #SEC_DMA_MEMORY_SIZE to be used internally by the driver
* to allocate data (like SEC descriptors) that needs to be passed to
* SEC device in physical addressing and later on retrieved from SEC device.
* At initialization the UA provides specialized ptov/vtop functions/macros to
* translate addresses allocated from this memory area.
*/
#define SEC_DMA_MEMORY_SIZE \
((SEC_DMA_MEM_JOB_RING_SIZE) * (MAX_SEC_JOB_RINGS))
/*
* SEC DEVICE related configuration.
* Enable/Disable logging support at compile time.
* Valid values:
* ON - enable logging
* OFF - disable logging
* The messages are logged at stdout.
*/
#define SEC_DRIVER_LOGGING OFF
/*
* Configure logging level at compile time.
* Valid values:
* SEC_DRIVER_LOG_ERROR - log only errors
* SEC_DRIVER_LOG_INFO - log errors and info messages
* SEC_DRIVER_LOG_DEBUG - log errors, info and debug messages
*/
#define SEC_DRIVER_LOGGING_LEVEL SEC_DRIVER_LOG_DEBUG
/*
* SEC JOB RING related configuration.
* Configure the size of the JOB RING.
* The maximum size of the ring is hardware limited to 1024.
* However the number of packets in flight in a time interval of
* 1ms can be calculated
* from the traffic rate (Mbps) and packet size.
* Here it was considered a packet size of 40 bytes.
* @note Round up to nearest power of 2 for optimized update
* of producer/consumer indexes of each job ring
* \todo Should set to 750, according to the calculation above, but
* the JR size must be power of 2, thus the next closest value must
* be chosen (i.e. 512 since 1024 is not available)
* For firmware choose this to be 16
*/
#define SEC_JOB_RING_SIZE 16
/*
* Interrupt coalescing related configuration.
* NOTE: SEC hardware enabled interrupt
* coalescing is not supported on SEC version 3.1!
* SEC version 4.4 has support for interrupt
* coalescing.
*/
#if SEC_NOTIFICATION_TYPE != SEC_NOTIFICATION_TYPE_POLL
#define SEC_INT_COALESCING_ENABLE ON
/*
* Interrupt Coalescing Descriptor Count Threshold.
* While interrupt coalescing is enabled (ICEN=1), this value determines
* how many Descriptors are completed before raising an interrupt.
* Valid values for this field are from 0 to 255.
* Note that a value of 1 functionally defeats the advantages of interrupt
* coalescing since the threshold value is reached each time that a
* Job Descriptor is completed. A value of 0 is treated in the same
* manner as a value of 1.
*
*/
#define SEC_INTERRUPT_COALESCING_DESCRIPTOR_COUNT_THRESH 10
/*
* Interrupt Coalescing Timer Threshold.
* While interrupt coalescing is enabled (ICEN=1), this value determines the
* maximum amount of time after processing a Descriptor before raising an
* interrupt.
* The threshold value is represented in units equal to 64 CAAM interface
* clocks. Valid values for this field are from 1 to 65535.
* A value of 0 results in behavior identical to that when interrupt
* coalescing is disabled.
*/
#define SEC_INTERRUPT_COALESCING_TIMER_THRESH 100
#endif /* SEC_NOTIFICATION_TYPE_POLL */
#endif /* _JR_DRIVER_CONFIG_H_ */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/crypto/caam/rsa.h
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/*
* Copyright 2017-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef _RSA_H__
#define _RSA_H__
/* RSA key size defines */
#define RSA_4K_KEY_SZ 4096
#define RSA_4K_KEY_SZ_BYTES (RSA_4K_KEY_SZ/8)
#define RSA_2K_KEY_SZ 2048
#define RSA_2K_KEY_SZ_BYTES (RSA_2K_KEY_SZ/8)
#define RSA_1K_KEY_SZ 1024
#define RSA_1K_KEY_SZ_BYTES (RSA_1K_KEY_SZ/8)
#define SHA256_BYTES (256/8)
struct pk_in_params {
uint8_t *e;
uint32_t e_siz;
uint8_t *n;
uint32_t n_siz;
uint8_t *a;
uint32_t a_siz;
uint8_t *b;
uint32_t b_siz;
};
struct rsa_context {
struct pk_in_params pkin;
};
int rsa_verify_signature(void *hash_ptr, unsigned int hash_len,
void *sig_ptr, unsigned int sig_len,
void *pk_ptr, unsigned int pk_len);
#endif
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/crypto/caam/sec_hw_specific.h
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/*
* Copyright 2017-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef _SEC_HW_SPECIFIC_H_
#define _SEC_HW_SPECIFIC_H_
#include "caam.h"
#include "sec_jr_driver.h"
/* DEFINES AND MACROS */
/* Used to retry resetting a job ring in SEC hardware. */
#define SEC_TIMEOUT 100000
/*
* Offset to the registers of a job ring.
*Is different for each job ring.
*/
#define CHAN_BASE(jr) ((phys_addr_t)(jr)->register_base_addr)
#define unlikely(x) __builtin_expect(!!(x), 0)
#define SEC_JOB_RING_IS_FULL(pi, ci, ring_max_size, ring_threshold) \
((((pi) + 1 + ((ring_max_size) - (ring_threshold))) & \
(ring_max_size - 1)) == ((ci)))
#define SEC_CIRCULAR_COUNTER(x, max) (((x) + 1) & (max - 1))
/* Struct representing various job ring registers */
struct jobring_regs {
#ifdef NXP_SEC_BE
unsigned int irba_h;
unsigned int irba_l;
#else
unsigned int irba_l;
unsigned int irba_h;
#endif
unsigned int rsvd1;
unsigned int irs;
unsigned int rsvd2;
unsigned int irsa;
unsigned int rsvd3;
unsigned int irja;
#ifdef NXP_SEC_BE
unsigned int orba_h;
unsigned int orba_l;
#else
unsigned int orba_l;
unsigned int orba_h;
#endif
unsigned int rsvd4;
unsigned int ors;
unsigned int rsvd5;
unsigned int orjr;
unsigned int rsvd6;
unsigned int orsf;
unsigned int rsvd7;
unsigned int jrsta;
unsigned int rsvd8;
unsigned int jrint;
unsigned int jrcfg0;
unsigned int jrcfg1;
unsigned int rsvd9;
unsigned int irri;
unsigned int rsvd10;
unsigned int orwi;
unsigned int rsvd11;
unsigned int jrcr;
};
/* Offsets representing common SEC Registers */
#define SEC_REG_MCFGR_OFFSET 0x0004
#define SEC_REG_SCFGR_OFFSET 0x000C
#define SEC_REG_JR0ICIDR_MS_OFFSET 0x0010
#define SEC_REG_JR0ICIDR_LS_OFFSET 0x0014
#define SEC_REG_JR1ICIDR_MS_OFFSET 0x0018
#define SEC_REG_JR1ICIDR_LS_OFFSET 0x001C
#define SEC_REG_JR2ICIDR_MS_OFFSET 0x0020
#define SEC_REG_JR2ICIDR_LS_OFFSET 0x0024
#define SEC_REG_JR3ICIDR_MS_OFFSET 0x0028
#define SEC_REG_JR3ICIDR_LS_OFFSET 0x002C
#define SEC_REG_JRSTARTR_OFFSET 0x005C
#define SEC_REG_CTPR_MS_OFFSET 0x0FA8
/* Offsets representing various RNG registers */
#define RNG_REG_RTMCTL_OFFSET 0x0600
#define RNG_REG_RTSDCTL_OFFSET 0x0610
#define RNG_REG_RTFRQMIN_OFFSET 0x0618
#define RNG_REG_RTFRQMAX_OFFSET 0x061C
#define RNG_REG_RDSTA_OFFSET 0x06C0
#define ALG_AAI_SH_SHIFT 4
/* SEC Registers Bitmasks */
#define MCFGR_PS_SHIFT 16
#define MCFGR_AWCACHE_SHIFT 8
#define MCFGR_AWCACHE_MASK (0xF << MCFGR_AWCACHE_SHIFT)
#define MCFGR_ARCACHE_SHIFT 12
#define MCFGR_ARCACHE_MASK (0xF << MCFGR_ARCACHE_SHIFT)
#define SCFGR_RNGSH0 0x00000200
#define SCFGR_VIRT_EN 0x00008000
#define JRICID_MS_LICID 0x80000000
#define JRICID_MS_LAMTD 0x00020000
#define JRICID_MS_AMTDT 0x00010000
#define JRICID_MS_TZ 0x00008000
#define JRICID_LS_SDID_MASK 0x00000FFF
#define JRICID_LS_NSEQID_MASK 0x0FFF0000
#define JRICID_LS_NSEQID_SHIFT 16
#define JRICID_LS_SEQID_MASK 0x00000FFF
#define JRSTARTR_STARTJR0 0x00000001
#define JRSTARTR_STARTJR1 0x00000002
#define JRSTARTR_STARTJR2 0x00000004
#define JRSTARTR_STARTJR3 0x00000008
#define CTPR_VIRT_EN_POR 0x00000002
#define CTPR_VIRT_EN_INC 0x00000001
/* RNG RDSTA bitmask */
#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
/* use von Neumann data in both entropy shifter and statistical checker */
#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0
/* use raw data in both entropy shifter and statistical checker */
#define RTMCTL_SAMP_MODE_RAW_ES_SC 1
/* use von Neumann data in entropy shifter, raw data in statistical checker */
#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2
/* invalid combination */
#define RTMCTL_SAMP_MODE_INVALID 3
#define RTSDCTL_ENT_DLY_MIN 3200
#define RTSDCTL_ENT_DLY_MAX 12800
#define RTSDCTL_ENT_DLY_SHIFT 16
#define RTSDCTL_ENT_DLY_MASK (U(0xffff) << RTSDCTL_ENT_DLY_SHIFT)
#define RTFRQMAX_DISABLE (1 << 20)
/* Constants for error handling on job ring */
#define JR_REG_JRINT_ERR_TYPE_SHIFT 8
#define JR_REG_JRINT_ERR_ORWI_SHIFT 16
#define JR_REG_JRINIT_JRE_SHIFT 1
#define JRINT_JRE (1 << JR_REG_JRINIT_JRE_SHIFT)
#define JRINT_ERR_WRITE_STATUS (1 << JR_REG_JRINT_ERR_TYPE_SHIFT)
#define JRINT_ERR_BAD_INPUT_BASE (3 << JR_REG_JRINT_ERR_TYPE_SHIFT)
#define JRINT_ERR_BAD_OUTPUT_BASE (4 << JR_REG_JRINT_ERR_TYPE_SHIFT)
#define JRINT_ERR_WRITE_2_IRBA (5 << JR_REG_JRINT_ERR_TYPE_SHIFT)
#define JRINT_ERR_WRITE_2_ORBA (6 << JR_REG_JRINT_ERR_TYPE_SHIFT)
#define JRINT_ERR_RES_B4_HALT (7 << JR_REG_JRINT_ERR_TYPE_SHIFT)
#define JRINT_ERR_REM_TOO_MANY (8 << JR_REG_JRINT_ERR_TYPE_SHIFT)
#define JRINT_ERR_ADD_TOO_MANY (9 << JR_REG_JRINT_ERR_TYPE_SHIFT)
#define JRINT_ERR_HALT_MASK 0x0C
#define JRINT_ERR_HALT_INPROGRESS 0x04
#define JRINT_ERR_HALT_COMPLETE 0x08
#define JR_REG_JRCR_VAL_RESET 0x00000001
#define JR_REG_JRCFG_LO_ICTT_SHIFT 0x10
#define JR_REG_JRCFG_LO_ICDCT_SHIFT 0x08
#define JR_REG_JRCFG_LO_ICEN_EN 0x02
#define JR_REG_JRCFG_LO_IMSK_EN 0x01
/* Constants for Descriptor Processing errors */
#define SEC_HW_ERR_SSRC_NO_SRC 0x00
#define SEC_HW_ERR_SSRC_CCB_ERR 0x02
#define SEC_HW_ERR_SSRC_JMP_HALT_U 0x03
#define SEC_HW_ERR_SSRC_DECO 0x04
#define SEC_HW_ERR_SSRC_JR 0x06
#define SEC_HW_ERR_SSRC_JMP_HALT_COND 0x07
#define SEC_HW_ERR_DECO_HFN_THRESHOLD 0xF1
#define SEC_HW_ERR_CCB_ICV_CHECK_FAIL 0x0A
/* Macros for extracting error codes for the job ring */
#define JR_REG_JRINT_ERR_TYPE_EXTRACT(value) \
((value) & 0x00000F00)
#define JR_REG_JRINT_ERR_ORWI_EXTRACT(value) \
(((value) & 0x3FFF0000) >> \
JR_REG_JRINT_ERR_ORWI_SHIFT)
#define JR_REG_JRINT_JRE_EXTRACT(value) \
((value) & JRINT_JRE)
/* Macros for manipulating JR registers */
typedef struct {
#ifdef NXP_SEC_BE
uint32_t high;
uint32_t low;
#else
uint32_t low;
uint32_t high;
#endif
} ptr_addr_t;
#if defined(CONFIG_PHYS_64BIT)
#define sec_read_addr(a) sec_in64((a))
#define sec_write_addr(a, v) sec_out64((a), (v))
#else
#define sec_read_addr(a) sec_in32((a))
#define sec_write_addr(a, v) sec_out32((a), (v))
#endif
#define JR_REG(name, jr) (CHAN_BASE(jr) + JR_REG_##name##_OFFSET)
#define JR_REG_LO(name, jr) (CHAN_BASE(jr) + JR_REG_##name##_OFFSET_LO)
#define GET_JR_REG(name, jr) (sec_in32(JR_REG(name, (jr))))
#define GET_JR_REG_LO(name, jr) (sec_in32(JR_REG_LO(name, (jr))))
#define SET_JR_REG(name, jr, val) \
(sec_out32(JR_REG(name, (jr)), (val)))
#define SET_JR_REG_LO(name, jr, val) \
(sec_out32(JR_REG_LO(name, (jr)), (val)))
/* STRUCTURES AND OTHER TYPEDEFS */
/* Lists the possible states for a job ring. */
typedef enum sec_job_ring_state_e {
SEC_JOB_RING_STATE_STARTED, /* Job ring is initialized */
SEC_JOB_RING_STATE_RESET, /* Job ring reset is in progres */
} sec_job_ring_state_t;
struct sec_job_ring_t {
/*
* Consumer index for job ring (jobs array).
* @note: cidx and pidx are accessed from
* different threads.
* Place the cidx and pidx inside the structure
* so that they lay on different cachelines, to
* avoid false sharing between threads when the
* threads run on different cores!
*/
uint32_t cidx;
/* Producer index for job ring (jobs array) */
uint32_t pidx;
/* Ring of input descriptors. Size of array is power of 2 to allow
* fast update of producer/consumer indexes with bitwise operations.
*/
phys_addr_t *input_ring;
/* Ring of output descriptors. */
struct sec_outring_entry *output_ring;
/* The file descriptor used for polling for interrupts notifications */
uint32_t irq_fd;
/* Model used by SEC Driver to receive notifications from SEC.
* Can be either of the three:
* #SEC_NOTIFICATION_TYPE_IRQ or
* #SEC_NOTIFICATION_TYPE_POLL
*/
uint32_t jr_mode;
/* Base address for SEC's register memory for this job ring. */
void *register_base_addr;
/* notifies if coelescing is enabled for the job ring */
uint8_t coalescing_en;
/* The state of this job ring */
sec_job_ring_state_t jr_state;
};
/* Forward structure declaration */
typedef struct sec_job_ring_t sec_job_ring_t;
struct sec_outring_entry {
phys_addr_t desc; /* Pointer to completed descriptor */
uint32_t status; /* Status for completed descriptor */
} __packed;
/* Lists the states possible for the SEC user space driver. */
typedef enum sec_driver_state_e {
SEC_DRIVER_STATE_IDLE, /*< Driver not initialized */
SEC_DRIVER_STATE_STARTED, /*< Driver initialized and */
SEC_DRIVER_STATE_RELEASE, /*< Driver release is in progress */
} sec_driver_state_t;
/* Union describing the possible error codes that */
/* can be set in the descriptor status word */
union hw_error_code {
uint32_t error;
union {
struct {
uint32_t ssrc:4;
uint32_t ssed_val:28;
} __packed value;
struct {
uint32_t ssrc:4;
uint32_t res:28;
} __packed no_status_src;
struct {
uint32_t ssrc:4;
uint32_t jmp:1;
uint32_t res:11;
uint32_t desc_idx:8;
uint32_t cha_id:4;
uint32_t err_id:4;
} __packed ccb_status_src;
struct {
uint32_t ssrc:4;
uint32_t jmp:1;
uint32_t res:11;
uint32_t desc_idx:8;
uint32_t offset:8;
} __packed jmp_halt_user_src;
struct {
uint32_t ssrc:4;
uint32_t jmp:1;
uint32_t res:11;
uint32_t desc_idx:8;
uint32_t desc_err:8;
} __packed deco_src;
struct {
uint32_t ssrc:4;
uint32_t res:17;
uint32_t naddr:3;
uint32_t desc_err:8;
} __packed jr_src;
struct {
uint32_t ssrc:4;
uint32_t jmp:1;
uint32_t res:11;
uint32_t desc_idx:8;
uint32_t cond:8;
} __packed jmp_halt_cond_src;
} __packed error_desc;
} __packed;
/* FUNCTION PROTOTYPES */
/*
* @brief Initialize a job ring/channel in SEC device.
* Write configuration register/s to properly initialize a job ring.
*
* @param [in] job_ring The job ring
*
* @retval 0 for success
* @retval other for error
*/
int hw_reset_job_ring(sec_job_ring_t *job_ring);
/*
* @brief Reset a job ring/channel in SEC device.
* Write configuration register/s to reset a job ring.
*
* @param [in] job_ring The job ring
*
* @retval 0 for success
* @retval -1 in case job ring reset failed
*/
int hw_shutdown_job_ring(sec_job_ring_t *job_ring);
/*
* @brief Handle a job ring/channel error in SEC device.
* Identify the error type and clear error bits if required.
*
* @param [in] job_ring The job ring
* @param [in] sec_error_code error code as first read from SEC engine
*/
void hw_handle_job_ring_error(sec_job_ring_t *job_ring,
uint32_t sec_error_code);
/*
* @brief Handle a job ring error in the device.
* Identify the error type and printout a explanatory
* messages.
*
* @param [in] job_ring The job ring
*
*/
int hw_job_ring_error(sec_job_ring_t *job_ring);
/* @brief Set interrupt coalescing parameters on the Job Ring.
* @param [in] job_ring The job ring
* @param [in] irq_coalesing_timer
* Interrupt coalescing timer threshold.
* This value determines the maximum
* amount of time after processing a descriptor
* before raising an interrupt.
* @param [in] irq_coalescing_count
* Interrupt coalescing count threshold.
* This value determines how many descriptors
* are completed before raising an interrupt.
*/
int hw_job_ring_set_coalescing_param(sec_job_ring_t *job_ring,
uint16_t irq_coalescing_timer,
uint8_t irq_coalescing_count);
/* @brief Enable interrupt coalescing on a job ring
* @param [in] job_ring The job ring
*/
int hw_job_ring_enable_coalescing(sec_job_ring_t *job_ring);
/*
* @brief Disable interrupt coalescing on a job ring
* @param [in] job_ring The job ring
*/
int hw_job_ring_disable_coalescing(sec_job_ring_t *job_ring);
/*
* @brief Poll the HW for already processed jobs in the JR
* and notify the available jobs to UA.
*
* @param [in] job_ring The job ring to poll.
* @param [in] limit The maximum number of jobs to notify.
* If set to negative value, all available
* jobs are notified.
*
* @retval >=0 for No of jobs notified to UA.
* @retval -1 for error
*/
int hw_poll_job_ring(struct sec_job_ring_t *job_ring, int32_t limit);
/* @brief Poll the HW for already processed jobs in the JR
* and silently discard the available jobs or notify them to UA
* with indicated error code.
* @param [in,out] job_ring The job ring to poll.
* @param [in] do_notify Can be #TRUE or #FALSE.
* Indicates if descriptors to be discarded
* or notified to UA with given error_code.
* @param [in] error_code The detailed SEC error code.
* @param [out] notified_descs Number of notified descriptors.
* Can be NULL if do_notify is #FALSE
*/
void hw_flush_job_ring(struct sec_job_ring_t *job_ring,
uint32_t do_notify,
uint32_t error_code, uint32_t *notified_descs);
/*
* @brief Flush job rings of any processed descs.
* The processed descs are silently dropped,
* WITHOUT being notified to UA.
*/
void flush_job_rings(void);
/*
* @brief Handle desc that generated error in SEC engine.
* Identify the exact type of error and handle the error.
* Depending on the error type, the job ring could be reset.
* All descs that are submitted for processing on this job ring
* are notified to User Application with error status and detailed error code.
* @param [in] job_ring Job ring
* @param [in] sec_error_code Error code read from job ring's Channel
* Status Register
* @param [out] notified_descs Number of notified descs. Can be NULL if
* do_notify is #FALSE
* @param [out] do_driver_shutdown If set to #TRUE, then UA is returned code
* #SEC_PROCESSING_ERROR
* which is indication that UA must call
* sec_release() after this.
*/
void sec_handle_desc_error(struct sec_job_ring_t *job_ring,
uint32_t sec_error_code,
uint32_t *notified_descs,
uint32_t *do_driver_shutdown);
/*
* @brief Release the software and hardware resources tied to a job ring.
* @param [in] job_ring The job ring
* @retval 0 for success
* @retval -1 for error
*/
int shutdown_job_ring(struct sec_job_ring_t *job_ring);
/*
* @brief Enable irqs on associated job ring.
* @param [in] job_ring The job ring
* @retval 0 for success
* @retval -1 for error
*/
int jr_enable_irqs(struct sec_job_ring_t *job_ring);
/*
* @brief Disable irqs on associated job ring.
* @param [in] job_ring The job ring
* @retval 0 for success
* @retval -1 for error
*/
int jr_disable_irqs(struct sec_job_ring_t *job_ring);
/*
* IRJA - Input Ring Jobs Added Register shows
* how many new jobs were added to the Input Ring.
*/
static inline void hw_enqueue_desc_on_job_ring(struct jobring_regs *regs,
int num)
{
sec_out32(&regs->irja, num);
}
#endif /* _SEC_HW_SPECIFIC_H_ */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/crypto/caam/sec_jr_driver.h
+178
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/*
* Copyright 2017-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef _JR_DRIVER_H_
#define _JR_DRIVER_H_
#include "jr_driver_config.h"
/* The maximum size of a SEC descriptor, in WORDs (32 bits). */
#define MAX_DESC_SIZE_WORDS 64
#define CAAM_TIMEOUT 200000 /* ms */
/* Return codes for JR user space driver APIs */
typedef enum sec_return_code_e {
SEC_SUCCESS = 0,
SEC_INVALID_INPUT_PARAM,
SEC_OUT_OF_MEMORY,
SEC_DESCRIPTOR_IN_FLIGHT,
SEC_LAST_DESCRIPTOR_IN_FLIGHT,
SEC_PROCESSING_ERROR,
SEC_DESC_PROCESSING_ERROR,
SEC_JR_IS_FULL,
SEC_DRIVER_RELEASE_IN_PROGRESS,
SEC_DRIVER_ALREADY_INITIALIZED,
SEC_DRIVER_NOT_INITIALIZED,
SEC_JOB_RING_RESET_IN_PROGRESS,
SEC_RESET_ENGINE_FAILED,
SEC_ENABLE_IRQS_FAILED,
SEC_DISABLE_IRQS_FAILED,
SEC_RETURN_CODE_MAX_VALUE,
} sec_return_code_t;
/* STRUCTURES AND OTHER TYPEDEFS */
/*
* @brief Function called by JR User Space driver to notify every processed
* descriptor.
*
* Callback provided by the User Application.
* Callback is invoked by JR User Space driver for each descriptor processed by
* SEC
* @param [in] status Status word indicating processing result for
* this descriptor.
* @param [in] arg Opaque data passed by User Application
* It is opaque from JR driver's point of view.
* @param [in] job_ring The job ring handle on which the processed
* descriptor word was enqueued
*/
typedef void (*user_callback) (uint32_t *desc, uint32_t status,
void *arg, void *job_ring);
/*
* Structure encompassing a job descriptor which is to be processed
* by SEC. User should also initialise this structure with the callback
* function pointer which will be called by driver after recieving proccessed
* descriptor from SEC. User data is also passed in this data structure which
* will be sent as an argument to the user callback function.
*/
struct job_descriptor {
uint32_t desc[MAX_DESC_SIZE_WORDS];
void *arg;
user_callback callback;
};
/*
* @brief Initialize the JR User Space driver.
* This function will handle initialization of sec library
* along with registering platform specific callbacks,
* as well as local data initialization.
* Call once during application startup.
* @note Global SEC initialization is done in SEC kernel driver.
* @note The hardware IDs of the initialized Job Rings are opaque to the UA.
* The exact Job Rings used by this library are decided between SEC user
* space driver and SEC kernel driver. A static partitioning of Job Rings is
* assumed, configured in DTS(device tree specification) file.
* @param [in] platform_cb Registering the platform specific
* callbacks with driver
* @retval ::0 for successful execution
* @retval ::-1 failure
*/
int sec_jr_lib_init(void);
/*
* @brief Initialize the software and hardware resources tied to a job ring.
* @param [in] jr_mode; Model to be used by SEC Driver to receive
* notifications from SEC. Can be either
* SEC_NOTIFICATION_TYPE_IRQ or
* SEC_NOTIFICATION_TYPE_POLL
* @param [in] irq_coalescing_timer This value determines the maximum
* amount of time after processing a
* descriptor before raising an interrupt.
* @param [in] irq_coalescing_count This value determines how many
* descriptors are completed before
* raising an interrupt.
* @param [in] reg_base_addr The job ring base address register
* @param [in] irq_id The job ring interrupt identification number.
* @retval job_ring_handle for successful job ring configuration
* @retval NULL on error
*/
void *init_job_ring(uint8_t jr_mode,
uint16_t irq_coalescing_timer,
uint8_t irq_coalescing_count,
void *reg_base_addr, uint32_t irq_id);
/*
* @brief Release the resources used by the JR User Space driver.
* Reset and release SEC's job rings indicated by the User Application at
* init_job_ring() and free any memory allocated internally.
* Call once during application tear down.
* @note In case there are any descriptors in-flight (descriptors received by
* JR driver for processing and for which no response was yet provided to UA),
* the descriptors are discarded without any notifications to User Application.
* @retval ::0 is returned for a successful execution
* @retval ::-1 is returned if JR driver release is in progress
*/
int sec_release(void);
/*
* @brief Submit a descriptor for SEC processing.
* This function creates a "job" which is meant to instruct SEC HW
* to perform the processing on the input buffer. The "job" is enqueued
* in the Job Ring associated. The function will return after the "job"
* enqueue is finished. The function will not wait for SEC to
* start or/and finish the "job" processing.
* After the processing is finished the SEC HW writes the processing result
* to the provided output buffer.
* The Caller must poll JR driver using jr_dequeue()
* to receive notifications of the processing completion
* status. The notifications are received by caller by means of callback
* (see ::user_callback).
* @param [in] job_ring_handle The handle of the job ring on which
* descriptor is to be enqueued
* @param [in] job_descriptor The job descriptor structure of type
* struct job_descriptor. This structure
* should be filled with job descriptor along
* with callback function to be called after
* processing of descriptor and some
* opaque data passed to be passed to the
* callback function
*
* @retval ::0 is returned for successful execution
* @retval ::-1 is returned if there is some enqueue failure
*/
int enq_jr_desc(void *job_ring_handle, struct job_descriptor *jobdescr);
/*
* @brief Polls for available descriptors processed by SEC on a specific
* Job Ring
* This function polls the SEC Job Rings and delivers processed descriptors
* Each processed descriptor has a user_callback registered.
* This user_callback is invoked for each processed descriptor.
* The polling is stopped when "limit" descriptors are notified or when
* there are no more descriptors to notify.
* @note The dequeue_jr() API cannot be called from within a user_callback
* function
* @param [in] job_ring_handle The Job Ring handle.
* @param [in] limit This value represents the maximum number
* of processed descriptors that can be
* notified API call on this Job Ring.
* Note that fewer descriptors may be notified
* if enough processed descriptors are not
* available.
* If limit has a negative value, then all
* ready descriptors will be notified.
*
* @retval :: >=0 is returned where retval is the total
* Number of descriptors notified
* during this function call.
* @retval :: -1 is returned in case of some error
*/
int dequeue_jr(void *job_ring_handle, int32_t limit);
#endif /* _JR_DRIVER_H_ */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/csu/csu.h
+42
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@@ -0,0 +1,42 @@
/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef CSU_H
#define CSU_H
#define CSU_SEC_ACCESS_REG_OFFSET (0x0021CU)
/* Bit mask */
#define TZASC_BYPASS_MUX_DISABLE (0x4U)
/* Macros defining access permissions to configure
* the regions controlled by Central Security Unit.
*/
enum csu_cslx_access {
CSU_NS_SUP_R = (0x8U),
CSU_NS_SUP_W = (0x80U),
CSU_NS_SUP_RW = (0x88U),
CSU_NS_USER_R = (0x4U),
CSU_NS_USER_W = (0x40U),
CSU_NS_USER_RW = (0x44U),
CSU_S_SUP_R = (0x2U),
CSU_S_SUP_W = (0x20U),
CSU_S_SUP_RW = (0x22U),
CSU_S_USER_R = (0x1U),
CSU_S_USER_W = (0x10U),
CSU_S_USER_RW = (0x11U),
CSU_ALL_RW = (0xffU),
};
struct csu_ns_dev_st {
uintptr_t ind;
uint32_t val;
};
void enable_layerscape_ns_access(struct csu_ns_dev_st *csu_ns_dev,
uint32_t num, uintptr_t nxp_csu_addr);
#endif
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/dcfg/dcfg.h
+103
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@@ -0,0 +1,103 @@
/*
* Copyright 2018-2022 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef DCFG_H
#define DCFG_H
#include <endian.h>
#if defined(CONFIG_CHASSIS_2)
#include <dcfg_lsch2.h>
#elif defined(CONFIG_CHASSIS_3_2) || defined(CONFIG_CHASSIS_3)
#include <dcfg_lsch3.h>
#endif
#ifdef NXP_GUR_BE
#define gur_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
#define gur_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
#elif defined(NXP_GUR_LE)
#define gur_in32(a) mmio_read_32((uintptr_t)(a))
#define gur_out32(a, v) mmio_write_32((uintptr_t)(a), v)
#else
#error Please define CCSR GUR register endianness
#endif
typedef struct {
union {
uint32_t val;
struct {
uint32_t min_ver:4;
uint32_t maj_ver:4;
#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2)
uint32_t personality:6;
uint32_t rsv1:2;
#elif defined(CONFIG_CHASSIS_2)
uint32_t personality:8;
#endif
#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2)
uint32_t dev_id:6;
uint32_t rsv2:2;
uint32_t family:4;
#elif defined(CONFIG_CHASSIS_2)
uint32_t dev_id:12;
#endif
uint32_t mfr_id;
} __packed bf;
struct {
uint32_t maj_min:8;
uint32_t version; /* SoC version without major and minor info */
} __packed bf_ver;
} __packed svr_reg;
bool sec_enabled;
bool is_populated;
} soc_info_t;
typedef struct {
bool is_populated;
uint8_t ocram_present;
uint8_t ddrc1_present;
#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2)
uint8_t ddrc2_present;
#endif
} devdisr5_info_t;
typedef struct {
uint32_t porsr1;
uintptr_t g_nxp_dcfg_addr;
unsigned long nxp_sysclk_freq;
unsigned long nxp_ddrclk_freq;
unsigned int nxp_plat_clk_divider;
} dcfg_init_info_t;
struct sysinfo {
unsigned long freq_platform;
unsigned long freq_ddr_pll0;
unsigned long freq_ddr_pll1;
};
int get_clocks(struct sysinfo *sys);
/* Read the PORSR1 register */
uint32_t read_reg_porsr1(void);
/*******************************************************************************
* Returns true if secur eboot is enabled on board
* mode = 0 (development mode - sb_en = 1)
* mode = 1 (production mode - ITS = 1)
******************************************************************************/
bool check_boot_mode_secure(uint32_t *mode);
const soc_info_t *get_soc_info();
const devdisr5_info_t *get_devdisr5_info();
void dcfg_init(dcfg_init_info_t *dcfg_init_data);
bool is_sec_enabled(void);
void error_handler(int error_code);
#endif /* DCFG_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/dcfg/dcfg_lsch2.h
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/*
* Copyright 2020-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef DCFG_LSCH2_H
#define DCFG_LSCH2_H
/* dcfg block register offsets and bitfields */
#define DCFG_PORSR1_OFFSET 0x00
#define DCFG_DEVDISR1_OFFSET 0x070
#define DCFG_DEVDISR2_OFFSET 0x074
#define DCFG_DEVDISR3_OFFSET 0x078
#define DCFG_DEVDISR4_OFFSET 0x07C
#define DCFG_DEVDISR5_OFFSET 0x080
#define DCFG_COREDISR_OFFSET 0x094
#define RCWSR0_OFFSET 0x100
#define RCWSR5_OFFSET 0x118
#define DCFG_BOOTLOCPTRL_OFFSET 0x400
#define DCFG_BOOTLOCPTRH_OFFSET 0x404
#define DCFG_COREDISABLEDSR_OFFSET 0x990
#define DCFG_SCRATCH4_OFFSET 0x20C
#define DCFG_SVR_OFFSET 0x0A4
#define DCFG_BRR_OFFSET 0x0E4
#define DCFG_RSTCR_OFFSET 0x0B0
#define RSTCR_RESET_REQ 0x2
#define DCFG_RSTRQSR1_OFFSET 0x0C8
#define DCFG_RSTRQMR1_OFFSET 0x0C0
/* PORSR1 bit mask */
#define PORSR1_RCW_MASK 0xff800000
#define PORSR1_RCW_SHIFT 23
/* DCFG DCSR Macros */
#define DCFG_DCSR_PORCR1_OFFSET 0x0
#define SVR_MFR_ID_MASK 0xF0000000
#define SVR_MFR_ID_SHIFT 28
#define SVR_DEV_ID_MASK 0xFFF0000
#define SVR_DEV_ID_SHIFT 16
#define SVR_PERSONALITY_MASK 0xFF00
#define SVR_PERSONALITY_SHIFT 8
#define SVR_SEC_MASK 0x100
#define SVR_SEC_SHIFT 8
#define SVR_MAJ_VER_MASK 0xF0
#define SVR_MAJ_VER_SHIFT 4
#define SVR_MIN_VER_MASK 0xF
#define SVR_MINOR_VER_0 0x00
#define SVR_MINOR_VER_1 0x01
#define DISR5_DDRC1_MASK 0x1
#define DISR5_OCRAM_MASK 0x40
/* DCFG regsiters bit masks */
#define RCWSR0_SYS_PLL_RAT_SHIFT 25
#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
#define RCWSR0_MEM_PLL_RAT_SHIFT 16
#define RCWSR0_MEM_PLL_RAT_MASK 0x3f
#define RCWSR0_MEM2_PLL_RAT_SHIFT 18
#define RCWSR0_MEM2_PLL_RAT_MASK 0x3f
#define RCWSR_SB_EN_OFFSET RCWSR5_OFFSET
#define RCWSR_SBEN_MASK 0x1
#define RCWSR_SBEN_SHIFT 21
/* RCW SRC NAND */
#define RCW_SRC_NAND_MASK (0x100)
#define RCW_SRC_NAND_VAL (0x100)
#define NAND_RESERVED_MASK (0xFC)
#define NAND_RESERVED_1 (0x0)
#define NAND_RESERVED_2 (0x80)
/* RCW SRC NOR */
#define RCW_SRC_NOR_MASK (0x1F0)
#define NOR_8B_VAL (0x10)
#define NOR_16B_VAL (0x20)
#define SD_VAL (0x40)
#define QSPI_VAL1 (0x44)
#define QSPI_VAL2 (0x45)
#endif /* DCFG_LSCH2_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/dcfg/dcfg_lsch3.h
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/*
* Copyright 2020-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef DCFG_LSCH3_H
#define DCFG_LSCH3_H
/* dcfg block register offsets and bitfields */
#define DCFG_PORSR1_OFFSET 0x00
#define DCFG_DEVDISR1_OFFSET 0x70
#define DCFG_DEVDISR1_SEC (1 << 22)
#define DCFG_DEVDISR2_OFFSET 0x74
#define DCFG_DEVDISR3_OFFSET 0x78
#define DCFG_DEVDISR3_QBMAIN (1 << 12)
#define DCFG_DEVDISR4_OFFSET 0x7C
#define DCFG_DEVDISR4_SPI_QSPI (1 << 4 | 1 << 5)
#define DCFG_DEVDISR5_OFFSET 0x80
#define DISR5_DDRC1_MASK 0x1
#define DISR5_DDRC2_MASK 0x2
#define DISR5_OCRAM_MASK 0x1000
#define DEVDISR5_MASK_ALL_MEM 0x00001003
#define DEVDISR5_MASK_DDR 0x00000003
#define DEVDISR5_MASK_DBG 0x00000400
#define DCFG_DEVDISR6_OFFSET 0x84
//#define DEVDISR6_MASK 0x00000001
#define DCFG_COREDISR_OFFSET 0x94
#define DCFG_SVR_OFFSET 0x0A4
#define SVR_MFR_ID_MASK 0xF0000000
#define SVR_MFR_ID_SHIFT 28
#define SVR_FAMILY_MASK 0xF000000
#define SVR_FAMILY_SHIFT 24
#define SVR_DEV_ID_MASK 0x3F0000
#define SVR_DEV_ID_SHIFT 16
#define SVR_PERSONALITY_MASK 0x3E00
#define SVR_PERSONALITY_SHIFT 9
#define SVR_SEC_MASK 0x100
#define SVR_SEC_SHIFT 8
#define SVR_MAJ_VER_MASK 0xF0
#define SVR_MAJ_VER_SHIFT 4
#define SVR_MIN_VER_MASK 0xF
#define RCWSR0_OFFSET 0x100
#define RCWSR0_SYS_PLL_RAT_SHIFT 2
#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
#define RCWSR0_MEM_PLL_RAT_SHIFT 10
#define RCWSR0_MEM_PLL_RAT_MASK 0x3f
#define RCWSR0_MEM2_PLL_RAT_SHIFT 18
#define RCWSR0_MEM2_PLL_RAT_MASK 0x3f
#define RCWSR5_OFFSET 0x110
#define RCWSR9_OFFSET 0x120
#define RCWSR_SB_EN_OFFSET RCWSR9_OFFSET
#define RCWSR_SBEN_MASK 0x1
#define RCWSR_SBEN_SHIFT 10
#define RCW_SR27_OFFSET 0x168
/* DCFG register to dump error code */
#define DCFG_SCRATCH4_OFFSET 0x20C
#define DCFG_SCRATCHRW5_OFFSET 0x210
#define DCFG_SCRATCHRW6_OFFSET 0x214
#define DCFG_SCRATCHRW7_OFFSET 0x218
#define DCFG_BOOTLOCPTRL_OFFSET 0x400
#define DCFG_BOOTLOCPTRH_OFFSET 0x404
#define DCFG_COREDISABLEDSR_OFFSET 0x990
/* Reset module bit field */
#define RSTCR_RESET_REQ 0x2
#endif /* DCFG_LSCH3_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/dcfg/scfg.h
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/*
* Copyright 2020-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef SCFG_H
#define SCFG_H
#ifdef CONFIG_CHASSIS_2
/* SCFG register offsets */
#define SCFG_CORE0_SFT_RST_OFFSET 0x0130
#define SCFG_SNPCNFGCR_OFFSET 0x01A4
#define SCFG_CORESRENCR_OFFSET 0x0204
#define SCFG_RVBAR0_0_OFFSET 0x0220
#define SCFG_RVBAR0_1_OFFSET 0x0224
#define SCFG_COREBCR_OFFSET 0x0680
#define SCFG_RETREQCR_OFFSET 0x0424
#define SCFG_COREPMCR_OFFSET 0x042C
#define COREPMCR_WFIL2 0x1
#define SCFG_GIC400_ADDR_ALIGN_OFFSET 0x0188
#define SCFG_BOOTLOCPTRH_OFFSET 0x0600
#define SCFG_BOOTLOCPTRL_OFFSET 0x0604
#define SCFG_SCRATCHRW2_OFFSET 0x0608
#define SCFG_SCRATCHRW3_OFFSET 0x060C
/* SCFG bit fields */
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
/* GIC Address Align Register */
#define SCFG_GIC400_ADDR_ALIGN_4KMODE_MASK 0x80000000
#define SCFG_GIC400_ADDR_ALIGN_4KMODE_EN 0x80000000
#define SCFG_GIC400_ADDR_ALIGN_4KMODE_DIS 0x0
#endif /* CONFIG_CHASSIS_2 */
#ifndef __ASSEMBLER__
#include <endian.h>
#include <lib/mmio.h>
#ifdef NXP_SCFG_BE
#define scfg_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
#define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
#define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v)
#define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v)
#define scfg_clrsetbits32(a, clear, set) \
mmio_clrsetbits_32((uintptr_t)(a), clear, set)
#elif defined(NXP_SCFG_LE)
#define scfg_in32(a) mmio_read_32((uintptr_t)(a))
#define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), v)
#define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v)
#define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v)
#define scfg_clrsetbits32(a, clear, set) \
mmio_clrsetbits_32((uintptr_t)(a), clear, set)
#else
#error Please define CCSR SCFG register endianness
#endif
#endif /* __ASSEMBLER__ */
#endif /* SCFG_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/ddr/ddr.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef DDR_H
#define DDR_H
#include "ddr_io.h"
#include "dimm.h"
#include "immap.h"
#ifndef DDRC_NUM_CS
#define DDRC_NUM_CS 4
#endif
/*
* This is irrespective of what is the number of DDR controller,
* number of DIMM used. This is set to maximum
* Max controllers = 2
* Max num of DIMM per controlle = 2
* MAX NUM CS = 4
* Not to be changed.
*/
#define MAX_DDRC_NUM 2
#define MAX_DIMM_NUM 2
#define MAX_CS_NUM 4
#include "opts.h"
#include "regs.h"
#include "utility.h"
#ifdef DDR_DEBUG
#define debug(...) INFO(__VA_ARGS__)
#else
#define debug(...) VERBOSE(__VA_ARGS__)
#endif
#ifndef DDRC_NUM_DIMM
#define DDRC_NUM_DIMM 1
#endif
#define CONFIG_CS_PER_SLOT \
(DDRC_NUM_CS / DDRC_NUM_DIMM)
/* Record of register values computed */
struct ddr_cfg_regs {
struct {
unsigned int bnds;
unsigned int config;
unsigned int config_2;
} cs[MAX_CS_NUM];
unsigned int dec[10];
unsigned int timing_cfg[10];
unsigned int sdram_cfg[3];
unsigned int sdram_mode[16];
unsigned int md_cntl;
unsigned int interval;
unsigned int data_init;
unsigned int clk_cntl;
unsigned int init_addr;
unsigned int init_ext_addr;
unsigned int zq_cntl;
unsigned int wrlvl_cntl[3];
unsigned int ddr_sr_cntr;
unsigned int sdram_rcw[6];
unsigned int dq_map[4];
unsigned int eor;
unsigned int cdr[2];
unsigned int err_disable;
unsigned int err_int_en;
unsigned int tx_cfg[4];
unsigned int debug[64];
};
struct ddr_conf {
int dimm_in_use[MAX_DIMM_NUM];
int cs_in_use; /* bitmask, bit 0 for cs0, bit 1 for cs1, etc. */
int cs_on_dimm[MAX_DIMM_NUM]; /* bitmask */
unsigned long long cs_base_addr[MAX_CS_NUM];
unsigned long long cs_size[MAX_CS_NUM];
unsigned long long base_addr;
unsigned long long total_mem;
};
struct ddr_info {
unsigned long clk;
unsigned long long mem_base;
unsigned int num_ctlrs;
unsigned int dimm_on_ctlr;
struct dimm_params dimm;
struct memctl_opt opt;
struct ddr_conf conf;
struct ddr_cfg_regs ddr_reg;
struct ccsr_ddr *ddr[MAX_DDRC_NUM];
uint16_t *phy[MAX_DDRC_NUM];
int *spd_addr;
unsigned int ip_rev;
uintptr_t phy_gen2_fw_img_buf;
void *img_loadr;
int warm_boot_flag;
};
struct rc_timing {
unsigned int speed_bin;
unsigned int clk_adj;
unsigned int wrlvl;
};
struct board_timing {
unsigned int rc;
struct rc_timing const *p;
unsigned int add1;
unsigned int add2;
};
enum warm_boot {
DDR_COLD_BOOT = 0,
DDR_WARM_BOOT = 1,
DDR_WRM_BOOT_NT_SUPPORTED = -1,
};
int disable_unused_ddrc(struct ddr_info *priv, int mask,
uintptr_t nxp_ccn_hn_f0_addr);
int ddr_board_options(struct ddr_info *priv);
int compute_ddrc(const unsigned long clk,
const struct memctl_opt *popts,
const struct ddr_conf *conf,
struct ddr_cfg_regs *ddr,
const struct dimm_params *dimm_params,
const unsigned int ip_rev);
int compute_ddr_phy(struct ddr_info *priv);
int ddrc_set_regs(const unsigned long clk,
const struct ddr_cfg_regs *regs,
const struct ccsr_ddr *ddr,
int twopass);
int cal_board_params(struct ddr_info *priv,
const struct board_timing *dimm,
int len);
/* return bit mask of used DIMM(s) */
int ddr_get_ddr_params(struct dimm_params *pdimm, struct ddr_conf *conf);
long long dram_init(struct ddr_info *priv
#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
, uintptr_t nxp_ccn_hn_f0_addr
#endif
);
long long board_static_ddr(struct ddr_info *info);
#endif /* DDR_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/ddr/ddr_io.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef DDR_IO_H
#define DDR_IO_H
#include <endian.h>
#include <lib/mmio.h>
#define min(a, b) (((a) > (b)) ? (b) : (a))
#define max(a, b) (((a) > (b)) ? (a) : (b))
/* macro for memory barrier */
#define mb() asm volatile("dsb sy" : : : "memory")
#ifdef NXP_DDR_BE
#define ddr_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
#define ddr_out32(a, v) mmio_write_32((uintptr_t)(a),\
bswap32(v))
#elif defined(NXP_DDR_LE)
#define ddr_in32(a) mmio_read_32((uintptr_t)(a))
#define ddr_out32(a, v) mmio_write_32((uintptr_t)(a), v)
#else
#error Please define CCSR DDR register endianness
#endif
#define ddr_setbits32(a, v) ddr_out32((a), ddr_in32(a) | (v))
#define ddr_clrbits32(a, v) ddr_out32((a), ddr_in32(a) & ~(v))
#define ddr_clrsetbits32(a, c, s) ddr_out32((a), (ddr_in32(a) & ~(c)) \
| (s))
#endif /* DDR_IO_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/ddr/dimm.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef DIMM_H
#define DIMM_H
#define SPD_MEMTYPE_DDR4 0x0C
#define DDR4_SPD_MODULETYPE_MASK 0x0f
#define DDR4_SPD_MODULETYPE_EXT 0x00
#define DDR4_SPD_RDIMM 0x01
#define DDR4_SPD_UDIMM 0x02
#define DDR4_SPD_SO_DIMM 0x03
#define DDR4_SPD_LRDIMM 0x04
#define DDR4_SPD_MINI_RDIMM 0x05
#define DDR4_SPD_MINI_UDIMM 0x06
#define DDR4_SPD_72B_SO_RDIMM 0x08
#define DDR4_SPD_72B_SO_UDIMM 0x09
#define DDR4_SPD_16B_SO_DIMM 0x0c
#define DDR4_SPD_32B_SO_DIMM 0x0d
#define SPD_SPA0_ADDRESS 0x36
#define SPD_SPA1_ADDRESS 0x37
#define spd_to_ps(mtb, ftb) \
((mtb) * pdimm->mtb_ps + ((ftb) * pdimm->ftb_10th_ps) / 10)
#ifdef DDR_DEBUG
#define dump_spd(spd, len) { \
register int i; \
register unsigned char *buf = (void *)(spd); \
\
for (i = 0; i < (len); i++) { \
print_uint(i); \
puts("\t: 0x"); \
print_hex(buf[i]); \
puts("\n"); \
} \
}
#else
#define dump_spd(spd, len) {}
#endif
/* From JEEC Standard No. 21-C release 23A */
struct ddr4_spd {
/* General Section: Bytes 0-127 */
unsigned char info_size_crc; /* 0 # bytes */
unsigned char spd_rev; /* 1 Total # bytes of SPD */
unsigned char mem_type; /* 2 Key Byte / mem type */
unsigned char module_type; /* 3 Key Byte / Module Type */
unsigned char density_banks; /* 4 Density and Banks */
unsigned char addressing; /* 5 Addressing */
unsigned char package_type; /* 6 Package type */
unsigned char opt_feature; /* 7 Optional features */
unsigned char thermal_ref; /* 8 Thermal and refresh */
unsigned char oth_opt_features; /* 9 Other optional features */
unsigned char res_10; /* 10 Reserved */
unsigned char module_vdd; /* 11 Module nominal voltage */
unsigned char organization; /* 12 Module Organization */
unsigned char bus_width; /* 13 Module Memory Bus Width */
unsigned char therm_sensor; /* 14 Module Thermal Sensor */
unsigned char ext_type; /* 15 Extended module type */
unsigned char res_16;
unsigned char timebases; /* 17 MTb and FTB */
unsigned char tck_min; /* 18 tCKAVGmin */
unsigned char tck_max; /* 19 TCKAVGmax */
unsigned char caslat_b1; /* 20 CAS latencies, 1st byte */
unsigned char caslat_b2; /* 21 CAS latencies, 2nd byte */
unsigned char caslat_b3; /* 22 CAS latencies, 3rd byte */
unsigned char caslat_b4; /* 23 CAS latencies, 4th byte */
unsigned char taa_min; /* 24 Min CAS Latency Time */
unsigned char trcd_min; /* 25 Min RAS# to CAS# Delay Time */
unsigned char trp_min; /* 26 Min Row Precharge Delay Time */
unsigned char tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */
unsigned char tras_min_lsb; /* 28 tRASmin, lsb */
unsigned char trc_min_lsb; /* 29 tRCmin, lsb */
unsigned char trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */
unsigned char trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */
unsigned char trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */
unsigned char trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */
unsigned char trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */
unsigned char trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */
unsigned char tfaw_msb; /* 36 Upper Nibble for tFAW */
unsigned char tfaw_min; /* 37 tFAW, lsb */
unsigned char trrds_min; /* 38 tRRD_Smin, MTB */
unsigned char trrdl_min; /* 39 tRRD_Lmin, MTB */
unsigned char tccdl_min; /* 40 tCCS_Lmin, MTB */
unsigned char res_41[60-41]; /* 41 Rserved */
unsigned char mapping[78-60]; /* 60~77 Connector to SDRAM bit map */
unsigned char res_78[117-78]; /* 78~116, Reserved */
signed char fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */
signed char fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */
signed char fine_trrds_min; /* 119 Fine offset for tRRD_Smin */
signed char fine_trc_min; /* 120 Fine offset for tRCmin */
signed char fine_trp_min; /* 121 Fine offset for tRPmin */
signed char fine_trcd_min; /* 122 Fine offset for tRCDmin */
signed char fine_taa_min; /* 123 Fine offset for tAAmin */
signed char fine_tck_max; /* 124 Fine offset for tCKAVGmax */
signed char fine_tck_min; /* 125 Fine offset for tCKAVGmin */
/* CRC: Bytes 126-127 */
unsigned char crc[2]; /* 126-127 SPD CRC */
/* Module-Specific Section: Bytes 128-255 */
union {
struct {
/* 128 (Unbuffered) Module Nominal Height */
unsigned char mod_height;
/* 129 (Unbuffered) Module Maximum Thickness */
unsigned char mod_thickness;
/* 130 (Unbuffered) Reference Raw Card Used */
unsigned char ref_raw_card;
/* 131 (Unbuffered) Address Mapping from
* Edge Connector to DRAM
*/
unsigned char addr_mapping;
/* 132~253 (Unbuffered) Reserved */
unsigned char res_132[254-132];
/* 254~255 CRC */
unsigned char crc[2];
} unbuffered;
struct {
/* 128 (Registered) Module Nominal Height */
unsigned char mod_height;
/* 129 (Registered) Module Maximum Thickness */
unsigned char mod_thickness;
/* 130 (Registered) Reference Raw Card Used */
unsigned char ref_raw_card;
/* 131 DIMM Module Attributes */
unsigned char modu_attr;
/* 132 RDIMM Thermal Heat Spreader Solution */
unsigned char thermal;
/* 133 Register Manufacturer ID Code, LSB */
unsigned char reg_id_lo;
/* 134 Register Manufacturer ID Code, MSB */
unsigned char reg_id_hi;
/* 135 Register Revision Number */
unsigned char reg_rev;
/* 136 Address mapping from register to DRAM */
unsigned char reg_map;
unsigned char ca_stren;
unsigned char clk_stren;
/* 139~253 Reserved */
unsigned char res_139[254-139];
/* 254~255 CRC */
unsigned char crc[2];
} registered;
struct {
/* 128 (Loadreduced) Module Nominal Height */
unsigned char mod_height;
/* 129 (Loadreduced) Module Maximum Thickness */
unsigned char mod_thickness;
/* 130 (Loadreduced) Reference Raw Card Used */
unsigned char ref_raw_card;
/* 131 DIMM Module Attributes */
unsigned char modu_attr;
/* 132 RDIMM Thermal Heat Spreader Solution */
unsigned char thermal;
/* 133 Register Manufacturer ID Code, LSB */
unsigned char reg_id_lo;
/* 134 Register Manufacturer ID Code, MSB */
unsigned char reg_id_hi;
/* 135 Register Revision Number */
unsigned char reg_rev;
/* 136 Address mapping from register to DRAM */
unsigned char reg_map;
/* 137 Register Output Drive Strength for CMD/Add*/
unsigned char reg_drv;
/* 138 Register Output Drive Strength for CK */
unsigned char reg_drv_ck;
/* 139 Data Buffer Revision Number */
unsigned char data_buf_rev;
/* 140 DRAM VrefDQ for Package Rank 0 */
unsigned char vrefqe_r0;
/* 141 DRAM VrefDQ for Package Rank 1 */
unsigned char vrefqe_r1;
/* 142 DRAM VrefDQ for Package Rank 2 */
unsigned char vrefqe_r2;
/* 143 DRAM VrefDQ for Package Rank 3 */
unsigned char vrefqe_r3;
/* 144 Data Buffer VrefDQ for DRAM Interface */
unsigned char data_intf;
/*
* 145 Data Buffer MDQ Drive Strength and RTT
* for data rate <= 1866
*/
unsigned char data_drv_1866;
/*
* 146 Data Buffer MDQ Drive Strength and RTT
* for 1866 < data rate <= 2400
*/
unsigned char data_drv_2400;
/*
* 147 Data Buffer MDQ Drive Strength and RTT
* for 2400 < data rate <= 3200
*/
unsigned char data_drv_3200;
/* 148 DRAM Drive Strength */
unsigned char dram_drv;
/*
* 149 DRAM ODT (RTT_WR, RTT_NOM)
* for data rate <= 1866
*/
unsigned char dram_odt_1866;
/*
* 150 DRAM ODT (RTT_WR, RTT_NOM)
* for 1866 < data rate <= 2400
*/
unsigned char dram_odt_2400;
/*
* 151 DRAM ODT (RTT_WR, RTT_NOM)
* for 2400 < data rate <= 3200
*/
unsigned char dram_odt_3200;
/*
* 152 DRAM ODT (RTT_PARK)
* for data rate <= 1866
*/
unsigned char dram_odt_park_1866;
/*
* 153 DRAM ODT (RTT_PARK)
* for 1866 < data rate <= 2400
*/
unsigned char dram_odt_park_2400;
/*
* 154 DRAM ODT (RTT_PARK)
* for 2400 < data rate <= 3200
*/
unsigned char dram_odt_park_3200;
unsigned char res_155[254-155]; /* Reserved */
/* 254~255 CRC */
unsigned char crc[2];
} loadreduced;
unsigned char uc[128]; /* 128-255 Module-Specific Section */
} mod_section;
unsigned char res_256[320-256]; /* 256~319 Reserved */
/* Module supplier's data: Byte 320~383 */
unsigned char mmid_lsb; /* 320 Module MfgID Code LSB */
unsigned char mmid_msb; /* 321 Module MfgID Code MSB */
unsigned char mloc; /* 322 Mfg Location */
unsigned char mdate[2]; /* 323~324 Mfg Date */
unsigned char sernum[4]; /* 325~328 Module Serial Number */
unsigned char mpart[20]; /* 329~348 Mfg's Module Part Number */
unsigned char mrev; /* 349 Module Revision Code */
unsigned char dmid_lsb; /* 350 DRAM MfgID Code LSB */
unsigned char dmid_msb; /* 351 DRAM MfgID Code MSB */
unsigned char stepping; /* 352 DRAM stepping */
unsigned char msd[29]; /* 353~381 Mfg's Specific Data */
unsigned char res_382[2]; /* 382~383 Reserved */
};
/* Parameters for a DDR dimm computed from the SPD */
struct dimm_params {
/* DIMM organization parameters */
char mpart[19]; /* guaranteed null terminated */
unsigned int n_ranks;
unsigned int die_density;
unsigned long long rank_density;
unsigned long long capacity;
unsigned int primary_sdram_width;
unsigned int ec_sdram_width;
unsigned int rdimm;
unsigned int package_3ds; /* number of dies in 3DS */
unsigned int device_width; /* x4, x8, x16 components */
unsigned int rc;
/* SDRAM device parameters */
unsigned int n_row_addr;
unsigned int n_col_addr;
unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
unsigned int bank_addr_bits;
unsigned int bank_group_bits;
unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
/* mirrored DIMMs */
unsigned int mirrored_dimm; /* only for ddr3 */
/* DIMM timing parameters */
int mtb_ps; /* medium timebase ps */
int ftb_10th_ps; /* fine timebase, in 1/10 ps */
int taa_ps; /* minimum CAS latency time */
int tfaw_ps; /* four active window delay */
/*
* SDRAM clock periods
* The range for these are 1000-10000 so a short should be sufficient
*/
int tckmin_x_ps;
int tckmax_ps;
/* SPD-defined CAS latencies */
unsigned int caslat_x;
/* basic timing parameters */
int trcd_ps;
int trp_ps;
int tras_ps;
int trfc1_ps;
int trfc2_ps;
int trfc4_ps;
int trrds_ps;
int trrdl_ps;
int tccdl_ps;
int trfc_slr_ps;
int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
int twr_ps; /* 15ns for all speed bins */
unsigned int refresh_rate_ps;
unsigned int extended_op_srt;
/* RDIMM */
unsigned char rcw[16]; /* Register Control Word 0-15 */
unsigned int dq_mapping[18];
unsigned int dq_mapping_ors;
};
int read_spd(unsigned char chip, void *buf, int len);
int crc16(unsigned char *ptr, int count);
int cal_dimm_params(const struct ddr4_spd *spd, struct dimm_params *pdimm);
#endif /* DIMM_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/ddr/fsl-mmdc/fsl_mmdc.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef FSL_MMDC_H
#define FSL_MMDC_H
/* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */
#define MPWLGCR_HW_WL_EN (1 << 0)
/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
#define MPPDCMPR2_MPR_COMPARE_EN (1 << 0)
/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
#define AUTO_RD_DQS_GATING_CALIBRATION_EN (1 << 28)
/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
#define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN (1 << 4)
/* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */
#define MMDC_MAPSR_PWR_SAV_CTRL_STAT 0x00001067
/* MMDC Core Refresh Control Register (MMDC_MDREF) */
#define MDREF_START_REFRESH (1 << 0)
/* MMDC Core Special Command Register (MDSCR) */
#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
#define MDSCR_DISABLE_CFG_REQ (0 << 15)
#define MDSCR_ENABLE_CON_REQ (1 << 15)
#define MDSCR_CON_ACK (1 << 14)
#define MDSCR_WL_EN (1 << 9)
#define CMD_NORMAL (0 << 4)
#define CMD_PRECHARGE (1 << 4)
#define CMD_AUTO_REFRESH (2 << 4)
#define CMD_LOAD_MODE_REG (3 << 4)
#define CMD_ZQ_CALIBRATION (4 << 4)
#define CMD_PRECHARGE_BANK_OPEN (5 << 4)
#define CMD_MRR (6 << 4)
#define CMD_BANK_ADDR_0 0x0
#define CMD_BANK_ADDR_1 0x1
#define CMD_BANK_ADDR_2 0x2
#define CMD_BANK_ADDR_3 0x3
#define CMD_BANK_ADDR_4 0x4
#define CMD_BANK_ADDR_5 0x5
#define CMD_BANK_ADDR_6 0x6
#define CMD_BANK_ADDR_7 0x7
/* MMDC Core Control Register (MDCTL) */
#define MDCTL_SDE0 (U(1) << 31)
#define MDCTL_SDE1 (1 << 30)
/* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */
#define MPZQHWCTRL_ZQ_HW_FORCE (1 << 16)
/* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */
#define MMDC_MPMUR0_FRC_MSR (1 << 11)
/* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */
/* default 64 for a quarter cycle delay */
#define MMDC_MPRDDLCTL_DEFAULT_DELAY 0x40404040
/* MMDC Registers */
struct mmdc_regs {
unsigned int mdctl;
unsigned int mdpdc;
unsigned int mdotc;
unsigned int mdcfg0;
unsigned int mdcfg1;
unsigned int mdcfg2;
unsigned int mdmisc;
unsigned int mdscr;
unsigned int mdref;
unsigned int res1[2];
unsigned int mdrwd;
unsigned int mdor;
unsigned int mdmrr;
unsigned int mdcfg3lp;
unsigned int mdmr4;
unsigned int mdasp;
unsigned int res2[239];
unsigned int maarcr;
unsigned int mapsr;
unsigned int maexidr0;
unsigned int maexidr1;
unsigned int madpcr0;
unsigned int madpcr1;
unsigned int madpsr0;
unsigned int madpsr1;
unsigned int madpsr2;
unsigned int madpsr3;
unsigned int madpsr4;
unsigned int madpsr5;
unsigned int masbs0;
unsigned int masbs1;
unsigned int res3[2];
unsigned int magenp;
unsigned int res4[239];
unsigned int mpzqhwctrl;
unsigned int mpzqswctrl;
unsigned int mpwlgcr;
unsigned int mpwldectrl0;
unsigned int mpwldectrl1;
unsigned int mpwldlst;
unsigned int mpodtctrl;
unsigned int mprddqby0dl;
unsigned int mprddqby1dl;
unsigned int mprddqby2dl;
unsigned int mprddqby3dl;
unsigned int mpwrdqby0dl;
unsigned int mpwrdqby1dl;
unsigned int mpwrdqby2dl;
unsigned int mpwrdqby3dl;
unsigned int mpdgctrl0;
unsigned int mpdgctrl1;
unsigned int mpdgdlst0;
unsigned int mprddlctl;
unsigned int mprddlst;
unsigned int mpwrdlctl;
unsigned int mpwrdlst;
unsigned int mpsdctrl;
unsigned int mpzqlp2ctl;
unsigned int mprddlhwctl;
unsigned int mpwrdlhwctl;
unsigned int mprddlhwst0;
unsigned int mprddlhwst1;
unsigned int mpwrdlhwst0;
unsigned int mpwrdlhwst1;
unsigned int mpwlhwerr;
unsigned int mpdghwst0;
unsigned int mpdghwst1;
unsigned int mpdghwst2;
unsigned int mpdghwst3;
unsigned int mppdcmpr1;
unsigned int mppdcmpr2;
unsigned int mpswdar0;
unsigned int mpswdrdr0;
unsigned int mpswdrdr1;
unsigned int mpswdrdr2;
unsigned int mpswdrdr3;
unsigned int mpswdrdr4;
unsigned int mpswdrdr5;
unsigned int mpswdrdr6;
unsigned int mpswdrdr7;
unsigned int mpmur0;
unsigned int mpwrcadl;
unsigned int mpdccr;
};
struct fsl_mmdc_info {
unsigned int mdctl;
unsigned int mdpdc;
unsigned int mdotc;
unsigned int mdcfg0;
unsigned int mdcfg1;
unsigned int mdcfg2;
unsigned int mdmisc;
unsigned int mdref;
unsigned int mdrwd;
unsigned int mdor;
unsigned int mdasp;
unsigned int mpodtctrl;
unsigned int mpzqhwctrl;
unsigned int mprddlctl;
};
void mmdc_init(const struct fsl_mmdc_info *priv, uintptr_t nxp_ddr_addr);
#endif /* FSL_MMDC_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/ddr/immap.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef DDR_IMMAP_H
#define DDR_IMMAP_H
#define DDR_DBUS_64 0
#define DDR_DBUS_32 1
#define DDR_DBUS_16 2
/*
* DDRC register file for DDRC 5.0 and above
*/
struct ccsr_ddr {
struct {
unsigned int a; /* 0x0, 0x8, 0x10, 0x18 */
unsigned int res; /* 0x4, 0xc, 0x14, 0x1c */
} bnds[4];
unsigned char res_20[0x40 - 0x20];
unsigned int dec[10]; /* 0x40 */
unsigned char res_68[0x80 - 0x68];
unsigned int csn_cfg[4]; /* 0x80, 0x84, 0x88, 0x8c */
unsigned char res_90[48];
unsigned int csn_cfg_2[4]; /* 0xc0, 0xc4, 0xc8, 0xcc */
unsigned char res_d0[48];
unsigned int timing_cfg_3; /* SDRAM Timing Configuration 3 */
unsigned int timing_cfg_0; /* SDRAM Timing Configuration 0 */
unsigned int timing_cfg_1; /* SDRAM Timing Configuration 1 */
unsigned int timing_cfg_2; /* SDRAM Timing Configuration 2 */
unsigned int sdram_cfg; /* SDRAM Control Configuration */
unsigned int sdram_cfg_2; /* SDRAM Control Configuration 2 */
unsigned int sdram_mode; /* SDRAM Mode Configuration */
unsigned int sdram_mode_2; /* SDRAM Mode Configuration 2 */
unsigned int sdram_md_cntl; /* SDRAM Mode Control */
unsigned int sdram_interval; /* SDRAM Interval Configuration */
unsigned int sdram_data_init; /* SDRAM Data initialization */
unsigned char res_12c[4];
unsigned int sdram_clk_cntl; /* SDRAM Clock Control */
unsigned char res_134[20];
unsigned int init_addr; /* training init addr */
unsigned int init_ext_addr; /* training init extended addr */
unsigned char res_150[16];
unsigned int timing_cfg_4; /* SDRAM Timing Configuration 4 */
unsigned int timing_cfg_5; /* SDRAM Timing Configuration 5 */
unsigned int timing_cfg_6; /* SDRAM Timing Configuration 6 */
unsigned int timing_cfg_7; /* SDRAM Timing Configuration 7 */
unsigned int zq_cntl; /* ZQ calibration control*/
unsigned int wrlvl_cntl; /* write leveling control*/
unsigned char reg_178[4];
unsigned int ddr_sr_cntr; /* self refresh counter */
unsigned int ddr_sdram_rcw_1; /* Control Words 1 */
unsigned int ddr_sdram_rcw_2; /* Control Words 2 */
unsigned char reg_188[8];
unsigned int ddr_wrlvl_cntl_2; /* write leveling control 2 */
unsigned int ddr_wrlvl_cntl_3; /* write leveling control 3 */
unsigned char res_198[0x1a0-0x198];
unsigned int ddr_sdram_rcw_3;
unsigned int ddr_sdram_rcw_4;
unsigned int ddr_sdram_rcw_5;
unsigned int ddr_sdram_rcw_6;
unsigned char res_1b0[0x200-0x1b0];
unsigned int sdram_mode_3; /* SDRAM Mode Configuration 3 */
unsigned int sdram_mode_4; /* SDRAM Mode Configuration 4 */
unsigned int sdram_mode_5; /* SDRAM Mode Configuration 5 */
unsigned int sdram_mode_6; /* SDRAM Mode Configuration 6 */
unsigned int sdram_mode_7; /* SDRAM Mode Configuration 7 */
unsigned int sdram_mode_8; /* SDRAM Mode Configuration 8 */
unsigned char res_218[0x220-0x218];
unsigned int sdram_mode_9; /* SDRAM Mode Configuration 9 */
unsigned int sdram_mode_10; /* SDRAM Mode Configuration 10 */
unsigned int sdram_mode_11; /* SDRAM Mode Configuration 11 */
unsigned int sdram_mode_12; /* SDRAM Mode Configuration 12 */
unsigned int sdram_mode_13; /* SDRAM Mode Configuration 13 */
unsigned int sdram_mode_14; /* SDRAM Mode Configuration 14 */
unsigned int sdram_mode_15; /* SDRAM Mode Configuration 15 */
unsigned int sdram_mode_16; /* SDRAM Mode Configuration 16 */
unsigned char res_240[0x250-0x240];
unsigned int timing_cfg_8; /* SDRAM Timing Configuration 8 */
unsigned int timing_cfg_9; /* SDRAM Timing Configuration 9 */
unsigned int timing_cfg_10; /* SDRAM Timing COnfigurtion 10 */
unsigned char res_258[0x260-0x25c];
unsigned int sdram_cfg_3;
unsigned char res_264[0x270-0x264];
unsigned int sdram_md_cntl_2;
unsigned char res_274[0x400-0x274];
unsigned int dq_map[4];
unsigned char res_410[0x800-0x410];
unsigned int tx_cfg[4];
unsigned char res_810[0xb20-0x810];
unsigned int ddr_dsr1; /* Debug Status 1 */
unsigned int ddr_dsr2; /* Debug Status 2 */
unsigned int ddr_cdr1; /* Control Driver 1 */
unsigned int ddr_cdr2; /* Control Driver 2 */
unsigned char res_b30[200];
unsigned int ip_rev1; /* IP Block Revision 1 */
unsigned int ip_rev2; /* IP Block Revision 2 */
unsigned int eor; /* Enhanced Optimization Register */
unsigned char res_c04[252];
unsigned int mtcr; /* Memory Test Control Register */
unsigned char res_d04[28];
unsigned int mtp[10]; /* Memory Test Patterns */
unsigned char res_d48[184];
unsigned int data_err_inject_hi; /* Data Path Err Injection Mask Hi*/
unsigned int data_err_inject_lo;/* Data Path Err Injection Mask Lo*/
unsigned int ecc_err_inject; /* Data Path Err Injection Mask ECC */
unsigned char res_e0c[20];
unsigned int capture_data_hi; /* Data Path Read Capture High */
unsigned int capture_data_lo; /* Data Path Read Capture Low */
unsigned int capture_ecc; /* Data Path Read Capture ECC */
unsigned char res_e2c[20];
unsigned int err_detect; /* Error Detect */
unsigned int err_disable; /* Error Disable */
unsigned int err_int_en;
unsigned int capture_attributes; /* Error Attrs Capture */
unsigned int capture_address; /* Error Addr Capture */
unsigned int capture_ext_address; /* Error Extended Addr Capture */
unsigned int err_sbe; /* Single-Bit ECC Error Management */
unsigned char res_e5c[164];
unsigned int debug[64]; /* debug_1 to debug_64 */
};
#endif /* DDR_IMMAP_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/ddr/opts.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef DDR_OPTS_H
#define DDR_OPTS_H
#define SDRAM_TYPE_DDR4 5 /* sdram_cfg register */
#define DDR_BC4 4 /* burst chop */
#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
#define DDR_BL8 8 /* burst length 8 */
#define DDR4_RTT_OFF 0
#define DDR4_RTT_60_OHM 1 /* RZQ/4 */
#define DDR4_RTT_120_OHM 2 /* RZQ/2 */
#define DDR4_RTT_40_OHM 3 /* RZQ/6 */
#define DDR4_RTT_240_OHM 4 /* RZQ/1 */
#define DDR4_RTT_48_OHM 5 /* RZQ/5 */
#define DDR4_RTT_80_OHM 6 /* RZQ/3 */
#define DDR4_RTT_34_OHM 7 /* RZQ/7 */
#define DDR4_RTT_WR_OFF 0
#define DDR4_RTT_WR_120_OHM 1
#define DDR4_RTT_WR_240_OHM 2
#define DDR4_RTT_WR_HZ 3
#define DDR4_RTT_WR_80_OHM 4
#define DDR_ODT_NEVER 0x0
#define DDR_ODT_CS 0x1
#define DDR_ODT_ALL_OTHER_CS 0x2
#define DDR_ODT_OTHER_DIMM 0x3
#define DDR_ODT_ALL 0x4
#define DDR_ODT_SAME_DIMM 0x5
#define DDR_ODT_CS_AND_OTHER_DIMM 0x6
#define DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
#define DDR_BA_INTLV_CS01 0x40
#define DDR_BA_INTLV_CS0123 0x64
#define DDR_BA_NONE 0
#define DDR_256B_INTLV 0x8
struct memctl_opt {
int rdimm;
unsigned int dbw_cap_shift;
struct local_opts_s {
unsigned int auto_precharge;
unsigned int odt_rd_cfg;
unsigned int odt_wr_cfg;
unsigned int odt_rtt_norm;
unsigned int odt_rtt_wr;
} cs_odt[DDRC_NUM_CS];
int ctlr_intlv;
unsigned int ctlr_intlv_mode;
unsigned int ba_intlv;
int addr_hash;
int ecc_mode;
int ctlr_init_ecc;
int self_refresh_in_sleep;
int self_refresh_irq_en;
int dynamic_power;
/* memory data width 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
unsigned int data_bus_dimm;
unsigned int data_bus_used; /* on individual board */
unsigned int burst_length; /* BC4, OTF and BL8 */
int otf_burst_chop_en;
int mirrored_dimm;
int quad_rank_present;
int output_driver_impedance;
int ap_en;
int x4_en;
int caslat_override;
unsigned int caslat_override_value;
int addt_lat_override;
unsigned int addt_lat_override_value;
unsigned int clk_adj;
unsigned int cpo_sample;
unsigned int wr_data_delay;
unsigned int cswl_override;
unsigned int wrlvl_override;
unsigned int wrlvl_sample;
unsigned int wrlvl_start;
unsigned int wrlvl_ctl_2;
unsigned int wrlvl_ctl_3;
int half_strength_drive_en;
int twot_en;
int threet_en;
unsigned int bstopre;
unsigned int tfaw_ps;
int rtt_override;
unsigned int rtt_override_value;
unsigned int rtt_wr_override_value;
unsigned int rtt_park;
int auto_self_refresh_en;
unsigned int sr_it;
unsigned int ddr_cdr1;
unsigned int ddr_cdr2;
unsigned int trwt_override;
unsigned int trwt;
unsigned int twrt;
unsigned int trrt;
unsigned int twwt;
unsigned int vref_phy;
unsigned int vref_dimm;
unsigned int odt;
unsigned int phy_tx_impedance;
unsigned int phy_atx_impedance;
unsigned int skip2d;
};
#endif /* DDR_OPTS_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/ddr/regs.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef DDR_REG_H
#define DDR_REG_H
#define SDRAM_CS_CONFIG_EN 0x80000000
/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
*/
#define SDRAM_CFG_MEM_EN 0x80000000
#define SDRAM_CFG_SREN 0x40000000
#define SDRAM_CFG_ECC_EN 0x20000000
#define SDRAM_CFG_RD_EN 0x10000000
#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
#define SDRAM_CFG_DBW_MASK 0x00180000
#define SDRAM_CFG_DBW_SHIFT 19
#define SDRAM_CFG_32_BW 0x00080000
#define SDRAM_CFG_16_BW 0x00100000
#define SDRAM_CFG_8_BW 0x00180000
#define SDRAM_CFG_8_BE 0x00040000
#define SDRAM_CFG_2T_EN 0x00008000
#define SDRAM_CFG_MEM_HLT 0x00000002
#define SDRAM_CFG_BI 0x00000001
#define SDRAM_CFG2_FRC_SR 0x80000000
#define SDRAM_CFG2_FRC_SR_CLEAR ~(SDRAM_CFG2_FRC_SR)
#define SDRAM_CFG2_D_INIT 0x00000010
#define SDRAM_CFG2_AP_EN 0x00000020
#define SDRAM_CFG2_ODT_ONLY_READ 2
#define SDRAM_CFG3_DDRC_RST 0x80000000
#define SDRAM_INTERVAL_REFINT 0xFFFF0000
#define SDRAM_INTERVAL_REFINT_CLEAR ~(SDRAM_INTERVAL_REFINT)
#define SDRAM_INTERVAL_BSTOPRE 0x3FFF
/* DDR_MD_CNTL */
#define MD_CNTL_MD_EN 0x80000000
#define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28)
#define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24)
#define MD_CNTL_CKE(x) (((x) & 0x3) << 20)
/* DDR_CDR1 */
#define DDR_CDR1_DHC_EN 0x80000000
#define DDR_CDR1_ODT_SHIFT 17
#define DDR_CDR1_ODT_MASK 0x6
#define DDR_CDR2_ODT_MASK 0x1
#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
#define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8))
#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
#define DDR_CDR2_VREF_RANGE_2 0x00000040
#define DDR_CDR_ODT_OFF 0x0
#define DDR_CDR_ODT_100ohm 0x1
#define DDR_CDR_ODT_120OHM 0x2
#define DDR_CDR_ODT_80ohm 0x3
#define DDR_CDR_ODT_60ohm 0x4
#define DDR_CDR_ODT_40ohm 0x5
#define DDR_CDR_ODT_50ohm 0x6
#define DDR_CDR_ODT_30ohm 0x7
/* DDR ERR_DISABLE */
#define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */
#define DDR_ERR_DISABLE_SBED (1 << 2) /* Address parity error disable */
#define DDR_ERR_DISABLE_MBED (1 << 3) /* Address parity error disable */
/* Mode Registers */
#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
/* DDR DSR2 register */
#define DDR_DSR_2_PHY_INIT_CMPLT 0x4
/* SDRAM TIMING_CFG_10 register */
#define DDR_TIMING_CFG_10_T_STAB 0x7FFF
/* DEBUG 2 register */
#define DDR_DBG_2_MEM_IDLE 0x00000002
/* DEBUG 26 register */
#define DDR_DEBUG_26_BIT_6 (0x1 << 6)
#define DDR_DEBUG_26_BIT_7 (0x1 << 7)
#define DDR_DEBUG_26_BIT_12 (0x1 << 12)
#define DDR_DEBUG_26_BIT_13 (0x1 << 13)
#define DDR_DEBUG_26_BIT_14 (0x1 << 14)
#define DDR_DEBUG_26_BIT_15 (0x1 << 15)
#define DDR_DEBUG_26_BIT_16 (0x1 << 16)
#define DDR_DEBUG_26_BIT_17 (0x1 << 17)
#define DDR_DEBUG_26_BIT_18 (0x1 << 18)
#define DDR_DEBUG_26_BIT_19 (0x1 << 19)
#define DDR_DEBUG_26_BIT_24 (0x1 << 24)
#define DDR_DEBUG_26_BIT_25 (0x1 << 25)
#define DDR_DEBUG_26_BIT_24_CLEAR ~(DDR_DEBUG_26_BIT_24)
/* DEBUG_29 register */
#define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */
#define DDR_INIT_ADDR_EXT_UIA (1 << 31)
#endif /* DDR_REG_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/ddr/utility.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef UTILITY_H
#define UTILITY_H
#include <dcfg.h>
#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
#define CCN_HN_F_SAM_CTL 0x8
#define CCN_HN_F_REGION_SIZE 0x10000
#endif
unsigned long get_ddr_freq(struct sysinfo *sys, int ctrl_num);
unsigned int get_memory_clk_ps(unsigned long clk);
unsigned int picos_to_mclk(unsigned long data_rate, unsigned int picos);
unsigned int get_ddrc_version(const struct ccsr_ddr *ddr);
void print_ddr_info(struct ccsr_ddr *ddr);
#endif
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/flexspi/flash_info.h
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright 2020-2021 NXP
*/
/**
* @Flash info
*
*/
#ifndef FLASH_INFO_H
#define FLASH_INFO_H
#define SZ_16M_BYTES 0x1000000U
/* Start of "if defined(CONFIG_MT25QU512A)" */
#if defined(CONFIG_MT25QU512A)
#define F_SECTOR_64K 0x10000U
#define F_PAGE_256 0x100U
#define F_SECTOR_4K 0x1000U
#define F_FLASH_SIZE_BYTES 0x4000000U
#define F_SECTOR_ERASE_SZ F_SECTOR_64K
#ifdef CONFIG_FSPI_4K_ERASE
#define F_SECTOR_ERASE_SZ F_SECTOR_4K
#endif
/* End of "if defined(CONFIG_MT25QU512A)" */
/* Start of "if defined(CONFIG_MX25U25645G)" */
#elif defined(CONFIG_MX25U25645G)
#define F_SECTOR_64K 0x10000U
#define F_PAGE_256 0x100U
#define F_SECTOR_4K 0x1000U
#define F_FLASH_SIZE_BYTES 0x2000000U
#define F_SECTOR_ERASE_SZ F_SECTOR_64K
#ifdef CONFIG_FSPI_4K_ERASE
#define F_SECTOR_ERASE_SZ F_SECTOR_4K
#endif
/* End of "if defined(CONFIG_MX25U25645G)" */
/* Start of "if defined(CONFIG_MX25U51245G)" */
#elif defined(CONFIG_MX25U51245G)
#define F_SECTOR_64K 0x10000U
#define F_PAGE_256 0x100U
#define F_SECTOR_4K 0x1000U
#define F_FLASH_SIZE_BYTES 0x4000000U
#define F_SECTOR_ERASE_SZ F_SECTOR_64K
#ifdef CONFIG_FSPI_4K_ERASE
#define F_SECTOR_ERASE_SZ F_SECTOR_4K
#endif
/* End of "if defined(CONFIG_MX25U51245G)" */
/* Start of "if defined(CONFIG_MT35XU512A)" */
#elif defined(CONFIG_MT35XU512A)
#define F_SECTOR_128K 0x20000U
#define F_SECTOR_32K 0x8000U
#define F_PAGE_256 0x100U
#define F_SECTOR_4K 0x1000U
#define F_FLASH_SIZE_BYTES 0x4000000U
#define F_SECTOR_ERASE_SZ F_SECTOR_128K
#ifdef CONFIG_FSPI_4K_ERASE
#define F_SECTOR_ERASE_SZ F_SECTOR_4K
#endif
/* If Warm boot is enabled for the platform,
* count of arm instruction N-OP(s) to mark
* the completion of write operation to flash;
* varies from one flash to other.
*/
#ifdef NXP_WARM_BOOT
#define FLASH_WR_COMP_WAIT_BY_NOP_COUNT 0x20000
#endif
/* End of "if defined(CONFIG_MT35XU512A)" */
/* Start of #elif defined(CONFIG_MT35XU02G) */
#elif defined(CONFIG_MT35XU02G)
#define F_SECTOR_128K 0x20000U
#define F_PAGE_256 0x100U
#define F_SECTOR_4K 0x1000U
#define F_FLASH_SIZE_BYTES 0x10000000U
#define F_SECTOR_ERASE_SZ F_SECTOR_128K
#ifdef CONFIG_FSPI_4K_ERASE
#define F_SECTOR_ERASE_SZ F_SECTOR_4K
#endif
#endif /* End of #elif defined(CONFIG_MT35XU02G) */
#endif /* FLASH_INFO_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/flexspi/fspi_api.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
/*!
* @file fspi_api.h
* @brief This file contains the FlexSPI/FSPI API to communicate
* to attached Slave device.
* @addtogroup FSPI_API
* @{
*/
#ifndef FSPI_API_H
#define FSPI_API_H
#if DEBUG_FLEXSPI
#define SZ_57M 0x3900000u
#endif
/*!
* Basic set of APIs.
*/
/*!
* @details AHB read/IP Read, decision to be internal to API
* Minimum Read size = 1Byte
* @param[in] src_off source offset from where data to read from flash
* @param[out] des Destination location where data needs to be copied
* @param[in] len length in Bytes,where 1-word=4-bytes/32-bits
*
* @return XSPI_SUCCESS or error code
*/
int xspi_read(uint32_t src_off, uint32_t *des, uint32_t len);
/*!
* @details Sector erase, Minimum size
* 256KB(0x40000)/128KB(0x20000)/64K(0x10000)/4K(0x1000)
* depending upon flash, Calls xspi_wren() internally
* @param[out] erase_offset Destination erase location on flash which
* has to be erased, needs to be multiple of 0x40000/0x20000/0x10000
* @param[in] erase_len length in bytes in Hex like 0x100000 for 1MB, minimum
* erase size is 1 sector(0x40000/0x20000/0x10000)
*
* @return XSPI_SUCCESS or error code
*/
int xspi_sector_erase(uint32_t erase_offset, uint32_t erase_len);
/*!
* @details IP write, For writing data to flash, calls xspi_wren() internally.
* Single/multiple page write can start @any offset, but performance will be low
* due to ERRATA
* @param[out] dst_off Destination location on flash where data needs to
* be written
* @param[in] src source offset from where data to be read
* @param[in] len length in bytes,where 1-word=4-bytes/32-bits
*
* @return XSPI_SUCCESS or error code
*/
int xspi_write(uint32_t dst_off, void *src, uint32_t len);
/*!
* @details fspi_init, Init function.
* @param[in] uint32_t base_reg_addr
* @param[in] uint32_t flash_start_addr
*
* @return XSPI_SUCCESS or error code
*/
int fspi_init(uint32_t base_reg_addr, uint32_t flash_start_addr);
/*!
* @details is_flash_busy, Check if any erase or write or lock is
* pending on flash/slave
* @param[in] void
*
* @return TRUE/FLASE
*/
bool is_flash_busy(void);
/*!
* Advanced set of APIs.
*/
/*!
* @details Write enable, to be used by advance users only.
* Step 1 for sending write commands to flash.
* @param[in] dst_off destination offset where data will be written
*
* @return XSPI_SUCCESS or error code
*/
int xspi_wren(uint32_t dst_off);
/*!
* @details AHB read, meaning direct memory mapped access to flash,
* Minimum Read size = 1Byte
* @param[in] src_off source offset from where data to read from flash,
* needs to be word aligned
* @param[out] des Destination location where data needs to be copied
* @param[in] len length in Bytes,where 1-word=4-bytes/32-bits
*
* @return XSPI_SUCCESS or error code
*/
int xspi_ahb_read(uint32_t src_off, uint32_t *des, uint32_t len);
/*!
* @details IP read, READ via RX buffer from flash, minimum READ size = 1Byte
* @param[in] src_off source offset from where data to be read from flash
* @param[out] des Destination location where data needs to be copied
* @param[in] len length in Bytes,where 1-word=4-bytes/32-bits
*
* @return XSPI_SUCCESS or error code
*/
int xspi_ip_read(uint32_t src_off, uint32_t *des, uint32_t len);
/*!
* @details CHIP erase, Erase complete chip in one go
*
* @return XSPI_SUCCESS or error code
*/
int xspi_bulk_erase(void);
/*!
* Add test cases to confirm flash read/erase/write functionality.
*/
void fspi_test(uint32_t fspi_test_addr, uint32_t size, int extra);
#endif /* FSPI_API_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/flexspi/xspi_error_codes.h
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/*
* Copyright 2020 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
/* error codes */
#ifndef XSPI_ERROR_CODES_H
#define XSPI_ERROR_CODES_H
#include <errno.h>
typedef enum {
XSPI_SUCCESS = 0,
XSPI_READ_FAIL = ELAST + 1,
XSPI_ERASE_FAIL,
XSPI_IP_READ_FAIL,
XSPI_AHB_READ_FAIL,
XSPI_IP_WRITE_FAIL,
XSPI_AHB_WRITE_FAIL,
XSPI_BLOCK_TIMEOUT,
XSPI_UNALIGN_ADDR,
XSPI_UNALIGN_SIZE,
} XSPI_STATUS_CODES;
#undef ELAST
#define ELAST XSPI_STATUS_CODES.XSPI_UNALIGN_SIZE
#endif
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/gic/gicv2/plat_gic.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef PLAT_GICV2_H
#define PLAT_GICV2_H
#include <drivers/arm/gicv2.h>
/* register offsets */
#define GICD_CTLR_OFFSET 0x0
#define GICD_CPENDSGIR3_OFFSET 0xF1C
#define GICD_SPENDSGIR3_OFFSET 0xF2C
#define GICD_SGIR_OFFSET 0xF00
#define GICD_IGROUPR0_OFFSET 0x080
#define GICD_TYPER_OFFSET 0x0004
#define GICD_ISENABLER0_OFFSET 0x0100
#define GICD_ICENABLER0_OFFSET 0x0180
#define GICD_IPRIORITYR3_OFFSET 0x040C
#define GICD_ISENABLERn_OFFSET 0x0100
#define GICD_ISACTIVER0_OFFSET 0x300
#define GICC_CTLR_OFFSET 0x0
#define GICC_PMR_OFFSET 0x0004
#define GICC_IAR_OFFSET 0x000C
#define GICC_DIR_OFFSET 0x1000
#define GICC_EOIR_OFFSET 0x0010
/* bitfield masks */
#define GICC_CTLR_EN_GRP0 0x1
#define GICC_CTLR_EN_GRP1 0x2
#define GICC_CTLR_EOImodeS_MASK 0x200
#define GICC_CTLR_DIS_BYPASS 0x60
#define GICC_CTLR_CBPR_MASK 0x10
#define GICC_CTLR_FIQ_EN_MASK 0x8
#define GICC_CTLR_ACKCTL_MASK 0x4
#define GICC_PMR_FILTER 0xFF
#define GICD_CTLR_EN_GRP0 0x1
#define GICD_CTLR_EN_GRP1 0x2
#define GICD_IGROUP0_SGI15 0x8000
#define GICD_ISENABLE0_SGI15 0x8000
#define GICD_ICENABLE0_SGI15 0x8000
#define GICD_ISACTIVER0_SGI15 0x8000
#define GICD_CPENDSGIR_CLR_MASK 0xFF000000
#define GICD_IPRIORITY_SGI15_MASK 0xFF000000
#define GICD_SPENDSGIR3_SGI15_MASK 0xFF000000
#define GICD_SPENDSGIR3_SGI15_OFFSET 0x18
#ifndef __ASSEMBLER__
/* GIC common API's */
void plat_ls_gic_driver_init(const uintptr_t nxp_gicd_addr,
const uintptr_t nxp_gicc_addr,
uint8_t plat_core_count,
interrupt_prop_t *ls_interrupt_props,
uint8_t ls_interrupt_prop_count,
uint32_t *target_mask_array);
void plat_ls_gic_init(void);
void plat_ls_gic_cpuif_enable(void);
void plat_ls_gic_cpuif_disable(void);
void plat_ls_gic_redistif_on(void);
void plat_ls_gic_redistif_off(void);
void plat_gic_pcpu_init(void);
/* GIC utility functions */
void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base);
#endif
#endif /* PLAT_GICV2_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/gic/gicv3/plat_gic.h
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/*
* Copyright 2021-2022 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef PLAT_GICV3_H
#define PLAT_GICV3_H
#include <drivers/arm/gicv3.h>
/* offset between redistributors */
#define GIC_RD_OFFSET 0x00020000
/* offset between SGI's */
#define GIC_SGI_OFFSET 0x00020000
/* offset from rd base to sgi base */
#define GIC_RD_2_SGI_OFFSET 0x00010000
/* register offsets */
#define GICD_CTLR_OFFSET 0x0
#define GICD_CLR_SPI_SR 0x58
#define GICD_IGROUPR_2 0x88
#define GICD_ISENABLER_1 0x104
#define GICD_ICENABLER_1 0x184
#define GICD_ISENABLER_2 0x108
#define GICD_ICENABLER_2 0x188
#define GICD_ISENABLER_3 0x10c
#define GICD_ICENABLER_3 0x18c
#define GICD_ICPENDR_2 0x288
#define GICD_ICACTIVER_2 0x388
#define GICD_IPRIORITYR_22 0x458
#define GICD_ICFGR_5 0xC14
#define GICD_IGRPMODR_2 0xD08
#define GICD_IROUTER60_OFFSET 0x61e0
#define GICD_IROUTER76_OFFSET 0x6260
#define GICD_IROUTER89_OFFSET 0x62C8
#define GICD_IROUTER112_OFFSET 0x6380
#define GICD_IROUTER113_OFFSET 0x6388
#define GICR_ICENABLER0_OFFSET 0x180
#define GICR_CTLR_OFFSET 0x0
#define GICR_IGROUPR0_OFFSET 0x80
#define GICR_IGRPMODR0_OFFSET 0xD00
#define GICR_IPRIORITYR3_OFFSET 0x40C
#define GICR_ICPENDR0_OFFSET 0x280
#define GICR_ISENABLER0_OFFSET 0x100
#define GICR_TYPER_OFFSET 0x8
#define GICR_WAKER_OFFSET 0x14
#define GICR_ICACTIVER0_OFFSET 0x380
#define GICR_ICFGR0_OFFSET 0xC00
/* bitfield masks */
#define GICD_CTLR_EN_GRP_MASK 0x7
#define GICD_CTLR_EN_GRP_1NS 0x2
#define GICD_CTLR_EN_GRP_1S 0x4
#define GICD_CTLR_EN_GRP_0 0x1
#define GICD_CTLR_ARE_S_MASK 0x10
#define GICD_CTLR_RWP 0x80000000
#define GICR_ICENABLER0_SGI15 0x00008000
#define GICR_CTLR_RWP 0x8
#define GICR_IGROUPR0_SGI15 0x00008000
#define GICR_IGRPMODR0_SGI15 0x00008000
#define GICR_ISENABLER0_SGI15 0x00008000
#define GICR_IPRIORITYR3_SGI15_MASK 0xFF000000
#define GICR_ICPENDR0_SGI15 0x8000
#define GIC_SPI_89_MASK 0x02000000
#define GIC_SPI89_PRIORITY_MASK 0xFF00
#define GIC_IRM_SPI89 0x80000000
#define GICD_IROUTER_VALUE 0x100
#define GICD_ISENABLER_1_VALUE 0x10000000
#define GICD_ISENABLER_2_VALUE 0x100
#define GICD_ISENABLER_3_VALUE 0x20100
#define GICR_WAKER_SLEEP_BIT 0x2
#define GICR_WAKER_ASLEEP (1 << 2 | 1 << 1)
#define ICC_SRE_EL3_SRE 0x1
#define ICC_IGRPEN0_EL1_EN 0x1
#define ICC_CTLR_EL3_CBPR_EL1S 0x1
#define ICC_CTLR_EL3_RM 0x20
#define ICC_CTLR_EL3_EOIMODE_EL3 0x4
#define ICC_CTLR_EL3_PMHE 0x40
#define ICC_PMR_EL1_P_FILTER 0xFF
#define ICC_IAR0_EL1_SGI15 0xF
#define ICC_SGI0R_EL1_INTID 0x0F000000
#define ICC_IAR0_INTID_SPI_89 0x59
#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
#define ICC_PMR_EL1 S3_0_C4_C6_0
#define ICC_SRE_EL3 S3_6_C12_C12_5
#define ICC_CTLR_EL3 S3_6_C12_C12_4
#define ICC_SRE_EL2 S3_4_C12_C9_5
#define ICC_CTLR_EL1 S3_0_C12_C12_4
#ifndef __ASSEMBLER__
/* GIC common API's */
typedef unsigned int (*my_core_pos_fn)(void);
void plat_ls_gic_driver_init(const uintptr_t nxp_gicd_addr,
const uintptr_t nxp_gicr_addr,
uint8_t plat_core_count,
interrupt_prop_t *ls_interrupt_props,
uint8_t ls_interrupt_prop_count,
uintptr_t *target_mask_array,
mpidr_hash_fn mpidr_to_core_pos);
//void plat_ls_gic_driver_init(void);
void plat_ls_gic_init(void);
void plat_ls_gic_cpuif_enable(void);
void plat_ls_gic_cpuif_disable(void);
void plat_ls_gic_redistif_on(void);
void plat_ls_gic_redistif_off(void);
void plat_gic_pcpu_init(void);
#endif
#endif /* PLAT_GICV3_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/gpio/nxp_gpio.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef PLAT_GPIO_H
#define PLAT_GPIO_H
#include <endian.h>
#include <lib/mmio.h>
/* GPIO Register offset */
#define GPIO_SEL_MASK 0x7F
#define GPIO_BIT_MASK 0x1F
#define GPDIR_REG_OFFSET 0x0
#define GPDAT_REG_OFFSET 0x8
#define GPIO_ID_BASE_ADDR_SHIFT 5U
#define GPIO_BITS_PER_BASE_REG 32U
#define GPIO_0 0
#define GPIO_1 1
#define GPIO_2 2
#define GPIO_3 3
#define GPIO_SUCCESS 0x0
#define GPIO_FAILURE 0x1
#ifdef NXP_GPIO_BE
#define gpio_read32(a) bswap32(mmio_read_32((uintptr_t)(a)))
#define gpio_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
#elif defined(NXP_GPIO_LE)
#define gpio_read32(a) mmio_read_32((uintptr_t)(a))
#define gpio_write32(a, v) mmio_write_32((uintptr_t)(a), (v))
#else
#error Please define GPIO register endianness
#endif
typedef struct {
uintptr_t gpio1_base_addr;
uintptr_t gpio2_base_addr;
uintptr_t gpio3_base_addr;
uintptr_t gpio4_base_addr;
} gpio_init_info_t;
void gpio_init(gpio_init_info_t *gpio_init_data);
uint32_t *select_gpio_n_bitnum(uint32_t povdd_gpio, uint32_t *bit_num);
int clr_gpio_bit(uint32_t *gpio_base_addr, uint32_t bit_num);
int set_gpio_bit(uint32_t *gpio_base_addr, uint32_t bit_num);
#endif /* PLAT_GPIO_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/i2c/i2c.h
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/*
* Copyright 2016-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef I2C_H
#define I2C_H
#include <lib/mmio.h>
#define I2C_TIMEOUT 1000 /* ms */
#define I2C_FD_CONSERV 0x7e
#define I2C_CR_DIS (1 << 7)
#define I2C_CR_EN (0 << 7)
#define I2C_CR_MA (1 << 5)
#define I2C_CR_TX (1 << 4)
#define I2C_CR_TX_NAK (1 << 3)
#define I2C_CR_RSTA (1 << 2)
#define I2C_SR_BB (1 << 5)
#define I2C_SR_IDLE (0 << 5)
#define I2C_SR_AL (1 << 4)
#define I2C_SR_IF (1 << 1)
#define I2C_SR_RX_NAK (1 << 0)
#define I2C_SR_RST (I2C_SR_AL | I2C_SR_IF)
#define I2C_GLITCH_EN 0x8
#define i2c_in(a) mmio_read_8((uintptr_t)(a))
#define i2c_out(a, v) mmio_write_8((uintptr_t)(a), (v))
struct ls_i2c {
unsigned char ad; /* I2c Bus Address Register */
unsigned char fd; /* I2c Bus Frequency Dividor Register */
unsigned char cr; /* I2c Bus Control Register */
unsigned char sr; /* I2c Bus Status Register */
unsigned char dr; /* I2C Bus Data I/O Register */
unsigned char ic; /* I2C Bus Interrupt Config Register */
unsigned char dbg; /* I2C Bus Debug Register */
};
void i2c_init(uintptr_t nxp_i2c_addr);
int i2c_read(unsigned char chip, int addr, int alen,
unsigned char *buf, int len);
int i2c_write(unsigned char chip, int addr, int alen,
const unsigned char *buf, int len);
int i2c_probe_chip(unsigned char chip);
#endif /* I2C_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/ifc/ifc_nand.h
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/*
* Copyright 2022 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef IFC_NAND_H
#define IFC_NAND_H
#define NXP_IFC_SRAM_BUFFER_SIZE UL(0x100000) /* 1M */
int ifc_nand_init(uintptr_t *block_dev_spec,
uintptr_t ifc_region_addr,
uintptr_t ifc_register_addr,
size_t ifc_sram_size,
uintptr_t ifc_nand_blk_offset,
size_t ifc_nand_blk_size);
#endif /*IFC_NAND_H*/
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/ifc/ifc_nor.h
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/*
* Copyright 2020-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef IFC_NOR_H
#define IFC_NOR_H
int ifc_nor_init(uintptr_t flash_addr, size_t flash_size);
#endif /*IFC_NOR_H*/
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/interconnect/ls_interconnect.h
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/*
* Copyright 2020-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef LS_INTERCONNECT_H
#define LS_INTERCONNECT_H
#if (INTERCONNECT == CCI400)
#define CCI_TERMINATE_BARRIER_TX 0x8
#endif
/* Interconnect CCI/CCN functions */
void plat_ls_interconnect_enter_coherency(unsigned int num_clusters);
void plat_ls_interconnect_exit_coherency(void);
#endif
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/pmu/pmu.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef PMU_H
#define PMU_H
/* PMU Registers' OFFSET */
#define PMU_PCPW20SR_OFFSET 0x830
#define PMU_CLL2FLUSHSETR_OFFSET 0x1110
#define PMU_CLSL2FLUSHCLRR_OFFSET 0x1114
#define PMU_CLL2FLUSHSR_OFFSET 0x1118
#define PMU_POWMGTCSR_VAL (1 << 20)
/* PMU Registers */
#define CORE_TIMEBASE_ENBL_OFFSET 0x8A0
#define CLUST_TIMER_BASE_ENBL_OFFSET 0x18A0
#define PMU_IDLE_CLUSTER_MASK 0x2
#define PMU_FLUSH_CLUSTER_MASK 0x2
#define PMU_IDLE_CORE_MASK 0xfe
/* pmu register offsets and bitmaps */
#define PMU_POWMGTDCR0_OFFSET 0xC20
#define PMU_POWMGTCSR_OFFSET 0x4000
#define PMU_CLAINACTSETR_OFFSET 0x1100
#define PMU_CLAINACTCLRR_OFFSET 0x1104
#define PMU_CLSINACTSETR_OFFSET 0x1108
#define PMU_CLSINACTCLRR_OFFSET 0x110C
#define PMU_CLL2FLUSHSETR_OFFSET 0x1110
#define PMU_CLL2FLUSHCLRR_OFFSET 0x1114
#define PMU_IPPDEXPCR0_OFFSET 0x4040
#define PMU_IPPDEXPCR1_OFFSET 0x4044
#define PMU_IPPDEXPCR2_OFFSET 0x4048
#define PMU_IPPDEXPCR3_OFFSET 0x404C
#define PMU_IPPDEXPCR4_OFFSET 0x4050
#define PMU_IPPDEXPCR5_OFFSET 0x4054
#define PMU_IPPDEXPCR6_OFFSET 0x4058
#define PMU_IPSTPCR0_OFFSET 0x4120
#define PMU_IPSTPCR1_OFFSET 0x4124
#define PMU_IPSTPCR2_OFFSET 0x4128
#define PMU_IPSTPCR3_OFFSET 0x412C
#define PMU_IPSTPCR4_OFFSET 0x4130
#define PMU_IPSTPCR5_OFFSET 0x4134
#define PMU_IPSTPCR6_OFFSET 0x4138
#define PMU_IPSTPACKSR0_OFFSET 0x4140
#define PMU_IPSTPACKSR1_OFFSET 0x4144
#define PMU_IPSTPACKSR2_OFFSET 0x4148
#define PMU_IPSTPACKSR3_OFFSET 0x414C
#define PMU_IPSTPACKSR4_OFFSET 0x4150
#define PMU_IPSTPACKSR5_OFFSET 0x4154
#define PMU_IPSTPACKSR6_OFFSET 0x4158
#define CLAINACT_DISABLE_ACP 0xFF
#define CLSINACT_DISABLE_SKY 0xFF
#define POWMGTDCR_STP_OV_EN 0x1
#define POWMGTCSR_LPM20_REQ 0x00100000
/* Used by PMU */
#define DEVDISR1_MASK 0x024F3504
#define DEVDISR2_MASK 0x0003FFFF
#define DEVDISR3_MASK 0x0000303F
#define DEVDISR4_MASK 0x0000FFFF
#define DEVDISR5_MASK 0x00F07603
#define DEVDISR6_MASK 0x00000001
#ifndef __ASSEMBLER__
void enable_timer_base_to_cluster(uintptr_t nxp_pmu_addr);
void enable_core_tb(uintptr_t nxp_pmu_addr);
#endif /* __ASSEMBLER__ */
#endif
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/qspi/qspi.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef QSPI_H
#define QSPI_H
#include <endian.h>
#include <lib/mmio.h>
#define CHS_QSPI_MCR 0x01550000
#define CHS_QSPI_64LE 0xC
#ifdef NXP_QSPI_BE
#define qspi_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
#define qspi_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
#elif defined(NXP_QSPI_LE)
#define qspi_in32(a) mmio_read_32((uintptr_t)(a))
#define qspi_out32(a, v) mmio_write_32((uintptr_t)(a), (v))
#else
#error Please define CCSR QSPI register endianness
#endif
int qspi_io_setup(uintptr_t nxp_qspi_flash_addr,
size_t nxp_qspi_flash_size,
uintptr_t fip_offset);
#endif /* __QSPI_H__ */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/sd/sd_mmc.h
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/*
* Copyright (c) 2015, 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef SD_MMC_H
#define SD_MMC_H
#include <lib/mmio.h>
/* operating freq */
#define CARD_IDENTIFICATION_FREQ 400000
#define SD_SS_25MHZ 20000000
#define SD_HS_50MHZ 40000000
#define MMC_SS_20MHZ 15000000
#define MMC_HS_26MHZ 20000000
#define MMC_HS_52MHZ 40000000
/* Need to check this value ? */
#define MAX_PLATFORM_CLOCK 800000000
/* eSDHC system control register defines */
#define ESDHC_SYSCTL_DTOCV(t) (((t) & 0xF) << 16)
#define ESDHC_SYSCTL_SDCLKFS(f) (((f) & 0xFF) << 8)
#define ESDHC_SYSCTL_DVS(d) (((d) & 0xF) << 4)
#define ESDHC_SYSCTL_SDCLKEN (0x00000008)
#define ESDHC_SYSCTL_RSTA (0x01000000)
/* Data timeout counter value. SDHC_CLK x 227 */
#define TIMEOUT_COUNTER_SDCLK_2_27 0xE
#define ESDHC_SYSCTL_INITA 0x08000000
/* eSDHC interrupt status enable register defines */
#define ESDHC_IRQSTATEN_CINS 0x00000040
#define ESDHC_IRQSTATEN_BWR 0x00000010
/* eSDHC interrupt status register defines */
#define ESDHC_IRQSTAT_DMAE (0x10000000)
#define ESDHC_IRQSTAT_AC12E (0x01000000)
#define ESDHC_IRQSTAT_DEBE (0x00400000)
#define ESDHC_IRQSTAT_DCE (0x00200000)
#define ESDHC_IRQSTAT_DTOE (0x00100000)
#define ESDHC_IRQSTAT_CIE (0x00080000)
#define ESDHC_IRQSTAT_CEBE (0x00040000)
#define ESDHC_IRQSTAT_CCE (0x00020000)
#define ESDHC_IRQSTAT_CTOE (0x00010000)
#define ESDHC_IRQSTAT_CINT (0x00000100)
#define ESDHC_IRQSTAT_CRM (0x00000080)
#define ESDHC_IRQSTAT_CINS (0x00000040)
#define ESDHC_IRQSTAT_BRR (0x00000020)
#define ESDHC_IRQSTAT_BWR (0x00000010)
#define ESDHC_IRQSTAT_DINT (0x00000008)
#define ESDHC_IRQSTAT_BGE (0x00000004)
#define ESDHC_IRQSTAT_TC (0x00000002)
#define ESDHC_IRQSTAT_CC (0x00000001)
#define ESDHC_IRQSTAT_CMD_ERR (ESDHC_IRQSTAT_CIE |\
ESDHC_IRQSTAT_CEBE |\
ESDHC_IRQSTAT_CCE)
#define ESDHC_IRQSTAT_DATA_ERR (ESDHC_IRQSTAT_DEBE |\
ESDHC_IRQSTAT_DCE |\
ESDHC_IRQSTAT_DTOE)
#define ESDHC_IRQSTAT_CLEAR_ALL (0xFFFFFFFF)
/* eSDHC present state register defines */
#define ESDHC_PRSSTAT_CLSL 0x00800000
#define ESDHC_PRSSTAT_WPSPL 0x00080000
#define ESDHC_PRSSTAT_CDPL 0x00040000
#define ESDHC_PRSSTAT_CINS 0x00010000
#define ESDHC_PRSSTAT_BREN 0x00000800
#define ESDHC_PRSSTAT_BWEN 0x00000400
#define ESDHC_PRSSTAT_RTA 0x00000200
#define ESDHC_PRSSTAT_WTA 0x00000100
#define ESDHC_PRSSTAT_SDOFF 0x00000080
#define ESDHC_PRSSTAT_PEROFF 0x00000040
#define ESDHC_PRSSTAT_HCKOFF 0x00000020
#define ESDHC_PRSSTAT_IPGOFF 0x00000010
#define ESDHC_PRSSTAT_DLA 0x00000004
#define ESDHC_PRSSTAT_CDIHB 0x00000002
#define ESDHC_PRSSTAT_CIHB 0x00000001
/* eSDHC protocol control register defines */
#define ESDHC_PROCTL_EMODE_LE 0x00000020
#define ESDHC_PROCTL_DTW_1BIT 0x00000000
#define ESDHC_PROCTL_DTW_4BIT 0x00000002
#define ESDHC_PROCTL_DTW_8BIT 0x00000004
/* Watermark Level Register (WML) */
#define ESDHC_WML_RD_WML(w) ((w) & 0x7F)
#define ESDHC_WML_WR_WML(w) (((w) & 0x7F) << 16)
#define ESDHC_WML_RD_BRST(w) (((w) & 0xF) << 8)
#define ESDHC_WML_WR_BRST(w) (((w) & 0xF) << 24)
#define ESDHC_WML_WR_BRST_MASK (0x0F000000)
#define ESDHC_WML_RD_BRST_MASK (0x00000F00)
#define ESDHC_WML_RD_WML_MASK (0x0000007F)
#define ESDHC_WML_WR_WML_MASK (0x007F0000)
#define WML_512_BYTES (0x0)
#define BURST_128_BYTES (0x0)
/* eSDHC control register define */
#define ESDHC_DCR_SNOOP 0x00000040
/* ESDHC Block attributes register */
#define ESDHC_BLKATTR_BLKCNT(c) (((c) & 0xffff) << 16)
#define ESDHC_BLKATTR_BLKSZE(s) ((s) & 0xfff)
/* Transfer Type Register */
#define ESDHC_XFERTYP_CMD(c) (((c) & 0x3F) << 24)
#define ESDHC_XFERTYP_CMDTYP_NORMAL (0x0)
#define ESDHC_XFERTYP_CMDTYP_SUSPEND (0x00400000)
#define ESDHC_XFERTYP_CMDTYP_RESUME (0x00800000)
#define ESDHC_XFERTYP_CMDTYP_ABORT (0x00C00000)
#define ESDHC_XFERTYP_DPSEL (0x00200000)
#define ESDHC_XFERTYP_CICEN (0x00100000)
#define ESDHC_XFERTYP_CCCEN (0x00080000)
#define ESDHC_XFERTYP_RSPTYP_NONE (0x0)
#define ESDHC_XFERTYP_RSPTYP_136 (0x00010000)
#define ESDHC_XFERTYP_RSPTYP_48 (0x00020000)
#define ESDHC_XFERTYP_RSPTYP_48_BUSY (0x00030000)
#define ESDHC_XFERTYP_MSBSEL (0x00000020)
#define ESDHC_XFERTYP_DTDSEL (0x00000010)
#define ESDHC_XFERTYP_AC12EN (0x00000004)
#define ESDHC_XFERTYP_BCEN (0x00000002)
#define ESDHC_XFERTYP_DMAEN (0x00000001)
#define MMC_VDD_HIGH_VOLTAGE 0x00000100
/* command index */
#define CMD0 0
#define CMD1 1
#define CMD2 2
#define CMD3 3
#define CMD5 5
#define CMD6 6
#define CMD7 7
#define CMD8 8
#define CMD9 9
#define CMD12 12
#define CMD13 13
#define CMD14 14
#define CMD16 16
#define CMD17 17
#define CMD18 18
#define CMD19 19
#define CMD24 24
#define CMD41 41
#define CMD42 42
#define CMD51 51
#define CMD55 55
#define CMD56 56
#define ACMD6 CMD6
#define ACMD13 CMD13
#define ACMD41 CMD41
#define ACMD42 CMD42
#define ACMD51 CMD51
/* commands abbreviations */
#define CMD_GO_IDLE_STATE CMD0
#define CMD_MMC_SEND_OP_COND CMD1
#define CMD_ALL_SEND_CID CMD2
#define CMD_SEND_RELATIVE_ADDR CMD3
#define CMD_SET_DSR CMD4
#define CMD_SWITCH_FUNC CMD6
#define CMD_SELECT_CARD CMD7
#define CMD_DESELECT_CARD CMD7
#define CMD_SEND_IF_COND CMD8
#define CMD_MMC_SEND_EXT_CSD CMD8
#define CMD_SEND_CSD CMD9
#define CMD_SEND_CID CMD10
#define CMD_STOP_TRANSMISSION CMD12
#define CMD_SEND_STATUS CMD13
#define CMD_BUS_TEST_R CMD14
#define CMD_GO_INACTIVE_STATE CMD15
#define CMD_SET_BLOCKLEN CMD16
#define CMD_READ_SINGLE_BLOCK CMD17
#define CMD_READ_MULTIPLE_BLOCK CMD18
#define CMD_WRITE_SINGLE_BLOCK CMD24
#define CMD_BUS_TEST_W CMD19
#define CMD_APP_CMD CMD55
#define CMD_GEN_CMD CMD56
#define CMD_SET_BUS_WIDTH ACMD6
#define CMD_SD_STATUS ACMD13
#define CMD_SD_SEND_OP_COND ACMD41
#define CMD_SET_CLR_CARD_DETECT ACMD42
#define CMD_SEND_SCR ACMD51
/* MMC card spec version */
#define MMC_CARD_VERSION_1_2 0
#define MMC_CARD_VERSION_1_4 1
#define MMC_CARD_VERSION_2_X 2
#define MMC_CARD_VERSION_3_X 3
#define MMC_CARD_VERSION_4_X 4
/* SD Card Spec Version */
/* May need to add version 3 here? */
#define SD_CARD_VERSION_1_0 0
#define SD_CARD_VERSION_1_10 1
#define SD_CARD_VERSION_2_0 2
/* card types */
#define MMC_CARD 0
#define SD_CARD 1
#define NOT_SD_CARD MMC_CARD
/* Card rca */
#define SD_MMC_CARD_RCA 0x1
#define BLOCK_LEN_512 512
/* card state */
#define STATE_IDLE 0
#define STATE_READY 1
#define STATE_IDENT 2
#define STATE_STBY 3
#define STATE_TRAN 4
#define STATE_DATA 5
#define STATE_RCV 6
#define STATE_PRG 7
#define STATE_DIS 8
/* Card OCR register */
/* VDD voltage window 1,65 to 1.95 */
#define MMC_OCR_VDD_165_195 0x00000080
/* VDD voltage window 2.7-2.8 */
#define MMC_OCR_VDD_FF8 0x00FF8000
#define MMC_OCR_CCS 0x40000000/* Card Capacity */
#define MMC_OCR_BUSY 0x80000000/* busy bit */
#define SD_OCR_HCS 0x40000000/* High capacity host */
#define MMC_OCR_SECTOR_MODE 0x40000000/* Access Mode as Sector */
/* mmc Switch function */
#define SET_EXT_CSD_HS_TIMING 0x03B90100/* set High speed */
/* check supports switching or not */
#define SD_SWITCH_FUNC_CHECK_MODE 0x00FFFFF1
#define SD_SWITCH_FUNC_SWITCH_MODE 0x80FFFFF1/* switch */
#define SD_SWITCH_FUNC_HIGH_SPEED 0x02/* HIGH SPEED FUNC */
#define SWITCH_ERROR 0x00000080
/* errors in sending commands */
#define RESP_TIMEOUT 0x1
#define COMMAND_ERROR 0x2
/* error in response */
#define R1_ERROR (1 << 19)
#define R1_CURRENT_STATE(x) (((x) & 0x00001E00) >> 9)
/* Host Controller Capabilities */
#define ESDHC_HOSTCAPBLT_DMAS (0x00400000)
/* SD/MMC memory map */
struct esdhc_regs {
uint32_t dsaddr; /* dma system address */
uint32_t blkattr; /* Block attributes */
uint32_t cmdarg; /* Command argument */
uint32_t xfertyp; /* Command transfer type */
uint32_t cmdrsp[4]; /* Command response0,1,2,3 */
uint32_t datport; /* Data buffer access port */
uint32_t prsstat; /* Present state */
uint32_t proctl; /* Protocol control */
uint32_t sysctl; /* System control */
uint32_t irqstat; /* Interrupt status */
uint32_t irqstaten; /* Interrupt status enable */
uint32_t irqsigen; /* Interrupt signal enable */
uint32_t autoc12err; /* Auto CMD12 status */
uint32_t hostcapblt; /* Host controller capabilities */
uint32_t wml; /* Watermark level */
uint32_t res1[2];
uint32_t fevt; /* Force event */
uint32_t res2;
uint32_t adsaddrl;
uint32_t adsaddrh;
uint32_t res3[39];
uint32_t hostver; /* Host controller version */
uint32_t res4;
uint32_t dmaerr; /* DMA error address */
uint32_t dmaerrh; /* DMA error address high */
uint32_t dmaerrattr; /* DMA error atrribute */
uint32_t res5;
uint32_t hostcapblt2;/* Host controller capabilities2 */
uint32_t res6[2];
uint32_t tcr; /* Tuning control */
uint32_t res7[7];
uint32_t dirctrl; /* Direction control */
uint32_t ccr; /* Clock control */
uint32_t res8[177];
uint32_t ctl; /* Control register */
};
/* SD/MMC card attributes */
struct card_attributes {
uint32_t type; /* sd or mmc card */
uint32_t version; /* version */
uint32_t block_len; /* block length */
uint32_t bus_freq; /* sdhc bus frequency */
uint16_t rca; /* relative card address */
uint8_t is_high_capacity; /* high capacity */
};
struct mmc {
struct esdhc_regs *esdhc_regs;
struct card_attributes card;
uint32_t block_len;
uint32_t voltages_caps; /* supported voltaes */
uint32_t dma_support; /* DMA support */
};
enum cntrl_num {
SDHC1 = 0,
SDHC2
};
int sd_emmc_init(uintptr_t *block_dev_spec,
uintptr_t nxp_esdhc_addr,
size_t nxp_sd_block_offset,
size_t nxp_sd_block_size,
bool card_detect);
int esdhc_emmc_init(struct mmc *mmc, bool card_detect);
int esdhc_read(struct mmc *mmc, uint32_t src_offset, uintptr_t dst,
size_t size);
int esdhc_write(struct mmc *mmc, uintptr_t src, uint32_t dst_offset,
size_t size);
#ifdef NXP_ESDHC_BE
#define esdhc_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
#define esdhc_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
#elif defined(NXP_ESDHC_LE)
#define esdhc_in32(a) mmio_read_32((uintptr_t)(a))
#define esdhc_out32(a, v) mmio_write_32((uintptr_t)(a), (v))
#else
#error Please define CCSR ESDHC register endianness
#endif
#endif /*SD_MMC_H*/
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/sec_mon/snvs.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef SNVS_H
#define SNVS_H
#ifndef __ASSEMBLER__
#include <endian.h>
#include <stdbool.h>
#include <lib/mmio.h>
struct snvs_regs {
uint32_t reserved1;
uint32_t hp_com; /* 0x04 SNVS_HP Command Register */
uint32_t reserved2[3];
uint32_t hp_stat; /* 0x14 SNVS_HP Status Register */
};
#ifdef NXP_SNVS_BE
#define snvs_read32(a) bswap32(mmio_read_32((uintptr_t)(a)))
#define snvs_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32((v)))
#elif defined(NXP_SNVS_LE)
#define snvs_read32(a) mmio_read_32((uintptr_t)(a))
#define snvs_write32(a, v) mmio_write_32((uintptr_t)(a), (v))
#else
#error Please define CCSR SNVS register endianness
#endif
void snvs_init(uintptr_t nxp_snvs_addr);
uint32_t get_snvs_state(void);
void transition_snvs_non_secure(void);
void transition_snvs_soft_fail(void);
uint32_t transition_snvs_trusted(void);
uint32_t transition_snvs_secure(void);
uint32_t snvs_read_lp_gpr_bit(uint32_t offset, uint32_t bit_pos);
void snvs_write_lp_gpr_bit(uint32_t offset, uint32_t bit_pos, bool flag_val);
void snvs_disable_zeroize_lp_gpr(void);
#if defined(NXP_NV_SW_MAINT_LAST_EXEC_DATA) && defined(NXP_COINED_BB)
uint32_t snvs_read_app_data(void);
uint32_t snvs_read_app_data_bit(uint32_t bit_pos);
void snvs_clear_app_data(void);
void snvs_write_app_data_bit(uint32_t bit_pos);
#endif
#endif /* __ASSEMBLER__ */
/* SSM_ST field in SNVS status reg */
#define HPSTS_CHECK_SSM_ST 0x900 /* SNVS is in check state */
#define HPSTS_NON_SECURE_SSM_ST 0xb00 /* SNVS is in non secure state */
#define HPSTS_TRUST_SSM_ST 0xd00 /* SNVS is in trusted state */
#define HPSTS_SECURE_SSM_ST 0xf00 /* SNVS is in secure state */
#define HPSTS_SOFT_FAIL_SSM_ST 0x300 /* SNVS is in soft fail state */
#define HPSTS_MASK_SSM_ST 0xf00 /* SSM_ST field mask in SNVS reg */
/* SNVS register bits */
#define HPCOM_SW_SV 0x100 /* Security Violation bit */
#define HPCOM_SW_FSV 0x200 /* Fatal Security Violation bit */
#define HPCOM_SSM_ST 0x1 /* SSM_ST field in SNVS command reg */
#define HPCOM_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */
#define HPCOM_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */
#define NXP_LP_GPR0_OFFSET 0x90
#define NXP_LPCR_OFFSET 0x38
#define NXP_GPR_Z_DIS_BIT 24
#ifdef NXP_COINED_BB
#ifndef NXP_APP_DATA_LP_GPR_OFFSET
#define NXP_APP_DATA_LP_GPR_OFFSET NXP_LP_GPR0_OFFSET
#endif
#define NXP_LPGPR_ZEROTH_BIT 0
#endif /* NXP_COINED_BB */
#endif /* SNVS_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/sfp/fuse_prov.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#if !defined(FUSE_PROV_H) && defined(POLICY_FUSE_PROVISION)
#define FUSE_PROV_H
#include <endian.h>
#include <lib/mmio.h>
#define MASK_NONE U(0xFFFFFFFF)
#define ERROR_WRITE U(0xA)
#define ERROR_ALREADY_BLOWN U(0xB)
/* Flag bit shifts */
#define FLAG_POVDD_SHIFT U(0)
#define FLAG_SYSCFG_SHIFT U(1)
#define FLAG_SRKH_SHIFT U(2)
#define FLAG_MC_SHIFT U(3)
#define FLAG_DCV0_SHIFT U(4)
#define FLAG_DCV1_SHIFT U(5)
#define FLAG_DRV0_SHIFT U(6)
#define FLAG_DRV1_SHIFT U(7)
#define FLAG_OUID0_SHIFT U(8)
#define FLAG_OUID1_SHIFT U(9)
#define FLAG_OUID2_SHIFT U(10)
#define FLAG_OUID3_SHIFT U(11)
#define FLAG_OUID4_SHIFT U(12)
#define FLAG_DBG_LVL_SHIFT U(13)
#define FLAG_OTPMK_SHIFT U(16)
#define FLAG_OUID_MASK U(0x1F)
#define FLAG_DEBUG_MASK U(0xF)
#define FLAG_OTPMK_MASK U(0xF)
/* OTPMK flag values */
#define PROG_OTPMK_MIN U(0x0)
#define PROG_OTPMK_RANDOM U(0x1)
#define PROG_OTPMK_USER U(0x2)
#define PROG_OTPMK_RANDOM_MIN U(0x5)
#define PROG_OTPMK_USER_MIN U(0x6)
#define PROG_NO_OTPMK U(0x8)
#define OTPMK_MIM_BITS_MASK U(0xF0000000)
/* System configuration bit shifts */
#define SCB_WP_SHIFT U(0)
#define SCB_ITS_SHIFT U(2)
#define SCB_NSEC_SHIFT U(4)
#define SCB_ZD_SHIFT U(5)
#define SCB_K0_SHIFT U(15)
#define SCB_K1_SHIFT U(14)
#define SCB_K2_SHIFT U(13)
#define SCB_K3_SHIFT U(12)
#define SCB_K4_SHIFT U(11)
#define SCB_K5_SHIFT U(10)
#define SCB_K6_SHIFT U(9)
#define SCB_FR0_SHIFT U(30)
#define SCB_FR1_SHIFT U(31)
/* Fuse Header Structure */
struct fuse_hdr_t {
uint8_t barker[4]; /* 0x00 Barker code */
uint32_t flags; /* 0x04 Script flags */
uint32_t povdd_gpio; /* 0x08 GPIO for POVDD */
uint32_t otpmk[8]; /* 0x0C-0x2B OTPMK */
uint32_t srkh[8]; /* 0x2C-0x4B SRKH */
uint32_t oem_uid[5]; /* 0x4C-0x5F OEM unique id's */
uint32_t dcv[2]; /* 0x60-0x67 Debug Challenge */
uint32_t drv[2]; /* 0x68-0x6F Debug Response */
uint32_t ospr1; /* 0x70 OSPR1 */
uint32_t sc; /* 0x74 OSPR0 (System Configuration) */
uint32_t reserved[2]; /* 0x78-0x7F Reserved */
};
/* Function to do fuse provisioning */
int provision_fuses(unsigned long long fuse_scr_addr,
bool en_povdd_status);
#define EFUSE_POWERUP_DELAY_mSec U(25)
#endif /* FUSE_PROV_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/sfp/sfp.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef SFP_H
#define SFP_H
#include <endian.h>
#include <lib/mmio.h>
/* SFP Configuration Register Offsets */
#define SFP_INGR_OFFSET U(0x20)
#define SFP_SVHESR_OFFSET U(0x24)
#define SFP_SFPCR_OFFSET U(0x28)
#define SFP_VER_OFFSET U(0x38)
/* SFP Hamming register masks for OTPMK and DRV */
#define SFP_SVHESR_DRV_MASK U(0x7F)
#define SFP_SVHESR_OTPMK_MASK U(0x7FC00)
/* SFP commands */
#define SFP_INGR_READFB_CMD U(0x1)
#define SFP_INGR_PROGFB_CMD U(0x2)
#define SFP_INGR_ERROR_MASK U(0x100)
/* SFPCR Masks */
#define SFP_SFPCR_WD U(0x80000000)
#define SFP_SFPCR_WDL U(0x40000000)
/* SFPCR Masks */
#define SFP_SFPCR_WD U(0x80000000)
#define SFP_SFPCR_WDL U(0x40000000)
#define SFP_FUSE_REGS_OFFSET U(0x200)
#ifdef NXP_SFP_VER_3_4
#define OSPR0_SC_MASK U(0xC000FE35)
#elif defined(NXP_SFP_VER_3_2)
#define OSPR0_SC_MASK U(0x0000E035)
#endif
#if defined(NXP_SFP_VER_3_4)
#define OSPR_KEY_REVOC_SHIFT U(9)
#define OSPR_KEY_REVOC_MASK U(0x0000fe00)
#elif defined(NXP_SFP_VER_3_2)
#define OSPR_KEY_REVOC_SHIFT U(13)
#define OSPR_KEY_REVOC_MASK U(0x0000e000)
#endif /* NXP_SFP_VER_3_4 */
#define OSPR1_MC_MASK U(0xFFFF0000)
#define OSPR1_DBG_LVL_MASK U(0x00000007)
#define OSPR_ITS_MASK U(0x00000004)
#define OSPR_WP_MASK U(0x00000001)
#define MAX_OEM_UID U(5)
#define SRK_HASH_SIZE U(32)
/* SFP CCSR Register Map */
struct sfp_ccsr_regs_t {
uint32_t ospr; /* 0x200 OSPR0 */
uint32_t ospr1; /* 0x204 OSPR1 */
uint32_t dcv[2]; /* 0x208 Debug Challenge Value */
uint32_t drv[2]; /* 0x210 Debug Response Value */
uint32_t fswpr; /* 0x218 FSL Section Write Protect */
uint32_t fsl_uid[2]; /* 0x21c FSL UID 0 */
uint32_t isbcr; /* 0x224 ISBC Configuration */
uint32_t fsspr[3]; /* 0x228 FSL Scratch Pad */
uint32_t otpmk[8]; /* 0x234 OTPMK */
uint32_t srk_hash[SRK_HASH_SIZE/sizeof(uint32_t)];
/* 0x254 Super Root Key Hash */
uint32_t oem_uid[MAX_OEM_UID]; /* 0x274 OEM UID 0 */
};
uintptr_t get_sfp_addr(void);
void sfp_init(uintptr_t nxp_sfp_addr);
uint32_t *get_sfp_srk_hash(void);
int sfp_check_its(void);
int sfp_check_oem_wp(void);
uint32_t get_key_revoc(void);
void set_sfp_wr_disable(void);
int sfp_program_fuses(void);
uint32_t sfp_read_oem_uid(uint8_t oem_uid);
uint32_t sfp_write_oem_uid(uint8_t oem_uid, uint32_t sfp_val);
#ifdef NXP_SFP_BE
#define sfp_read32(a) bswap32(mmio_read_32((uintptr_t)(a)))
#define sfp_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
#elif defined(NXP_SFP_LE)
#define sfp_read32(a) mmio_read_32((uintptr_t)(a))
#define sfp_write32(a, v) mmio_write_32((uintptr_t)(a), (v))
#else
#error Please define CCSR SFP register endianness
#endif
#endif/* SFP_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/sfp/sfp_error_codes.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef SFP_ERROR_CODES_H
#define SFP_ERROR_CODES_H
/* Error codes */
#define ERROR_FUSE_BARKER 0x1
#define ERROR_READFB_CMD 0x2
#define ERROR_PROGFB_CMD 0x3
#define ERROR_SRKH_ALREADY_BLOWN 0x4
#define ERROR_SRKH_WRITE 0x5
#define ERROR_OEMUID_ALREADY_BLOWN 0x6
#define ERROR_OEMUID_WRITE 0x7
#define ERROR_DCV_ALREADY_BLOWN 0x8
#define ERROR_DCV_WRITE 0x9
#define ERROR_DRV_ALREADY_BLOWN 0xa
#define ERROR_DRV_HAMMING_ERROR 0xb
#define ERROR_DRV_WRITE 0x18
#define ERROR_OTPMK_ALREADY_BLOWN 0xc
#define ERROR_OTPMK_HAMMING_ERROR 0xd
#define ERROR_OTPMK_USER_MIN 0xe
#define ERROR_OSPR1_ALREADY_BLOWN 0xf
#define ERROR_OSPR1_WRITE 0x10
#define ERROR_SC_ALREADY_BLOWN 0x11
#define ERROR_SC_WRITE 0x12
#define ERROR_POVDD_GPIO_FAIL 0x13
#define ERROR_GPIO_SET_FAIL 0x14
#define ERROR_GPIO_RESET_FAIL 0x15
#define ERROR_OTPMK_SEC_DISABLED 0x16
#define ERROR_OTPMK_SEC_ERROR 0x17
#define ERROR_OTPMK_WRITE 0x19
#define PLAT_ERROR_ENABLE_POVDD 0x20
#define PLAT_ERROR_DISABLE_POVDD 0x21
#endif /* SFP_ERROR_CODES_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/smmu/nxp_smmu.h
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/*
* Copyright 2018-2020 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef NXP_SMMU_H
#define NXP_SMMU_H
#define SMMU_SCR0 (0x0)
#define SMMU_NSCR0 (0x400)
#define SMMU_SACR (0x10)
#define SCR0_CLIENTPD_MASK 0x00000001
#define SCR0_USFCFG_MASK 0x00000400
#define SMMU_SACR_CACHE_LOCK_ENABLE_BIT (1ULL << 26U)
static inline void bypass_smmu(uintptr_t smmu_base_addr)
{
uint32_t val;
val = (mmio_read_32(smmu_base_addr + SMMU_SCR0) | SCR0_CLIENTPD_MASK) &
~(SCR0_USFCFG_MASK);
mmio_write_32((smmu_base_addr + SMMU_SCR0), val);
val = (mmio_read_32(smmu_base_addr + SMMU_NSCR0) | SCR0_CLIENTPD_MASK) &
~(SCR0_USFCFG_MASK);
mmio_write_32((smmu_base_addr + SMMU_NSCR0), val);
}
static inline void smmu_cache_unlock(uintptr_t smmu_base_addr)
{
uint32_t val;
val = mmio_read_32((smmu_base_addr + SMMU_SACR));
val &= (uint32_t)~SMMU_SACR_CACHE_LOCK_ENABLE_BIT;
mmio_write_32((smmu_base_addr + SMMU_SACR), val);
}
#endif
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/timer/nxp_timer.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#
#ifndef NXP_TIMER_H
#define NXP_TIMER_H
/* System Counter Offset and Bit Mask */
#define SYS_COUNTER_CNTCR_OFFSET 0x0
#define SYS_COUNTER_CNTCR_EN 0x00000001
#define CNTCR_EN_MASK 0x1
#ifndef __ASSEMBLER__
uint64_t get_timer_val(uint64_t start);
#ifdef IMAGE_BL31
void ls_configure_sys_timer(uintptr_t ls_sys_timctl_base,
uint8_t ls_config_cntacr,
uint8_t plat_ls_ns_timer_frame_id);
void enable_init_timer(void);
#endif
/*
* Initialise the nxp on-chip free rolling usec counter as the delay
* timer.
*/
void delay_timer_init(uintptr_t nxp_timer_addr);
void ls_bl31_timer_init(uintptr_t nxp_timer_addr);
#endif /* __ASSEMBLER__ */
#endif /* NXP_TIMER_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/tzc/plat_tzc380.h
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/*
* Copyright 2018-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#if !defined(PLAT_TZC380_H) && defined(IMAGE_BL2)
#define PLAT_TZC380_H
#include <tzc380.h>
/* Number of DRAM regions to be configured
* for the platform can be over-written.
*
* Array tzc400_reg_list too, needs be over-written
* if there is any changes to default DRAM region
* configuration.
*/
#ifndef MAX_NUM_TZC_REGION
/* 3 regions:
* Region 0(default),
* Region 1 (DRAM0, Secure Memory),
* Region 2 (DRAM0, Shared memory)
*/
#define MAX_NUM_TZC_REGION 3
#define DEFAULT_TZASC_CONFIG 1
#endif
struct tzc380_reg {
unsigned int secure;
unsigned int enabled;
uint64_t addr;
uint64_t size;
unsigned int sub_mask;
};
void mem_access_setup(uintptr_t base, uint32_t total_regions,
struct tzc380_reg *tzc380_reg_list);
int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list,
int dram_idx, int list_idx,
uint64_t dram_start_addr,
uint64_t dram_size,
uint32_t secure_dram_sz,
uint32_t shrd_dram_sz);
#endif /* PLAT_TZC380_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/nxp/tzc/plat_tzc400.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#if !defined(PLAT_TZC400_H) && defined(IMAGE_BL2)
#define PLAT_TZC400_H
#include <tzc400.h>
/* Structure to configure TZC Regions' boundaries and attributes. */
struct tzc400_reg {
uint8_t reg_filter_en;
unsigned long long start_addr;
unsigned long long end_addr;
unsigned int sec_attr;
unsigned int nsaid_permissions;
};
#define TZC_REGION_NS_NONE 0x00000000U
/* NXP Platforms do not support NS Access ID (NSAID) based non-secure access.
* Supports only non secure through generic NS ACCESS ID
*/
#define TZC_NS_ACCESS_ID 0xFFFFFFFFU
/* Number of DRAM regions to be configured
* for the platform can be over-written.
*
* Array tzc400_reg_list too, needs be over-written
* if there is any changes to default DRAM region
* configuration.
*/
#ifndef MAX_NUM_TZC_REGION
/* 3 regions:
* Region 0(default),
* Region 1 (DRAM0, Secure Memory),
* Region 2 (DRAM0, Shared memory)
*/
#define MAX_NUM_TZC_REGION NUM_DRAM_REGIONS + 3
#define DEFAULT_TZASC_CONFIG 1
#endif
void mem_access_setup(uintptr_t base, uint32_t total_regions,
struct tzc400_reg *tzc400_reg_list);
int populate_tzc400_reg_list(struct tzc400_reg *tzc400_reg_list,
int dram_idx, int list_idx,
uint64_t dram_start_addr,
uint64_t dram_size,
uint32_t secure_dram_sz,
uint32_t shrd_dram_sz);
#endif /* PLAT_TZC400_H */