GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#if !defined(FUSE_PROV_H) && defined(POLICY_FUSE_PROVISION)
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#define FUSE_PROV_H
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#include <endian.h>
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#include <lib/mmio.h>
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#define MASK_NONE U(0xFFFFFFFF)
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#define ERROR_WRITE U(0xA)
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#define ERROR_ALREADY_BLOWN U(0xB)
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/* Flag bit shifts */
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#define FLAG_POVDD_SHIFT U(0)
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#define FLAG_SYSCFG_SHIFT U(1)
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#define FLAG_SRKH_SHIFT U(2)
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#define FLAG_MC_SHIFT U(3)
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#define FLAG_DCV0_SHIFT U(4)
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#define FLAG_DCV1_SHIFT U(5)
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#define FLAG_DRV0_SHIFT U(6)
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#define FLAG_DRV1_SHIFT U(7)
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#define FLAG_OUID0_SHIFT U(8)
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#define FLAG_OUID1_SHIFT U(9)
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#define FLAG_OUID2_SHIFT U(10)
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#define FLAG_OUID3_SHIFT U(11)
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#define FLAG_OUID4_SHIFT U(12)
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#define FLAG_DBG_LVL_SHIFT U(13)
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#define FLAG_OTPMK_SHIFT U(16)
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#define FLAG_OUID_MASK U(0x1F)
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#define FLAG_DEBUG_MASK U(0xF)
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#define FLAG_OTPMK_MASK U(0xF)
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/* OTPMK flag values */
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#define PROG_OTPMK_MIN U(0x0)
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#define PROG_OTPMK_RANDOM U(0x1)
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#define PROG_OTPMK_USER U(0x2)
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#define PROG_OTPMK_RANDOM_MIN U(0x5)
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#define PROG_OTPMK_USER_MIN U(0x6)
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#define PROG_NO_OTPMK U(0x8)
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#define OTPMK_MIM_BITS_MASK U(0xF0000000)
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/* System configuration bit shifts */
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#define SCB_WP_SHIFT U(0)
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#define SCB_ITS_SHIFT U(2)
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#define SCB_NSEC_SHIFT U(4)
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#define SCB_ZD_SHIFT U(5)
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#define SCB_K0_SHIFT U(15)
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#define SCB_K1_SHIFT U(14)
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#define SCB_K2_SHIFT U(13)
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#define SCB_K3_SHIFT U(12)
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#define SCB_K4_SHIFT U(11)
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#define SCB_K5_SHIFT U(10)
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#define SCB_K6_SHIFT U(9)
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#define SCB_FR0_SHIFT U(30)
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#define SCB_FR1_SHIFT U(31)
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/* Fuse Header Structure */
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struct fuse_hdr_t {
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uint8_t barker[4]; /* 0x00 Barker code */
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uint32_t flags; /* 0x04 Script flags */
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uint32_t povdd_gpio; /* 0x08 GPIO for POVDD */
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uint32_t otpmk[8]; /* 0x0C-0x2B OTPMK */
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uint32_t srkh[8]; /* 0x2C-0x4B SRKH */
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uint32_t oem_uid[5]; /* 0x4C-0x5F OEM unique id's */
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uint32_t dcv[2]; /* 0x60-0x67 Debug Challenge */
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uint32_t drv[2]; /* 0x68-0x6F Debug Response */
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uint32_t ospr1; /* 0x70 OSPR1 */
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uint32_t sc; /* 0x74 OSPR0 (System Configuration) */
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uint32_t reserved[2]; /* 0x78-0x7F Reserved */
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};
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/* Function to do fuse provisioning */
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int provision_fuses(unsigned long long fuse_scr_addr,
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bool en_povdd_status);
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#define EFUSE_POWERUP_DELAY_mSec U(25)
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#endif /* FUSE_PROV_H */
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef SFP_H
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#define SFP_H
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#include <endian.h>
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#include <lib/mmio.h>
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/* SFP Configuration Register Offsets */
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#define SFP_INGR_OFFSET U(0x20)
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#define SFP_SVHESR_OFFSET U(0x24)
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#define SFP_SFPCR_OFFSET U(0x28)
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#define SFP_VER_OFFSET U(0x38)
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/* SFP Hamming register masks for OTPMK and DRV */
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#define SFP_SVHESR_DRV_MASK U(0x7F)
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#define SFP_SVHESR_OTPMK_MASK U(0x7FC00)
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/* SFP commands */
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#define SFP_INGR_READFB_CMD U(0x1)
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#define SFP_INGR_PROGFB_CMD U(0x2)
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#define SFP_INGR_ERROR_MASK U(0x100)
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/* SFPCR Masks */
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#define SFP_SFPCR_WD U(0x80000000)
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#define SFP_SFPCR_WDL U(0x40000000)
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/* SFPCR Masks */
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#define SFP_SFPCR_WD U(0x80000000)
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#define SFP_SFPCR_WDL U(0x40000000)
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#define SFP_FUSE_REGS_OFFSET U(0x200)
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#ifdef NXP_SFP_VER_3_4
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#define OSPR0_SC_MASK U(0xC000FE35)
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#elif defined(NXP_SFP_VER_3_2)
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#define OSPR0_SC_MASK U(0x0000E035)
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#endif
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#if defined(NXP_SFP_VER_3_4)
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#define OSPR_KEY_REVOC_SHIFT U(9)
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#define OSPR_KEY_REVOC_MASK U(0x0000fe00)
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#elif defined(NXP_SFP_VER_3_2)
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#define OSPR_KEY_REVOC_SHIFT U(13)
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#define OSPR_KEY_REVOC_MASK U(0x0000e000)
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#endif /* NXP_SFP_VER_3_4 */
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#define OSPR1_MC_MASK U(0xFFFF0000)
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#define OSPR1_DBG_LVL_MASK U(0x00000007)
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#define OSPR_ITS_MASK U(0x00000004)
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#define OSPR_WP_MASK U(0x00000001)
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#define MAX_OEM_UID U(5)
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#define SRK_HASH_SIZE U(32)
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/* SFP CCSR Register Map */
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struct sfp_ccsr_regs_t {
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uint32_t ospr; /* 0x200 OSPR0 */
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uint32_t ospr1; /* 0x204 OSPR1 */
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uint32_t dcv[2]; /* 0x208 Debug Challenge Value */
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uint32_t drv[2]; /* 0x210 Debug Response Value */
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uint32_t fswpr; /* 0x218 FSL Section Write Protect */
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uint32_t fsl_uid[2]; /* 0x21c FSL UID 0 */
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uint32_t isbcr; /* 0x224 ISBC Configuration */
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uint32_t fsspr[3]; /* 0x228 FSL Scratch Pad */
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uint32_t otpmk[8]; /* 0x234 OTPMK */
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uint32_t srk_hash[SRK_HASH_SIZE/sizeof(uint32_t)];
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/* 0x254 Super Root Key Hash */
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uint32_t oem_uid[MAX_OEM_UID]; /* 0x274 OEM UID 0 */
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};
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uintptr_t get_sfp_addr(void);
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void sfp_init(uintptr_t nxp_sfp_addr);
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uint32_t *get_sfp_srk_hash(void);
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int sfp_check_its(void);
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int sfp_check_oem_wp(void);
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uint32_t get_key_revoc(void);
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void set_sfp_wr_disable(void);
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int sfp_program_fuses(void);
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uint32_t sfp_read_oem_uid(uint8_t oem_uid);
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uint32_t sfp_write_oem_uid(uint8_t oem_uid, uint32_t sfp_val);
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#ifdef NXP_SFP_BE
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#define sfp_read32(a) bswap32(mmio_read_32((uintptr_t)(a)))
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#define sfp_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
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#elif defined(NXP_SFP_LE)
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#define sfp_read32(a) mmio_read_32((uintptr_t)(a))
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#define sfp_write32(a, v) mmio_write_32((uintptr_t)(a), (v))
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#else
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#error Please define CCSR SFP register endianness
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#endif
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#endif/* SFP_H */
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+40
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef SFP_ERROR_CODES_H
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#define SFP_ERROR_CODES_H
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/* Error codes */
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#define ERROR_FUSE_BARKER 0x1
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#define ERROR_READFB_CMD 0x2
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#define ERROR_PROGFB_CMD 0x3
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#define ERROR_SRKH_ALREADY_BLOWN 0x4
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#define ERROR_SRKH_WRITE 0x5
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#define ERROR_OEMUID_ALREADY_BLOWN 0x6
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#define ERROR_OEMUID_WRITE 0x7
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#define ERROR_DCV_ALREADY_BLOWN 0x8
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#define ERROR_DCV_WRITE 0x9
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#define ERROR_DRV_ALREADY_BLOWN 0xa
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#define ERROR_DRV_HAMMING_ERROR 0xb
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#define ERROR_DRV_WRITE 0x18
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#define ERROR_OTPMK_ALREADY_BLOWN 0xc
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#define ERROR_OTPMK_HAMMING_ERROR 0xd
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#define ERROR_OTPMK_USER_MIN 0xe
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#define ERROR_OSPR1_ALREADY_BLOWN 0xf
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#define ERROR_OSPR1_WRITE 0x10
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#define ERROR_SC_ALREADY_BLOWN 0x11
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#define ERROR_SC_WRITE 0x12
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#define ERROR_POVDD_GPIO_FAIL 0x13
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#define ERROR_GPIO_SET_FAIL 0x14
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#define ERROR_GPIO_RESET_FAIL 0x15
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#define ERROR_OTPMK_SEC_DISABLED 0x16
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#define ERROR_OTPMK_SEC_ERROR 0x17
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#define ERROR_OTPMK_WRITE 0x19
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#define PLAT_ERROR_ENABLE_POVDD 0x20
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#define PLAT_ERROR_DISABLE_POVDD 0x21
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#endif /* SFP_ERROR_CODES_H */
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