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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
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source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/bsec.h
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/*
* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BSEC_H
#define BSEC_H
#include <stdbool.h>
#include <stdint.h>
#include <lib/utils_def.h>
/*
* IP configuration
*/
#define BSEC_OTP_MASK GENMASK(4, 0)
#define BSEC_OTP_BANK_SHIFT 5
#define BSEC_TIMEOUT_VALUE 0xFFFF
/*
* Return status
*/
#define BSEC_OK 0U
#define BSEC_ERROR 0xFFFFFFFFU
#define BSEC_DISTURBED 0xFFFFFFFEU
#define BSEC_INVALID_PARAM 0xFFFFFFFCU
#define BSEC_PROG_FAIL 0xFFFFFFFBU
#define BSEC_LOCK_FAIL 0xFFFFFFFAU
#define BSEC_TIMEOUT 0xFFFFFFF9U
#define BSEC_RETRY 0xFFFFFFF8U
#define BSEC_NOT_SUPPORTED 0xFFFFFFF7U
#define BSEC_WRITE_LOCKED 0xFFFFFFF6U
#define BSEC_ERROR_INVALID_FVR 0xFFFFFFF5U
/*
* OTP MODE
*/
#define BSEC_MODE_OPEN1 0x00U
#define BSEC_MODE_SECURED 0x01U
#define BSEC_MODE_OPEN2 0x02U
#define BSEC_MODE_INVALID 0x04U
/*
* OTP Lock services definition.
* Value must corresponding to the bit number in the register.
* Special case: (bit number << 1) for BSEC3.
*/
#define BSEC_LOCK_UPPER_OTP 0x00
#define BSEC_LOCK_GWLOCK 0x01
#define BSEC_LOCK_DEBUG 0x02
#define BSEC_LOCK_PROGRAM 0x03
#define BSEC_LOCK_KVLOCK 0x04
/*
* Values for struct bsec_config::freq
*/
#define FREQ_10_20_MHZ 0x0
#define FREQ_20_30_MHZ 0x1
#define FREQ_30_45_MHZ 0x2
#define FREQ_45_67_MHZ 0x3
/*
* Device info structure, providing device-specific functions and a means of
* adding driver-specific state.
*/
struct bsec_config {
uint8_t den_lock; /*
* Debug enable sticky lock
* 1 debug enable is locked until next reset
*/
/* BSEC2 only */
uint8_t tread; /* SAFMEM Reading current level default 0 */
uint8_t pulse_width; /* SAFMEM Programming pulse width default 1 */
uint8_t freq; /*
* SAFMEM CLOCK see freq value define
* default FREQ_45_67_MHZ
*/
uint8_t power; /* Power up SAFMEM. 1 power up, 0 power off */
uint8_t prog_lock; /*
* Programming Sticky lock
* 1 programming is locked until next reset
*/
uint8_t upper_otp_lock; /*
* Shadowing of upper OTP sticky lock
* 1 shadowing of upper OTP is locked
* until next reset
*/
};
uint32_t bsec_probe(void);
uint32_t bsec_get_base(void);
uint32_t bsec_set_config(struct bsec_config *cfg);
uint32_t bsec_get_config(struct bsec_config *cfg);
uint32_t bsec_shadow_register(uint32_t otp);
uint32_t bsec_read_otp(uint32_t *val, uint32_t otp);
uint32_t bsec_write_otp(uint32_t val, uint32_t otp);
uint32_t bsec_program_otp(uint32_t val, uint32_t otp);
uint32_t bsec_permanent_lock_otp(uint32_t otp);
void bsec_write_debug_conf(uint32_t val);
uint32_t bsec_read_debug_conf(void);
void bsec_write_scratch(uint32_t val);
uint32_t bsec_read_scratch(void);
uint32_t bsec_get_status(void);
uint32_t bsec_get_hw_conf(void);
uint32_t bsec_get_version(void);
uint32_t bsec_get_id(void);
uint32_t bsec_get_magic_id(void);
uint32_t bsec_set_sr_lock(uint32_t otp);
uint32_t bsec_read_sr_lock(uint32_t otp, bool *value);
uint32_t bsec_set_sw_lock(uint32_t otp);
uint32_t bsec_read_sw_lock(uint32_t otp, bool *value);
uint32_t bsec_set_sp_lock(uint32_t otp);
uint32_t bsec_read_sp_lock(uint32_t otp, bool *value);
uint32_t bsec_read_permanent_lock(uint32_t otp, bool *value);
uint32_t bsec_otp_lock(uint32_t service);
uint32_t bsec_shadow_read_otp(uint32_t *otp_value, uint32_t word);
uint32_t bsec_check_nsec_access_rights(uint32_t otp);
#endif /* BSEC_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/bsec2_reg.h
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/*
* Copyright (c) 2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BSEC2_REG_H
#define BSEC2_REG_H
#include <lib/utils_def.h>
/* IP configuration */
#define ADDR_LOWER_OTP_PERLOCK_SHIFT 0x03
#define DATA_LOWER_OTP_PERLOCK_BIT 0x03U /* 2 significants bits are used */
#define DATA_LOWER_OTP_PERLOCK_MASK GENMASK(2, 0)
#define ADDR_UPPER_OTP_PERLOCK_SHIFT 0x04
#define DATA_UPPER_OTP_PERLOCK_BIT 0x01U /* 1 significants bits are used */
#define DATA_UPPER_OTP_PERLOCK_MASK GENMASK(3, 0)
/* BSEC REGISTER OFFSET (base relative) */
#define BSEC_OTP_CONF_OFF U(0x000)
#define BSEC_OTP_CTRL_OFF U(0x004)
#define BSEC_OTP_WRDATA_OFF U(0x008)
#define BSEC_OTP_STATUS_OFF U(0x00C)
#define BSEC_OTP_LOCK_OFF U(0x010)
#define BSEC_DEN_OFF U(0x014)
#define BSEC_DISTURBED_OFF U(0x01C)
#define BSEC_DISTURBED1_OFF U(0x020)
#define BSEC_DISTURBED2_OFF U(0x024)
#define BSEC_ERROR_OFF U(0x034)
#define BSEC_ERROR1_OFF U(0x038)
#define BSEC_ERROR2_OFF U(0x03C)
#define BSEC_WRLOCK_OFF U(0x04C) /* Safmem permanent lock */
#define BSEC_WRLOCK1_OFF U(0x050)
#define BSEC_WRLOCK2_OFF U(0x054)
#define BSEC_SPLOCK_OFF U(0x064) /* Program safmem sticky lock */
#define BSEC_SPLOCK1_OFF U(0x068)
#define BSEC_SPLOCK2_OFF U(0x06C)
#define BSEC_SWLOCK_OFF U(0x07C) /* Write in OTP sticky lock */
#define BSEC_SWLOCK1_OFF U(0x080)
#define BSEC_SWLOCK2_OFF U(0x084)
#define BSEC_SRLOCK_OFF U(0x094) /* Shadowing sticky lock */
#define BSEC_SRLOCK1_OFF U(0x098)
#define BSEC_SRLOCK2_OFF U(0x09C)
#define BSEC_JTAG_IN_OFF U(0x0AC)
#define BSEC_JTAG_OUT_OFF U(0x0B0)
#define BSEC_SCRATCH_OFF U(0x0B4)
#define BSEC_OTP_DATA_OFF U(0x200)
#define BSEC_IPHW_CFG_OFF U(0xFF0)
#define BSEC_IPVR_OFF U(0xFF4)
#define BSEC_IP_ID_OFF U(0xFF8)
#define BSEC_IP_MAGIC_ID_OFF U(0xFFC)
#define BSEC_WRLOCK(n) (BSEC_WRLOCK_OFF + U(0x04) * (n))
#define BSEC_SPLOCK(n) (BSEC_SPLOCK_OFF + U(0x04) * (n))
#define BSEC_SWLOCK(n) (BSEC_SWLOCK_OFF + U(0x04) * (n))
#define BSEC_SRLOCK(n) (BSEC_SRLOCK_OFF + U(0x04) * (n))
/* BSEC_CONFIGURATION Register */
#define BSEC_CONF_POWER_UP_MASK BIT(0)
#define BSEC_CONF_POWER_UP_SHIFT 0
#define BSEC_CONF_FRQ_MASK GENMASK(2, 1)
#define BSEC_CONF_FRQ_SHIFT 1
#define BSEC_CONF_PRG_WIDTH_MASK GENMASK(6, 3)
#define BSEC_CONF_PRG_WIDTH_SHIFT 3
#define BSEC_CONF_TREAD_MASK GENMASK(8, 7)
#define BSEC_CONF_TREAD_SHIFT 7
/* BSEC_CONTROL Register */
#define BSEC_READ 0U
#define BSEC_WRITE BIT(8)
#define BSEC_LOCK BIT(9)
/* BSEC_OTP_LOCK register */
#define UPPER_OTP_LOCK_MASK BIT(0)
#define UPPER_OTP_LOCK_SHIFT 0
#define DENREG_LOCK_MASK BIT(2)
#define DENREG_LOCK_SHIFT 2
#define GPLOCK_LOCK_MASK BIT(4)
#define GPLOCK_LOCK_SHIFT 4
/* BSEC_OTP_STATUS Register */
#define BSEC_MODE_STATUS_MASK GENMASK(2, 0)
#define BSEC_MODE_SECURE_MASK BIT(0)
#define BSEC_MODE_FULLDBG_MASK BIT(1)
#define BSEC_MODE_INVALID_MASK BIT(2)
#define BSEC_MODE_BUSY_MASK BIT(3)
#define BSEC_MODE_PROGFAIL_MASK BIT(4)
#define BSEC_MODE_PWR_MASK BIT(5)
#define BSEC_MODE_BIST1_LOCK_MASK BIT(6)
#define BSEC_MODE_BIST2_LOCK_MASK BIT(7)
/* BSEC_DENABLE Register */
#define BSEC_HDPEN BIT(4)
#define BSEC_SPIDEN BIT(5)
#define BSEC_SPINDEN BIT(6)
#define BSEC_DBGSWGEN BIT(10)
#define BSEC_DEN_ALL_MSK GENMASK(10, 0)
/* BSEC_FENABLE Register */
#define BSEC_FEN_ALL_MSK GENMASK(14, 0)
/* BSEC_IPVR Register */
#define BSEC_IPVR_MSK GENMASK(7, 0)
#endif /* BSEC2_REG_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/etzpc.h
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/*
* Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef DRIVERS_ST_ETZPC_H
#define DRIVERS_ST_ETZPC_H
#include <stdbool.h>
#include <stdint.h>
/* Define security level for each peripheral (DECPROT) */
enum etzpc_decprot_attributes {
ETZPC_DECPROT_S_RW = 0,
ETZPC_DECPROT_NS_R_S_W = 1,
ETZPC_DECPROT_MCU_ISOLATION = 2,
ETZPC_DECPROT_NS_RW = 3,
ETZPC_DECPROT_MAX = 4,
};
void etzpc_configure_decprot(uint32_t decprot_id,
enum etzpc_decprot_attributes decprot_attr);
enum etzpc_decprot_attributes etzpc_get_decprot(uint32_t decprot_id);
void etzpc_lock_decprot(uint32_t decprot_id);
void etzpc_configure_tzma(uint32_t tzma_id, uint16_t tzma_value);
uint16_t etzpc_get_tzma(uint32_t tzma_id);
void etzpc_lock_tzma(uint32_t tzma_id);
bool etzpc_get_lock_tzma(uint32_t tzma_id);
uint8_t etzpc_get_num_per_sec(void);
uint8_t etzpc_get_revision(void);
uintptr_t etzpc_get_base_address(void);
int etzpc_init(void);
#endif /* DRIVERS_ST_ETZPC_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/io_mmc.h
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/*
* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef IO_MMC_H
#define IO_MMC_H
#include <drivers/io/io_driver.h>
struct io_mmc_dev_spec {
bool use_boot_part;
};
int register_io_dev_mmc(const io_dev_connector_t **dev_con);
#endif /* IO_MMC_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/regulator.h
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/*
* Copyright (c) 2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef REGULATOR_H
#define REGULATOR_H
#include <platform_def.h>
#ifndef PLAT_NB_RDEVS
#error "Missing PLAT_NB_RDEVS"
#endif
/*
* Consumer interface
*/
/* regulator-always-on : regulator should never be disabled */
#define REGUL_ALWAYS_ON BIT(0)
/*
* regulator-boot-on:
* It's expected that this regulator was left on by the bootloader.
* The core shouldn't prevent it from being turned off later.
* The regulator is needed to exit from suspend so it is turned on during suspend entry.
*/
#define REGUL_BOOT_ON BIT(1)
/* regulator-over-current-protection: Enable over current protection. */
#define REGUL_OCP BIT(2)
/* regulator-active-discharge: enable active discharge. */
#define REGUL_ACTIVE_DISCHARGE BIT(3)
/* regulator-pull-down: Enable pull down resistor when the regulator is disabled. */
#define REGUL_PULL_DOWN BIT(4)
/*
* st,mask-reset: set mask reset for the regulator, meaning that the regulator
* setting is maintained during pmic reset.
*/
#define REGUL_MASK_RESET BIT(5)
/* st,regulator-sink-source: set the regulator in sink source mode */
#define REGUL_SINK_SOURCE BIT(6)
/* st,regulator-bypass: set the regulator in bypass mode */
#define REGUL_ENABLE_BYPASS BIT(7)
struct rdev *regulator_get_by_name(const char *node_name);
struct rdev *regulator_get_by_supply_name(const void *fdt, int node, const char *name);
int regulator_enable(struct rdev *rdev);
int regulator_disable(struct rdev *rdev);
int regulator_is_enabled(const struct rdev *rdev);
int regulator_set_voltage(struct rdev *rdev, uint16_t volt);
int regulator_set_min_voltage(struct rdev *rdev);
int regulator_get_voltage(const struct rdev *rdev);
int regulator_list_voltages(const struct rdev *rdev, const uint16_t **levels, size_t *count);
void regulator_get_range(const struct rdev *rdev, uint16_t *min_mv, uint16_t *max_mv);
int regulator_set_flag(struct rdev *rdev, uint16_t flag);
/*
* Driver Interface
*/
/* set_state() arguments */
#define STATE_DISABLE false
#define STATE_ENABLE true
struct regul_description {
const char *node_name;
const struct regul_ops *ops;
const void *driver_data;
const char *supply_name;
const uint32_t enable_ramp_delay;
};
struct regul_ops {
int (*set_state)(const struct regul_description *desc, bool state);
int (*get_state)(const struct regul_description *desc);
int (*set_voltage)(const struct regul_description *desc, uint16_t mv);
int (*get_voltage)(const struct regul_description *desc);
int (*list_voltages)(const struct regul_description *desc,
const uint16_t **levels, size_t *count);
int (*set_flag)(const struct regul_description *desc, uint16_t flag);
void (*lock)(const struct regul_description *desc);
void (*unlock)(const struct regul_description *desc);
};
int regulator_register(const struct regul_description *desc, int node);
/*
* Internal regulator structure
* The structure is internal to the core, and the content should not be used
* by a consumer nor a driver.
*/
struct rdev {
const struct regul_description *desc;
int32_t phandle;
uint16_t min_mv;
uint16_t max_mv;
uint16_t flags;
uint32_t enable_ramp_delay;
};
#endif /* REGULATOR_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/regulator_fixed.h
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/*
* Copyright (c) 2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef REGULATOR_FIXED_H
#define REGULATOR_FIXED_H
int fixed_regulator_register(void);
#endif /* REGULATOR_FIXED_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32_console.h
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/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32_CONSOLE_H
#define STM32_CONSOLE_H
#include <drivers/console.h>
#ifndef __ASSEMBLER__
#include <stdint.h>
/*
* Initialize a new STM32 console instance and register it with the console
* framework. The |console| pointer must point to storage that will be valid
* for the lifetime of the console, such as a global or static local variable.
* Its contents will be reinitialized from scratch.
*/
int console_stm32_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_t *console);
#endif /*__ASSEMBLER__*/
#endif /* STM32_CONSOLE_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32_fmc2_nand.h
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/*
* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
#ifndef STM32_FMC2_NAND_H
#define STM32_FMC2_NAND_H
int stm32_fmc2_init(void);
#endif /* STM32_FMC2_NAND_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32_gpio.h
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/*
* Copyright (c) 2015-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32_GPIO_H
#define STM32_GPIO_H
#include <lib/utils_def.h>
#define GPIO_MODE_OFFSET U(0x00)
#define GPIO_TYPE_OFFSET U(0x04)
#define GPIO_SPEED_OFFSET U(0x08)
#define GPIO_PUPD_OFFSET U(0x0C)
#define GPIO_OD_OFFSET U(0x14)
#define GPIO_BSRR_OFFSET U(0x18)
#define GPIO_AFRL_OFFSET U(0x20)
#define GPIO_AFRH_OFFSET U(0x24)
#define GPIO_SECR_OFFSET U(0x30)
#define GPIO_ALT_LOWER_LIMIT U(0x08)
#define GPIO_PIN_(_x) U(_x)
#define GPIO_PIN_MAX GPIO_PIN_(15)
#define GPIO_ALTERNATE_(_x) U(_x)
#define GPIO_ALTERNATE_MASK U(0x0F)
#define GPIO_MODE_INPUT U(0x00)
#define GPIO_MODE_OUTPUT U(0x01)
#define GPIO_MODE_ALTERNATE U(0x02)
#define GPIO_MODE_ANALOG U(0x03)
#define GPIO_MODE_MASK U(0x03)
#define GPIO_TYPE_PUSH_PULL U(0x00)
#define GPIO_TYPE_OPEN_DRAIN U(0x01)
#define GPIO_TYPE_MASK U(0x01)
#define GPIO_SPEED_LOW U(0x00)
#define GPIO_SPEED_MEDIUM U(0x01)
#define GPIO_SPEED_HIGH U(0x02)
#define GPIO_SPEED_VERY_HIGH U(0x03)
#define GPIO_SPEED_MASK U(0x03)
#define GPIO_NO_PULL U(0x00)
#define GPIO_PULL_UP U(0x01)
#define GPIO_PULL_DOWN U(0x02)
#define GPIO_PULL_MASK U(0x03)
#define GPIO_OD_OUTPUT_LOW U(0x00)
#define GPIO_OD_OUTPUT_HIGH U(0x01)
#define GPIO_OD_MASK U(0x01)
#ifndef __ASSEMBLER__
#include <stdint.h>
int dt_set_pinctrl_config(int node);
void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure);
void set_gpio_reset_cfg(uint32_t bank, uint32_t pin);
#endif /*__ASSEMBLER__*/
#endif /* STM32_GPIO_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32_hash.h
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/*
* Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32_HASH_H
#define STM32_HASH_H
#include <stdint.h>
enum stm32_hash_algo_mode {
#if STM32_HASH_VER == 2
HASH_MD5SUM,
#endif
HASH_SHA1,
HASH_SHA224,
HASH_SHA256,
#if STM32_HASH_VER == 4
HASH_SHA384,
HASH_SHA512,
#endif
};
int stm32_hash_update(const uint8_t *buffer, size_t length);
int stm32_hash_final(uint8_t *digest);
int stm32_hash_final_update(const uint8_t *buffer, uint32_t buf_length,
uint8_t *digest);
void stm32_hash_init(enum stm32_hash_algo_mode mode);
int stm32_hash_register(void);
#endif /* STM32_HASH_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32_i2c.h
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/*
* Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32_I2C_H
#define STM32_I2C_H
#include <stdint.h>
#include <lib/utils_def.h>
/* Bit definition for I2C_CR1 register */
#define I2C_CR1_PE BIT(0)
#define I2C_CR1_TXIE BIT(1)
#define I2C_CR1_RXIE BIT(2)
#define I2C_CR1_ADDRIE BIT(3)
#define I2C_CR1_NACKIE BIT(4)
#define I2C_CR1_STOPIE BIT(5)
#define I2C_CR1_TCIE BIT(6)
#define I2C_CR1_ERRIE BIT(7)
#define I2C_CR1_DNF GENMASK(11, 8)
#define I2C_CR1_ANFOFF BIT(12)
#define I2C_CR1_SWRST BIT(13)
#define I2C_CR1_TXDMAEN BIT(14)
#define I2C_CR1_RXDMAEN BIT(15)
#define I2C_CR1_SBC BIT(16)
#define I2C_CR1_NOSTRETCH BIT(17)
#define I2C_CR1_WUPEN BIT(18)
#define I2C_CR1_GCEN BIT(19)
#define I2C_CR1_SMBHEN BIT(22)
#define I2C_CR1_SMBDEN BIT(21)
#define I2C_CR1_ALERTEN BIT(22)
#define I2C_CR1_PECEN BIT(23)
/* Bit definition for I2C_CR2 register */
#define I2C_CR2_SADD GENMASK(9, 0)
#define I2C_CR2_RD_WRN BIT(10)
#define I2C_CR2_RD_WRN_OFFSET 10U
#define I2C_CR2_ADD10 BIT(11)
#define I2C_CR2_HEAD10R BIT(12)
#define I2C_CR2_START BIT(13)
#define I2C_CR2_STOP BIT(14)
#define I2C_CR2_NACK BIT(15)
#define I2C_CR2_NBYTES GENMASK(23, 16)
#define I2C_CR2_NBYTES_OFFSET 16U
#define I2C_CR2_RELOAD BIT(24)
#define I2C_CR2_AUTOEND BIT(25)
#define I2C_CR2_PECBYTE BIT(26)
/* Bit definition for I2C_OAR1 register */
#define I2C_OAR1_OA1 GENMASK(9, 0)
#define I2C_OAR1_OA1MODE BIT(10)
#define I2C_OAR1_OA1EN BIT(15)
/* Bit definition for I2C_OAR2 register */
#define I2C_OAR2_OA2 GENMASK(7, 1)
#define I2C_OAR2_OA2MSK GENMASK(10, 8)
#define I2C_OAR2_OA2NOMASK 0
#define I2C_OAR2_OA2MASK01 BIT(8)
#define I2C_OAR2_OA2MASK02 BIT(9)
#define I2C_OAR2_OA2MASK03 GENMASK(9, 8)
#define I2C_OAR2_OA2MASK04 BIT(10)
#define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10))
#define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10))
#define I2C_OAR2_OA2MASK07 GENMASK(10, 8)
#define I2C_OAR2_OA2EN BIT(15)
/* Bit definition for I2C_TIMINGR register */
#define I2C_TIMINGR_SCLL GENMASK(7, 0)
#define I2C_TIMINGR_SCLH GENMASK(15, 8)
#define I2C_TIMINGR_SDADEL GENMASK(19, 16)
#define I2C_TIMINGR_SCLDEL GENMASK(23, 20)
#define I2C_TIMINGR_PRESC GENMASK(31, 28)
/* Bit definition for I2C_TIMEOUTR register */
#define I2C_TIMEOUTR_TIMEOUTA GENMASK(11, 0)
#define I2C_TIMEOUTR_TIDLE BIT(12)
#define I2C_TIMEOUTR_TIMOUTEN BIT(15)
#define I2C_TIMEOUTR_TIMEOUTB GENMASK(27, 16)
#define I2C_TIMEOUTR_TEXTEN BIT(31)
/* Bit definition for I2C_ISR register */
#define I2C_ISR_TXE BIT(0)
#define I2C_ISR_TXIS BIT(1)
#define I2C_ISR_RXNE BIT(2)
#define I2C_ISR_ADDR BIT(3)
#define I2C_ISR_NACKF BIT(4)
#define I2C_ISR_STOPF BIT(5)
#define I2C_ISR_TC BIT(6)
#define I2C_ISR_TCR BIT(7)
#define I2C_ISR_BERR BIT(8)
#define I2C_ISR_ARLO BIT(9)
#define I2C_ISR_OVR BIT(10)
#define I2C_ISR_PECERR BIT(11)
#define I2C_ISR_TIMEOUT BIT(12)
#define I2C_ISR_ALERT BIT(13)
#define I2C_ISR_BUSY BIT(15)
#define I2C_ISR_DIR BIT(16)
#define I2C_ISR_ADDCODE GENMASK(23, 17)
/* Bit definition for I2C_ICR register */
#define I2C_ICR_ADDRCF BIT(3)
#define I2C_ICR_NACKCF BIT(4)
#define I2C_ICR_STOPCF BIT(5)
#define I2C_ICR_BERRCF BIT(8)
#define I2C_ICR_ARLOCF BIT(9)
#define I2C_ICR_OVRCF BIT(10)
#define I2C_ICR_PECCF BIT(11)
#define I2C_ICR_TIMOUTCF BIT(12)
#define I2C_ICR_ALERTCF BIT(13)
enum i2c_speed_e {
I2C_SPEED_STANDARD, /* 100 kHz */
I2C_SPEED_FAST, /* 400 kHz */
I2C_SPEED_FAST_PLUS, /* 1 MHz */
};
#define STANDARD_RATE 100000
#define FAST_RATE 400000
#define FAST_PLUS_RATE 1000000
struct stm32_i2c_init_s {
uint32_t own_address1; /*
* Specifies the first device own
* address. This parameter can be a
* 7-bit or 10-bit address.
*/
uint32_t addressing_mode; /*
* Specifies if 7-bit or 10-bit
* addressing mode is selected.
* This parameter can be a value of
* @ref I2C_ADDRESSING_MODE.
*/
uint32_t dual_address_mode; /*
* Specifies if dual addressing mode is
* selected.
* This parameter can be a value of @ref
* I2C_DUAL_ADDRESSING_MODE.
*/
uint32_t own_address2; /*
* Specifies the second device own
* address if dual addressing mode is
* selected. This parameter can be a
* 7-bit address.
*/
uint32_t own_address2_masks; /*
* Specifies the acknowledge mask
* address second device own address
* if dual addressing mode is selected
* This parameter can be a value of @ref
* I2C_OWN_ADDRESS2_MASKS.
*/
uint32_t general_call_mode; /*
* Specifies if general call mode is
* selected.
* This parameter can be a value of @ref
* I2C_GENERAL_CALL_ADDRESSING_MODE.
*/
uint32_t no_stretch_mode; /*
* Specifies if nostretch mode is
* selected.
* This parameter can be a value of @ref
* I2C_NOSTRETCH_MODE.
*/
uint32_t rise_time; /*
* Specifies the SCL clock pin rising
* time in nanoseconds.
*/
uint32_t fall_time; /*
* Specifies the SCL clock pin falling
* time in nanoseconds.
*/
enum i2c_speed_e speed_mode; /*
* Specifies the I2C clock source
* frequency mode.
* This parameter can be a value of @ref
* i2c_speed_mode_e.
*/
int analog_filter; /*
* Specifies if the I2C analog noise
* filter is selected.
* This parameter can be 0 (filter
* off), all other values mean filter
* on.
*/
uint8_t digital_filter_coef; /*
* Specifies the I2C digital noise
* filter coefficient.
* This parameter can be a value
* between 0 and
* STM32_I2C_DIGITAL_FILTER_MAX.
*/
};
enum i2c_state_e {
I2C_STATE_RESET = 0x00U, /* Not yet initialized */
I2C_STATE_READY = 0x20U, /* Ready for use */
I2C_STATE_BUSY = 0x24U, /* Internal process ongoing */
I2C_STATE_BUSY_TX = 0x21U, /* Data Transmission ongoing */
I2C_STATE_BUSY_RX = 0x22U, /* Data Reception ongoing */
};
enum i2c_mode_e {
I2C_MODE_NONE = 0x00U, /* No active communication */
I2C_MODE_MASTER = 0x10U, /* Communication in Master Mode */
I2C_MODE_SLAVE = 0x20U, /* Communication in Slave Mode */
I2C_MODE_MEM = 0x40U /* Communication in Memory Mode */
};
#define I2C_ERROR_NONE 0x00000000U /* No error */
#define I2C_ERROR_BERR 0x00000001U /* BERR error */
#define I2C_ERROR_ARLO 0x00000002U /* ARLO error */
#define I2C_ERROR_AF 0x00000004U /* ACKF error */
#define I2C_ERROR_OVR 0x00000008U /* OVR error */
#define I2C_ERROR_DMA 0x00000010U /* DMA transfer error */
#define I2C_ERROR_TIMEOUT 0x00000020U /* Timeout error */
#define I2C_ERROR_SIZE 0x00000040U /* Size Management error */
struct i2c_handle_s {
uint32_t i2c_base_addr; /* Registers base address */
unsigned int dt_status; /* DT nsec/sec status */
unsigned int clock; /* Clock reference */
uint8_t lock; /* Locking object */
enum i2c_state_e i2c_state; /* Communication state */
enum i2c_mode_e i2c_mode; /* Communication mode */
uint32_t i2c_err; /* Error code */
};
#define I2C_ADDRESSINGMODE_7BIT 0x00000001U
#define I2C_ADDRESSINGMODE_10BIT 0x00000002U
#define I2C_DUALADDRESS_DISABLE 0x00000000U
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
#define I2C_GENERALCALL_DISABLE 0x00000000U
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
#define I2C_NOSTRETCH_DISABLE 0x00000000U
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define I2C_MEMADD_SIZE_8BIT 0x00000001U
#define I2C_MEMADD_SIZE_16BIT 0x00000002U
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE 0x00000000U
#define I2C_NO_STARTSTOP 0x00000000U
#define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP)
#define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \
I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START)
#define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS
#define I2C_FLAG_RXNE I2C_ISR_RXNE
#define I2C_FLAG_ADDR I2C_ISR_ADDR
#define I2C_FLAG_AF I2C_ISR_NACKF
#define I2C_FLAG_STOPF I2C_ISR_STOPF
#define I2C_FLAG_TC I2C_ISR_TC
#define I2C_FLAG_TCR I2C_ISR_TCR
#define I2C_FLAG_BERR I2C_ISR_BERR
#define I2C_FLAG_ARLO I2C_ISR_ARLO
#define I2C_FLAG_OVR I2C_ISR_OVR
#define I2C_FLAG_PECERR I2C_ISR_PECERR
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define I2C_FLAG_ALERT I2C_ISR_ALERT
#define I2C_FLAG_BUSY I2C_ISR_BUSY
#define I2C_FLAG_DIR I2C_ISR_DIR
#define I2C_RESET_CR2 (I2C_CR2_SADD | I2C_CR2_HEAD10R | \
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
I2C_CR2_RD_WRN)
#define I2C_TIMEOUT_BUSY_MS 25U
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/* STM32 specific defines */
#define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */
#define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */
#define STM32_I2C_SPEED_DEFAULT I2C_SPEED_STANDARD
#define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
#define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
#define STM32_I2C_DIGITAL_FILTER_MAX 16
int stm32_i2c_get_setup_from_fdt(void *fdt, int node,
struct stm32_i2c_init_s *init);
int stm32_i2c_init(struct i2c_handle_s *hi2c,
struct stm32_i2c_init_s *init_data);
int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint16_t mem_addr, uint16_t mem_add_size,
uint8_t *p_data, uint16_t size, uint32_t timeout_ms);
int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint16_t mem_addr, uint16_t mem_add_size,
uint8_t *p_data, uint16_t size, uint32_t timeout_ms);
int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint8_t *p_data, uint16_t size,
uint32_t timeout_ms);
int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint8_t *p_data, uint16_t size,
uint32_t timeout_ms);
bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint32_t trials, uint32_t timeout_ms);
#endif /* STM32_I2C_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32_iwdg.h
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/*
* Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32_IWDG_H
#define STM32_IWDG_H
#include <stdint.h>
#define IWDG_HW_ENABLED BIT(0)
#define IWDG_DISABLE_ON_STOP BIT(1)
#define IWDG_DISABLE_ON_STANDBY BIT(2)
int stm32_iwdg_init(void);
void stm32_iwdg_refresh(void);
#endif /* STM32_IWDG_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32_pka.h
+46
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/*
* Copyright (c) 2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32_PKA_H
#define STM32_PKA_H
#include <stdint.h>
#if !PKA_USE_NIST_P256 && !PKA_USE_BRAINPOOL_P256R1 && !PKA_USE_BRAINPOOL_P256T1 && \
!PKA_USE_NIST_P521
#error "At least one ECDSA curve needs to be selected"
#endif
enum stm32_pka_ecdsa_curve_id {
#if PKA_USE_NIST_P256
PKA_NIST_P256,
#endif
#if PKA_USE_BRAINPOOL_P256R1
PKA_BRAINPOOL_P256R1,
#endif
#if PKA_USE_BRAINPOOL_P256T1
PKA_BRAINPOOL_P256T1,
#endif
#if PKA_USE_NIST_P521
PKA_NIST_P521,
#endif
};
struct stm32_pka_platdata {
uintptr_t base;
unsigned long clock_id;
unsigned int reset_id;
};
int stm32_pka_init(void);
int stm32_pka_ecdsa_verif(void *hash, unsigned int hash_size,
void *sig_r_ptr, unsigned int sig_r_size,
void *sig_s_ptr, unsigned int sig_s_size,
void *pk_x_ptr, unsigned int pk_x_size,
void *pk_y_ptr, unsigned int pk_y_size,
enum stm32_pka_ecdsa_curve_id cid);
#endif /* STM32_PKA_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32_qspi.h
+12
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/*
* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
#ifndef STM32_QSPI_H
#define STM32_QSPI_H
int stm32_qspi_init(void);
#endif /* STM32_QSPI_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32_rng.h
+15
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/*
* Copyright (c) 2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32_RNG_H
#define STM32_RNG_H
#include <stdint.h>
int stm32_rng_read(uint8_t *out, uint32_t size);
int stm32_rng_init(void);
#endif /* STM32_RNG_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32_saes.h
+59
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/*
* Copyright (c) 2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32_SAES_H
#define STM32_SAES_H
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#define DT_SAES_COMPAT "st,stm32-saes"
struct stm32_saes_platdata {
uintptr_t base;
unsigned long clock_id;
unsigned int reset_id;
};
enum stm32_saes_chaining_mode {
STM32_SAES_MODE_ECB,
STM32_SAES_MODE_CBC,
STM32_SAES_MODE_CTR,
STM32_SAES_MODE_GCM,
STM32_SAES_MODE_CCM, /* Not use in TF-A */
};
enum stm32_saes_key_selection {
STM32_SAES_KEY_SOFT,
STM32_SAES_KEY_DHU, /* Derived HW unique key */
STM32_SAES_KEY_BH, /* Boot HW key */
STM32_SAES_KEY_BHU_XOR_BH, /* XOR of DHUK and BHK */
STM32_SAES_KEY_WRAPPED
};
struct stm32_saes_context {
uintptr_t base;
uint32_t cr;
uint32_t assoc_len;
uint32_t load_len;
uint32_t key[8]; /* In HW byte order */
uint32_t iv[4]; /* In HW byte order */
};
int stm32_saes_driver_init(void);
int stm32_saes_init(struct stm32_saes_context *ctx, bool is_decrypt,
enum stm32_saes_chaining_mode ch_mode, enum stm32_saes_key_selection key_select,
const void *key, size_t key_len, const void *iv, size_t iv_len);
int stm32_saes_update(struct stm32_saes_context *ctx, bool last_block,
uint8_t *data_in, uint8_t *data_out, size_t data_len);
int stm32_saes_update_assodata(struct stm32_saes_context *ctx, bool last_block,
uint8_t *data, size_t data_len);
int stm32_saes_update_load(struct stm32_saes_context *ctx, bool last_block,
uint8_t *data_in, uint8_t *data_out, size_t data_len);
int stm32_saes_final(struct stm32_saes_context *ctx, uint8_t *tag, size_t tag_len);
#endif
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32_sdmmc2.h
+35
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/*
* Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32_SDMMC2_H
#define STM32_SDMMC2_H
#include <stdbool.h>
#include <drivers/mmc.h>
#include <drivers/st/regulator.h>
struct stm32_sdmmc2_params {
uintptr_t reg_base;
unsigned int clk_rate;
unsigned int bus_width;
unsigned int flags;
struct mmc_device_info *device_info;
unsigned int pin_ckin;
unsigned int negedge;
unsigned int dirpol;
unsigned int clock_id;
unsigned int reset_id;
unsigned int max_freq;
bool use_dma;
struct rdev *vmmc_regu;
};
unsigned long long stm32_sdmmc2_mmc_get_device_size(void);
int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params);
bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory);
#endif /* STM32_SDMMC2_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32_uart.h
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/*
* Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32_UART_H
#define STM32_UART_H
/* UART word length */
#define STM32_UART_WORDLENGTH_7B USART_CR1_M1
#define STM32_UART_WORDLENGTH_8B 0x00000000U
#define STM32_UART_WORDLENGTH_9B USART_CR1_M0
/* UART number of stop bits */
#define STM32_UART_STOPBITS_0_5 USART_CR2_STOP_0
#define STM32_UART_STOPBITS_1 0x00000000U
#define STM32_UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define STM32_UART_STOPBITS_2 USART_CR2_STOP_1
/* UART parity */
#define STM32_UART_PARITY_NONE 0x00000000U
#define STM32_UART_PARITY_EVEN USART_CR1_PCE
#define STM32_UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
/* UART transfer mode */
#define STM32_UART_MODE_RX USART_CR1_RE
#define STM32_UART_MODE_TX USART_CR1_TE
#define STM32_UART_MODE_TX_RX (USART_CR1_TE | USART_CR1_RE)
/* UART hardware flow control */
#define STM32_UART_HWCONTROL_NONE 0x00000000U
#define STM32_UART_HWCONTROL_RTS USART_CR3_RTSE
#define STM32_UART_HWCONTROL_CTS USART_CR3_CTSE
#define STM32_UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
/* UART prescaler */
#define STM32_UART_PRESCALER_DIV1 0x00000000U
#define STM32_UART_PRESCALER_DIV2 0x00000001U
#define STM32_UART_PRESCALER_DIV4 0x00000002U
#define STM32_UART_PRESCALER_DIV6 0x00000003U
#define STM32_UART_PRESCALER_DIV8 0x00000004U
#define STM32_UART_PRESCALER_DIV10 0x00000005U
#define STM32_UART_PRESCALER_DIV12 0x00000006U
#define STM32_UART_PRESCALER_DIV16 0x00000007U
#define STM32_UART_PRESCALER_DIV32 0x00000008U
#define STM32_UART_PRESCALER_DIV64 0x00000009U
#define STM32_UART_PRESCALER_DIV128 0x0000000AU
#define STM32_UART_PRESCALER_DIV256 0x0000000BU
#define STM32_UART_PRESCALER_NB 0x0000000CU
/* UART fifo mode */
#define STM32_UART_FIFOMODE_EN USART_CR1_FIFOEN
#define STM32_UART_FIFOMODE_DIS 0x00000000U
/* UART TXFIFO threshold level */
#define STM32_UART_TXFIFO_THRESHOLD_1EIGHTHFULL 0x00000000U
#define STM32_UART_TXFIFO_THRESHOLD_1QUARTERFUL USART_CR3_TXFTCFG_0
#define STM32_UART_TXFIFO_THRESHOLD_HALFFULL USART_CR3_TXFTCFG_1
#define STM32_UART_TXFIFO_THRESHOLD_3QUARTERSFULL (USART_CR3_TXFTCFG_0 | USART_CR3_TXFTCFG_1)
#define STM32_UART_TXFIFO_THRESHOLD_7EIGHTHFULL USART_CR3_TXFTCFG_2
#define STM32_UART_TXFIFO_THRESHOLD_EMPTY (USART_CR3_TXFTCFG_2 | USART_CR3_TXFTCFG_0)
/* UART RXFIFO threshold level */
#define STM32_UART_RXFIFO_THRESHOLD_1EIGHTHFULL 0x00000000U
#define STM32_UART_RXFIFO_THRESHOLD_1QUARTERFULL USART_CR3_RXFTCFG_0
#define STM32_UART_RXFIFO_THRESHOLD_HALFFULL USART_CR3_RXFTCFG_1
#define STM32_UART_RXFIFO_THRESHOLD_3QUARTERSFULL (USART_CR3_RXFTCFG_0 | USART_CR3_RXFTCFG_1)
#define STM32_UART_RXFIFO_THRESHOLD_7EIGHTHFULL USART_CR3_RXFTCFG_2
#define STM32_UART_RXFIFO_THRESHOLD_FULL (USART_CR3_RXFTCFG_2 | USART_CR3_RXFTCFG_0)
struct stm32_uart_init_s {
uint32_t baud_rate; /*
* Configures the UART communication
* baud rate.
*/
uint32_t word_length; /*
* Specifies the number of data bits
* transmitted or received in a frame.
* This parameter can be a value of
* @ref STM32_UART_WORDLENGTH_*.
*/
uint32_t stop_bits; /*
* Specifies the number of stop bits
* transmitted. This parameter can be
* a value of @ref STM32_UART_STOPBITS_*.
*/
uint32_t parity; /*
* Specifies the parity mode.
* This parameter can be a value of
* @ref STM32_UART_PARITY_*.
*/
uint32_t mode; /*
* Specifies whether the receive or
* transmit mode is enabled or
* disabled. This parameter can be a
* value of @ref @ref STM32_UART_MODE_*.
*/
uint32_t hw_flow_control; /*
* Specifies whether the hardware flow
* control mode is enabled or
* disabled. This parameter can be a
* value of @ref STM32_UARTHWCONTROL_*.
*/
uint32_t one_bit_sampling; /*
* Specifies whether a single sample
* or three samples' majority vote is
* selected. This parameter can be 0
* or USART_CR3_ONEBIT.
*/
uint32_t prescaler; /*
* Specifies the prescaler value used
* to divide the UART clock source.
* This parameter can be a value of
* @ref STM32_UART_PRESCALER_*.
*/
uint32_t fifo_mode; /*
* Specifies if the FIFO mode will be
* used. This parameter can be a value
* of @ref STM32_UART_FIFOMODE_*.
*/
uint32_t tx_fifo_threshold; /*
* Specifies the TXFIFO threshold
* level. This parameter can be a
* value of @ref
* STM32_UART_TXFIFO_THRESHOLD_*.
*/
uint32_t rx_fifo_threshold; /*
* Specifies the RXFIFO threshold
* level. This parameter can be a
* value of @ref
* STM32_UART_RXFIFO_THRESHOLD_*.
*/
};
struct stm32_uart_handle_s {
uint32_t base;
uint32_t rdr_mask;
};
int stm32_uart_init(struct stm32_uart_handle_s *huart,
uintptr_t base_addr,
const struct stm32_uart_init_s *init);
void stm32_uart_stop(uintptr_t base_addr);
int stm32_uart_putc(struct stm32_uart_handle_s *huart, int c);
int stm32_uart_flush(struct stm32_uart_handle_s *huart);
int stm32_uart_getc(struct stm32_uart_handle_s *huart);
#endif /* STM32_UART_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32_uart_regs.h
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/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32_UART_REGS_H
#define STM32_UART_REGS_H
#include <lib/utils_def.h>
#define USART_CR1 U(0x00)
#define USART_CR2 U(0x04)
#define USART_CR3 U(0x08)
#define USART_BRR U(0x0C)
#define USART_GTPR U(0x10)
#define USART_RTOR U(0x14)
#define USART_RQR U(0x18)
#define USART_ISR U(0x1C)
#define USART_ICR U(0x20)
#define USART_RDR U(0x24)
#define USART_TDR U(0x28)
#define USART_PRESC U(0x2C)
/* USART_CR1 register fields */
#define USART_CR1_UE BIT(0)
#define USART_CR1_UESM BIT(1)
#define USART_CR1_RE BIT(2)
#define USART_CR1_TE BIT(3)
#define USART_CR1_IDLEIE BIT(4)
#define USART_CR1_RXNEIE BIT(5)
#define USART_CR1_TCIE BIT(6)
#define USART_CR1_TXEIE BIT(7)
#define USART_CR1_PEIE BIT(8)
#define USART_CR1_PS BIT(9)
#define USART_CR1_PCE BIT(10)
#define USART_CR1_WAKE BIT(11)
#define USART_CR1_M (BIT(28) | BIT(12))
#define USART_CR1_M0 BIT(12)
#define USART_CR1_MME BIT(13)
#define USART_CR1_CMIE BIT(14)
#define USART_CR1_OVER8 BIT(15)
#define USART_CR1_DEDT GENMASK(20, 16)
#define USART_CR1_DEDT_0 BIT(16)
#define USART_CR1_DEDT_1 BIT(17)
#define USART_CR1_DEDT_2 BIT(18)
#define USART_CR1_DEDT_3 BIT(19)
#define USART_CR1_DEDT_4 BIT(20)
#define USART_CR1_DEAT GENMASK(25, 21)
#define USART_CR1_DEAT_0 BIT(21)
#define USART_CR1_DEAT_1 BIT(22)
#define USART_CR1_DEAT_2 BIT(23)
#define USART_CR1_DEAT_3 BIT(24)
#define USART_CR1_DEAT_4 BIT(25)
#define USART_CR1_RTOIE BIT(26)
#define USART_CR1_EOBIE BIT(27)
#define USART_CR1_M1 BIT(28)
#define USART_CR1_FIFOEN BIT(29)
#define USART_CR1_TXFEIE BIT(30)
#define USART_CR1_RXFFIE BIT(31)
/* USART_CR2 register fields */
#define USART_CR2_SLVEN BIT(0)
#define USART_CR2_DIS_NSS BIT(3)
#define USART_CR2_ADDM7 BIT(4)
#define USART_CR2_LBDL BIT(5)
#define USART_CR2_LBDIE BIT(6)
#define USART_CR2_LBCL BIT(8)
#define USART_CR2_CPHA BIT(9)
#define USART_CR2_CPOL BIT(10)
#define USART_CR2_CLKEN BIT(11)
#define USART_CR2_STOP GENMASK(13, 12)
#define USART_CR2_STOP_0 BIT(12)
#define USART_CR2_STOP_1 BIT(13)
#define USART_CR2_LINEN BIT(14)
#define USART_CR2_SWAP BIT(15)
#define USART_CR2_RXINV BIT(16)
#define USART_CR2_TXINV BIT(17)
#define USART_CR2_DATAINV BIT(18)
#define USART_CR2_MSBFIRST BIT(19)
#define USART_CR2_ABREN BIT(20)
#define USART_CR2_ABRMODE GENMASK(22, 21)
#define USART_CR2_ABRMODE_0 BIT(21)
#define USART_CR2_ABRMODE_1 BIT(22)
#define USART_CR2_RTOEN BIT(23)
#define USART_CR2_ADD GENMASK(31, 24)
/* USART_CR3 register fields */
#define USART_CR3_EIE BIT(0)
#define USART_CR3_IREN BIT(1)
#define USART_CR3_IRLP BIT(2)
#define USART_CR3_HDSEL BIT(3)
#define USART_CR3_NACK BIT(4)
#define USART_CR3_SCEN BIT(5)
#define USART_CR3_DMAR BIT(6)
#define USART_CR3_DMAT BIT(7)
#define USART_CR3_RTSE BIT(8)
#define USART_CR3_CTSE BIT(9)
#define USART_CR3_CTSIE BIT(10)
#define USART_CR3_ONEBIT BIT(11)
#define USART_CR3_OVRDIS BIT(12)
#define USART_CR3_DDRE BIT(13)
#define USART_CR3_DEM BIT(14)
#define USART_CR3_DEP BIT(15)
#define USART_CR3_SCARCNT GENMASK(19, 17)
#define USART_CR3_SCARCNT_0 BIT(17)
#define USART_CR3_SCARCNT_1 BIT(18)
#define USART_CR3_SCARCNT_2 BIT(19)
#define USART_CR3_WUS GENMASK(21, 20)
#define USART_CR3_WUS_0 BIT(20)
#define USART_CR3_WUS_1 BIT(21)
#define USART_CR3_WUFIE BIT(22)
#define USART_CR3_TXFTIE BIT(23)
#define USART_CR3_TCBGTIE BIT(24)
#define USART_CR3_RXFTCFG GENMASK(27, 25)
#define USART_CR3_RXFTCFG_0 BIT(25)
#define USART_CR3_RXFTCFG_1 BIT(26)
#define USART_CR3_RXFTCFG_2 BIT(27)
#define USART_CR3_RXFTIE BIT(28)
#define USART_CR3_TXFTCFG GENMASK(31, 29)
#define USART_CR3_TXFTCFG_0 BIT(29)
#define USART_CR3_TXFTCFG_1 BIT(30)
#define USART_CR3_TXFTCFG_2 BIT(31)
/* USART_BRR register fields */
#define USART_BRR_DIV_FRACTION GENMASK(3, 0)
#define USART_BRR_DIV_MANTISSA GENMASK(15, 4)
/* USART_GTPR register fields */
#define USART_GTPR_PSC GENMASK(7, 0)
#define USART_GTPR_GT GENMASK(15, 8)
/* USART_RTOR register fields */
#define USART_RTOR_RTO GENMASK(23, 0)
#define USART_RTOR_BLEN GENMASK(31, 24)
/* USART_RQR register fields */
#define USART_RQR_ABRRQ BIT(0)
#define USART_RQR_SBKRQ BIT(1)
#define USART_RQR_MMRQ BIT(2)
#define USART_RQR_RXFRQ BIT(3)
#define USART_RQR_TXFRQ BIT(4)
/* USART_ISR register fields */
#define USART_ISR_PE BIT(0)
#define USART_ISR_FE BIT(1)
#define USART_ISR_NE BIT(2)
#define USART_ISR_ORE BIT(3)
#define USART_ISR_IDLE BIT(4)
#define USART_ISR_RXNE BIT(5)
#define USART_ISR_TC BIT(6)
#define USART_ISR_TXE BIT(7)
#define USART_ISR_LBDF BIT(8)
#define USART_ISR_CTSIF BIT(9)
#define USART_ISR_CTS BIT(10)
#define USART_ISR_RTOF BIT(11)
#define USART_ISR_EOBF BIT(12)
#define USART_ISR_UDR BIT(13)
#define USART_ISR_ABRE BIT(14)
#define USART_ISR_ABRF BIT(15)
#define USART_ISR_BUSY BIT(16)
#define USART_ISR_CMF BIT(17)
#define USART_ISR_SBKF BIT(18)
#define USART_ISR_RWU BIT(19)
#define USART_ISR_WUF BIT(20)
#define USART_ISR_TEACK BIT(21)
#define USART_ISR_REACK BIT(22)
#define USART_ISR_TXFE BIT(23)
#define USART_ISR_RXFF BIT(24)
#define USART_ISR_TCBGT BIT(25)
#define USART_ISR_RXFT BIT(26)
#define USART_ISR_TXFT BIT(27)
/* USART_ICR register fields */
#define USART_ICR_PECF BIT(0)
#define USART_ICR_FECF BIT(1)
#define USART_ICR_NCF BIT(2)
#define USART_ICR_ORECF BIT(3)
#define USART_ICR_IDLECF BIT(4)
#define USART_ICR_TCCF BIT(6)
#define USART_ICR_TCBGT BIT(7)
#define USART_ICR_LBDCF BIT(8)
#define USART_ICR_CTSCF BIT(9)
#define USART_ICR_RTOCF BIT(11)
#define USART_ICR_EOBCF BIT(12)
#define USART_ICR_UDRCF BIT(13)
#define USART_ICR_CMCF BIT(17)
#define USART_ICR_WUCF BIT(20)
/* USART_RDR register fields */
#define USART_RDR_RDR GENMASK(8, 0)
/* USART_TDR register fields */
#define USART_TDR_TDR GENMASK(8, 0)
/* USART_PRESC register fields */
#define USART_PRESC_PRESCALER GENMASK(3, 0)
#endif /* STM32_UART_REGS_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32mp13_rcc.h
+1878
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source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32mp15_rcc.h
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source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32mp1_clk.h
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/*
* Copyright (c) 2018-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP1_CLK_H
#define STM32MP1_CLK_H
#include <arch_helpers.h>
enum stm32mp_osc_id {
_HSI,
_HSE,
_CSI,
_LSI,
_LSE,
_I2S_CKIN,
NB_OSC,
_UNKNOWN_OSC_ID = 0xFF
};
extern const char *stm32mp_osc_node_label[NB_OSC];
int stm32mp1_clk_probe(void);
int stm32mp1_clk_init(void);
bool stm32mp1_rcc_is_secure(void);
bool stm32mp1_rcc_is_mckprot(void);
/* SMP protection on RCC registers access */
void stm32mp1_clk_rcc_regs_lock(void);
void stm32mp1_clk_rcc_regs_unlock(void);
#ifdef STM32MP_SHARED_RESOURCES
void stm32mp1_register_clock_parents_secure(unsigned long id);
#endif
#endif /* STM32MP1_CLK_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32mp1_ddr.h
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/*
* Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
#ifndef STM32MP1_DDR_H
#define STM32MP1_DDR_H
#include <stdbool.h>
#include <stdint.h>
#include <drivers/st/stm32mp_ddr.h>
struct stm32mp1_ddrctrl_reg {
uint32_t mstr;
uint32_t mrctrl0;
uint32_t mrctrl1;
uint32_t derateen;
uint32_t derateint;
uint32_t pwrctl;
uint32_t pwrtmg;
uint32_t hwlpctl;
uint32_t rfshctl0;
uint32_t rfshctl3;
uint32_t crcparctl0;
uint32_t zqctl0;
uint32_t dfitmg0;
uint32_t dfitmg1;
uint32_t dfilpcfg0;
uint32_t dfiupd0;
uint32_t dfiupd1;
uint32_t dfiupd2;
uint32_t dfiphymstr;
uint32_t odtmap;
uint32_t dbg0;
uint32_t dbg1;
uint32_t dbgcmd;
uint32_t poisoncfg;
uint32_t pccfg;
};
struct stm32mp1_ddrctrl_timing {
uint32_t rfshtmg;
uint32_t dramtmg0;
uint32_t dramtmg1;
uint32_t dramtmg2;
uint32_t dramtmg3;
uint32_t dramtmg4;
uint32_t dramtmg5;
uint32_t dramtmg6;
uint32_t dramtmg7;
uint32_t dramtmg8;
uint32_t dramtmg14;
uint32_t odtcfg;
};
struct stm32mp1_ddrctrl_map {
uint32_t addrmap1;
uint32_t addrmap2;
uint32_t addrmap3;
uint32_t addrmap4;
uint32_t addrmap5;
uint32_t addrmap6;
uint32_t addrmap9;
uint32_t addrmap10;
uint32_t addrmap11;
};
struct stm32mp1_ddrctrl_perf {
uint32_t sched;
uint32_t sched1;
uint32_t perfhpr1;
uint32_t perflpr1;
uint32_t perfwr1;
uint32_t pcfgr_0;
uint32_t pcfgw_0;
uint32_t pcfgqos0_0;
uint32_t pcfgqos1_0;
uint32_t pcfgwqos0_0;
uint32_t pcfgwqos1_0;
#if STM32MP_DDR_DUAL_AXI_PORT
uint32_t pcfgr_1;
uint32_t pcfgw_1;
uint32_t pcfgqos0_1;
uint32_t pcfgqos1_1;
uint32_t pcfgwqos0_1;
uint32_t pcfgwqos1_1;
#endif
};
struct stm32mp1_ddrphy_reg {
uint32_t pgcr;
uint32_t aciocr;
uint32_t dxccr;
uint32_t dsgcr;
uint32_t dcr;
uint32_t odtcr;
uint32_t zq0cr1;
uint32_t dx0gcr;
uint32_t dx1gcr;
#if STM32MP_DDR_32BIT_INTERFACE
uint32_t dx2gcr;
uint32_t dx3gcr;
#endif
};
struct stm32mp1_ddrphy_timing {
uint32_t ptr0;
uint32_t ptr1;
uint32_t ptr2;
uint32_t dtpr0;
uint32_t dtpr1;
uint32_t dtpr2;
uint32_t mr0;
uint32_t mr1;
uint32_t mr2;
uint32_t mr3;
};
struct stm32mp_ddr_config {
struct stm32mp_ddr_info info;
struct stm32mp1_ddrctrl_reg c_reg;
struct stm32mp1_ddrctrl_timing c_timing;
struct stm32mp1_ddrctrl_map c_map;
struct stm32mp1_ddrctrl_perf c_perf;
struct stm32mp1_ddrphy_reg p_reg;
struct stm32mp1_ddrphy_timing p_timing;
};
int stm32mp1_ddr_clk_enable(struct stm32mp_ddr_priv *priv, uint32_t mem_speed);
void stm32mp1_ddr_init(struct stm32mp_ddr_priv *priv, struct stm32mp_ddr_config *config);
#endif /* STM32MP1_DDR_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32mp1_ddr_helpers.h
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/*
* Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP1_DDR_HELPERS_H
#define STM32MP1_DDR_HELPERS_H
void ddr_enable_clock(void);
#endif /* STM32MP1_DDR_HELPERS_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32mp1_ddr_regs.h
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/*
* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
#ifndef STM32MP1_DDR_REGS_H
#define STM32MP1_DDR_REGS_H
#include <drivers/st/stm32mp_ddrctrl_regs.h>
#include <lib/utils_def.h>
/* DDR Physical Interface Control (DDRPHYC) registers*/
struct stm32mp_ddrphy {
uint32_t ridr; /* 0x00 R Revision Identification */
uint32_t pir; /* 0x04 R/W PHY Initialization */
uint32_t pgcr; /* 0x08 R/W PHY General Configuration */
uint32_t pgsr; /* 0x0C PHY General Status */
uint32_t dllgcr; /* 0x10 R/W DLL General Control */
uint32_t acdllcr; /* 0x14 R/W AC DLL Control */
uint32_t ptr0; /* 0x18 R/W PHY Timing 0 */
uint32_t ptr1; /* 0x1C R/W PHY Timing 1 */
uint32_t ptr2; /* 0x20 R/W PHY Timing 2 */
uint32_t aciocr; /* 0x24 AC I/O Configuration */
uint32_t dxccr; /* 0x28 DATX8 Common Configuration */
uint32_t dsgcr; /* 0x2C DDR System General Configuration */
uint32_t dcr; /* 0x30 DRAM Configuration */
uint32_t dtpr0; /* 0x34 DRAM Timing Parameters0 */
uint32_t dtpr1; /* 0x38 DRAM Timing Parameters1 */
uint32_t dtpr2; /* 0x3C DRAM Timing Parameters2 */
uint32_t mr0; /* 0x40 Mode 0 */
uint32_t mr1; /* 0x44 Mode 1 */
uint32_t mr2; /* 0x48 Mode 2 */
uint32_t mr3; /* 0x4C Mode 3 */
uint32_t odtcr; /* 0x50 ODT Configuration */
uint32_t dtar; /* 0x54 data training address */
uint32_t dtdr0; /* 0x58 */
uint32_t dtdr1; /* 0x5c */
uint8_t res1[0x0c0 - 0x060]; /* 0x60 */
uint32_t dcuar; /* 0xc0 Address */
uint32_t dcudr; /* 0xc4 DCU Data */
uint32_t dcurr; /* 0xc8 DCU Run */
uint32_t dculr; /* 0xcc DCU Loop */
uint32_t dcugcr; /* 0xd0 DCU General Configuration */
uint32_t dcutpr; /* 0xd4 DCU Timing Parameters */
uint32_t dcusr0; /* 0xd8 DCU Status 0 */
uint32_t dcusr1; /* 0xdc DCU Status 1 */
uint8_t res2[0x100 - 0xe0]; /* 0xe0 */
uint32_t bistrr; /* 0x100 BIST Run */
uint32_t bistmskr0; /* 0x104 BIST Mask 0 */
uint32_t bistmskr1; /* 0x108 BIST Mask 0 */
uint32_t bistwcr; /* 0x10c BIST Word Count */
uint32_t bistlsr; /* 0x110 BIST LFSR Seed */
uint32_t bistar0; /* 0x114 BIST Address 0 */
uint32_t bistar1; /* 0x118 BIST Address 1 */
uint32_t bistar2; /* 0x11c BIST Address 2 */
uint32_t bistupdr; /* 0x120 BIST User Data Pattern */
uint32_t bistgsr; /* 0x124 BIST General Status */
uint32_t bistwer; /* 0x128 BIST Word Error */
uint32_t bistber0; /* 0x12c BIST Bit Error 0 */
uint32_t bistber1; /* 0x130 BIST Bit Error 1 */
uint32_t bistber2; /* 0x134 BIST Bit Error 2 */
uint32_t bistwcsr; /* 0x138 BIST Word Count Status */
uint32_t bistfwr0; /* 0x13c BIST Fail Word 0 */
uint32_t bistfwr1; /* 0x140 BIST Fail Word 1 */
uint8_t res3[0x178 - 0x144]; /* 0x144 */
uint32_t gpr0; /* 0x178 General Purpose 0 (GPR0) */
uint32_t gpr1; /* 0x17C General Purpose 1 (GPR1) */
uint32_t zq0cr0; /* 0x180 zq 0 control 0 */
uint32_t zq0cr1; /* 0x184 zq 0 control 1 */
uint32_t zq0sr0; /* 0x188 zq 0 status 0 */
uint32_t zq0sr1; /* 0x18C zq 0 status 1 */
uint8_t res4[0x1C0 - 0x190]; /* 0x190 */
uint32_t dx0gcr; /* 0x1c0 Byte lane 0 General Configuration */
uint32_t dx0gsr0; /* 0x1c4 Byte lane 0 General Status 0 */
uint32_t dx0gsr1; /* 0x1c8 Byte lane 0 General Status 1 */
uint32_t dx0dllcr; /* 0x1cc Byte lane 0 DLL Control */
uint32_t dx0dqtr; /* 0x1d0 Byte lane 0 DQ Timing */
uint32_t dx0dqstr; /* 0x1d4 Byte lane 0 DQS Timing */
uint8_t res5[0x200 - 0x1d8]; /* 0x1d8 */
uint32_t dx1gcr; /* 0x200 Byte lane 1 General Configuration */
uint32_t dx1gsr0; /* 0x204 Byte lane 1 General Status 0 */
uint32_t dx1gsr1; /* 0x208 Byte lane 1 General Status 1 */
uint32_t dx1dllcr; /* 0x20c Byte lane 1 DLL Control */
uint32_t dx1dqtr; /* 0x210 Byte lane 1 DQ Timing */
uint32_t dx1dqstr; /* 0x214 Byte lane 1 QS Timing */
uint8_t res6[0x240 - 0x218]; /* 0x218 */
#if STM32MP_DDR_32BIT_INTERFACE
uint32_t dx2gcr; /* 0x240 Byte lane 2 General Configuration */
uint32_t dx2gsr0; /* 0x244 Byte lane 2 General Status 0 */
uint32_t dx2gsr1; /* 0x248 Byte lane 2 General Status 1 */
uint32_t dx2dllcr; /* 0x24c Byte lane 2 DLL Control */
uint32_t dx2dqtr; /* 0x250 Byte lane 2 DQ Timing */
uint32_t dx2dqstr; /* 0x254 Byte lane 2 QS Timing */
uint8_t res7[0x280 - 0x258]; /* 0x258 */
uint32_t dx3gcr; /* 0x280 Byte lane 3 General Configuration */
uint32_t dx3gsr0; /* 0x284 Byte lane 3 General Status 0 */
uint32_t dx3gsr1; /* 0x288 Byte lane 3 General Status 1 */
uint32_t dx3dllcr; /* 0x28c Byte lane 3 DLL Control */
uint32_t dx3dqtr; /* 0x290 Byte lane 3 DQ Timing */
uint32_t dx3dqstr; /* 0x294 Byte lane 3 QS Timing */
#endif
} __packed;
/* DDR PHY registers offsets */
#define DDRPHYC_PIR 0x004
#define DDRPHYC_PGCR 0x008
#define DDRPHYC_PGSR 0x00C
#define DDRPHYC_DLLGCR 0x010
#define DDRPHYC_ACDLLCR 0x014
#define DDRPHYC_PTR0 0x018
#define DDRPHYC_ACIOCR 0x024
#define DDRPHYC_DXCCR 0x028
#define DDRPHYC_DSGCR 0x02C
#define DDRPHYC_ZQ0CR0 0x180
#define DDRPHYC_DX0GCR 0x1C0
#define DDRPHYC_DX0DLLCR 0x1CC
#define DDRPHYC_DX1GCR 0x200
#define DDRPHYC_DX1DLLCR 0x20C
#if STM32MP_DDR_32BIT_INTERFACE
#define DDRPHYC_DX2GCR 0x240
#define DDRPHYC_DX2DLLCR 0x24C
#define DDRPHYC_DX3GCR 0x280
#define DDRPHYC_DX3DLLCR 0x28C
#endif
/* DDR PHY Register fields */
#define DDRPHYC_PIR_INIT BIT(0)
#define DDRPHYC_PIR_DLLSRST BIT(1)
#define DDRPHYC_PIR_DLLLOCK BIT(2)
#define DDRPHYC_PIR_ZCAL BIT(3)
#define DDRPHYC_PIR_ITMSRST BIT(4)
#define DDRPHYC_PIR_DRAMRST BIT(5)
#define DDRPHYC_PIR_DRAMINIT BIT(6)
#define DDRPHYC_PIR_QSTRN BIT(7)
#define DDRPHYC_PIR_RVTRN BIT(8)
#define DDRPHYC_PIR_ICPC BIT(16)
#define DDRPHYC_PIR_ZCALBYP BIT(30)
#define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7)
#define DDRPHYC_PGCR_DFTCMP BIT(2)
#define DDRPHYC_PGCR_PDDISDX BIT(24)
#define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25)
#define DDRPHYC_PGSR_IDONE BIT(0)
#define DDRPHYC_PGSR_DTERR BIT(5)
#define DDRPHYC_PGSR_DTIERR BIT(6)
#define DDRPHYC_PGSR_DFTERR BIT(7)
#define DDRPHYC_PGSR_RVERR BIT(8)
#define DDRPHYC_PGSR_RVEIRR BIT(9)
#define DDRPHYC_DLLGCR_BPS200 BIT(23)
#define DDRPHYC_ACDLLCR_DLLSRST BIT(30)
#define DDRPHYC_ACDLLCR_DLLDIS BIT(31)
#define DDRPHYC_PTR0_TDLLSRST_OFFSET 0
#define DDRPHYC_PTR0_TDLLSRST_MASK GENMASK(5, 0)
#define DDRPHYC_PTR0_TDLLLOCK_OFFSET 6
#define DDRPHYC_PTR0_TDLLLOCK_MASK GENMASK(17, 6)
#define DDRPHYC_PTR0_TITMSRST_OFFSET 18
#define DDRPHYC_PTR0_TITMSRST_MASK GENMASK(21, 18)
#define DDRPHYC_ACIOCR_ACPDD BIT(3)
#define DDRPHYC_ACIOCR_ACPDR BIT(4)
#define DDRPHYC_ACIOCR_CKPDD_MASK GENMASK(10, 8)
#define DDRPHYC_ACIOCR_CKPDD_0 BIT(8)
#define DDRPHYC_ACIOCR_CKPDR_MASK GENMASK(13, 11)
#define DDRPHYC_ACIOCR_CKPDR_0 BIT(11)
#define DDRPHYC_ACIOCR_CSPDD_MASK GENMASK(21, 18)
#define DDRPHYC_ACIOCR_CSPDD_0 BIT(18)
#define DDRPHYC_ACIOCR_RSTPDD BIT(27)
#define DDRPHYC_ACIOCR_RSTPDR BIT(28)
#define DDRPHYC_DXCCR_DXPDD BIT(2)
#define DDRPHYC_DXCCR_DXPDR BIT(3)
#define DDRPHYC_DSGCR_CKEPDD_MASK GENMASK(19, 16)
#define DDRPHYC_DSGCR_CKEPDD_0 BIT(16)
#define DDRPHYC_DSGCR_ODTPDD_MASK GENMASK(23, 20)
#define DDRPHYC_DSGCR_ODTPDD_0 BIT(20)
#define DDRPHYC_DSGCR_NL2PD BIT(24)
#define DDRPHYC_ZQ0CRN_ZDATA_MASK GENMASK(27, 0)
#define DDRPHYC_ZQ0CRN_ZDATA_SHIFT 0
#define DDRPHYC_ZQ0CRN_ZDEN BIT(28)
#define DDRPHYC_ZQ0CRN_ZQPD BIT(31)
#define DDRPHYC_DXNGCR_DXEN BIT(0)
#define DDRPHYC_DXNDLLCR_DLLSRST BIT(30)
#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31)
#define DDRPHYC_DXNDLLCR_SDPHASE_MASK GENMASK(17, 14)
#define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT 14
#endif /* STM32MP1_DDR_REGS_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32mp1_pwr.h
+32
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/*
* Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP1_PWR_H
#define STM32MP1_PWR_H
#include <lib/utils_def.h>
#define PWR_CR1 U(0x00)
#define PWR_CR2 U(0x08)
#define PWR_CR3 U(0x0C)
#define PWR_MPUCR U(0x10)
#define PWR_WKUPCR U(0x20)
#define PWR_MPUWKUPENR U(0x28)
#define PWR_CR1_LPDS BIT(0)
#define PWR_CR1_LPCFG BIT(1)
#define PWR_CR1_LVDS BIT(2)
#define PWR_CR1_DBP BIT(8)
#define PWR_CR3_DDRSREN BIT(10)
#define PWR_CR3_DDRSRDIS BIT(11)
#define PWR_CR3_DDRRETEN BIT(12)
#define PWR_MPUCR_PDDS BIT(0)
#define PWR_MPUCR_CSTDBYDIS BIT(3)
#define PWR_MPUCR_CSSF BIT(9)
#endif /* STM32MP1_PWR_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32mp1_ram.h
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/*
* Copyright (c) 2015-2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP1_RAM_H
#define STM32MP1_RAM_H
int stm32mp1_ddr_probe(void);
#endif /* STM32MP1_RAM_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32mp1_rcc.h
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/*
* Copyright (c) 2015-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#if STM32MP13
#include "stm32mp13_rcc.h"
#endif
#if STM32MP15
#include "stm32mp15_rcc.h"
#endif
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32mp1_usb.h
+16
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/*
* Copyright (c) 2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP1_USB_H
#define STM32MP1_USB_H
#include <drivers/usb_device.h>
void stm32mp1_usb_init_driver(struct usb_handle *usb_core_handle,
struct pcd_handle *pcd_handle,
void *base_register);
#endif /* STM32MP1_USB_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32mp_clkfunc.h
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/*
* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP_CLKFUNC_H
#define STM32MP_CLKFUNC_H
#include <stdbool.h>
#include <libfdt.h>
#include <platform_def.h>
int fdt_osc_read_freq(const char *name, uint32_t *freq);
bool fdt_clk_read_bool(const char *node_label, const char *prop_name);
uint32_t fdt_clk_read_uint32_default(const char *node_label,
const char *prop_name,
uint32_t dflt_value);
int fdt_rcc_read_uint32_array(const char *prop_name, uint32_t count,
uint32_t *array);
int fdt_rcc_subnode_offset(const char *name);
const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp);
bool fdt_get_rcc_secure_state(void);
int fdt_get_clock_id(int node);
unsigned long fdt_get_uart_clock_freq(uintptr_t instance);
void stm32mp_stgen_config(unsigned long rate);
void stm32mp_stgen_restore_counter(unsigned long long value,
unsigned long long offset_in_ms);
unsigned long long stm32mp_stgen_get_counter(void);
#endif /* STM32MP_CLKFUNC_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32mp_ddr.h
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/*
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
#ifndef STM32MP_DDR_H
#define STM32MP_DDR_H
#include <platform_def.h>
enum stm32mp_ddr_base_type {
DDR_BASE,
DDRPHY_BASE,
NONE_BASE
};
enum stm32mp_ddr_reg_type {
REG_REG,
REG_TIMING,
REG_PERF,
REG_MAP,
REGPHY_REG,
REGPHY_TIMING,
REG_TYPE_NB
};
struct stm32mp_ddr_reg_desc {
const char *name;
uint16_t offset; /* Offset for base address */
uint8_t par_offset; /* Offset for parameter array */
};
struct stm32mp_ddr_reg_info {
const char *name;
const struct stm32mp_ddr_reg_desc *desc;
uint8_t size;
enum stm32mp_ddr_base_type base;
};
struct stm32mp_ddr_size {
uint64_t base;
uint64_t size;
};
struct stm32mp_ddr_priv {
struct stm32mp_ddr_size info;
struct stm32mp_ddrctl *ctl;
struct stm32mp_ddrphy *phy;
uintptr_t pwr;
uintptr_t rcc;
};
struct stm32mp_ddr_info {
const char *name;
uint32_t speed; /* in kHZ */
uint32_t size; /* Memory size in byte = col * row * width */
};
#define TIMEOUT_US_1S 1000000U
void stm32mp_ddr_set_reg(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_reg_type type,
const void *param, const struct stm32mp_ddr_reg_info *ddr_registers);
void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl);
void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl);
void stm32mp_ddr_enable_axi_port(struct stm32mp_ddrctl *ctl);
int stm32mp_board_ddr_power_init(enum ddr_type ddr_type);
#endif /* STM32MP_DDR_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32mp_ddr_test.h
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/*
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP_DDR_TEST_H
#define STM32MP_DDR_TEST_H
#include <stdint.h>
uint32_t stm32mp_ddr_test_rw_access(void);
uint32_t stm32mp_ddr_test_data_bus(void);
uint32_t stm32mp_ddr_test_addr_bus(uint64_t size);
uint32_t stm32mp_ddr_check_size(void);
#endif /* STM32MP_DDR_TEST_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32mp_ddrctrl_regs.h
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/*
* Copyright (c) 2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
#ifndef STM32MP_DDRCTRL_REGS_H
#define STM32MP_DDRCTRL_REGS_H
#include <cdefs.h>
#include <stdint.h>
#include <lib/utils_def.h>
/* DDR Controller (DDRCTRL) registers */
struct stm32mp_ddrctl {
uint32_t mstr ; /* 0x0 Master */
uint32_t stat; /* 0x4 Operating Mode Status */
uint8_t reserved008[0x10 - 0x8];
uint32_t mrctrl0; /* 0x10 Control 0 */
uint32_t mrctrl1; /* 0x14 Control 1 */
uint32_t mrstat; /* 0x18 Status */
uint32_t mrctrl2; /* 0x1c Control 2 */
uint32_t derateen; /* 0x20 Temperature Derate Enable */
uint32_t derateint; /* 0x24 Temperature Derate Interval */
uint32_t reserved028;
uint32_t deratectl; /* 0x2c Temperature Derate Control */
uint32_t pwrctl; /* 0x30 Low Power Control */
uint32_t pwrtmg; /* 0x34 Low Power Timing */
uint32_t hwlpctl; /* 0x38 Hardware Low Power Control */
uint8_t reserved03c[0x50 - 0x3c];
uint32_t rfshctl0; /* 0x50 Refresh Control 0 */
uint32_t rfshctl1; /* 0x54 Refresh Control 1 */
uint32_t reserved058; /* 0x58 Refresh Control 2 */
uint32_t reserved05C;
uint32_t rfshctl3; /* 0x60 Refresh Control 0 */
uint32_t rfshtmg; /* 0x64 Refresh Timing */
uint32_t rfshtmg1; /* 0x68 Refresh Timing 1 */
uint8_t reserved06c[0xc0 - 0x6c];
uint32_t crcparctl0; /* 0xc0 CRC Parity Control0 */
uint32_t crcparctl1; /* 0xc4 CRC Parity Control1 */
uint32_t reserved0c8; /* 0xc8 CRC Parity Control2 */
uint32_t crcparstat; /* 0xcc CRC Parity Status */
uint32_t init0; /* 0xd0 SDRAM Initialization 0 */
uint32_t init1; /* 0xd4 SDRAM Initialization 1 */
uint32_t init2; /* 0xd8 SDRAM Initialization 2 */
uint32_t init3; /* 0xdc SDRAM Initialization 3 */
uint32_t init4; /* 0xe0 SDRAM Initialization 4 */
uint32_t init5; /* 0xe4 SDRAM Initialization 5 */
uint32_t init6; /* 0xe8 SDRAM Initialization 6 */
uint32_t init7; /* 0xec SDRAM Initialization 7 */
uint32_t dimmctl; /* 0xf0 DIMM Control */
uint32_t rankctl; /* 0xf4 Rank Control */
uint8_t reserved0f4[0x100 - 0xf8];
uint32_t dramtmg0; /* 0x100 SDRAM Timing 0 */
uint32_t dramtmg1; /* 0x104 SDRAM Timing 1 */
uint32_t dramtmg2; /* 0x108 SDRAM Timing 2 */
uint32_t dramtmg3; /* 0x10c SDRAM Timing 3 */
uint32_t dramtmg4; /* 0x110 SDRAM Timing 4 */
uint32_t dramtmg5; /* 0x114 SDRAM Timing 5 */
uint32_t dramtmg6; /* 0x118 SDRAM Timing 6 */
uint32_t dramtmg7; /* 0x11c SDRAM Timing 7 */
uint32_t dramtmg8; /* 0x120 SDRAM Timing 8 */
uint32_t dramtmg9; /* 0x124 SDRAM Timing 9 */
uint32_t dramtmg10; /* 0x128 SDRAM Timing 10 */
uint32_t dramtmg11; /* 0x12c SDRAM Timing 11 */
uint32_t dramtmg12; /* 0x130 SDRAM Timing 12 */
uint32_t dramtmg13; /* 0x134 SDRAM Timing 13 */
uint32_t dramtmg14; /* 0x138 SDRAM Timing 14 */
uint32_t dramtmg15; /* 0x13c SDRAM Timing 15 */
uint8_t reserved140[0x180 - 0x140];
uint32_t zqctl0; /* 0x180 ZQ Control 0 */
uint32_t zqctl1; /* 0x184 ZQ Control 1 */
uint32_t zqctl2; /* 0x188 ZQ Control 2 */
uint32_t zqstat; /* 0x18c ZQ Status */
uint32_t dfitmg0; /* 0x190 DFI Timing 0 */
uint32_t dfitmg1; /* 0x194 DFI Timing 1 */
uint32_t dfilpcfg0; /* 0x198 DFI Low Power Configuration 0 */
uint32_t dfilpcfg1; /* 0x19c DFI Low Power Configuration 1 */
uint32_t dfiupd0; /* 0x1a0 DFI Update 0 */
uint32_t dfiupd1; /* 0x1a4 DFI Update 1 */
uint32_t dfiupd2; /* 0x1a8 DFI Update 2 */
uint32_t reserved1ac;
uint32_t dfimisc; /* 0x1b0 DFI Miscellaneous Control */
uint32_t dfitmg2; /* 0x1b4 DFI Timing 2 */
uint32_t dfitmg3; /* 0x1b8 DFI Timing 3 */
uint32_t dfistat; /* 0x1bc DFI Status */
uint32_t dbictl; /* 0x1c0 DM/DBI Control */
uint32_t dfiphymstr; /* 0x1c4 DFI PHY Master interface */
uint8_t reserved1c8[0x200 - 0x1c8];
uint32_t addrmap0; /* 0x200 Address Map 0 */
uint32_t addrmap1; /* 0x204 Address Map 1 */
uint32_t addrmap2; /* 0x208 Address Map 2 */
uint32_t addrmap3; /* 0x20c Address Map 3 */
uint32_t addrmap4; /* 0x210 Address Map 4 */
uint32_t addrmap5; /* 0x214 Address Map 5 */
uint32_t addrmap6; /* 0x218 Address Map 6 */
uint32_t addrmap7; /* 0x21c Address Map 7 */
uint32_t addrmap8; /* 0x220 Address Map 8 */
uint32_t addrmap9; /* 0x224 Address Map 9 */
uint32_t addrmap10; /* 0x228 Address Map 10 */
uint32_t addrmap11; /* 0x22C Address Map 11 */
uint8_t reserved230[0x240 - 0x230];
uint32_t odtcfg; /* 0x240 ODT Configuration */
uint32_t odtmap; /* 0x244 ODT/Rank Map */
uint8_t reserved248[0x250 - 0x248];
uint32_t sched; /* 0x250 Scheduler Control */
uint32_t sched1; /* 0x254 Scheduler Control 1 */
uint32_t reserved258;
uint32_t perfhpr1; /* 0x25c High Priority Read CAM 1 */
uint32_t reserved260;
uint32_t perflpr1; /* 0x264 Low Priority Read CAM 1 */
uint32_t reserved268;
uint32_t perfwr1; /* 0x26c Write CAM 1 */
uint8_t reserved27c[0x300 - 0x270];
uint32_t dbg0; /* 0x300 Debug 0 */
uint32_t dbg1; /* 0x304 Debug 1 */
uint32_t dbgcam; /* 0x308 CAM Debug */
uint32_t dbgcmd; /* 0x30c Command Debug */
uint32_t dbgstat; /* 0x310 Status Debug */
uint8_t reserved314[0x320 - 0x314];
uint32_t swctl; /* 0x320 Software Programming Control Enable */
uint32_t swstat; /* 0x324 Software Programming Control Status */
uint8_t reserved328[0x36c - 0x328];
uint32_t poisoncfg; /* 0x36c AXI Poison Configuration Register */
uint32_t poisonstat; /* 0x370 AXI Poison Status Register */
uint8_t reserved374[0x3f0 - 0x374];
uint32_t deratestat; /* 0x3f0 Temperature Derate Status */
uint8_t reserved3f4[0x3fc - 0x3f4];
/* Multi Port registers */
uint32_t pstat; /* 0x3fc Port Status */
uint32_t pccfg; /* 0x400 Port Common Configuration */
/* PORT 0 */
uint32_t pcfgr_0; /* 0x404 Configuration Read */
uint32_t pcfgw_0; /* 0x408 Configuration Write */
uint8_t reserved40c[0x490 - 0x40c];
uint32_t pctrl_0; /* 0x490 Port Control Register */
uint32_t pcfgqos0_0; /* 0x494 Read QoS Configuration 0 */
uint32_t pcfgqos1_0; /* 0x498 Read QoS Configuration 1 */
uint32_t pcfgwqos0_0; /* 0x49c Write QoS Configuration 0 */
uint32_t pcfgwqos1_0; /* 0x4a0 Write QoS Configuration 1 */
uint8_t reserved4a4[0x4b4 - 0x4a4];
#if STM32MP_DDR_DUAL_AXI_PORT
/* PORT 1 */
uint32_t pcfgr_1; /* 0x4b4 Configuration Read */
uint32_t pcfgw_1; /* 0x4b8 Configuration Write */
uint8_t reserved4bc[0x540 - 0x4bc];
uint32_t pctrl_1; /* 0x540 Port 2 Control Register */
uint32_t pcfgqos0_1; /* 0x544 Read QoS Configuration 0 */
uint32_t pcfgqos1_1; /* 0x548 Read QoS Configuration 1 */
uint32_t pcfgwqos0_1; /* 0x54c Write QoS Configuration 0 */
uint32_t pcfgwqos1_1; /* 0x550 Write QoS Configuration 1 */
#endif
uint8_t reserved554[0xff0 - 0x554];
uint32_t umctl2_ver_number; /* 0xff0 UMCTL2 Version Number */
} __packed;
/* DDR Controller registers offsets */
#define DDRCTRL_MSTR 0x000
#define DDRCTRL_STAT 0x004
#define DDRCTRL_MRCTRL0 0x010
#define DDRCTRL_MRSTAT 0x018
#define DDRCTRL_PWRCTL 0x030
#define DDRCTRL_PWRTMG 0x034
#define DDRCTRL_HWLPCTL 0x038
#define DDRCTRL_RFSHCTL3 0x060
#define DDRCTRL_RFSHTMG 0x064
#define DDRCTRL_INIT0 0x0D0
#define DDRCTRL_DFIMISC 0x1B0
#define DDRCTRL_DBG1 0x304
#define DDRCTRL_DBGCAM 0x308
#define DDRCTRL_DBGCMD 0x30C
#define DDRCTRL_DBGSTAT 0x310
#define DDRCTRL_SWCTL 0x320
#define DDRCTRL_SWSTAT 0x324
#define DDRCTRL_PSTAT 0x3FC
#define DDRCTRL_PCTRL_0 0x490
#if STM32MP_DDR_DUAL_AXI_PORT
#define DDRCTRL_PCTRL_1 0x540
#endif
/* DDR Controller Register fields */
#define DDRCTRL_MSTR_DDR3 BIT(0)
#define DDRCTRL_MSTR_LPDDR2 BIT(2)
#define DDRCTRL_MSTR_LPDDR3 BIT(3)
#define DDRCTRL_MSTR_DDR4 BIT(4)
#define DDRCTRL_MSTR_LPDDR4 BIT(5)
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL 0
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF BIT(12)
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER BIT(13)
#define DDRCTRL_MSTR_DLL_OFF_MODE BIT(15)
#define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0)
#define DDRCTRL_STAT_OPERATING_MODE_NORMAL BIT(0)
#define DDRCTRL_STAT_OPERATING_MODE_SR (BIT(0) | BIT(1))
#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4)
#define DDRCTRL_STAT_SELFREF_TYPE_ASR (BIT(4) | BIT(5))
#define DDRCTRL_STAT_SELFREF_TYPE_SR BIT(5)
#define DDRCTRL_MRCTRL0_MR_TYPE_WRITE U(0)
/* Only one rank supported */
#define DDRCTRL_MRCTRL0_MR_RANK_SHIFT 4
#define DDRCTRL_MRCTRL0_MR_RANK_ALL \
BIT(DDRCTRL_MRCTRL0_MR_RANK_SHIFT)
#define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT 12
#define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12)
#define DDRCTRL_MRCTRL0_MR_WR BIT(31)
#define DDRCTRL_MRSTAT_MR_WR_BUSY BIT(0)
#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0)
#define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1)
#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3)
#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5)
#define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16)
#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 BIT(16)
#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0)
#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL BIT(1)
#define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0)
#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16)
#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT 16
#define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK GENMASK(31, 30)
#define DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL BIT(30)
#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0)
#define DDRCTRL_DFIMISC_DFI_INIT_START BIT(5)
#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE BIT(0)
#define DDRCTRL_DBG1_DIS_HIF BIT(1)
#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY BIT(29)
#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY BIT(28)
#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY BIT(26)
#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8)
#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0)
#define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \
(DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \
DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY)
#define DDRCTRL_DBGCAM_DBG_Q_DEPTH \
(DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \
DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \
DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH)
#define DDRCTRL_DBGCMD_RANK0_REFRESH BIT(0)
#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY BIT(0)
#define DDRCTRL_SWCTL_SW_DONE BIT(0)
#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0)
#define DDRCTRL_PCTRL_N_PORT_EN BIT(0)
#endif /* STM32MP_DDRCTRL_REGS_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32mp_pmic.h
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/*
* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP_PMIC_H
#define STM32MP_PMIC_H
#include <stdbool.h>
#include <platform_def.h>
/*
* dt_pmic_status - Check PMIC status from device tree
*
* Returns the status of the PMIC (secure, non-secure), or a negative value on
* error
*/
int dt_pmic_status(void);
/*
* initialize_pmic_i2c - Initialize I2C for the PMIC control
*
* Returns true if PMIC is available, false if not found, panics on errors
*/
bool initialize_pmic_i2c(void);
/*
* initialize_pmic - Main PMIC initialization function, called at platform init
*
* Panics on errors
*/
void initialize_pmic(void);
#if DEBUG
void print_pmic_info_and_debug(void);
#else
static inline void print_pmic_info_and_debug(void)
{
}
#endif
/*
* pmic_ddr_power_init - Initialize regulators required for DDR
*
* Returns 0 on success, and negative values on errors
*/
int pmic_ddr_power_init(enum ddr_type ddr_type);
/*
* pmic_voltages_init - Update voltages for platform init
*
* Returns 0 on success, and negative values on errors
*/
int pmic_voltages_init(void);
#endif /* STM32MP_PMIC_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32mp_ram.h
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/*
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP_RAM_H
#define STM32MP_RAM_H
#include <stdbool.h>
#include <drivers/st/stm32mp_ddr.h>
#define PARAM(x, y) \
{ \
.name = x, \
.offset = offsetof(struct stm32mp_ddr_config, y), \
.size = sizeof(config.y) / sizeof(uint32_t), \
}
#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x)
#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x)
struct stm32mp_ddr_param {
const char *name; /* Name in DT */
const uint32_t offset; /* Offset in config struct */
const uint32_t size; /* Size of parameters */
};
int stm32mp_ddr_dt_get_info(void *fdt, int node, struct stm32mp_ddr_info *info);
int stm32mp_ddr_dt_get_param(void *fdt, int node, const struct stm32mp_ddr_param *param,
uint32_t param_size, uintptr_t config);
#endif /* STM32MP_RAM_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stm32mp_reset.h
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/*
* Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP_RESET_H
#define STM32MP_RESET_H
#include <stdint.h>
/*
* Assert target reset, if @to_us non null, wait until reset is asserted
*
* @reset_id: Reset controller ID
* @to_us: Timeout in microsecond, or 0 if not waiting
* Return 0 on success and -ETIMEDOUT if waiting and timeout expired
*/
int stm32mp_reset_assert(uint32_t reset_id, unsigned int to_us);
/*
* Enable reset control for target resource
*
* @reset_id: Reset controller ID
*/
static inline void stm32mp_reset_set(uint32_t reset_id)
{
(void)stm32mp_reset_assert(reset_id, 0U);
}
/*
* Deassert target reset, if @to_us non null, wait until reset is deasserted
*
* @reset_id: Reset controller ID
* @to_us: Timeout in microsecond, or 0 if not waiting
* Return 0 on success and -ETIMEDOUT if waiting and timeout expired
*/
int stm32mp_reset_deassert(uint32_t reset_id, unsigned int to_us);
/*
* Release reset control for target resource
*
* @reset_id: Reset controller ID
*/
static inline void stm32mp_reset_release(uint32_t reset_id)
{
(void)stm32mp_reset_deassert(reset_id, 0U);
}
#endif /* STM32MP_RESET_H */
source/trusted-firmware/trusted-firmware-a-2.8/include/drivers/st/stpmic1.h
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/*
* Copyright (c) 2016-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STPMIC1_H
#define STPMIC1_H
#include <drivers/st/stm32_i2c.h>
#include <lib/utils_def.h>
#define TURN_ON_REG 0x1U
#define TURN_OFF_REG 0x2U
#define ICC_LDO_TURN_OFF_REG 0x3U
#define ICC_BUCK_TURN_OFF_REG 0x4U
#define RESET_STATUS_REG 0x5U
#define VERSION_STATUS_REG 0x6U
#define MAIN_CONTROL_REG 0x10U
#define PADS_PULL_REG 0x11U
#define BUCK_PULL_DOWN_REG 0x12U
#define LDO14_PULL_DOWN_REG 0x13U
#define LDO56_PULL_DOWN_REG 0x14U
#define VIN_CONTROL_REG 0x15U
#define PONKEY_TIMER_REG 0x16U
#define MASK_RANK_BUCK_REG 0x17U
#define MASK_RESET_BUCK_REG 0x18U
#define MASK_RANK_LDO_REG 0x19U
#define MASK_RESET_LDO_REG 0x1AU
#define WATCHDOG_CONTROL_REG 0x1BU
#define WATCHDOG_TIMER_REG 0x1CU
#define BUCK_ICC_TURNOFF_REG 0x1DU
#define LDO_ICC_TURNOFF_REG 0x1EU
#define BUCK_APM_CONTROL_REG 0x1FU
#define BUCK1_CONTROL_REG 0x20U
#define BUCK2_CONTROL_REG 0x21U
#define BUCK3_CONTROL_REG 0x22U
#define BUCK4_CONTROL_REG 0x23U
#define VREF_DDR_CONTROL_REG 0x24U
#define LDO1_CONTROL_REG 0x25U
#define LDO2_CONTROL_REG 0x26U
#define LDO3_CONTROL_REG 0x27U
#define LDO4_CONTROL_REG 0x28U
#define LDO5_CONTROL_REG 0x29U
#define LDO6_CONTROL_REG 0x2AU
#define BUCK1_PWRCTRL_REG 0x30U
#define BUCK2_PWRCTRL_REG 0x31U
#define BUCK3_PWRCTRL_REG 0x32U
#define BUCK4_PWRCTRL_REG 0x33U
#define VREF_DDR_PWRCTRL_REG 0x34U
#define LDO1_PWRCTRL_REG 0x35U
#define LDO2_PWRCTRL_REG 0x36U
#define LDO3_PWRCTRL_REG 0x37U
#define LDO4_PWRCTRL_REG 0x38U
#define LDO5_PWRCTRL_REG 0x39U
#define LDO6_PWRCTRL_REG 0x3AU
#define FREQUENCY_SPREADING_REG 0x3BU
#define USB_CONTROL_REG 0x40U
#define ITLATCH1_REG 0x50U
#define ITLATCH2_REG 0x51U
#define ITLATCH3_REG 0x52U
#define ITLATCH4_REG 0x53U
#define ITSETLATCH1_REG 0x60U
#define ITSETLATCH2_REG 0x61U
#define ITSETLATCH3_REG 0x62U
#define ITSETLATCH4_REG 0x63U
#define ITCLEARLATCH1_REG 0x70U
#define ITCLEARLATCH2_REG 0x71U
#define ITCLEARLATCH3_REG 0x72U
#define ITCLEARLATCH4_REG 0x73U
#define ITMASK1_REG 0x80U
#define ITMASK2_REG 0x81U
#define ITMASK3_REG 0x82U
#define ITMASK4_REG 0x83U
#define ITSETMASK1_REG 0x90U
#define ITSETMASK2_REG 0x91U
#define ITSETMASK3_REG 0x92U
#define ITSETMASK4_REG 0x93U
#define ITCLEARMASK1_REG 0xA0U
#define ITCLEARMASK2_REG 0xA1U
#define ITCLEARMASK3_REG 0xA2U
#define ITCLEARMASK4_REG 0xA3U
#define ITSOURCE1_REG 0xB0U
#define ITSOURCE2_REG 0xB1U
#define ITSOURCE3_REG 0xB2U
#define ITSOURCE4_REG 0xB3U
/* Registers masks */
#define LDO_VOLTAGE_MASK GENMASK(6, 2)
#define BUCK_VOLTAGE_MASK GENMASK(7, 2)
#define LDO_BUCK_VOLTAGE_SHIFT 2
#define LDO_BUCK_ENABLE_MASK BIT(0)
#define LDO_BUCK_HPLP_ENABLE_MASK BIT(1)
#define LDO_BUCK_HPLP_SHIFT 1
#define LDO_BUCK_RANK_MASK BIT(0)
#define LDO_BUCK_RESET_MASK BIT(0)
#define LDO_BUCK_PULL_DOWN_MASK GENMASK(1, 0)
/* Pull down register */
#define BUCK1_PULL_DOWN_SHIFT 0
#define BUCK2_PULL_DOWN_SHIFT 2
#define BUCK3_PULL_DOWN_SHIFT 4
#define BUCK4_PULL_DOWN_SHIFT 6
#define VREF_DDR_PULL_DOWN_SHIFT 4
/* ICC register */
#define BUCK1_ICC_SHIFT 0
#define BUCK2_ICC_SHIFT 1
#define BUCK3_ICC_SHIFT 2
#define BUCK4_ICC_SHIFT 3
#define PWR_SW1_ICC_SHIFT 4
#define PWR_SW2_ICC_SHIFT 5
#define BOOST_ICC_SHIFT 6
#define LDO1_ICC_SHIFT 0
#define LDO2_ICC_SHIFT 1
#define LDO3_ICC_SHIFT 2
#define LDO4_ICC_SHIFT 3
#define LDO5_ICC_SHIFT 4
#define LDO6_ICC_SHIFT 5
/* Buck Mask reset register */
#define BUCK1_MASK_RESET 0
#define BUCK2_MASK_RESET 1
#define BUCK3_MASK_RESET 2
#define BUCK4_MASK_RESET 3
/* LDO Mask reset register */
#define LDO1_MASK_RESET 0
#define LDO2_MASK_RESET 1
#define LDO3_MASK_RESET 2
#define LDO4_MASK_RESET 3
#define LDO5_MASK_RESET 4
#define LDO6_MASK_RESET 5
#define VREF_DDR_MASK_RESET 6
/* LDO3 Special modes */
#define LDO3_BYPASS BIT(7)
#define LDO3_DDR_SEL 31U
/* Main PMIC Control Register (MAIN_CONTROL_REG) */
#define ICC_EVENT_ENABLED BIT(4)
#define PWRCTRL_POLARITY_HIGH BIT(3)
#define PWRCTRL_PIN_VALID BIT(2)
#define RESTART_REQUEST_ENABLED BIT(1)
#define SOFTWARE_SWITCH_OFF_ENABLED BIT(0)
/* Main PMIC PADS Control Register (PADS_PULL_REG) */
#define WAKEUP_DETECTOR_DISABLED BIT(4)
#define PWRCTRL_PD_ACTIVE BIT(3)
#define PWRCTRL_PU_ACTIVE BIT(2)
#define WAKEUP_PD_ACTIVE BIT(1)
#define PONKEY_PU_ACTIVE BIT(0)
/* Main PMIC VINLOW Control Register (VIN_CONTROL_REGC DMSC) */
#define SWIN_DETECTOR_ENABLED BIT(7)
#define SWOUT_DETECTOR_ENABLED BIT(6)
#define VINLOW_HYST_MASK GENMASK(1, 0)
#define VINLOW_HYST_SHIFT 4
#define VINLOW_THRESHOLD_MASK GENMASK(2, 0)
#define VINLOW_THRESHOLD_SHIFT 1
#define VINLOW_ENABLED BIT(0)
#define VINLOW_CTRL_REG_MASK GENMASK(7, 0)
/* USB Control Register */
#define BOOST_OVP_DISABLED BIT(7)
#define VBUS_OTG_DETECTION_DISABLED BIT(6)
#define SW_OUT_DISCHARGE BIT(5)
#define VBUS_OTG_DISCHARGE BIT(4)
#define OCP_LIMIT_HIGH BIT(3)
#define SWIN_SWOUT_ENABLED BIT(2)
#define USBSW_OTG_SWITCH_ENABLED BIT(1)
#define BOOST_ENABLED BIT(0)
int stpmic1_powerctrl_on(void);
int stpmic1_switch_off(void);
int stpmic1_register_read(uint8_t register_id, uint8_t *value);
int stpmic1_register_write(uint8_t register_id, uint8_t value);
int stpmic1_register_update(uint8_t register_id, uint8_t value, uint8_t mask);
int stpmic1_regulator_enable(const char *name);
int stpmic1_regulator_disable(const char *name);
bool stpmic1_is_regulator_enabled(const char *name);
int stpmic1_regulator_voltage_set(const char *name, uint16_t millivolts);
int stpmic1_regulator_levels_mv(const char *name, const uint16_t **levels,
size_t *levels_count);
int stpmic1_regulator_voltage_get(const char *name);
int stpmic1_regulator_pull_down_set(const char *name);
int stpmic1_regulator_mask_reset_set(const char *name);
int stpmic1_regulator_icc_set(const char *name);
int stpmic1_regulator_sink_mode_set(const char *name);
int stpmic1_regulator_bypass_mode_set(const char *name);
int stpmic1_active_discharge_mode_set(const char *name);
void stpmic1_bind_i2c(struct i2c_handle_s *i2c_handle, uint16_t i2c_addr);
int stpmic1_get_version(unsigned long *version);
void stpmic1_dump_regulators(void);
#endif /* STPMIC1_H */