GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_BL_COMMON_EXP_H
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#define ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_BL_COMMON_EXP_H
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/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
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#include "ep_info_exp.h"
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#include "tbbr/tbbr_img_def_exp.h"
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/*
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* The following are used for image state attributes.
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* Image can only be in one of the following state.
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*/
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#define IMAGE_STATE_RESET U(0)
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#define IMAGE_STATE_COPIED U(1)
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#define IMAGE_STATE_COPYING U(2)
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#define IMAGE_STATE_AUTHENTICATED U(3)
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#define IMAGE_STATE_EXECUTED U(4)
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#define IMAGE_STATE_INTERRUPTED U(5)
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#define IMAGE_ATTRIB_SKIP_LOADING U(0x02)
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#define IMAGE_ATTRIB_PLAT_SETUP U(0x04)
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#define INVALID_IMAGE_ID U(0xFFFFFFFF)
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#ifndef __ASSEMBLER__
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/*****************************************************************************
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* Image info binary provides information from the image loader that
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* can be used by the firmware to manage available trusted RAM.
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* More advanced firmware image formats can provide additional
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* information that enables optimization or greater flexibility in the
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* common firmware code
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*****************************************************************************/
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typedef struct image_info {
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param_header_t h;
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uintptr_t image_base; /* physical address of base of image */
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uint32_t image_size; /* bytes read from image file */
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uint32_t image_max_size;
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} image_info_t;
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/* BL image node in the BL image execution sequence */
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typedef struct bl_params_node {
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unsigned int image_id;
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image_info_t *image_info;
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entry_point_info_t *ep_info;
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struct bl_params_node *next_params_info;
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} bl_params_node_t;
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/*
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* BL image head node in the BL image execution sequence
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* It is also used to pass information to next BL image.
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*/
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typedef struct bl_params {
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param_header_t h;
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bl_params_node_t *head;
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} bl_params_t;
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/*****************************************************************************
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* The image descriptor struct definition.
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*****************************************************************************/
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typedef struct image_desc {
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/* Contains unique image id for the image. */
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unsigned int image_id;
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/*
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* This member contains Image state information.
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* Refer IMAGE_STATE_XXX defined above.
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*/
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unsigned int state;
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uint32_t copied_size; /* image size copied in blocks */
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image_info_t image_info;
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entry_point_info_t ep_info;
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} image_desc_t;
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/* BL image node in the BL image loading sequence */
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typedef struct bl_load_info_node {
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unsigned int image_id;
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image_info_t *image_info;
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struct bl_load_info_node *next_load_info;
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} bl_load_info_node_t;
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/* BL image head node in the BL image loading sequence */
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typedef struct bl_load_info {
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param_header_t h;
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bl_load_info_node_t *head;
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} bl_load_info_t;
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#endif /* __ASSEMBLER__ */
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#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_BL_COMMON_EXP_H */
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/*
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* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_EP_INFO_EXP_H
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#define ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_EP_INFO_EXP_H
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/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
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#include "../lib/utils_def_exp.h"
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#include "param_header_exp.h"
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/*******************************************************************************
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* Constants that allow assembler code to access members of and the
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* 'entry_point_info' structure at their correct offsets.
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******************************************************************************/
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#define ENTRY_POINT_INFO_PC_OFFSET U(0x08)
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#ifdef __aarch64__
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#define ENTRY_POINT_INFO_ARGS_OFFSET U(0x18)
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#else
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#define ENTRY_POINT_INFO_LR_SVC_OFFSET U(0x10)
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#define ENTRY_POINT_INFO_ARGS_OFFSET U(0x14)
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#endif
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/*
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* Security state of the image. Bit 0 and
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* bit 5 are used to determine the security
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* state of the image as follows:
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*
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* ---------------------------------
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* Bit 5 | Bit 0 | Security state
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* ---------------------------------
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* 0 0 EP_SECURE
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* 0 1 EP_NON_SECURE
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* 1 1 EP_REALM
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*/
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#define EP_SECURITY_MASK UL(0x21)
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#define EP_SECURITY_SHIFT UL(0)
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#define EP_SECURE UL(0x0)
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#define EP_NON_SECURE UL(0x1)
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#define EP_REALM UL(0x21)
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/* Endianness of the image. */
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#define EP_EE_MASK U(0x2)
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#define EP_EE_SHIFT U(1)
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#define EP_EE_LITTLE U(0x0)
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#define EP_EE_BIG U(0x2)
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#define EP_GET_EE(x) ((x) & EP_EE_MASK)
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#define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee))
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/* Enable or disable access to the secure timer from secure images. */
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#define EP_ST_MASK U(0x4)
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#define EP_ST_SHIFT U(2)
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#define EP_ST_DISABLE U(0x0)
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#define EP_ST_ENABLE U(0x4)
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#define EP_GET_ST(x) ((x) & EP_ST_MASK)
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#define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee))
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/* Determine if an image is executable or not. */
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#define EP_EXE_MASK U(0x8)
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#define EP_EXE_SHIFT U(3)
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#define EP_NON_EXECUTABLE U(0x0)
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#define EP_EXECUTABLE U(0x8)
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#define EP_GET_EXE(x) ((x) & EP_EXE_MASK)
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#define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee))
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/* Flag to indicate the first image that is executed. */
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#define EP_FIRST_EXE_MASK U(0x10)
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#define EP_FIRST_EXE_SHIFT U(4)
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#define EP_FIRST_EXE U(0x10)
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#define EP_GET_FIRST_EXE(x) ((x) & EP_FIRST_EXE_MASK)
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#define EP_SET_FIRST_EXE(x, ee) ((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee))
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#ifndef __ASSEMBLER__
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typedef struct aapcs64_params {
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uint64_t arg0;
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uint64_t arg1;
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uint64_t arg2;
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uint64_t arg3;
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uint64_t arg4;
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uint64_t arg5;
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uint64_t arg6;
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uint64_t arg7;
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} aapcs64_params_t;
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typedef struct aapcs32_params {
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uint32_t arg0;
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uint32_t arg1;
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uint32_t arg2;
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uint32_t arg3;
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} aapcs32_params_t;
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/*****************************************************************************
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* This structure represents the superset of information needed while
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* switching exception levels. The only two mechanisms to do so are
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* ERET & SMC. Security state is indicated using bit zero of header
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* attribute
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* NOTE: BL1 expects entrypoint followed by spsr at an offset from the start
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* of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while
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* processing SMC to jump to BL31.
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*****************************************************************************/
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typedef struct entry_point_info {
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param_header_t h;
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uintptr_t pc;
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uint32_t spsr;
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#ifdef __aarch64__
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aapcs64_params_t args;
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#else
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uintptr_t lr_svc;
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aapcs32_params_t args;
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#endif
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} entry_point_info_t;
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#endif /*__ASSEMBLER__*/
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#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_EP_INFO_EXP_H */
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_PARAM_HEADER_EXP_H
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#define ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_PARAM_HEADER_EXP_H
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/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
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#include "../lib/utils_def_exp.h"
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/* Param header types */
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#define PARAM_EP U(0x01)
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#define PARAM_IMAGE_BINARY U(0x02)
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#define PARAM_BL31 U(0x03)
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#define PARAM_BL_LOAD_INFO U(0x04)
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#define PARAM_BL_PARAMS U(0x05)
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#define PARAM_PSCI_LIB_ARGS U(0x06)
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#define PARAM_SP_IMAGE_BOOT_INFO U(0x07)
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/* Param header version */
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#define PARAM_VERSION_1 U(0x01)
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#define PARAM_VERSION_2 U(0x02)
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#ifndef __ASSEMBLER__
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/***************************************************************************
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* This structure provides version information and the size of the
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* structure, attributes for the structure it represents
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***************************************************************************/
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typedef struct param_header {
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uint8_t type; /* type of the structure */
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uint8_t version; /* version of this structure */
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uint16_t size; /* size of this structure in bytes */
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uint32_t attr; /* attributes: unused bits SBZ */
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} param_header_t;
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#endif /*__ASSEMBLER__*/
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#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_PARAM_HEADER_EXP_H */
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/*
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* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_TBBR_TBBR_IMG_DEF_EXP_H
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#define ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_TBBR_TBBR_IMG_DEF_EXP_H
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/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
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#include "../../lib/utils_def_exp.h"
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/* Firmware Image Package */
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#define FIP_IMAGE_ID U(0)
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/* Trusted Boot Firmware BL2 */
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#define BL2_IMAGE_ID U(1)
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/* SCP Firmware SCP_BL2 */
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#define SCP_BL2_IMAGE_ID U(2)
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/* EL3 Runtime Firmware BL31 */
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#define BL31_IMAGE_ID U(3)
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/* Secure Payload BL32 (Trusted OS) */
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#define BL32_IMAGE_ID U(4)
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/* Non-Trusted Firmware BL33 */
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#define BL33_IMAGE_ID U(5)
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/* Certificates */
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#define TRUSTED_BOOT_FW_CERT_ID U(6)
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#define TRUSTED_KEY_CERT_ID U(7)
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#define SCP_FW_KEY_CERT_ID U(8)
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#define SOC_FW_KEY_CERT_ID U(9)
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#define TRUSTED_OS_FW_KEY_CERT_ID U(10)
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#define NON_TRUSTED_FW_KEY_CERT_ID U(11)
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#define SCP_FW_CONTENT_CERT_ID U(12)
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#define SOC_FW_CONTENT_CERT_ID U(13)
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#define TRUSTED_OS_FW_CONTENT_CERT_ID U(14)
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#define NON_TRUSTED_FW_CONTENT_CERT_ID U(15)
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/* Non-Trusted ROM Firmware NS_BL1U */
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#define NS_BL1U_IMAGE_ID U(16)
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/* Trusted FWU Certificate */
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#define FWU_CERT_ID U(17)
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/* Trusted FWU SCP Firmware SCP_BL2U */
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#define SCP_BL2U_IMAGE_ID U(18)
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/* Trusted FWU Boot Firmware BL2U */
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#define BL2U_IMAGE_ID U(19)
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/* Non-Trusted FWU Firmware NS_BL2U */
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#define NS_BL2U_IMAGE_ID U(20)
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/* Secure Payload BL32_EXTRA1 (Trusted OS Extra1) */
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#define BL32_EXTRA1_IMAGE_ID U(21)
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/* Secure Payload BL32_EXTRA2 (Trusted OS Extra2) */
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#define BL32_EXTRA2_IMAGE_ID U(22)
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/* HW_CONFIG (e.g. Kernel DT) */
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#define HW_CONFIG_ID U(23)
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/* TB_FW_CONFIG */
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#define TB_FW_CONFIG_ID U(24)
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/* SOC_FW_CONFIG */
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#define SOC_FW_CONFIG_ID U(25)
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/* TOS_FW_CONFIG */
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#define TOS_FW_CONFIG_ID U(26)
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/* NT_FW_CONFIG */
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#define NT_FW_CONFIG_ID U(27)
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/* GPT Partition */
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#define GPT_IMAGE_ID U(28)
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/* Binary with STM32 header */
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#define STM32_IMAGE_ID U(29)
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/* Encrypted image identifier */
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#define ENC_IMAGE_ID U(30)
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/* FW_CONFIG */
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#define FW_CONFIG_ID U(31)
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/*
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* Primary FWU metadata image ID
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*/
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#define FWU_METADATA_IMAGE_ID U(32)
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/*
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* Backup FWU metadata image ID
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*/
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#define BKUP_FWU_METADATA_IMAGE_ID U(33)
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/* Realm Monitor Manager (RMM) */
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#define RMM_IMAGE_ID U(34)
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/* CCA Content Certificate ID */
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#define CCA_CONTENT_CERT_ID U(35)
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/* Core SWD Key Certificate ID */
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#define CORE_SWD_KEY_CERT_ID U(36)
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/* Platform Key Certificate ID */
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#define PLAT_KEY_CERT_ID U(37)
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/* Max Images */
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#define MAX_IMAGE_IDS U(38)
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#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_TBBR_TBBR_IMG_DEF_EXP_H */
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