GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,105 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef BAKERY_LOCK_H
|
||||
#define BAKERY_LOCK_H
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#define BAKERY_LOCK_MAX_CPUS PLATFORM_CORE_COUNT
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <cdefs.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/*****************************************************************************
|
||||
* Internal helpers used by the bakery lock implementation.
|
||||
****************************************************************************/
|
||||
|
||||
/* Convert a ticket to priority */
|
||||
static inline unsigned int bakery_get_priority(unsigned int t, unsigned int pos)
|
||||
{
|
||||
return (t << 8) | pos;
|
||||
}
|
||||
|
||||
#define CHOOSING_TICKET U(0x1)
|
||||
#define CHOSEN_TICKET U(0x0)
|
||||
|
||||
static inline bool bakery_is_choosing(unsigned int info)
|
||||
{
|
||||
return (info & 1U) == CHOOSING_TICKET;
|
||||
}
|
||||
|
||||
static inline unsigned int bakery_ticket_number(unsigned int info)
|
||||
{
|
||||
return (info >> 1) & 0x7FFFU;
|
||||
}
|
||||
|
||||
static inline uint16_t make_bakery_data(unsigned int choosing, unsigned int num)
|
||||
{
|
||||
unsigned int val = (choosing & 0x1U) | (num << 1);
|
||||
|
||||
return (uint16_t) val;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* External bakery lock interface.
|
||||
****************************************************************************/
|
||||
#if USE_COHERENT_MEM
|
||||
/*
|
||||
* Bakery locks are stored in coherent memory
|
||||
*
|
||||
* Each lock's data is contiguous and fully allocated by the compiler
|
||||
*/
|
||||
|
||||
typedef struct bakery_lock {
|
||||
/*
|
||||
* The lock_data is a bit-field of 2 members:
|
||||
* Bit[0] : choosing. This field is set when the CPU is
|
||||
* choosing its bakery number.
|
||||
* Bits[1 - 15] : number. This is the bakery number allocated.
|
||||
*/
|
||||
volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS];
|
||||
} bakery_lock_t;
|
||||
|
||||
#else
|
||||
/*
|
||||
* Bakery locks are stored in normal .bss memory
|
||||
*
|
||||
* Each lock's data is spread across multiple cache lines, one per CPU,
|
||||
* but multiple locks can share the same cache line.
|
||||
* The compiler will allocate enough memory for one CPU's bakery locks,
|
||||
* the remaining cache lines are allocated by the linker script
|
||||
*/
|
||||
|
||||
typedef struct bakery_info {
|
||||
/*
|
||||
* The lock_data is a bit-field of 2 members:
|
||||
* Bit[0] : choosing. This field is set when the CPU is
|
||||
* choosing its bakery number.
|
||||
* Bits[1 - 15] : number. This is the bakery number allocated.
|
||||
*/
|
||||
volatile uint16_t lock_data;
|
||||
} bakery_info_t;
|
||||
|
||||
typedef bakery_info_t bakery_lock_t;
|
||||
|
||||
#endif /* __USE_COHERENT_MEM__ */
|
||||
|
||||
static inline void bakery_lock_init(bakery_lock_t *bakery) {}
|
||||
void bakery_lock_get(bakery_lock_t *bakery);
|
||||
void bakery_lock_release(bakery_lock_t *bakery);
|
||||
|
||||
#define DEFINE_BAKERY_LOCK(_name) bakery_lock_t _name __section("bakery_lock")
|
||||
|
||||
#define DECLARE_BAKERY_LOCK(_name) extern bakery_lock_t _name
|
||||
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
#endif /* BAKERY_LOCK_H */
|
||||
+30
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef LIB_BL_AUX_PARAMS_H
|
||||
#define LIB_BL_AUX_PARAMS_H
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <export/lib/bl_aux_params/bl_aux_params_exp.h>
|
||||
|
||||
/*
|
||||
* Handler function that handles an individual aux parameter. Return true if
|
||||
* the parameter was handled, and flase if bl_aux_params_parse() should make its
|
||||
* own attempt at handling it (for generic parameters).
|
||||
*/
|
||||
typedef bool (*bl_aux_param_handler_t)(struct bl_aux_param_header *param);
|
||||
|
||||
/*
|
||||
* Interprets head as the start of an aux parameter list, and passes the
|
||||
* parameters individually to handler(). Handles generic parameters directly if
|
||||
* handler() hasn't already done so. If only generic parameters are expected,
|
||||
* handler() can be NULL.
|
||||
*/
|
||||
void bl_aux_params_parse(u_register_t head,
|
||||
bl_aux_param_handler_t handler);
|
||||
|
||||
#endif /* LIB_BL_AUX_PARAMS_H */
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CASSERT_H
|
||||
#define CASSERT_H
|
||||
|
||||
#include <cdefs.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro to flag a compile time assertion. It uses the preprocessor to generate
|
||||
* an invalid C construct if 'cond' evaluates to false.
|
||||
* The following compilation error is triggered if the assertion fails:
|
||||
* "error: size of array 'msg' is negative"
|
||||
* The 'unused' attribute ensures that the unused typedef does not emit a
|
||||
* compiler warning.
|
||||
******************************************************************************/
|
||||
#define CASSERT(cond, msg) \
|
||||
typedef char msg[(cond) ? 1 : -1] __unused
|
||||
|
||||
#endif /* CASSERT_H */
|
||||
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef COREBOOT_H
|
||||
#define COREBOOT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
uint32_t type; /* always 2 (memory-mapped) on ARM */
|
||||
uint32_t baseaddr;
|
||||
uint32_t baud;
|
||||
uint32_t regwidth; /* in bytes, i.e. usually 4 */
|
||||
uint32_t input_hertz;
|
||||
uint32_t uart_pci_addr; /* unused on current ARM systems */
|
||||
} coreboot_serial_t;
|
||||
extern coreboot_serial_t coreboot_serial;
|
||||
|
||||
#define COREBOOT_MAX_MEMRANGES 32 /* libpayload also uses this limit */
|
||||
|
||||
typedef struct __packed {
|
||||
uint64_t start;
|
||||
uint64_t size;
|
||||
uint32_t type;
|
||||
} coreboot_memrange_t;
|
||||
extern coreboot_memrange_t coreboot_memranges[COREBOOT_MAX_MEMRANGES];
|
||||
|
||||
typedef enum {
|
||||
CB_MEM_NONE = 0, /* coreboot will never report this */
|
||||
CB_MEM_RAM = 1,
|
||||
CB_MEM_RESERVED = 2,
|
||||
CB_MEM_ACPI = 3,
|
||||
CB_MEM_NVS = 4,
|
||||
CB_MEM_UNUSABLE = 5,
|
||||
CB_MEM_VENDOR_RSVD = 6,
|
||||
CB_MEM_TABLE = 16,
|
||||
} coreboot_memory_t;
|
||||
|
||||
coreboot_memory_t coreboot_get_memory_type(uintptr_t start, size_t size);
|
||||
void coreboot_table_setup(void *base);
|
||||
|
||||
#endif /* COREBOOT_H */
|
||||
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef AEM_GENERIC_H
|
||||
#define AEM_GENERIC_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* BASE AEM midr for revision 0 */
|
||||
#define BASE_AEM_MIDR U(0x410FD0F0)
|
||||
|
||||
#endif /* AEM_GENERIC_H */
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A12_H
|
||||
#define CORTEX_A12_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Cortex-A12 midr with version/revision set to 0
|
||||
******************************************************************************/
|
||||
#define CORTEX_A12_MIDR U(0x410FC0D0)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A12_ACTLR_SMP_BIT (U(1) << 6)
|
||||
|
||||
#endif /* CORTEX_A12_H */
|
||||
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A15_H
|
||||
#define CORTEX_A15_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Auxiliary Control Register 2 specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A15_ACTLR2 p15, 1, c15, c0, 4
|
||||
|
||||
#define CORTEX_A15_ACTLR2_INV_DCC_BIT (U(1) << 0)
|
||||
|
||||
/*******************************************************************************
|
||||
* Cortex-A15 midr with version/revision set to 0
|
||||
******************************************************************************/
|
||||
#define CORTEX_A15_MIDR U(0x410FC0F0)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A15_ACTLR_INV_BTB_BIT (U(1) << 0)
|
||||
#define CORTEX_A15_ACTLR_SMP_BIT (U(1) << 6)
|
||||
|
||||
#endif /* CORTEX_A15_H */
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A17_H
|
||||
#define CORTEX_A17_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Cortex-A17 midr with version/revision set to 0
|
||||
******************************************************************************/
|
||||
#define CORTEX_A17_MIDR U(0x410FC0E0)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A17_ACTLR_SMP_BIT (U(1) << 6)
|
||||
|
||||
/*******************************************************************************
|
||||
* Implementation defined register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A17_IMP_DEF_REG1 p15, 0, c15, c0, 1
|
||||
|
||||
#endif /* CORTEX_A17_H */
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A32_H
|
||||
#define CORTEX_A32_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A32 Main ID register for revision 0 */
|
||||
#define CORTEX_A32_MIDR U(0x410FD010)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
* CPUECTLR_EL1 is an implementation-specific register.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A32_CPUECTLR_EL1 p15, 1, c15
|
||||
#define CORTEX_A32_CPUECTLR_SMPEN_BIT (ULL(1) << 6)
|
||||
|
||||
#endif /* CORTEX_A32_H */
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A5_H
|
||||
#define CORTEX_A5_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Cortex-A8 midr with version/revision set to 0
|
||||
******************************************************************************/
|
||||
#define CORTEX_A5_MIDR U(0x410FC050)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A5_ACTLR_SMP_BIT (U(1) << 6)
|
||||
|
||||
#endif /* CORTEX_A5_H */
|
||||
@@ -0,0 +1,73 @@
|
||||
/*
|
||||
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A53_H
|
||||
#define CORTEX_A53_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A53 midr for revision 0 */
|
||||
#define CORTEX_A53_MIDR U(0x410FD030)
|
||||
|
||||
/* Retention timer tick definitions */
|
||||
#define RETENTION_ENTRY_TICKS_2 U(0x1)
|
||||
#define RETENTION_ENTRY_TICKS_8 U(0x2)
|
||||
#define RETENTION_ENTRY_TICKS_32 U(0x3)
|
||||
#define RETENTION_ENTRY_TICKS_64 U(0x4)
|
||||
#define RETENTION_ENTRY_TICKS_128 U(0x5)
|
||||
#define RETENTION_ENTRY_TICKS_256 U(0x6)
|
||||
#define RETENTION_ENTRY_TICKS_512 U(0x7)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A53_ECTLR p15, 1, c15
|
||||
|
||||
#define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6)
|
||||
|
||||
#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0)
|
||||
#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
|
||||
|
||||
#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3)
|
||||
#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A53_MERRSR p15, 2, c15
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A53_CPUACTLR p15, 0, c15
|
||||
|
||||
#define CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT U(44)
|
||||
#define CORTEX_A53_CPUACTLR_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT)
|
||||
#define CORTEX_A53_CPUACTLR_DTAH_SHIFT U(24)
|
||||
#define CORTEX_A53_CPUACTLR_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_DTAH_SHIFT)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A53_L2ACTLR p15, 1, c15, c0, 0
|
||||
|
||||
#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14)
|
||||
#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A53_L2ECTLR p15, 1, c9, c0, 3
|
||||
|
||||
#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0)
|
||||
#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A53_L2MERRSR p15, 3, c15
|
||||
|
||||
#endif /* CORTEX_A53_H */
|
||||
@@ -0,0 +1,84 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A57_H
|
||||
#define CORTEX_A57_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A57 midr for revision 0 */
|
||||
#define CORTEX_A57_MIDR U(0x410FD070)
|
||||
|
||||
/* Retention timer tick definitions */
|
||||
#define RETENTION_ENTRY_TICKS_2 U(0x1)
|
||||
#define RETENTION_ENTRY_TICKS_8 U(0x2)
|
||||
#define RETENTION_ENTRY_TICKS_32 U(0x3)
|
||||
#define RETENTION_ENTRY_TICKS_64 U(0x4)
|
||||
#define RETENTION_ENTRY_TICKS_128 U(0x5)
|
||||
#define RETENTION_ENTRY_TICKS_256 U(0x6)
|
||||
#define RETENTION_ENTRY_TICKS_512 U(0x7)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A57_ECTLR p15, 1, c15
|
||||
|
||||
#define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)
|
||||
#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
|
||||
#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
|
||||
#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
|
||||
|
||||
#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0)
|
||||
#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A57_CPUMERRSR p15, 2, c15
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A57_CPUACTLR p15, 0, c15
|
||||
|
||||
#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59)
|
||||
#define CORTEX_A57_CPUACTLR_DIS_DMB_NULLIFICATION (ULL(1) << 58)
|
||||
#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55)
|
||||
#define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
|
||||
#define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52)
|
||||
#define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
|
||||
#define CORTEX_A57_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
|
||||
#define CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38)
|
||||
#define CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32)
|
||||
#define CORTEX_A57_CPUACTLR_DIS_STREAMING (ULL(3) << 27)
|
||||
#define CORTEX_A57_CPUACTLR_DIS_L1_STREAMING (ULL(3) << 25)
|
||||
#define CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2
|
||||
|
||||
#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
|
||||
#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
|
||||
|
||||
#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
|
||||
#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3
|
||||
|
||||
#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0)
|
||||
#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A57_L2MERRSR p15, 3, c15
|
||||
|
||||
#endif /* CORTEX_A57_H */
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A7_H
|
||||
#define CORTEX_A7_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Cortex-A7 midr with version/revision set to 0
|
||||
******************************************************************************/
|
||||
#define CORTEX_A7_MIDR U(0x410FC070)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A7_ACTLR_SMP_BIT (U(1) << 6)
|
||||
|
||||
#endif /* CORTEX_A7_H */
|
||||
@@ -0,0 +1,58 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A72_H
|
||||
#define CORTEX_A72_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A72 midr for revision 0 */
|
||||
#define CORTEX_A72_MIDR U(0x410FD080)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_ECTLR p15, 1, c15
|
||||
|
||||
#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
|
||||
#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
|
||||
#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
|
||||
#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_MERRSR p15, 2, c15
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_CPUACTLR p15, 0, c15
|
||||
|
||||
#define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
|
||||
#define CORTEX_A72_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55)
|
||||
#define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
|
||||
#define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
|
||||
#define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2
|
||||
|
||||
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
|
||||
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
|
||||
|
||||
#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
|
||||
#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1)
|
||||
#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_L2MERRSR p15, 3, c15
|
||||
|
||||
#endif /* CORTEX_A72_H */
|
||||
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A9_H
|
||||
#define CORTEX_A9_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Cortex-A9 midr with version/revision set to 0
|
||||
******************************************************************************/
|
||||
#define CORTEX_A9_MIDR U(0x410FC090)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A9_ACTLR_SMP_BIT (U(1) << 6)
|
||||
#define CORTEX_A9_ACTLR_FLZW_BIT (U(1) << 3)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control Register
|
||||
******************************************************************************/
|
||||
#define PCR p15, 0, c15, c0, 0
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <arch_helpers.h>
|
||||
DEFINE_COPROCR_RW_FUNCS(pcr, PCR)
|
||||
#endif
|
||||
|
||||
#endif /* CORTEX_A9_H */
|
||||
@@ -0,0 +1,230 @@
|
||||
/*
|
||||
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef CPU_MACROS_S
|
||||
#define CPU_MACROS_S
|
||||
|
||||
#include <arch.h>
|
||||
#include <lib/cpus/errata_report.h>
|
||||
|
||||
#if defined(IMAGE_BL1) || defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3)
|
||||
#define IMAGE_AT_EL3
|
||||
#endif
|
||||
|
||||
#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
|
||||
(MIDR_PN_MASK << MIDR_PN_SHIFT)
|
||||
|
||||
/* The number of CPU operations allowed */
|
||||
#define CPU_MAX_PWR_DWN_OPS 2
|
||||
|
||||
/* Special constant to specify that CPU has no reset function */
|
||||
#define CPU_NO_RESET_FUNC 0
|
||||
|
||||
/* Word size for 32-bit CPUs */
|
||||
#define CPU_WORD_SIZE 4
|
||||
|
||||
/*
|
||||
* Whether errata status needs reporting. Errata status is printed in debug
|
||||
* builds for both BL1 and BL32 images.
|
||||
*/
|
||||
#if (defined(IMAGE_BL1) || defined(IMAGE_BL32)) && DEBUG
|
||||
# define REPORT_ERRATA 1
|
||||
#else
|
||||
# define REPORT_ERRATA 0
|
||||
#endif
|
||||
|
||||
|
||||
.equ CPU_MIDR_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS
|
||||
.equ CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_ERRATA_LOCK_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_ERRATA_PRINTED_SIZE, CPU_WORD_SIZE
|
||||
|
||||
#ifndef IMAGE_AT_EL3
|
||||
.equ CPU_RESET_FUNC_SIZE, 0
|
||||
#endif
|
||||
|
||||
/* The power down core and cluster is needed only in BL32 */
|
||||
#ifndef IMAGE_BL32
|
||||
.equ CPU_PWR_DWN_OPS_SIZE, 0
|
||||
#endif
|
||||
|
||||
/* Fields required to print errata status */
|
||||
#if !REPORT_ERRATA
|
||||
.equ CPU_ERRATA_FUNC_SIZE, 0
|
||||
#endif
|
||||
|
||||
/* Only BL32 requires mutual exclusion and printed flag. */
|
||||
#if !(REPORT_ERRATA && defined(IMAGE_BL32))
|
||||
.equ CPU_ERRATA_LOCK_SIZE, 0
|
||||
.equ CPU_ERRATA_PRINTED_SIZE, 0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Define the offsets to the fields in cpu_ops structure.
|
||||
* Every offset is defined based on the offset and size of the previous
|
||||
* field.
|
||||
*/
|
||||
.equ CPU_MIDR, 0
|
||||
.equ CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE
|
||||
.equ CPU_PWR_DWN_OPS, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
|
||||
.equ CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE
|
||||
.equ CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE
|
||||
.equ CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE
|
||||
.equ CPU_OPS_SIZE, CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE
|
||||
|
||||
/*
|
||||
* Write given expressions as words
|
||||
*
|
||||
* _count:
|
||||
* Write at least _count words. If the given number of expressions
|
||||
* is less than _count, repeat the last expression to fill _count
|
||||
* words in total
|
||||
* _rest:
|
||||
* Optional list of expressions. _this is for parameter extraction
|
||||
* only, and has no significance to the caller
|
||||
*
|
||||
* Invoked as:
|
||||
* fill_constants 2, foo, bar, blah, ...
|
||||
*/
|
||||
.macro fill_constants _count:req, _this, _rest:vararg
|
||||
.ifgt \_count
|
||||
/* Write the current expression */
|
||||
.ifb \_this
|
||||
.error "Nothing to fill"
|
||||
.endif
|
||||
.word \_this
|
||||
|
||||
/* Invoke recursively for remaining expressions */
|
||||
.ifnb \_rest
|
||||
fill_constants \_count-1, \_rest
|
||||
.else
|
||||
fill_constants \_count-1, \_this
|
||||
.endif
|
||||
.endif
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Declare CPU operations
|
||||
*
|
||||
* _name:
|
||||
* Name of the CPU for which operations are being specified
|
||||
* _midr:
|
||||
* Numeric value expected to read from CPU's MIDR
|
||||
* _resetfunc:
|
||||
* Reset function for the CPU. If there's no CPU reset function,
|
||||
* specify CPU_NO_RESET_FUNC
|
||||
* _power_down_ops:
|
||||
* Comma-separated list of functions to perform power-down
|
||||
* operatios on the CPU. At least one, and up to
|
||||
* CPU_MAX_PWR_DWN_OPS number of functions may be specified.
|
||||
* Starting at power level 0, these functions shall handle power
|
||||
* down at subsequent power levels. If there aren't exactly
|
||||
* CPU_MAX_PWR_DWN_OPS functions, the last specified one will be
|
||||
* used to handle power down at subsequent levels
|
||||
*/
|
||||
.macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
|
||||
_power_down_ops:vararg
|
||||
.section cpu_ops, "a"
|
||||
.align 2
|
||||
.type cpu_ops_\_name, %object
|
||||
.word \_midr
|
||||
#if defined(IMAGE_AT_EL3)
|
||||
.word \_resetfunc
|
||||
#endif
|
||||
#ifdef IMAGE_BL32
|
||||
/* Insert list of functions */
|
||||
fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops
|
||||
#endif
|
||||
|
||||
#if REPORT_ERRATA
|
||||
.ifndef \_name\()_cpu_str
|
||||
/*
|
||||
* Place errata reported flag, and the spinlock to arbitrate access to
|
||||
* it in the data section.
|
||||
*/
|
||||
.pushsection .data
|
||||
define_asm_spinlock \_name\()_errata_lock
|
||||
\_name\()_errata_reported:
|
||||
.word 0
|
||||
.popsection
|
||||
|
||||
/* Place CPU string in rodata */
|
||||
.pushsection .rodata
|
||||
\_name\()_cpu_str:
|
||||
.asciz "\_name"
|
||||
.popsection
|
||||
.endif
|
||||
|
||||
/*
|
||||
* Mandatory errata status printing function for CPUs of
|
||||
* this class.
|
||||
*/
|
||||
.word \_name\()_errata_report
|
||||
|
||||
#ifdef IMAGE_BL32
|
||||
/* Pointers to errata lock and reported flag */
|
||||
.word \_name\()_errata_lock
|
||||
.word \_name\()_errata_reported
|
||||
#endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
#if REPORT_ERRATA
|
||||
/*
|
||||
* Print status of a CPU errata
|
||||
*
|
||||
* _chosen:
|
||||
* Identifier indicating whether or not a CPU errata has been
|
||||
* compiled in.
|
||||
* _cpu:
|
||||
* Name of the CPU
|
||||
* _id:
|
||||
* Errata identifier
|
||||
* _rev_var:
|
||||
* Register containing the combined value CPU revision and variant
|
||||
* - typically the return value of cpu_get_rev_var
|
||||
*/
|
||||
.macro report_errata _chosen, _cpu, _id, _rev_var=r4
|
||||
/* Stash a string with errata ID */
|
||||
.pushsection .rodata
|
||||
\_cpu\()_errata_\_id\()_str:
|
||||
.asciz "\_id"
|
||||
.popsection
|
||||
|
||||
/* Check whether errata applies */
|
||||
mov r0, \_rev_var
|
||||
bl check_errata_\_id
|
||||
|
||||
.ifeq \_chosen
|
||||
/*
|
||||
* Errata workaround has not been compiled in. If the errata would have
|
||||
* applied had it been compiled in, print its status as missing.
|
||||
*/
|
||||
cmp r0, #0
|
||||
movne r0, #ERRATA_MISSING
|
||||
.endif
|
||||
ldr r1, =\_cpu\()_cpu_str
|
||||
ldr r2, =\_cpu\()_errata_\_id\()_str
|
||||
bl errata_print_msg
|
||||
.endm
|
||||
#endif
|
||||
/*
|
||||
* Helper macro that reads the part number of the current CPU and jumps
|
||||
* to the given label if it matches the CPU MIDR provided.
|
||||
*
|
||||
* Clobbers: r0-r1
|
||||
*/
|
||||
.macro jump_if_cpu_midr _cpu_midr, _label
|
||||
ldcopr r0, MIDR
|
||||
ubfx r0, r0, #MIDR_PN_SHIFT, #12
|
||||
ldr r1, =((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
|
||||
cmp r0, r1
|
||||
beq \_label
|
||||
.endm
|
||||
|
||||
#endif /* CPU_MACROS_S */
|
||||
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright (c) 2022, Fujitsu Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef A64FX_H
|
||||
#define A64FX_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* A64FX midr for revision 0 */
|
||||
#define A64FX_MIDR U(0x461f0010)
|
||||
|
||||
#endif /* A64FX_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef AEM_GENERIC_H
|
||||
#define AEM_GENERIC_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* BASE AEM midr for revision 0 */
|
||||
#define BASE_AEM_MIDR U(0x410FD0F0)
|
||||
|
||||
/* Foundation AEM midr for revision 0 */
|
||||
#define FOUNDATION_AEM_MIDR U(0x410FD000)
|
||||
|
||||
#endif /* AEM_GENERIC_H */
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A35_H
|
||||
#define CORTEX_A35_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A35 Main ID register for revision 0 */
|
||||
#define CORTEX_A35_MIDR U(0x410FD040)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
* CPUECTLR_EL1 is an implementation-specific register.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1
|
||||
#define CORTEX_A35_CPUECTLR_SMPEN_BIT (ULL(1) << 6)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A35_CPUACTLR_EL1 S3_1_C15_C2_0
|
||||
|
||||
#define CORTEX_A35_CPUACTLR_EL1_ENDCCASCI (ULL(1) << 44)
|
||||
|
||||
#endif /* CORTEX_A35_H */
|
||||
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* Copyright (c) 2022, ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A510_H
|
||||
#define CORTEX_A510_H
|
||||
|
||||
#define CORTEX_A510_MIDR U(0x410FD460)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19)
|
||||
#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1)
|
||||
#define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23)
|
||||
#define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46)
|
||||
#define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2)
|
||||
#define CORTEX_A510_CPUECTLR_EL1_ATOM U(38)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
/*******************************************************************************
|
||||
* Complex auxiliary control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3
|
||||
|
||||
/*******************************************************************************
|
||||
* Auxiliary control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
#define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17)
|
||||
#define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38)
|
||||
|
||||
#endif /* CORTEX_A510_H */
|
||||
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A53_H
|
||||
#define CORTEX_A53_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A53 midr for revision 0 */
|
||||
#define CORTEX_A53_MIDR U(0x410FD030)
|
||||
|
||||
/* Retention timer tick definitions */
|
||||
#define RETENTION_ENTRY_TICKS_2 U(0x1)
|
||||
#define RETENTION_ENTRY_TICKS_8 U(0x2)
|
||||
#define RETENTION_ENTRY_TICKS_32 U(0x3)
|
||||
#define RETENTION_ENTRY_TICKS_64 U(0x4)
|
||||
#define RETENTION_ENTRY_TICKS_128 U(0x5)
|
||||
#define RETENTION_ENTRY_TICKS_256 U(0x6)
|
||||
#define RETENTION_ENTRY_TICKS_512 U(0x7)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1
|
||||
|
||||
#define CORTEX_A53_ECTLR_SMP_BIT (ULL(1) << 6)
|
||||
|
||||
#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0)
|
||||
#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
|
||||
|
||||
#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3)
|
||||
#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A53_MERRSR_EL1 S3_1_C15_C2_2
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A53_CPUACTLR_EL1 S3_1_C15_C2_0
|
||||
|
||||
#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT U(44)
|
||||
#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT)
|
||||
#define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT U(27)
|
||||
#define CORTEX_A53_CPUACTLR_EL1_RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT)
|
||||
#define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT U(25)
|
||||
#define CORTEX_A53_CPUACTLR_EL1_L1RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT)
|
||||
#define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT U(24)
|
||||
#define CORTEX_A53_CPUACTLR_EL1_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT)
|
||||
#define CORTEX_A53_CPUACTLR_EL1_L1PCTL_SHIFT U(13)
|
||||
#define CORTEX_A53_CPUACTLR_EL1_L1PCTL (ULL(7) << CORTEX_A53_CPUACTLR_EL1_L1PCTL_SHIFT)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0
|
||||
|
||||
#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14)
|
||||
#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3)
|
||||
/*******************************************************************************
|
||||
* L2 Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3
|
||||
|
||||
#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0)
|
||||
#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3
|
||||
|
||||
/*******************************************************************************
|
||||
* Helper function to access a53_cpuectlr_el1 register on Cortex-A53 CPUs
|
||||
******************************************************************************/
|
||||
#ifndef __ASSEMBLER__
|
||||
DEFINE_RENAME_SYSREG_RW_FUNCS(a53_cpuectlr_el1, CORTEX_A53_ECTLR_EL1)
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* CORTEX_A53_H */
|
||||
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A55_H
|
||||
#define CORTEX_A55_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A55 MIDR for revision 0 */
|
||||
#define CORTEX_A55_MIDR U(0x410fd050)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
#define CORTEX_A55_CPUECTLR_EL1_L1WSCTL (ULL(3) << 25)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A55_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
|
||||
#define CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING (ULL(1) << 24)
|
||||
#define CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE (ULL(1) << 31)
|
||||
#define CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS (ULL(1) << 49)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Identification register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A55_CLIDR_EL1 S3_1_C0_C0_1
|
||||
|
||||
#define CORTEX_A55_CLIDR_EL1_CTYPE3 (ULL(7) << 6)
|
||||
|
||||
/* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */
|
||||
#define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1)
|
||||
|
||||
/* Instruction patching registers */
|
||||
#define CPUPSELR_EL3 S3_6_C15_C8_0
|
||||
#define CPUPCR_EL3 S3_6_C15_C8_1
|
||||
#define CPUPOR_EL3 S3_6_C15_C8_2
|
||||
#define CPUPMR_EL3 S3_6_C15_C8_3
|
||||
|
||||
#endif /* CORTEX_A55_H */
|
||||
@@ -0,0 +1,88 @@
|
||||
/*
|
||||
* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A57_H
|
||||
#define CORTEX_A57_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A57 midr for revision 0 */
|
||||
#define CORTEX_A57_MIDR U(0x410FD070)
|
||||
|
||||
/* Retention timer tick definitions */
|
||||
#define RETENTION_ENTRY_TICKS_2 U(0x1)
|
||||
#define RETENTION_ENTRY_TICKS_8 U(0x2)
|
||||
#define RETENTION_ENTRY_TICKS_32 U(0x3)
|
||||
#define RETENTION_ENTRY_TICKS_64 U(0x4)
|
||||
#define RETENTION_ENTRY_TICKS_128 U(0x5)
|
||||
#define RETENTION_ENTRY_TICKS_256 U(0x6)
|
||||
#define RETENTION_ENTRY_TICKS_512 U(0x7)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1
|
||||
|
||||
#define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)
|
||||
#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
|
||||
#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
|
||||
#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
|
||||
|
||||
#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0)
|
||||
#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A57_MERRSR_EL1 S3_1_C15_C2_2
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0
|
||||
|
||||
#define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION (ULL(1) << 58)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD (ULL(1) << 24)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2
|
||||
|
||||
#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
|
||||
#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
|
||||
|
||||
#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
|
||||
#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
|
||||
|
||||
#define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A57_L2ECTLR_EL1 S3_1_C11_C0_3
|
||||
|
||||
#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0)
|
||||
#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3
|
||||
|
||||
#endif /* CORTEX_A57_H */
|
||||
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (c) 2019, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A65_H
|
||||
#define CORTEX_A65_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#define CORTEX_A65_MIDR U(0x410FD060)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A65_ECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A65_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
|
||||
#define CORTEX_A65_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
|
||||
|
||||
#endif /* CORTEX_A65_H */
|
||||
+31
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (c) 2019, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A65AE_H
|
||||
#define CORTEX_A65AE_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#define CORTEX_A65AE_MIDR U(0x410FD430)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A65AE_ECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A65AE_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
|
||||
#define CORTEX_A65AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
|
||||
|
||||
#endif /* CORTEX_A65AE_H */
|
||||
@@ -0,0 +1,65 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A710_H
|
||||
#define CORTEX_A710_H
|
||||
|
||||
#define CORTEX_A710_MIDR U(0x410FD470)
|
||||
|
||||
/* Cortex-A710 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_A710_BHB_LOOP_COUNT U(32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
#define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
#define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
|
||||
#define CORTEX_A710_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register 2 specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A710_CPUACTLR2_EL1 S3_0_C15_C1_1
|
||||
#define CORTEX_A710_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
|
||||
#define CORTEX_A710_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register 5 specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0
|
||||
#define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
|
||||
#define CORTEX_A710_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
|
||||
#define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A710_CPUECTLR2_EL1 S3_0_C15_C1_5
|
||||
#define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
|
||||
#define CPUECTLR2_EL1_PF_MODE_LSB U(11)
|
||||
#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Selected Instruction Private register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A710_CPUPSELR_EL3 S3_6_C15_C8_0
|
||||
#define CORTEX_A710_CPUPCR_EL3 S3_6_C15_C8_1
|
||||
#define CORTEX_A710_CPUPOR_EL3 S3_6_C15_C8_2
|
||||
#define CORTEX_A710_CPUPMR_EL3 S3_6_C15_C8_3
|
||||
|
||||
#endif /* CORTEX_A710_H */
|
||||
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A72_H
|
||||
#define CORTEX_A72_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A72 midr for revision 0 */
|
||||
#define CORTEX_A72_MIDR U(0x410FD080)
|
||||
|
||||
/* Cortex-A72 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_A72_BHB_LOOP_COUNT U(8)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1
|
||||
|
||||
#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
|
||||
#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
|
||||
#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
|
||||
#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_CPUACTLR_EL1 S3_1_C15_C2_0
|
||||
|
||||
#define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
|
||||
#define CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55)
|
||||
#define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
|
||||
#define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
|
||||
#define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0
|
||||
|
||||
#define CORTEX_A72_L2ACTLR_FORCE_TAG_BANK_CLK_ACTIVE (ULL(1) << 28)
|
||||
#define CORTEX_A72_L2ACTLR_FORCE_L2_LOGIC_CLK_ACTIVE (ULL(1) << 27)
|
||||
#define CORTEX_A72_L2ACTLR_FORCE_L2_GIC_TIMER_RCG_CLK_ACTIVE (ULL(1) << 26)
|
||||
#define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN (ULL(1) << 14)
|
||||
#define CORTEX_A72_L2ACTLR_DISABLE_DSB_WITH_NO_DVM_SYNC (ULL(1) << 11)
|
||||
#define CORTEX_A72_L2ACTLR_DISABLE_DVM_CMO_BROADCAST (ULL(1) << 8)
|
||||
#define CORTEX_A72_L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT (ULL(1) << 7)
|
||||
#define CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI (ULL(1) << 6)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
|
||||
|
||||
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
|
||||
#define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT U(5)
|
||||
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
|
||||
#define CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT U(9)
|
||||
|
||||
#define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK U(0x7)
|
||||
#define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK U(0x7)
|
||||
#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
|
||||
#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1)
|
||||
#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3
|
||||
|
||||
#endif /* CORTEX_A72_H */
|
||||
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A73_H
|
||||
#define CORTEX_A73_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A73 midr for revision 0 */
|
||||
#define CORTEX_A73_MIDR U(0x410FD090)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A73_CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */
|
||||
|
||||
#define CORTEX_A73_CPUECTLR_SMP_BIT (ULL(1) << 6)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A73_L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU implementation defined register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A73_IMP_DEF_REG1 S3_0_C15_C0_0
|
||||
|
||||
#define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (ULL(1) << 3)
|
||||
|
||||
#define CORTEX_A73_DIAGNOSTIC_REGISTER S3_0_C15_C0_1
|
||||
|
||||
#define CORTEX_A73_IMP_DEF_REG2 S3_0_C15_C0_2
|
||||
|
||||
/*******************************************************************************
|
||||
* Helper function to access a73_cpuectlr_el1 register on Cortex-A73 CPUs
|
||||
******************************************************************************/
|
||||
#ifndef __ASSEMBLER__
|
||||
DEFINE_RENAME_SYSREG_RW_FUNCS(a73_cpuectlr_el1, CORTEX_A73_CPUECTLR_EL1)
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* CORTEX_A73_H */
|
||||
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A75_H
|
||||
#define CORTEX_A75_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A75 MIDR */
|
||||
#define CORTEX_A75_MIDR U(0x410fd0a0)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A75_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_A75_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A75_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
|
||||
#define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 35)
|
||||
|
||||
/* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */
|
||||
#define CORTEX_A75_CORE_PWRDN_EN_MASK U(0x1)
|
||||
|
||||
#define CORTEX_A75_ACTLR_AMEN_BIT (ULL(1) << 4)
|
||||
|
||||
/*
|
||||
* The Cortex-A75 core implements five counters, 0-4. Events 0, 1, 2, are
|
||||
* fixed and are enabled (Group 0). Events 3 and 4 (Group 1) are
|
||||
* programmable by programming the appropriate Event count bits in
|
||||
* CPUAMEVTYPER<n> register and are disabled by default. Platforms may
|
||||
* enable this with suitable programming.
|
||||
*/
|
||||
#define CORTEX_A75_AMU_NR_COUNTERS U(5)
|
||||
#define CORTEX_A75_AMU_GROUP0_MASK U(0x7)
|
||||
#define CORTEX_A75_AMU_GROUP1_MASK (U(0) << 3)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <stdint.h>
|
||||
|
||||
uint64_t cortex_a75_amu_cnt_read(int idx);
|
||||
void cortex_a75_amu_cnt_write(int idx, uint64_t val);
|
||||
unsigned int cortex_a75_amu_read_cpuamcntenset_el0(void);
|
||||
unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void);
|
||||
void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask);
|
||||
void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask);
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* CORTEX_A75_H */
|
||||
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A76_H
|
||||
#define CORTEX_A76_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A76 MIDR for revision 0 */
|
||||
#define CORTEX_A76_MIDR U(0x410fd0b0)
|
||||
|
||||
/* Cortex-A76 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_A76_BHB_LOOP_COUNT U(24)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24)
|
||||
#define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A76_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
|
||||
#define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6)
|
||||
|
||||
#define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
|
||||
|
||||
#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1
|
||||
|
||||
#define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
|
||||
|
||||
#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16)
|
||||
|
||||
#define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2
|
||||
|
||||
#define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10)
|
||||
|
||||
|
||||
/* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */
|
||||
#define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1)
|
||||
|
||||
#endif /* CORTEX_A76_H */
|
||||
+28
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A76AE_H
|
||||
#define CORTEX_A76AE_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A76AE MIDR for revision 0 */
|
||||
#define CORTEX_A76AE_MIDR U(0x410FD0E0)
|
||||
|
||||
/* Cortex-A76 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_A76AE_BHB_LOOP_COUNT U(24)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A76AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
|
||||
/* Definitions of register field mask in CORTEX_A76AE_CPUPWRCTLR_EL1 */
|
||||
#define CORTEX_A76AE_CORE_PWRDN_EN_MASK U(0x1)
|
||||
|
||||
#define CORTEX_A76AE_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
#endif /* CORTEX_A76AE_H */
|
||||
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A77_H
|
||||
#define CORTEX_A77_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A77 MIDR */
|
||||
#define CORTEX_A77_MIDR U(0x410FD0D0)
|
||||
|
||||
/* Cortex-A77 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_A77_BHB_LOOP_COUNT U(24)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
#define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
|
||||
#define CORTEX_A77_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A77_ACTLR2_EL1 S3_0_C15_C1_1
|
||||
#define CORTEX_A77_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
|
||||
#define CORTEX_A77_ACTLR2_EL1_BIT_0 ULL(1)
|
||||
|
||||
#define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0
|
||||
#define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1
|
||||
#define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2
|
||||
#define CORTEX_A77_CPUPMR_EL3 S3_6_C15_C8_3
|
||||
#define CORTEX_A77_CPUPOR2_EL3 S3_6_C15_C8_4
|
||||
#define CORTEX_A77_CPUPMR2_EL3 S3_6_C15_C8_5
|
||||
|
||||
#endif /* CORTEX_A77_H */
|
||||
@@ -0,0 +1,58 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2023, ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A78_H
|
||||
#define CORTEX_A78_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#define CORTEX_A78_MIDR U(0x410FD410)
|
||||
|
||||
/* Cortex-A78 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_A78_BHB_LOOP_COUNT U(32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
#define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
|
||||
#define CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)
|
||||
#define CPUECTLR_EL1_PF_MODE_LSB U(6)
|
||||
#define CPUECTLR_EL1_PF_MODE_WIDTH U(2)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
|
||||
|
||||
#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
|
||||
#define CORTEX_A78_ACTLR2_EL1_BIT_0 (ULL(1) << 0)
|
||||
#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
|
||||
#define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
|
||||
#define CORTEX_A78_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
|
||||
|
||||
#define CORTEX_A78_ACTLR3_EL1 S3_0_C15_C1_2
|
||||
|
||||
#define CORTEX_A78_ACTLR5_EL1 S3_0_C15_C9_0
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Activity Monitor Unit register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
|
||||
#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
|
||||
#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
|
||||
#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
|
||||
|
||||
#define CORTEX_A78_AMU_GROUP0_MASK U(0xF)
|
||||
#define CORTEX_A78_AMU_GROUP1_MASK U(0x7)
|
||||
|
||||
#endif /* CORTEX_A78_H */
|
||||
+31
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2022, ARM Limited. All rights reserved.
|
||||
* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A78_AE_H
|
||||
#define CORTEX_A78_AE_H
|
||||
|
||||
#include <cortex_a78.h>
|
||||
|
||||
#define CORTEX_A78_AE_MIDR U(0x410FD420)
|
||||
|
||||
/* Cortex-A78AE loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_A78_AE_BHB_LOOP_COUNT U(32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A78_AE_CPUECTLR_EL1 CORTEX_A78_CPUECTLR_EL1
|
||||
#define CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 CORTEX_A78_CPUECTLR_EL1_BIT_8
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register 2 specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A78_AE_ACTLR2_EL1 CORTEX_A78_ACTLR2_EL1
|
||||
#define CORTEX_A78_AE_ACTLR2_EL1_BIT_0 CORTEX_A78_ACTLR2_EL1_BIT_0
|
||||
#define CORTEX_A78_AE_ACTLR2_EL1_BIT_40 CORTEX_A78_ACTLR2_EL1_BIT_40
|
||||
|
||||
#endif /* CORTEX_A78_AE_H */
|
||||
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A78C_H
|
||||
#define CORTEX_A78C_H
|
||||
|
||||
|
||||
#define CORTEX_A78C_MIDR U(0x410FD4B1)
|
||||
|
||||
/* Cortex-A76 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_A78C_BHB_LOOP_COUNT U(32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register 2 specific definitions.
|
||||
* ****************************************************************************/
|
||||
#define CORTEX_A78C_CPUACTLR2_EL1 S3_0_C15_C1_1
|
||||
#define CORTEX_A78C_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
|
||||
#define CORTEX_A78C_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
#define CORTEX_A78C_CPUECTLR_EL1_BIT_6 (ULL(1) << 6)
|
||||
#define CORTEX_A78C_CPUECTLR_EL1_BIT_7 (ULL(1) << 7)
|
||||
#define CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN (ULL(1) << 53)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A78C_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register 3 specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A78C_ACTLR3_EL1 S3_0_C15_C1_2
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Implementation Specific Selected Instruction registers
|
||||
******************************************************************************/
|
||||
#define CORTEX_A78C_IMP_CPUPSELR_EL3 S3_6_C15_C8_0
|
||||
#define CORTEX_A78C_IMP_CPUPCR_EL3 S3_6_C15_C8_1
|
||||
#define CORTEX_A78C_IMP_CPUPOR_EL3 S3_6_C15_C8_2
|
||||
#define CORTEX_A78C_IMP_CPUPMR_EL3 S3_6_C15_C8_3
|
||||
|
||||
#endif /* CORTEX_A78C_H */
|
||||
+23
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_HAYES_H
|
||||
#define CORTEX_HAYES_H
|
||||
|
||||
#define CORTEX_HAYES_MIDR U(0x410FD800)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_HAYES_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_HAYES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_HAYES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
#endif /* CORTEX_HAYES_H */
|
||||
+26
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_HUNTER_H
|
||||
#define CORTEX_HUNTER_H
|
||||
|
||||
#define CORTEX_HUNTER_MIDR U(0x410FD810)
|
||||
|
||||
/* Cortex Hunter loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_HUNTER_BHB_LOOP_COUNT U(132)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_HUNTER_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_HUNTER_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_HUNTER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
#endif /* CORTEX_HUNTER_H */
|
||||
+26
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (c) 2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_HUNTER_ELP_ARM_H
|
||||
#define CORTEX_HUNTER_ELP_ARM_H
|
||||
|
||||
#define CORTEX_HUNTER_ELP_ARM_MIDR U(0x410FD821)
|
||||
|
||||
/* Cortex Hunter ELP loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_HUNTER_ELP_ARM_BHB_LOOP_COUNT U(132)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_HUNTER_ELP_ARM_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
#endif /* CORTEX_HUNTER_ELP_ARM_H */
|
||||
+26
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_MAKALU_H
|
||||
#define CORTEX_MAKALU_H
|
||||
|
||||
#define CORTEX_MAKALU_MIDR U(0x410FD4D0)
|
||||
|
||||
/* Cortex Makalu loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_MAKALU_BHB_LOOP_COUNT U(38)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_MAKALU_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_MAKALU_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
#endif /* CORTEX_MAKALU_H */
|
||||
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Copyright (c) 2022, Google LLC. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_X1_H
|
||||
#define CORTEX_X1_H
|
||||
|
||||
/* Cortex-X1 MIDR for r1p0 */
|
||||
#define CORTEX_X1_MIDR U(0x411fd440)
|
||||
|
||||
/* Cortex-X1 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_X1_BHB_LOOP_COUNT U(32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_X1_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_X1_ACTLR2_EL1 S3_0_C15_C1_1
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_X1_CORE_PWRDN_EN_MASK U(0x1)
|
||||
|
||||
#endif /* CORTEX_X1_H */
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_X2_H
|
||||
#define CORTEX_X2_H
|
||||
|
||||
#define CORTEX_X2_MIDR U(0x410FD480)
|
||||
|
||||
/* Cortex-X2 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_X2_BHB_LOOP_COUNT U(32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
#define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register 2 specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X2_CPUECTLR2_EL1 S3_0_C15_C1_5
|
||||
|
||||
#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT U(11)
|
||||
#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
|
||||
#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control Register definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X2_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
#define CORTEX_X2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control Register 2 definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X2_CPUACTLR2_EL1 S3_0_C15_C1_1
|
||||
#define CORTEX_X2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control Register 5 definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0
|
||||
#define CORTEX_X2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Implementation Specific Selected Instruction registers
|
||||
******************************************************************************/
|
||||
#define CORTEX_X2_IMP_CPUPSELR_EL3 S3_6_C15_C8_0
|
||||
#define CORTEX_X2_IMP_CPUPCR_EL3 S3_6_C15_C8_1
|
||||
#define CORTEX_X2_IMP_CPUPOR_EL3 S3_6_C15_C8_2
|
||||
#define CORTEX_X2_IMP_CPUPMR_EL3 S3_6_C15_C8_3
|
||||
|
||||
#endif /* CORTEX_X2_H */
|
||||
@@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_X3_H
|
||||
#define CORTEX_X3_H
|
||||
|
||||
#define CORTEX_X3_MIDR U(0x410FD4E0)
|
||||
|
||||
/* Cortex-X3 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_X3_BHB_LOOP_COUNT U(132)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X3_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
#define CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT U(4)
|
||||
#define CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT U(7)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register 2 specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1
|
||||
#define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
|
||||
|
||||
#endif /* CORTEX_X3_H */
|
||||
@@ -0,0 +1,314 @@
|
||||
/*
|
||||
* Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef CPU_MACROS_S
|
||||
#define CPU_MACROS_S
|
||||
|
||||
#include <arch.h>
|
||||
#include <assert_macros.S>
|
||||
#include <lib/cpus/errata_report.h>
|
||||
|
||||
#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
|
||||
(MIDR_PN_MASK << MIDR_PN_SHIFT)
|
||||
|
||||
/* The number of CPU operations allowed */
|
||||
#define CPU_MAX_PWR_DWN_OPS 2
|
||||
|
||||
/* Special constant to specify that CPU has no reset function */
|
||||
#define CPU_NO_RESET_FUNC 0
|
||||
|
||||
#define CPU_NO_EXTRA1_FUNC 0
|
||||
#define CPU_NO_EXTRA2_FUNC 0
|
||||
#define CPU_NO_EXTRA3_FUNC 0
|
||||
|
||||
/* Word size for 64-bit CPUs */
|
||||
#define CPU_WORD_SIZE 8
|
||||
|
||||
/*
|
||||
* Whether errata status needs reporting. Errata status is printed in debug
|
||||
* builds for both BL1 and BL31 images.
|
||||
*/
|
||||
#if (defined(IMAGE_BL1) || defined(IMAGE_BL31)) && DEBUG
|
||||
# define REPORT_ERRATA 1
|
||||
#else
|
||||
# define REPORT_ERRATA 0
|
||||
#endif
|
||||
|
||||
|
||||
.equ CPU_MIDR_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_EXTRA1_FUNC_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_EXTRA2_FUNC_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_EXTRA3_FUNC_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_E_HANDLER_FUNC_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS
|
||||
.equ CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_ERRATA_LOCK_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_ERRATA_PRINTED_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_REG_DUMP_SIZE, CPU_WORD_SIZE
|
||||
|
||||
#ifndef IMAGE_AT_EL3
|
||||
.equ CPU_RESET_FUNC_SIZE, 0
|
||||
#endif
|
||||
|
||||
/* The power down core and cluster is needed only in BL31 */
|
||||
#ifndef IMAGE_BL31
|
||||
.equ CPU_PWR_DWN_OPS_SIZE, 0
|
||||
#endif
|
||||
|
||||
/* Fields required to print errata status. */
|
||||
#if !REPORT_ERRATA
|
||||
.equ CPU_ERRATA_FUNC_SIZE, 0
|
||||
#endif
|
||||
|
||||
/* Only BL31 requieres mutual exclusion and printed flag. */
|
||||
#if !(REPORT_ERRATA && defined(IMAGE_BL31))
|
||||
.equ CPU_ERRATA_LOCK_SIZE, 0
|
||||
.equ CPU_ERRATA_PRINTED_SIZE, 0
|
||||
#endif
|
||||
|
||||
#if !defined(IMAGE_BL31) || !CRASH_REPORTING
|
||||
.equ CPU_REG_DUMP_SIZE, 0
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Define the offsets to the fields in cpu_ops structure.
|
||||
* Every offset is defined based in the offset and size of the previous
|
||||
* field.
|
||||
*/
|
||||
.equ CPU_MIDR, 0
|
||||
.equ CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE
|
||||
.equ CPU_EXTRA1_FUNC, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
|
||||
.equ CPU_EXTRA2_FUNC, CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE
|
||||
.equ CPU_EXTRA3_FUNC, CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE
|
||||
.equ CPU_E_HANDLER_FUNC, CPU_EXTRA3_FUNC + CPU_EXTRA3_FUNC_SIZE
|
||||
.equ CPU_PWR_DWN_OPS, CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE
|
||||
.equ CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE
|
||||
.equ CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE
|
||||
.equ CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE
|
||||
.equ CPU_REG_DUMP, CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE
|
||||
.equ CPU_OPS_SIZE, CPU_REG_DUMP + CPU_REG_DUMP_SIZE
|
||||
|
||||
/*
|
||||
* Write given expressions as quad words
|
||||
*
|
||||
* _count:
|
||||
* Write at least _count quad words. If the given number of
|
||||
* expressions is less than _count, repeat the last expression to
|
||||
* fill _count quad words in total
|
||||
* _rest:
|
||||
* Optional list of expressions. _this is for parameter extraction
|
||||
* only, and has no significance to the caller
|
||||
*
|
||||
* Invoked as:
|
||||
* fill_constants 2, foo, bar, blah, ...
|
||||
*/
|
||||
.macro fill_constants _count:req, _this, _rest:vararg
|
||||
.ifgt \_count
|
||||
/* Write the current expression */
|
||||
.ifb \_this
|
||||
.error "Nothing to fill"
|
||||
.endif
|
||||
.quad \_this
|
||||
|
||||
/* Invoke recursively for remaining expressions */
|
||||
.ifnb \_rest
|
||||
fill_constants \_count-1, \_rest
|
||||
.else
|
||||
fill_constants \_count-1, \_this
|
||||
.endif
|
||||
.endif
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Declare CPU operations
|
||||
*
|
||||
* _name:
|
||||
* Name of the CPU for which operations are being specified
|
||||
* _midr:
|
||||
* Numeric value expected to read from CPU's MIDR
|
||||
* _resetfunc:
|
||||
* Reset function for the CPU. If there's no CPU reset function,
|
||||
* specify CPU_NO_RESET_FUNC
|
||||
* _extra1:
|
||||
* This is a placeholder for future per CPU operations. Currently,
|
||||
* some CPUs use this entry to set a test function to determine if
|
||||
* the workaround for CVE-2017-5715 needs to be applied or not.
|
||||
* _extra2:
|
||||
* This is a placeholder for future per CPU operations. Currently
|
||||
* some CPUs use this entry to set a function to disable the
|
||||
* workaround for CVE-2018-3639.
|
||||
* _extra3:
|
||||
* This is a placeholder for future per CPU operations. Currently,
|
||||
* some CPUs use this entry to set a test function to determine if
|
||||
* the workaround for CVE-2022-23960 needs to be applied or not.
|
||||
* _e_handler:
|
||||
* This is a placeholder for future per CPU exception handlers.
|
||||
* _power_down_ops:
|
||||
* Comma-separated list of functions to perform power-down
|
||||
* operatios on the CPU. At least one, and up to
|
||||
* CPU_MAX_PWR_DWN_OPS number of functions may be specified.
|
||||
* Starting at power level 0, these functions shall handle power
|
||||
* down at subsequent power levels. If there aren't exactly
|
||||
* CPU_MAX_PWR_DWN_OPS functions, the last specified one will be
|
||||
* used to handle power down at subsequent levels
|
||||
*/
|
||||
.macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \
|
||||
_extra1:req, _extra2:req, _extra3:req, _e_handler:req, _power_down_ops:vararg
|
||||
.section cpu_ops, "a"
|
||||
.align 3
|
||||
.type cpu_ops_\_name, %object
|
||||
.quad \_midr
|
||||
#if defined(IMAGE_AT_EL3)
|
||||
.quad \_resetfunc
|
||||
#endif
|
||||
.quad \_extra1
|
||||
.quad \_extra2
|
||||
.quad \_extra3
|
||||
.quad \_e_handler
|
||||
#ifdef IMAGE_BL31
|
||||
/* Insert list of functions */
|
||||
fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops
|
||||
#endif
|
||||
|
||||
#if REPORT_ERRATA
|
||||
.ifndef \_name\()_cpu_str
|
||||
/*
|
||||
* Place errata reported flag, and the spinlock to arbitrate access to
|
||||
* it in the data section.
|
||||
*/
|
||||
.pushsection .data
|
||||
define_asm_spinlock \_name\()_errata_lock
|
||||
\_name\()_errata_reported:
|
||||
.word 0
|
||||
.popsection
|
||||
|
||||
/* Place CPU string in rodata */
|
||||
.pushsection .rodata
|
||||
\_name\()_cpu_str:
|
||||
.asciz "\_name"
|
||||
.popsection
|
||||
.endif
|
||||
|
||||
/*
|
||||
* Mandatory errata status printing function for CPUs of
|
||||
* this class.
|
||||
*/
|
||||
.quad \_name\()_errata_report
|
||||
|
||||
#ifdef IMAGE_BL31
|
||||
/* Pointers to errata lock and reported flag */
|
||||
.quad \_name\()_errata_lock
|
||||
.quad \_name\()_errata_reported
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(IMAGE_BL31) && CRASH_REPORTING
|
||||
.quad \_name\()_cpu_reg_dump
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
|
||||
_power_down_ops:vararg
|
||||
declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, 0, 0, \
|
||||
\_power_down_ops
|
||||
.endm
|
||||
|
||||
.macro declare_cpu_ops_eh _name:req, _midr:req, _resetfunc:req, \
|
||||
_e_handler:req, _power_down_ops:vararg
|
||||
declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
|
||||
0, 0, 0, \_e_handler, \_power_down_ops
|
||||
.endm
|
||||
|
||||
.macro declare_cpu_ops_wa _name:req, _midr:req, \
|
||||
_resetfunc:req, _extra1:req, _extra2:req, \
|
||||
_extra3:req, _power_down_ops:vararg
|
||||
declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
|
||||
\_extra1, \_extra2, \_extra3, 0, \_power_down_ops
|
||||
.endm
|
||||
|
||||
#if REPORT_ERRATA
|
||||
/*
|
||||
* Print status of a CPU errata
|
||||
*
|
||||
* _chosen:
|
||||
* Identifier indicating whether or not a CPU errata has been
|
||||
* compiled in.
|
||||
* _cpu:
|
||||
* Name of the CPU
|
||||
* _id:
|
||||
* Errata identifier
|
||||
* _rev_var:
|
||||
* Register containing the combined value CPU revision and variant
|
||||
* - typically the return value of cpu_get_rev_var
|
||||
*/
|
||||
.macro report_errata _chosen, _cpu, _id, _rev_var=x8
|
||||
/* Stash a string with errata ID */
|
||||
.pushsection .rodata
|
||||
\_cpu\()_errata_\_id\()_str:
|
||||
.asciz "\_id"
|
||||
.popsection
|
||||
|
||||
/* Check whether errata applies */
|
||||
mov x0, \_rev_var
|
||||
/* Shall clobber: x0-x7 */
|
||||
bl check_errata_\_id
|
||||
|
||||
.ifeq \_chosen
|
||||
/*
|
||||
* Errata workaround has not been compiled in. If the errata would have
|
||||
* applied had it been compiled in, print its status as missing.
|
||||
*/
|
||||
cbz x0, 900f
|
||||
mov x0, #ERRATA_MISSING
|
||||
.endif
|
||||
900:
|
||||
adr x1, \_cpu\()_cpu_str
|
||||
adr x2, \_cpu\()_errata_\_id\()_str
|
||||
bl errata_print_msg
|
||||
.endm
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This macro is used on some CPUs to detect if they are vulnerable
|
||||
* to CVE-2017-5715.
|
||||
*/
|
||||
.macro cpu_check_csv2 _reg _label
|
||||
mrs \_reg, id_aa64pfr0_el1
|
||||
ubfx \_reg, \_reg, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH
|
||||
/*
|
||||
* If the field equals 1, branch targets trained in one context cannot
|
||||
* affect speculative execution in a different context.
|
||||
*
|
||||
* If the field equals 2, it means that the system is also aware of
|
||||
* SCXTNUM_ELx register contexts. We aren't using them in the TF, so we
|
||||
* expect users of the registers to do the right thing.
|
||||
*
|
||||
* Only apply mitigations if the value of this field is 0.
|
||||
*/
|
||||
#if ENABLE_ASSERTIONS
|
||||
cmp \_reg, #3 /* Only values 0 to 2 are expected */
|
||||
ASM_ASSERT(lo)
|
||||
#endif
|
||||
|
||||
cmp \_reg, #0
|
||||
bne \_label
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Helper macro that reads the part number of the current
|
||||
* CPU and jumps to the given label if it matches the CPU
|
||||
* MIDR provided.
|
||||
*
|
||||
* Clobbers x0.
|
||||
*/
|
||||
.macro jump_if_cpu_midr _cpu_midr, _label
|
||||
mrs x0, midr_el1
|
||||
ubfx x0, x0, MIDR_PN_SHIFT, #12
|
||||
cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
|
||||
b.eq \_label
|
||||
.endm
|
||||
|
||||
#endif /* CPU_MACROS_S */
|
||||
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CPUAMU_H
|
||||
#define CPUAMU_H
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Activity Monitor Unit register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CPUAMCNTENCLR_EL0 S3_3_C15_C9_7
|
||||
#define CPUAMCNTENSET_EL0 S3_3_C15_C9_6
|
||||
#define CPUAMCFGR_EL0 S3_3_C15_C10_6
|
||||
#define CPUAMUSERENR_EL0 S3_3_C15_C10_7
|
||||
|
||||
/* Activity Monitor Event Counter Registers */
|
||||
#define CPUAMEVCNTR0_EL0 S3_3_C15_C9_0
|
||||
#define CPUAMEVCNTR1_EL0 S3_3_C15_C9_1
|
||||
#define CPUAMEVCNTR2_EL0 S3_3_C15_C9_2
|
||||
#define CPUAMEVCNTR3_EL0 S3_3_C15_C9_3
|
||||
#define CPUAMEVCNTR4_EL0 S3_3_C15_C9_4
|
||||
|
||||
/* Activity Monitor Event Type Registers */
|
||||
#define CPUAMEVTYPER0_EL0 S3_3_C15_C10_0
|
||||
#define CPUAMEVTYPER1_EL0 S3_3_C15_C10_1
|
||||
#define CPUAMEVTYPER2_EL0 S3_3_C15_C10_2
|
||||
#define CPUAMEVTYPER3_EL0 S3_3_C15_C10_3
|
||||
#define CPUAMEVTYPER4_EL0 S3_3_C15_C10_4
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <stdint.h>
|
||||
|
||||
uint64_t cpuamu_cnt_read(unsigned int idx);
|
||||
void cpuamu_cnt_write(unsigned int idx, uint64_t val);
|
||||
unsigned int cpuamu_read_cpuamcntenset_el0(void);
|
||||
unsigned int cpuamu_read_cpuamcntenclr_el0(void);
|
||||
void cpuamu_write_cpuamcntenset_el0(unsigned int mask);
|
||||
void cpuamu_write_cpuamcntenclr_el0(unsigned int mask);
|
||||
|
||||
int midr_match(unsigned int cpu_midr);
|
||||
void cpuamu_context_save(unsigned int nr_counters);
|
||||
void cpuamu_context_restore(unsigned int nr_counters);
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* CPUAMU_H */
|
||||
@@ -0,0 +1,54 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef DENVER_H
|
||||
#define DENVER_H
|
||||
|
||||
/* MIDR values for Denver */
|
||||
#define DENVER_MIDR_PN0 U(0x4E0F0000)
|
||||
#define DENVER_MIDR_PN1 U(0x4E0F0010)
|
||||
#define DENVER_MIDR_PN2 U(0x4E0F0020)
|
||||
#define DENVER_MIDR_PN3 U(0x4E0F0030)
|
||||
#define DENVER_MIDR_PN4 U(0x4E0F0040)
|
||||
#define DENVER_MIDR_PN5 U(0x4E0F0050)
|
||||
#define DENVER_MIDR_PN6 U(0x4E0F0060)
|
||||
#define DENVER_MIDR_PN7 U(0x4E0F0070)
|
||||
#define DENVER_MIDR_PN8 U(0x4E0F0080)
|
||||
#define DENVER_MIDR_PN9 U(0x4E0F0090)
|
||||
|
||||
/* Implementer code in the MIDR register */
|
||||
#define DENVER_IMPL U(0x4E)
|
||||
|
||||
/* CPU state ids - implementation defined */
|
||||
#define DENVER_CPU_STATE_POWER_DOWN U(0x3)
|
||||
|
||||
/* Speculative store buffering */
|
||||
#define DENVER_CPU_DIS_SSB_EL3 (U(1) << 11)
|
||||
#define DENVER_PN4_CPU_DIS_SSB_EL3 (U(1) << 18)
|
||||
|
||||
/* Speculative memory disambiguation */
|
||||
#define DENVER_CPU_DIS_MD_EL3 (U(1) << 9)
|
||||
#define DENVER_PN4_CPU_DIS_MD_EL3 (U(1) << 17)
|
||||
|
||||
/* Core power management states */
|
||||
#define DENVER_CPU_PMSTATE_C1 U(0x1)
|
||||
#define DENVER_CPU_PMSTATE_C6 U(0x6)
|
||||
#define DENVER_CPU_PMSTATE_C7 U(0x7)
|
||||
#define DENVER_CPU_PMSTATE_MASK U(0xF)
|
||||
|
||||
/* ACTRL_ELx bits to enable dual execution*/
|
||||
#define DENVER_CPU_ENABLE_DUAL_EXEC_EL2 (ULL(1) << 9)
|
||||
#define DENVER_CPU_ENABLE_DUAL_EXEC_EL3 (ULL(1) << 9)
|
||||
#define DENVER_CPU_ENABLE_DUAL_EXEC_EL1 (U(1) << 4)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
/* Disable Dynamic Code Optimisation */
|
||||
void denver_disable_dco(void);
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* DENVER_H */
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef DSU_DEF_H
|
||||
#define DSU_DEF_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/********************************************************************
|
||||
* DSU Cluster Configuration registers definitions
|
||||
********************************************************************/
|
||||
#define CLUSTERCFR_EL1 S3_0_C15_C3_0
|
||||
|
||||
#define CLUSTERCFR_ACP_SHIFT U(11)
|
||||
|
||||
/********************************************************************
|
||||
* DSU Cluster Main Revision ID registers definitions
|
||||
********************************************************************/
|
||||
#define CLUSTERIDR_EL1 S3_0_C15_C3_1
|
||||
|
||||
#define CLUSTERIDR_REV_SHIFT U(0)
|
||||
#define CLUSTERIDR_REV_BITS U(4)
|
||||
#define CLUSTERIDR_VAR_SHIFT U(4)
|
||||
#define CLUSTERIDR_VAR_BITS U(4)
|
||||
|
||||
/********************************************************************
|
||||
* DSU Cluster Auxiliary Control registers definitions
|
||||
********************************************************************/
|
||||
#define CLUSTERACTLR_EL1 S3_0_C15_C3_3
|
||||
|
||||
#define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15)
|
||||
#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15)
|
||||
|
||||
/********************************************************************
|
||||
* Masks applied for DSU errata workarounds
|
||||
********************************************************************/
|
||||
#define DSU_ERRATA_936184_MASK (U(0x3) << 15)
|
||||
|
||||
#endif /* DSU_DEF_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Arm Limited. All rights reserverd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef AARCH64_GENERIC_H
|
||||
#define AARCH64_GENERIC_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/*
|
||||
* 0x0 value on the MIDR implementer value is reserved for software use,
|
||||
* so use an MIDR value of 0 for a default CPU library.
|
||||
*/
|
||||
#define AARCH64_GENERIC_MIDR U(0)
|
||||
|
||||
#endif /* AARCH64_GENERIC_H */
|
||||
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef NEOVERSE_E1_H
|
||||
#define NEOVERSE_E1_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#define NEOVERSE_E1_MIDR U(0x410FD4A0)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_E1_ECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_E1_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions.
|
||||
******************************************************************************/
|
||||
|
||||
#define NEOVERSE_E1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
|
||||
|
||||
#endif /* NEOVERSE_E1_H */
|
||||
@@ -0,0 +1,70 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef NEOVERSE_N1_H
|
||||
#define NEOVERSE_N1_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Neoverse N1 MIDR for revision 0 */
|
||||
#define NEOVERSE_N1_MIDR U(0x410fd0c0)
|
||||
|
||||
/* Neoverse N1 loop count for CVE-2022-23960 mitigation */
|
||||
#define NEOVERSE_N1_BHB_LOOP_COUNT U(24)
|
||||
|
||||
/* Exception Syndrome register EC code for IC Trap */
|
||||
#define NEOVERSE_N1_EC_IC_TRAP U(0x1f)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
|
||||
/* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */
|
||||
#define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1)
|
||||
|
||||
#define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4)
|
||||
|
||||
#define NEOVERSE_N1_AMU_NR_COUNTERS U(5)
|
||||
#define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
#define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24)
|
||||
#define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51)
|
||||
#define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
|
||||
#define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6)
|
||||
#define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
|
||||
|
||||
#define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1
|
||||
|
||||
#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
|
||||
#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
|
||||
#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11)
|
||||
#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15)
|
||||
#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16)
|
||||
#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)
|
||||
|
||||
#define NEOVERSE_N1_CPUACTLR3_EL1 S3_0_C15_C1_2
|
||||
|
||||
#define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10)
|
||||
|
||||
/* Instruction patching registers */
|
||||
#define CPUPSELR_EL3 S3_6_C15_C8_0
|
||||
#define CPUPCR_EL3 S3_6_C15_C8_1
|
||||
#define CPUPOR_EL3 S3_6_C15_C8_2
|
||||
#define CPUPMR_EL3 S3_6_C15_C8_3
|
||||
|
||||
#endif /* NEOVERSE_N1_H */
|
||||
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Copyright (c) 2020-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef NEOVERSE_N2_H
|
||||
#define NEOVERSE_N2_H
|
||||
|
||||
/* Neoverse N2 ID register for revision r0p0 */
|
||||
#define NEOVERSE_N2_MIDR U(0x410FD490)
|
||||
|
||||
/* Neoverse N2 loop count for CVE-2022-23960 mitigation */
|
||||
#define NEOVERSE_N2_BHB_LOOP_COUNT U(32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power control register
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
|
||||
#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
|
||||
#define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register 2 specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
|
||||
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
|
||||
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
|
||||
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
|
||||
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register 5 specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0
|
||||
#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
|
||||
#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
|
||||
#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5
|
||||
#define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
|
||||
#define CPUECTLR2_EL1_PF_MODE_LSB U(11)
|
||||
#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
|
||||
|
||||
#endif /* NEOVERSE_N2_H */
|
||||
+18
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef NEOVERSE_N_COMMON_H
|
||||
#define NEOVERSE_N_COMMON_H
|
||||
|
||||
/******************************************************************************
|
||||
* Neoverse Nx CPU Configuration register definitions
|
||||
*****************************************************************************/
|
||||
#define CPUCFR_EL1 S3_0_C15_C0_0
|
||||
|
||||
/* SCU bit of CPU Configuration Register, EL1 */
|
||||
#define SCU_SHIFT U(2)
|
||||
|
||||
#endif /* NEOVERSE_N_COMMON_H */
|
||||
+27
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (c) 2022, ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef NEOVERSE_POSEIDON_H
|
||||
#define NEOVERSE_POSEIDON_H
|
||||
|
||||
|
||||
#define NEOVERSE_POSEIDON_MIDR U(0x410FD830)
|
||||
|
||||
/* Neoverse Poseidon loop count for CVE-2022-23960 mitigation */
|
||||
#define NEOVERSE_POSEIDON_BHB_LOOP_COUNT U(132)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_POSEIDON_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
#endif /* NEOVERSE_POSEIDON_H */
|
||||
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2023, ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef NEOVERSE_V1_H
|
||||
#define NEOVERSE_V1_H
|
||||
|
||||
#define NEOVERSE_V1_MIDR U(0x410FD400)
|
||||
|
||||
/* Neoverse V1 loop count for CVE-2022-23960 mitigation */
|
||||
#define NEOVERSE_V1_BHB_LOOP_COUNT U(32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
#define NEOVERSE_V1_CPUPSELR_EL3 S3_6_C15_C8_0
|
||||
#define NEOVERSE_V1_CPUPOR_EL3 S3_6_C15_C8_2
|
||||
#define NEOVERSE_V1_CPUPMR_EL3 S3_6_C15_C8_3
|
||||
#define NEOVERSE_V1_CPUPCR_EL3 S3_6_C15_C8_1
|
||||
#define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
|
||||
#define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
|
||||
#define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)
|
||||
#define CPUECTLR_EL1_PF_MODE_LSB U(6)
|
||||
#define CPUECTLR_EL1_PF_MODE_WIDTH U(2)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1
|
||||
#define NEOVERSE_V1_ACTLR2_EL1_BIT_0 ULL(1)
|
||||
#define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
|
||||
#define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28)
|
||||
#define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
|
||||
|
||||
#define NEOVERSE_V1_ACTLR3_EL1 S3_0_C15_C1_2
|
||||
|
||||
#define NEOVERSE_V1_ACTLR5_EL1 S3_0_C15_C9_0
|
||||
|
||||
#endif /* NEOVERSE_V1_H */
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef NEOVERSE_V2_H
|
||||
#define NEOVERSE_V2_H
|
||||
|
||||
#define NEOVERSE_V2_MIDR U(0x410FD4F0)
|
||||
|
||||
/* Neoverse V2 loop count for CVE-2022-23960 mitigation */
|
||||
#define NEOVERSE_V2_BHB_LOOP_COUNT U(132)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
#endif /* NEOVERSE_V2_H */
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QEMU_MAX_H
|
||||
#define QEMU_MAX_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/*
|
||||
* QEMU MAX midr for revision 0
|
||||
* 00 - Reserved for software use
|
||||
* 0 - Variant
|
||||
* F - Architectural features identified in ID_* registers
|
||||
* 051 - 'Q', in a 12-bit field.
|
||||
* 0 - Revision
|
||||
*/
|
||||
#define QEMU_MAX_MIDR U(0x000F0510)
|
||||
|
||||
#endif /* QEMU_MAX_H */
|
||||
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef RAINIER_H
|
||||
#define RAINIER_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* RAINIER MIDR for revision 0 */
|
||||
#define RAINIER_MIDR U(0x3f0f4120)
|
||||
|
||||
/* Exception Syndrome register EC code for IC Trap */
|
||||
#define RAINIER_EC_IC_TRAP U(0x1f)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define RAINIER_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
|
||||
/* Definitions of register field mask in RAINIER_CPUPWRCTLR_EL1 */
|
||||
#define RAINIER_CORE_PWRDN_EN_MASK U(0x1)
|
||||
|
||||
#define RAINIER_ACTLR_AMEN_BIT (U(1) << 4)
|
||||
|
||||
#define RAINIER_AMU_NR_COUNTERS U(5)
|
||||
#define RAINIER_AMU_GROUP0_MASK U(0x1f)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define RAINIER_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
#define RAINIER_WS_THR_L2_MASK (ULL(3) << 24)
|
||||
#define RAINIER_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define RAINIER_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
|
||||
#define RAINIER_CPUACTLR_EL1_BIT_6 (ULL(1) << 6)
|
||||
#define RAINIER_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
|
||||
|
||||
#define RAINIER_CPUACTLR2_EL1 S3_0_C15_C1_1
|
||||
|
||||
#define RAINIER_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
|
||||
#define RAINIER_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
|
||||
#define RAINIER_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11)
|
||||
#define RAINIER_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15)
|
||||
#define RAINIER_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16)
|
||||
#define RAINIER_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)
|
||||
|
||||
#define RAINIER_CPUACTLR3_EL1 S3_0_C15_C1_2
|
||||
|
||||
#define RAINIER_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10)
|
||||
|
||||
/* Instruction patching registers */
|
||||
#define CPUPSELR_EL3 S3_6_C15_C8_0
|
||||
#define CPUPCR_EL3 S3_6_C15_C8_1
|
||||
#define CPUPOR_EL3 S3_6_C15_C8_2
|
||||
#define CPUPMR_EL3 S3_6_C15_C8_3
|
||||
|
||||
#endif /* RAINIER_H */
|
||||
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef ERRATA_REPORT_H
|
||||
#define ERRATA_REPORT_H
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <arch.h>
|
||||
#include <arch_helpers.h>
|
||||
#include <lib/spinlock.h>
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#if DEBUG
|
||||
void print_errata_status(void);
|
||||
#else
|
||||
static inline void print_errata_status(void) {}
|
||||
#endif
|
||||
|
||||
void errata_print_msg(unsigned int status, const char *cpu, const char *id);
|
||||
int errata_needs_reporting(spinlock_t *lock, uint32_t *reported);
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
/* Errata status */
|
||||
#define ERRATA_NOT_APPLIES 0
|
||||
#define ERRATA_APPLIES 1
|
||||
#define ERRATA_MISSING 2
|
||||
|
||||
/* Macro to get CPU revision code for checking errata version compatibility. */
|
||||
#define CPU_REV(r, p) ((r << 4) | p)
|
||||
|
||||
#endif /* ERRATA_REPORT_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef WA_CVE_2017_5715_H
|
||||
#define WA_CVE_2017_5715_H
|
||||
|
||||
int check_wa_cve_2017_5715(void);
|
||||
|
||||
#endif /* WA_CVE_2017_5715_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef WA_CVE_2018_3639_H
|
||||
#define WA_CVE_2018_3639_H
|
||||
|
||||
void *wa_cve_2018_3639_get_disable_ptr(void);
|
||||
|
||||
#endif /* WA_CVE_2018_3639_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
/*
|
||||
* Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef WA_CVE_2022_23960_H
|
||||
#define WA_CVE_2022_23960_H
|
||||
|
||||
int check_smccc_arch_wa3_applies(void);
|
||||
|
||||
#endif /* WA_CVE_2022_23960_H */
|
||||
@@ -0,0 +1,83 @@
|
||||
/*
|
||||
* Copyright (c) 2019, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef DEBUGFS_H
|
||||
#define DEBUGFS_H
|
||||
|
||||
#define NAMELEN 13 /* Maximum length of a file name */
|
||||
#define PATHLEN 41 /* Maximum length of a path */
|
||||
#define STATLEN 41 /* Size of static part of dir format */
|
||||
#define ROOTLEN (2 + 4) /* Size needed to encode root string */
|
||||
#define FILNAMLEN (2 + NAMELEN) /* Size needed to encode filename */
|
||||
#define DIRLEN (STATLEN + FILNAMLEN + 3*ROOTLEN) /* Size of dir entry */
|
||||
|
||||
#define KSEEK_SET 0
|
||||
#define KSEEK_CUR 1
|
||||
#define KSEEK_END 2
|
||||
|
||||
#define NELEM(tab) (sizeof(tab) / sizeof((tab)[0]))
|
||||
|
||||
typedef unsigned short qid_t; /* FIXME: short type not recommended? */
|
||||
|
||||
/*******************************************************************************
|
||||
* This structure contains the necessary information to represent a 9p
|
||||
* directory.
|
||||
******************************************************************************/
|
||||
typedef struct {
|
||||
char name[NAMELEN];
|
||||
long length;
|
||||
unsigned char mode;
|
||||
unsigned char index;
|
||||
unsigned char dev;
|
||||
qid_t qid;
|
||||
} dir_t;
|
||||
|
||||
/* Permission definitions used as flags */
|
||||
#define O_READ (1 << 0)
|
||||
#define O_WRITE (1 << 1)
|
||||
#define O_RDWR (1 << 2)
|
||||
#define O_BIND (1 << 3)
|
||||
#define O_DIR (1 << 4)
|
||||
#define O_STAT (1 << 5)
|
||||
|
||||
/* 9p interface */
|
||||
int mount(const char *srv, const char *mnt, const char *spec);
|
||||
int create(const char *name, int flags);
|
||||
int open(const char *name, int flags);
|
||||
int close(int fd);
|
||||
int read(int fd, void *buf, int n);
|
||||
int write(int fd, void *buf, int n);
|
||||
int seek(int fd, long off, int whence);
|
||||
int bind(const char *path, const char *where);
|
||||
int stat(const char *path, dir_t *dir);
|
||||
|
||||
/* DebugFS initialization */
|
||||
void debugfs_init(void);
|
||||
int debugfs_smc_setup(void);
|
||||
|
||||
/* Debugfs version returned through SMC interface */
|
||||
#define DEBUGFS_VERSION (0x000000001U)
|
||||
|
||||
/* Function ID for accessing the debugfs interface */
|
||||
#define DEBUGFS_FID_VALUE (0x30U)
|
||||
|
||||
#define is_debugfs_fid(_fid) \
|
||||
(((_fid) & FUNCID_NUM_MASK) == DEBUGFS_FID_VALUE)
|
||||
|
||||
/* Error code for debugfs SMC interface failures */
|
||||
#define DEBUGFS_E_INVALID_PARAMS (-2)
|
||||
#define DEBUGFS_E_DENIED (-3)
|
||||
|
||||
uintptr_t debugfs_smc_handler(unsigned int smc_fid,
|
||||
u_register_t cmd,
|
||||
u_register_t arg2,
|
||||
u_register_t arg3,
|
||||
u_register_t arg4,
|
||||
void *cookie,
|
||||
void *handle,
|
||||
uintptr_t flags);
|
||||
|
||||
#endif /* DEBUGFS_H */
|
||||
+70
@@ -0,0 +1,70 @@
|
||||
/*
|
||||
* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CONTEXT_H
|
||||
#define CONTEXT_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Constants that allow assembler code to access members of and the 'regs'
|
||||
* structure at their correct offsets.
|
||||
******************************************************************************/
|
||||
#define CTX_REGS_OFFSET U(0x0)
|
||||
#define CTX_GPREG_R0 U(0x0)
|
||||
#define CTX_GPREG_R1 U(0x4)
|
||||
#define CTX_GPREG_R2 U(0x8)
|
||||
#define CTX_GPREG_R3 U(0xC)
|
||||
#define CTX_LR U(0x10)
|
||||
#define CTX_SCR U(0x14)
|
||||
#define CTX_SPSR U(0x18)
|
||||
#define CTX_NS_SCTLR U(0x1C)
|
||||
#define CTX_REGS_END U(0x20)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <lib/cassert.h>
|
||||
|
||||
/*
|
||||
* Common constants to help define the 'cpu_context' structure and its
|
||||
* members below.
|
||||
*/
|
||||
#define WORD_SHIFT U(2)
|
||||
#define DEFINE_REG_STRUCT(name, num_regs) \
|
||||
typedef struct name { \
|
||||
uint32_t ctx_regs[num_regs]; \
|
||||
} __aligned(8) name##_t
|
||||
|
||||
/* Constants to determine the size of individual context structures */
|
||||
#define CTX_REG_ALL (CTX_REGS_END >> WORD_SHIFT)
|
||||
|
||||
DEFINE_REG_STRUCT(regs, CTX_REG_ALL);
|
||||
|
||||
#undef CTX_REG_ALL
|
||||
|
||||
#define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[offset >> WORD_SHIFT])
|
||||
#define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[offset >> WORD_SHIFT]) \
|
||||
= val)
|
||||
typedef struct cpu_context {
|
||||
regs_t regs_ctx;
|
||||
} cpu_context_t;
|
||||
|
||||
/* Macros to access members of the 'cpu_context_t' structure */
|
||||
#define get_regs_ctx(h) (&((cpu_context_t *) h)->regs_ctx)
|
||||
|
||||
/*
|
||||
* Compile time assertions related to the 'cpu_context' structure to
|
||||
* ensure that the assembler and the compiler view of the offsets of
|
||||
* the structure members is the same.
|
||||
*/
|
||||
CASSERT(CTX_REGS_OFFSET == __builtin_offsetof(cpu_context_t, regs_ctx), \
|
||||
assert_core_context_regs_offset_mismatch);
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* CONTEXT_H */
|
||||
+567
@@ -0,0 +1,567 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CONTEXT_H
|
||||
#define CONTEXT_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Constants that allow assembler code to access members of and the 'gp_regs'
|
||||
* structure at their correct offsets.
|
||||
******************************************************************************/
|
||||
#define CTX_GPREGS_OFFSET U(0x0)
|
||||
#define CTX_GPREG_X0 U(0x0)
|
||||
#define CTX_GPREG_X1 U(0x8)
|
||||
#define CTX_GPREG_X2 U(0x10)
|
||||
#define CTX_GPREG_X3 U(0x18)
|
||||
#define CTX_GPREG_X4 U(0x20)
|
||||
#define CTX_GPREG_X5 U(0x28)
|
||||
#define CTX_GPREG_X6 U(0x30)
|
||||
#define CTX_GPREG_X7 U(0x38)
|
||||
#define CTX_GPREG_X8 U(0x40)
|
||||
#define CTX_GPREG_X9 U(0x48)
|
||||
#define CTX_GPREG_X10 U(0x50)
|
||||
#define CTX_GPREG_X11 U(0x58)
|
||||
#define CTX_GPREG_X12 U(0x60)
|
||||
#define CTX_GPREG_X13 U(0x68)
|
||||
#define CTX_GPREG_X14 U(0x70)
|
||||
#define CTX_GPREG_X15 U(0x78)
|
||||
#define CTX_GPREG_X16 U(0x80)
|
||||
#define CTX_GPREG_X17 U(0x88)
|
||||
#define CTX_GPREG_X18 U(0x90)
|
||||
#define CTX_GPREG_X19 U(0x98)
|
||||
#define CTX_GPREG_X20 U(0xa0)
|
||||
#define CTX_GPREG_X21 U(0xa8)
|
||||
#define CTX_GPREG_X22 U(0xb0)
|
||||
#define CTX_GPREG_X23 U(0xb8)
|
||||
#define CTX_GPREG_X24 U(0xc0)
|
||||
#define CTX_GPREG_X25 U(0xc8)
|
||||
#define CTX_GPREG_X26 U(0xd0)
|
||||
#define CTX_GPREG_X27 U(0xd8)
|
||||
#define CTX_GPREG_X28 U(0xe0)
|
||||
#define CTX_GPREG_X29 U(0xe8)
|
||||
#define CTX_GPREG_LR U(0xf0)
|
||||
#define CTX_GPREG_SP_EL0 U(0xf8)
|
||||
#define CTX_GPREGS_END U(0x100)
|
||||
|
||||
/*******************************************************************************
|
||||
* Constants that allow assembler code to access members of and the 'el3_state'
|
||||
* structure at their correct offsets. Note that some of the registers are only
|
||||
* 32-bits wide but are stored as 64-bit values for convenience
|
||||
******************************************************************************/
|
||||
#define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END)
|
||||
#define CTX_SCR_EL3 U(0x0)
|
||||
#define CTX_ESR_EL3 U(0x8)
|
||||
#define CTX_RUNTIME_SP U(0x10)
|
||||
#define CTX_SPSR_EL3 U(0x18)
|
||||
#define CTX_ELR_EL3 U(0x20)
|
||||
#define CTX_PMCR_EL0 U(0x28)
|
||||
#define CTX_IS_IN_EL3 U(0x30)
|
||||
#define CTX_CPTR_EL3 U(0x38)
|
||||
#define CTX_ZCR_EL3 U(0x40)
|
||||
#define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */
|
||||
|
||||
/*******************************************************************************
|
||||
* Constants that allow assembler code to access members of and the
|
||||
* 'el1_sys_regs' structure at their correct offsets. Note that some of the
|
||||
* registers are only 32-bits wide but are stored as 64-bit values for
|
||||
* convenience
|
||||
******************************************************************************/
|
||||
#define CTX_EL1_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END)
|
||||
#define CTX_SPSR_EL1 U(0x0)
|
||||
#define CTX_ELR_EL1 U(0x8)
|
||||
#define CTX_SCTLR_EL1 U(0x10)
|
||||
#define CTX_TCR_EL1 U(0x18)
|
||||
#define CTX_CPACR_EL1 U(0x20)
|
||||
#define CTX_CSSELR_EL1 U(0x28)
|
||||
#define CTX_SP_EL1 U(0x30)
|
||||
#define CTX_ESR_EL1 U(0x38)
|
||||
#define CTX_TTBR0_EL1 U(0x40)
|
||||
#define CTX_TTBR1_EL1 U(0x48)
|
||||
#define CTX_MAIR_EL1 U(0x50)
|
||||
#define CTX_AMAIR_EL1 U(0x58)
|
||||
#define CTX_ACTLR_EL1 U(0x60)
|
||||
#define CTX_TPIDR_EL1 U(0x68)
|
||||
#define CTX_TPIDR_EL0 U(0x70)
|
||||
#define CTX_TPIDRRO_EL0 U(0x78)
|
||||
#define CTX_PAR_EL1 U(0x80)
|
||||
#define CTX_FAR_EL1 U(0x88)
|
||||
#define CTX_AFSR0_EL1 U(0x90)
|
||||
#define CTX_AFSR1_EL1 U(0x98)
|
||||
#define CTX_CONTEXTIDR_EL1 U(0xa0)
|
||||
#define CTX_VBAR_EL1 U(0xa8)
|
||||
|
||||
/*
|
||||
* If the platform is AArch64-only, there is no need to save and restore these
|
||||
* AArch32 registers.
|
||||
*/
|
||||
#if CTX_INCLUDE_AARCH32_REGS
|
||||
#define CTX_SPSR_ABT U(0xb0) /* Align to the next 16 byte boundary */
|
||||
#define CTX_SPSR_UND U(0xb8)
|
||||
#define CTX_SPSR_IRQ U(0xc0)
|
||||
#define CTX_SPSR_FIQ U(0xc8)
|
||||
#define CTX_DACR32_EL2 U(0xd0)
|
||||
#define CTX_IFSR32_EL2 U(0xd8)
|
||||
#define CTX_AARCH32_END U(0xe0) /* Align to the next 16 byte boundary */
|
||||
#else
|
||||
#define CTX_AARCH32_END U(0xb0) /* Align to the next 16 byte boundary */
|
||||
#endif /* CTX_INCLUDE_AARCH32_REGS */
|
||||
|
||||
/*
|
||||
* If the timer registers aren't saved and restored, we don't have to reserve
|
||||
* space for them in the context
|
||||
*/
|
||||
#if NS_TIMER_SWITCH
|
||||
#define CTX_CNTP_CTL_EL0 (CTX_AARCH32_END + U(0x0))
|
||||
#define CTX_CNTP_CVAL_EL0 (CTX_AARCH32_END + U(0x8))
|
||||
#define CTX_CNTV_CTL_EL0 (CTX_AARCH32_END + U(0x10))
|
||||
#define CTX_CNTV_CVAL_EL0 (CTX_AARCH32_END + U(0x18))
|
||||
#define CTX_CNTKCTL_EL1 (CTX_AARCH32_END + U(0x20))
|
||||
#define CTX_TIMER_SYSREGS_END (CTX_AARCH32_END + U(0x30)) /* Align to the next 16 byte boundary */
|
||||
#else
|
||||
#define CTX_TIMER_SYSREGS_END CTX_AARCH32_END
|
||||
#endif /* NS_TIMER_SWITCH */
|
||||
|
||||
#if CTX_INCLUDE_MTE_REGS
|
||||
#define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0))
|
||||
#define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8))
|
||||
#define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10))
|
||||
#define CTX_GCR_EL1 (CTX_TIMER_SYSREGS_END + U(0x18))
|
||||
|
||||
/* Align to the next 16 byte boundary */
|
||||
#define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20))
|
||||
#else
|
||||
#define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END
|
||||
#endif /* CTX_INCLUDE_MTE_REGS */
|
||||
|
||||
/*
|
||||
* End of system registers.
|
||||
*/
|
||||
#define CTX_EL1_SYSREGS_END CTX_MTE_REGS_END
|
||||
|
||||
/*
|
||||
* EL2 register set
|
||||
*/
|
||||
|
||||
#if CTX_INCLUDE_EL2_REGS
|
||||
/* For later discussion
|
||||
* ICH_AP0R<n>_EL2
|
||||
* ICH_AP1R<n>_EL2
|
||||
* AMEVCNTVOFF0<n>_EL2
|
||||
* AMEVCNTVOFF1<n>_EL2
|
||||
* ICH_LR<n>_EL2
|
||||
*/
|
||||
#define CTX_EL2_SYSREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END)
|
||||
|
||||
#define CTX_ACTLR_EL2 U(0x0)
|
||||
#define CTX_AFSR0_EL2 U(0x8)
|
||||
#define CTX_AFSR1_EL2 U(0x10)
|
||||
#define CTX_AMAIR_EL2 U(0x18)
|
||||
#define CTX_CNTHCTL_EL2 U(0x20)
|
||||
#define CTX_CNTVOFF_EL2 U(0x28)
|
||||
#define CTX_CPTR_EL2 U(0x30)
|
||||
#define CTX_DBGVCR32_EL2 U(0x38)
|
||||
#define CTX_ELR_EL2 U(0x40)
|
||||
#define CTX_ESR_EL2 U(0x48)
|
||||
#define CTX_FAR_EL2 U(0x50)
|
||||
#define CTX_HACR_EL2 U(0x58)
|
||||
#define CTX_HCR_EL2 U(0x60)
|
||||
#define CTX_HPFAR_EL2 U(0x68)
|
||||
#define CTX_HSTR_EL2 U(0x70)
|
||||
#define CTX_ICC_SRE_EL2 U(0x78)
|
||||
#define CTX_ICH_HCR_EL2 U(0x80)
|
||||
#define CTX_ICH_VMCR_EL2 U(0x88)
|
||||
#define CTX_MAIR_EL2 U(0x90)
|
||||
#define CTX_MDCR_EL2 U(0x98)
|
||||
#define CTX_PMSCR_EL2 U(0xa0)
|
||||
#define CTX_SCTLR_EL2 U(0xa8)
|
||||
#define CTX_SPSR_EL2 U(0xb0)
|
||||
#define CTX_SP_EL2 U(0xb8)
|
||||
#define CTX_TCR_EL2 U(0xc0)
|
||||
#define CTX_TPIDR_EL2 U(0xc8)
|
||||
#define CTX_TTBR0_EL2 U(0xd0)
|
||||
#define CTX_VBAR_EL2 U(0xd8)
|
||||
#define CTX_VMPIDR_EL2 U(0xe0)
|
||||
#define CTX_VPIDR_EL2 U(0xe8)
|
||||
#define CTX_VTCR_EL2 U(0xf0)
|
||||
#define CTX_VTTBR_EL2 U(0xf8)
|
||||
|
||||
// Only if MTE registers in use
|
||||
#define CTX_TFSR_EL2 U(0x100)
|
||||
|
||||
// Only if ENABLE_MPAM_FOR_LOWER_ELS==1
|
||||
#define CTX_MPAM2_EL2 U(0x108)
|
||||
#define CTX_MPAMHCR_EL2 U(0x110)
|
||||
#define CTX_MPAMVPM0_EL2 U(0x118)
|
||||
#define CTX_MPAMVPM1_EL2 U(0x120)
|
||||
#define CTX_MPAMVPM2_EL2 U(0x128)
|
||||
#define CTX_MPAMVPM3_EL2 U(0x130)
|
||||
#define CTX_MPAMVPM4_EL2 U(0x138)
|
||||
#define CTX_MPAMVPM5_EL2 U(0x140)
|
||||
#define CTX_MPAMVPM6_EL2 U(0x148)
|
||||
#define CTX_MPAMVPM7_EL2 U(0x150)
|
||||
#define CTX_MPAMVPMV_EL2 U(0x158)
|
||||
|
||||
// Starting with Armv8.6
|
||||
#define CTX_HDFGRTR_EL2 U(0x160)
|
||||
#define CTX_HAFGRTR_EL2 U(0x168)
|
||||
#define CTX_HDFGWTR_EL2 U(0x170)
|
||||
#define CTX_HFGITR_EL2 U(0x178)
|
||||
#define CTX_HFGRTR_EL2 U(0x180)
|
||||
#define CTX_HFGWTR_EL2 U(0x188)
|
||||
#define CTX_CNTPOFF_EL2 U(0x190)
|
||||
|
||||
// Starting with Armv8.4
|
||||
#define CTX_CONTEXTIDR_EL2 U(0x198)
|
||||
#define CTX_TTBR1_EL2 U(0x1a0)
|
||||
#define CTX_VDISR_EL2 U(0x1a8)
|
||||
#define CTX_VSESR_EL2 U(0x1b0)
|
||||
#define CTX_VNCR_EL2 U(0x1b8)
|
||||
#define CTX_TRFCR_EL2 U(0x1c0)
|
||||
|
||||
// Starting with Armv8.5
|
||||
#define CTX_SCXTNUM_EL2 U(0x1c8)
|
||||
|
||||
// Register for FEAT_HCX
|
||||
#define CTX_HCRX_EL2 U(0x1d0)
|
||||
|
||||
/* Align to the next 16 byte boundary */
|
||||
#define CTX_EL2_SYSREGS_END U(0x1e0)
|
||||
|
||||
#endif /* CTX_INCLUDE_EL2_REGS */
|
||||
|
||||
/*******************************************************************************
|
||||
* Constants that allow assembler code to access members of and the 'fp_regs'
|
||||
* structure at their correct offsets.
|
||||
******************************************************************************/
|
||||
#if CTX_INCLUDE_EL2_REGS
|
||||
# define CTX_FPREGS_OFFSET (CTX_EL2_SYSREGS_OFFSET + CTX_EL2_SYSREGS_END)
|
||||
#else
|
||||
# define CTX_FPREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END)
|
||||
#endif
|
||||
#if CTX_INCLUDE_FPREGS
|
||||
#define CTX_FP_Q0 U(0x0)
|
||||
#define CTX_FP_Q1 U(0x10)
|
||||
#define CTX_FP_Q2 U(0x20)
|
||||
#define CTX_FP_Q3 U(0x30)
|
||||
#define CTX_FP_Q4 U(0x40)
|
||||
#define CTX_FP_Q5 U(0x50)
|
||||
#define CTX_FP_Q6 U(0x60)
|
||||
#define CTX_FP_Q7 U(0x70)
|
||||
#define CTX_FP_Q8 U(0x80)
|
||||
#define CTX_FP_Q9 U(0x90)
|
||||
#define CTX_FP_Q10 U(0xa0)
|
||||
#define CTX_FP_Q11 U(0xb0)
|
||||
#define CTX_FP_Q12 U(0xc0)
|
||||
#define CTX_FP_Q13 U(0xd0)
|
||||
#define CTX_FP_Q14 U(0xe0)
|
||||
#define CTX_FP_Q15 U(0xf0)
|
||||
#define CTX_FP_Q16 U(0x100)
|
||||
#define CTX_FP_Q17 U(0x110)
|
||||
#define CTX_FP_Q18 U(0x120)
|
||||
#define CTX_FP_Q19 U(0x130)
|
||||
#define CTX_FP_Q20 U(0x140)
|
||||
#define CTX_FP_Q21 U(0x150)
|
||||
#define CTX_FP_Q22 U(0x160)
|
||||
#define CTX_FP_Q23 U(0x170)
|
||||
#define CTX_FP_Q24 U(0x180)
|
||||
#define CTX_FP_Q25 U(0x190)
|
||||
#define CTX_FP_Q26 U(0x1a0)
|
||||
#define CTX_FP_Q27 U(0x1b0)
|
||||
#define CTX_FP_Q28 U(0x1c0)
|
||||
#define CTX_FP_Q29 U(0x1d0)
|
||||
#define CTX_FP_Q30 U(0x1e0)
|
||||
#define CTX_FP_Q31 U(0x1f0)
|
||||
#define CTX_FP_FPSR U(0x200)
|
||||
#define CTX_FP_FPCR U(0x208)
|
||||
#if CTX_INCLUDE_AARCH32_REGS
|
||||
#define CTX_FP_FPEXC32_EL2 U(0x210)
|
||||
#define CTX_FPREGS_END U(0x220) /* Align to the next 16 byte boundary */
|
||||
#else
|
||||
#define CTX_FPREGS_END U(0x210) /* Align to the next 16 byte boundary */
|
||||
#endif
|
||||
#else
|
||||
#define CTX_FPREGS_END U(0)
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Registers related to CVE-2018-3639
|
||||
******************************************************************************/
|
||||
#define CTX_CVE_2018_3639_OFFSET (CTX_FPREGS_OFFSET + CTX_FPREGS_END)
|
||||
#define CTX_CVE_2018_3639_DISABLE U(0)
|
||||
#define CTX_CVE_2018_3639_END U(0x10) /* Align to the next 16 byte boundary */
|
||||
|
||||
/*******************************************************************************
|
||||
* Registers related to ARMv8.3-PAuth.
|
||||
******************************************************************************/
|
||||
#define CTX_PAUTH_REGS_OFFSET (CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_END)
|
||||
#if CTX_INCLUDE_PAUTH_REGS
|
||||
#define CTX_PACIAKEY_LO U(0x0)
|
||||
#define CTX_PACIAKEY_HI U(0x8)
|
||||
#define CTX_PACIBKEY_LO U(0x10)
|
||||
#define CTX_PACIBKEY_HI U(0x18)
|
||||
#define CTX_PACDAKEY_LO U(0x20)
|
||||
#define CTX_PACDAKEY_HI U(0x28)
|
||||
#define CTX_PACDBKEY_LO U(0x30)
|
||||
#define CTX_PACDBKEY_HI U(0x38)
|
||||
#define CTX_PACGAKEY_LO U(0x40)
|
||||
#define CTX_PACGAKEY_HI U(0x48)
|
||||
#define CTX_PAUTH_REGS_END U(0x50) /* Align to the next 16 byte boundary */
|
||||
#else
|
||||
#define CTX_PAUTH_REGS_END U(0)
|
||||
#endif /* CTX_INCLUDE_PAUTH_REGS */
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <lib/cassert.h>
|
||||
|
||||
/*
|
||||
* Common constants to help define the 'cpu_context' structure and its
|
||||
* members below.
|
||||
*/
|
||||
#define DWORD_SHIFT U(3)
|
||||
#define DEFINE_REG_STRUCT(name, num_regs) \
|
||||
typedef struct name { \
|
||||
uint64_t ctx_regs[num_regs]; \
|
||||
} __aligned(16) name##_t
|
||||
|
||||
/* Constants to determine the size of individual context structures */
|
||||
#define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT)
|
||||
#define CTX_EL1_SYSREGS_ALL (CTX_EL1_SYSREGS_END >> DWORD_SHIFT)
|
||||
#if CTX_INCLUDE_EL2_REGS
|
||||
# define CTX_EL2_SYSREGS_ALL (CTX_EL2_SYSREGS_END >> DWORD_SHIFT)
|
||||
#endif
|
||||
#if CTX_INCLUDE_FPREGS
|
||||
# define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT)
|
||||
#endif
|
||||
#define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT)
|
||||
#define CTX_CVE_2018_3639_ALL (CTX_CVE_2018_3639_END >> DWORD_SHIFT)
|
||||
#if CTX_INCLUDE_PAUTH_REGS
|
||||
# define CTX_PAUTH_REGS_ALL (CTX_PAUTH_REGS_END >> DWORD_SHIFT)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* AArch64 general purpose register context structure. Usually x0-x18,
|
||||
* lr are saved as the compiler is expected to preserve the remaining
|
||||
* callee saved registers if used by the C runtime and the assembler
|
||||
* does not touch the remaining. But in case of world switch during
|
||||
* exception handling, we need to save the callee registers too.
|
||||
*/
|
||||
DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL);
|
||||
|
||||
/*
|
||||
* AArch64 EL1 system register context structure for preserving the
|
||||
* architectural state during world switches.
|
||||
*/
|
||||
DEFINE_REG_STRUCT(el1_sysregs, CTX_EL1_SYSREGS_ALL);
|
||||
|
||||
|
||||
/*
|
||||
* AArch64 EL2 system register context structure for preserving the
|
||||
* architectural state during world switches.
|
||||
*/
|
||||
#if CTX_INCLUDE_EL2_REGS
|
||||
DEFINE_REG_STRUCT(el2_sysregs, CTX_EL2_SYSREGS_ALL);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* AArch64 floating point register context structure for preserving
|
||||
* the floating point state during switches from one security state to
|
||||
* another.
|
||||
*/
|
||||
#if CTX_INCLUDE_FPREGS
|
||||
DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous registers used by EL3 firmware to maintain its state
|
||||
* across exception entries and exits
|
||||
*/
|
||||
DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL);
|
||||
|
||||
/* Function pointer used by CVE-2018-3639 dynamic mitigation */
|
||||
DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL);
|
||||
|
||||
/* Registers associated to ARMv8.3-PAuth */
|
||||
#if CTX_INCLUDE_PAUTH_REGS
|
||||
DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Macros to access members of any of the above structures using their
|
||||
* offsets
|
||||
*/
|
||||
#define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT])
|
||||
#define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \
|
||||
= (uint64_t) (val))
|
||||
|
||||
/*
|
||||
* Top-level context structure which is used by EL3 firmware to preserve
|
||||
* the state of a core at the next lower EL in a given security state and
|
||||
* save enough EL3 meta data to be able to return to that EL and security
|
||||
* state. The context management library will be used to ensure that
|
||||
* SP_EL3 always points to an instance of this structure at exception
|
||||
* entry and exit.
|
||||
*/
|
||||
typedef struct cpu_context {
|
||||
gp_regs_t gpregs_ctx;
|
||||
el3_state_t el3state_ctx;
|
||||
el1_sysregs_t el1_sysregs_ctx;
|
||||
#if CTX_INCLUDE_EL2_REGS
|
||||
el2_sysregs_t el2_sysregs_ctx;
|
||||
#endif
|
||||
#if CTX_INCLUDE_FPREGS
|
||||
fp_regs_t fpregs_ctx;
|
||||
#endif
|
||||
cve_2018_3639_t cve_2018_3639_ctx;
|
||||
#if CTX_INCLUDE_PAUTH_REGS
|
||||
pauth_t pauth_ctx;
|
||||
#endif
|
||||
} cpu_context_t;
|
||||
|
||||
/* Macros to access members of the 'cpu_context_t' structure */
|
||||
#define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx)
|
||||
#if CTX_INCLUDE_FPREGS
|
||||
# define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx)
|
||||
#endif
|
||||
#define get_el1_sysregs_ctx(h) (&((cpu_context_t *) h)->el1_sysregs_ctx)
|
||||
#if CTX_INCLUDE_EL2_REGS
|
||||
# define get_el2_sysregs_ctx(h) (&((cpu_context_t *) h)->el2_sysregs_ctx)
|
||||
#endif
|
||||
#define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx)
|
||||
#define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx)
|
||||
#if CTX_INCLUDE_PAUTH_REGS
|
||||
# define get_pauth_ctx(h) (&((cpu_context_t *) h)->pauth_ctx)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Compile time assertions related to the 'cpu_context' structure to
|
||||
* ensure that the assembler and the compiler view of the offsets of
|
||||
* the structure members is the same.
|
||||
*/
|
||||
CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \
|
||||
assert_core_context_gp_offset_mismatch);
|
||||
CASSERT(CTX_EL1_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el1_sysregs_ctx), \
|
||||
assert_core_context_el1_sys_offset_mismatch);
|
||||
#if CTX_INCLUDE_EL2_REGS
|
||||
CASSERT(CTX_EL2_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el2_sysregs_ctx), \
|
||||
assert_core_context_el2_sys_offset_mismatch);
|
||||
#endif
|
||||
#if CTX_INCLUDE_FPREGS
|
||||
CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \
|
||||
assert_core_context_fp_offset_mismatch);
|
||||
#endif
|
||||
CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \
|
||||
assert_core_context_el3state_offset_mismatch);
|
||||
CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), \
|
||||
assert_core_context_cve_2018_3639_offset_mismatch);
|
||||
#if CTX_INCLUDE_PAUTH_REGS
|
||||
CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), \
|
||||
assert_core_context_pauth_offset_mismatch);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Helper macro to set the general purpose registers that correspond to
|
||||
* parameters in an aapcs_64 call i.e. x0-x7
|
||||
*/
|
||||
#define set_aapcs_args0(ctx, x0) do { \
|
||||
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \
|
||||
} while (0)
|
||||
#define set_aapcs_args1(ctx, x0, x1) do { \
|
||||
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \
|
||||
set_aapcs_args0(ctx, x0); \
|
||||
} while (0)
|
||||
#define set_aapcs_args2(ctx, x0, x1, x2) do { \
|
||||
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \
|
||||
set_aapcs_args1(ctx, x0, x1); \
|
||||
} while (0)
|
||||
#define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \
|
||||
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \
|
||||
set_aapcs_args2(ctx, x0, x1, x2); \
|
||||
} while (0)
|
||||
#define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \
|
||||
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \
|
||||
set_aapcs_args3(ctx, x0, x1, x2, x3); \
|
||||
} while (0)
|
||||
#define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \
|
||||
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \
|
||||
set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \
|
||||
} while (0)
|
||||
#define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \
|
||||
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \
|
||||
set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \
|
||||
} while (0)
|
||||
#define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \
|
||||
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \
|
||||
set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \
|
||||
} while (0)
|
||||
|
||||
/*******************************************************************************
|
||||
* Function prototypes
|
||||
******************************************************************************/
|
||||
void el1_sysregs_context_save(el1_sysregs_t *regs);
|
||||
void el1_sysregs_context_restore(el1_sysregs_t *regs);
|
||||
|
||||
#if CTX_INCLUDE_EL2_REGS
|
||||
void el2_sysregs_context_save_common(el2_sysregs_t *regs);
|
||||
void el2_sysregs_context_restore_common(el2_sysregs_t *regs);
|
||||
#if ENABLE_SPE_FOR_LOWER_ELS
|
||||
void el2_sysregs_context_save_spe(el2_sysregs_t *regs);
|
||||
void el2_sysregs_context_restore_spe(el2_sysregs_t *regs);
|
||||
#endif /* ENABLE_SPE_FOR_LOWER_ELS */
|
||||
#if CTX_INCLUDE_MTE_REGS
|
||||
void el2_sysregs_context_save_mte(el2_sysregs_t *regs);
|
||||
void el2_sysregs_context_restore_mte(el2_sysregs_t *regs);
|
||||
#endif /* CTX_INCLUDE_MTE_REGS */
|
||||
#if ENABLE_MPAM_FOR_LOWER_ELS
|
||||
void el2_sysregs_context_save_mpam(el2_sysregs_t *regs);
|
||||
void el2_sysregs_context_restore_mpam(el2_sysregs_t *regs);
|
||||
#endif /* ENABLE_MPAM_FOR_LOWER_ELS */
|
||||
#if ENABLE_FEAT_FGT
|
||||
void el2_sysregs_context_save_fgt(el2_sysregs_t *regs);
|
||||
void el2_sysregs_context_restore_fgt(el2_sysregs_t *regs);
|
||||
#endif /* ENABLE_FEAT_FGT */
|
||||
#if ENABLE_FEAT_ECV
|
||||
void el2_sysregs_context_save_ecv(el2_sysregs_t *regs);
|
||||
void el2_sysregs_context_restore_ecv(el2_sysregs_t *regs);
|
||||
#endif /* ENABLE_FEAT_ECV */
|
||||
#if ENABLE_FEAT_VHE
|
||||
void el2_sysregs_context_save_vhe(el2_sysregs_t *regs);
|
||||
void el2_sysregs_context_restore_vhe(el2_sysregs_t *regs);
|
||||
#endif /* ENABLE_FEAT_VHE */
|
||||
#if RAS_EXTENSION
|
||||
void el2_sysregs_context_save_ras(el2_sysregs_t *regs);
|
||||
void el2_sysregs_context_restore_ras(el2_sysregs_t *regs);
|
||||
#endif /* RAS_EXTENSION */
|
||||
#if CTX_INCLUDE_NEVE_REGS
|
||||
void el2_sysregs_context_save_nv2(el2_sysregs_t *regs);
|
||||
void el2_sysregs_context_restore_nv2(el2_sysregs_t *regs);
|
||||
#endif /* CTX_INCLUDE_NEVE_REGS */
|
||||
#if ENABLE_TRF_FOR_NS
|
||||
void el2_sysregs_context_save_trf(el2_sysregs_t *regs);
|
||||
void el2_sysregs_context_restore_trf(el2_sysregs_t *regs);
|
||||
#endif /* ENABLE_TRF_FOR_NS */
|
||||
#if ENABLE_FEAT_CSV2_2
|
||||
void el2_sysregs_context_save_csv2(el2_sysregs_t *regs);
|
||||
void el2_sysregs_context_restore_csv2(el2_sysregs_t *regs);
|
||||
#endif /* ENABLE_FEAT_CSV2_2 */
|
||||
#if ENABLE_FEAT_HCX
|
||||
void el2_sysregs_context_save_hcx(el2_sysregs_t *regs);
|
||||
void el2_sysregs_context_restore_hcx(el2_sysregs_t *regs);
|
||||
#endif /* ENABLE_FEAT_HCX */
|
||||
#endif /* CTX_INCLUDE_EL2_REGS */
|
||||
|
||||
#if CTX_INCLUDE_FPREGS
|
||||
void fpregs_context_save(fp_regs_t *regs);
|
||||
void fpregs_context_restore(fp_regs_t *regs);
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* CONTEXT_H */
|
||||
@@ -0,0 +1,89 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CONTEXT_MGMT_H
|
||||
#define CONTEXT_MGMT_H
|
||||
|
||||
#include <assert.h>
|
||||
#include <context.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <arch.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Forward declarations
|
||||
******************************************************************************/
|
||||
struct entry_point_info;
|
||||
|
||||
/*******************************************************************************
|
||||
* Function & variable prototypes
|
||||
******************************************************************************/
|
||||
void cm_init(void);
|
||||
void *cm_get_context_by_index(unsigned int cpu_idx,
|
||||
unsigned int security_state);
|
||||
void cm_set_context_by_index(unsigned int cpu_idx,
|
||||
void *context,
|
||||
unsigned int security_state);
|
||||
void *cm_get_context(uint32_t security_state);
|
||||
void cm_set_context(void *context, uint32_t security_state);
|
||||
void cm_init_my_context(const struct entry_point_info *ep);
|
||||
void cm_init_context_by_index(unsigned int cpu_idx,
|
||||
const struct entry_point_info *ep);
|
||||
void cm_setup_context(cpu_context_t *ctx, const struct entry_point_info *ep);
|
||||
void cm_prepare_el3_exit(uint32_t security_state);
|
||||
void cm_prepare_el3_exit_ns(void);
|
||||
|
||||
#ifdef __aarch64__
|
||||
#if CTX_INCLUDE_EL2_REGS
|
||||
void cm_el2_sysregs_context_save(uint32_t security_state);
|
||||
void cm_el2_sysregs_context_restore(uint32_t security_state);
|
||||
#endif
|
||||
|
||||
void cm_el1_sysregs_context_save(uint32_t security_state);
|
||||
void cm_el1_sysregs_context_restore(uint32_t security_state);
|
||||
void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint);
|
||||
void cm_set_elr_spsr_el3(uint32_t security_state,
|
||||
uintptr_t entrypoint, uint32_t spsr);
|
||||
void cm_write_scr_el3_bit(uint32_t security_state,
|
||||
uint32_t bit_pos,
|
||||
uint32_t value);
|
||||
void cm_set_next_eret_context(uint32_t security_state);
|
||||
u_register_t cm_get_scr_el3(uint32_t security_state);
|
||||
|
||||
/* Inline definitions */
|
||||
|
||||
/*******************************************************************************
|
||||
* This function is used to program the context that's used for exception
|
||||
* return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
|
||||
* the required security state
|
||||
******************************************************************************/
|
||||
static inline void cm_set_next_context(void *context)
|
||||
{
|
||||
#if ENABLE_ASSERTIONS
|
||||
uint64_t sp_mode;
|
||||
|
||||
/*
|
||||
* Check that this function is called with SP_EL0 as the stack
|
||||
* pointer
|
||||
*/
|
||||
__asm__ volatile("mrs %0, SPSel\n"
|
||||
: "=r" (sp_mode));
|
||||
|
||||
assert(sp_mode == MODE_SP_EL0);
|
||||
#endif /* ENABLE_ASSERTIONS */
|
||||
|
||||
__asm__ volatile("msr spsel, #1\n"
|
||||
"mov sp, %0\n"
|
||||
"msr spsel, #0\n"
|
||||
: : "r" (context));
|
||||
}
|
||||
|
||||
#else
|
||||
void *cm_get_next_context(void);
|
||||
void cm_set_next_context(void *context);
|
||||
#endif /* __aarch64__ */
|
||||
|
||||
#endif /* CONTEXT_MGMT_H */
|
||||
@@ -0,0 +1,237 @@
|
||||
/*
|
||||
* Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CPU_DATA_H
|
||||
#define CPU_DATA_H
|
||||
|
||||
#include <platform_def.h> /* CACHE_WRITEBACK_GRANULE required */
|
||||
|
||||
#include <bl31/ehf.h>
|
||||
|
||||
/* Size of psci_cpu_data structure */
|
||||
#define PSCI_CPU_DATA_SIZE 12
|
||||
|
||||
#ifdef __aarch64__
|
||||
|
||||
/* 8-bytes aligned size of psci_cpu_data structure */
|
||||
#define PSCI_CPU_DATA_SIZE_ALIGNED ((PSCI_CPU_DATA_SIZE + 7) & ~7)
|
||||
|
||||
#if ENABLE_RME
|
||||
/* Size of cpu_context array */
|
||||
#define CPU_DATA_CONTEXT_NUM 3
|
||||
/* Offset of cpu_ops_ptr, size 8 bytes */
|
||||
#define CPU_DATA_CPU_OPS_PTR 0x18
|
||||
#else /* ENABLE_RME */
|
||||
#define CPU_DATA_CONTEXT_NUM 2
|
||||
#define CPU_DATA_CPU_OPS_PTR 0x10
|
||||
#endif /* ENABLE_RME */
|
||||
|
||||
#if ENABLE_PAUTH
|
||||
/* 8-bytes aligned offset of apiakey[2], size 16 bytes */
|
||||
#define CPU_DATA_APIAKEY_OFFSET (0x8 + PSCI_CPU_DATA_SIZE_ALIGNED \
|
||||
+ CPU_DATA_CPU_OPS_PTR)
|
||||
#define CPU_DATA_CRASH_BUF_OFFSET (0x10 + CPU_DATA_APIAKEY_OFFSET)
|
||||
#else /* ENABLE_PAUTH */
|
||||
#define CPU_DATA_CRASH_BUF_OFFSET (0x8 + PSCI_CPU_DATA_SIZE_ALIGNED \
|
||||
+ CPU_DATA_CPU_OPS_PTR)
|
||||
#endif /* ENABLE_PAUTH */
|
||||
|
||||
/* need enough space in crash buffer to save 8 registers */
|
||||
#define CPU_DATA_CRASH_BUF_SIZE 64
|
||||
|
||||
#else /* !__aarch64__ */
|
||||
|
||||
#if CRASH_REPORTING
|
||||
#error "Crash reporting is not supported in AArch32"
|
||||
#endif
|
||||
#define CPU_DATA_CPU_OPS_PTR 0x0
|
||||
#define CPU_DATA_CRASH_BUF_OFFSET (0x4 + PSCI_CPU_DATA_SIZE)
|
||||
|
||||
#endif /* __aarch64__ */
|
||||
|
||||
#if CRASH_REPORTING
|
||||
#define CPU_DATA_CRASH_BUF_END (CPU_DATA_CRASH_BUF_OFFSET + \
|
||||
CPU_DATA_CRASH_BUF_SIZE)
|
||||
#else
|
||||
#define CPU_DATA_CRASH_BUF_END CPU_DATA_CRASH_BUF_OFFSET
|
||||
#endif
|
||||
|
||||
/* cpu_data size is the data size rounded up to the platform cache line size */
|
||||
#define CPU_DATA_SIZE (((CPU_DATA_CRASH_BUF_END + \
|
||||
CACHE_WRITEBACK_GRANULE - 1) / \
|
||||
CACHE_WRITEBACK_GRANULE) * \
|
||||
CACHE_WRITEBACK_GRANULE)
|
||||
|
||||
#if ENABLE_RUNTIME_INSTRUMENTATION
|
||||
/* Temporary space to store PMF timestamps from assembly code */
|
||||
#define CPU_DATA_PMF_TS_COUNT 1
|
||||
#define CPU_DATA_PMF_TS0_OFFSET CPU_DATA_CRASH_BUF_END
|
||||
#define CPU_DATA_PMF_TS0_IDX 0
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <lib/cassert.h>
|
||||
#include <lib/psci/psci.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
/* Offsets for the cpu_data structure */
|
||||
#define CPU_DATA_PSCI_LOCK_OFFSET __builtin_offsetof\
|
||||
(cpu_data_t, psci_svc_cpu_data.pcpu_bakery_info)
|
||||
|
||||
#if PLAT_PCPU_DATA_SIZE
|
||||
#define CPU_DATA_PLAT_PCPU_OFFSET __builtin_offsetof\
|
||||
(cpu_data_t, platform_cpu_data)
|
||||
#endif
|
||||
|
||||
typedef enum context_pas {
|
||||
CPU_CONTEXT_SECURE = 0,
|
||||
CPU_CONTEXT_NS,
|
||||
#if ENABLE_RME
|
||||
CPU_CONTEXT_REALM,
|
||||
#endif
|
||||
CPU_CONTEXT_NUM
|
||||
} context_pas_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Function & variable prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Cache of frequently used per-cpu data:
|
||||
* Pointers to non-secure, realm, and secure security state contexts
|
||||
* Address of the crash stack
|
||||
* It is aligned to the cache line boundary to allow efficient concurrent
|
||||
* manipulation of these pointers on different cpus
|
||||
*
|
||||
* The data structure and the _cpu_data accessors should not be used directly
|
||||
* by components that have per-cpu members. The member access macros should be
|
||||
* used for this.
|
||||
******************************************************************************/
|
||||
typedef struct cpu_data {
|
||||
#ifdef __aarch64__
|
||||
void *cpu_context[CPU_DATA_CONTEXT_NUM];
|
||||
#endif /* __aarch64__ */
|
||||
uintptr_t cpu_ops_ptr;
|
||||
struct psci_cpu_data psci_svc_cpu_data;
|
||||
#if ENABLE_PAUTH
|
||||
uint64_t apiakey[2];
|
||||
#endif
|
||||
#if CRASH_REPORTING
|
||||
u_register_t crash_buf[CPU_DATA_CRASH_BUF_SIZE >> 3];
|
||||
#endif
|
||||
#if ENABLE_RUNTIME_INSTRUMENTATION
|
||||
uint64_t cpu_data_pmf_ts[CPU_DATA_PMF_TS_COUNT];
|
||||
#endif
|
||||
#if PLAT_PCPU_DATA_SIZE
|
||||
uint8_t platform_cpu_data[PLAT_PCPU_DATA_SIZE];
|
||||
#endif
|
||||
#if defined(IMAGE_BL31) && EL3_EXCEPTION_HANDLING
|
||||
pe_exc_data_t ehf_data;
|
||||
#endif
|
||||
} __aligned(CACHE_WRITEBACK_GRANULE) cpu_data_t;
|
||||
|
||||
extern cpu_data_t percpu_data[PLATFORM_CORE_COUNT];
|
||||
|
||||
#ifdef __aarch64__
|
||||
CASSERT(CPU_DATA_CONTEXT_NUM == CPU_CONTEXT_NUM,
|
||||
assert_cpu_data_context_num_mismatch);
|
||||
#endif
|
||||
|
||||
#if ENABLE_PAUTH
|
||||
CASSERT(CPU_DATA_APIAKEY_OFFSET == __builtin_offsetof
|
||||
(cpu_data_t, apiakey),
|
||||
assert_cpu_data_pauth_stack_offset_mismatch);
|
||||
#endif
|
||||
|
||||
#if CRASH_REPORTING
|
||||
/* verify assembler offsets match data structures */
|
||||
CASSERT(CPU_DATA_CRASH_BUF_OFFSET == __builtin_offsetof
|
||||
(cpu_data_t, crash_buf),
|
||||
assert_cpu_data_crash_stack_offset_mismatch);
|
||||
#endif
|
||||
|
||||
CASSERT(CPU_DATA_SIZE == sizeof(cpu_data_t),
|
||||
assert_cpu_data_size_mismatch);
|
||||
|
||||
CASSERT(CPU_DATA_CPU_OPS_PTR == __builtin_offsetof
|
||||
(cpu_data_t, cpu_ops_ptr),
|
||||
assert_cpu_data_cpu_ops_ptr_offset_mismatch);
|
||||
|
||||
#if ENABLE_RUNTIME_INSTRUMENTATION
|
||||
CASSERT(CPU_DATA_PMF_TS0_OFFSET == __builtin_offsetof
|
||||
(cpu_data_t, cpu_data_pmf_ts[0]),
|
||||
assert_cpu_data_pmf_ts0_offset_mismatch);
|
||||
#endif
|
||||
|
||||
struct cpu_data *_cpu_data_by_index(uint32_t cpu_index);
|
||||
|
||||
#ifdef __aarch64__
|
||||
/* Return the cpu_data structure for the current CPU. */
|
||||
static inline struct cpu_data *_cpu_data(void)
|
||||
{
|
||||
return (cpu_data_t *)read_tpidr_el3();
|
||||
}
|
||||
#else
|
||||
struct cpu_data *_cpu_data(void);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Returns the index of the cpu_context array for the given security state.
|
||||
* All accesses to cpu_context should be through this helper to make sure
|
||||
* an access is not out-of-bounds. The function assumes security_state is
|
||||
* valid.
|
||||
*/
|
||||
static inline context_pas_t get_cpu_context_index(uint32_t security_state)
|
||||
{
|
||||
if (security_state == SECURE) {
|
||||
return CPU_CONTEXT_SECURE;
|
||||
} else {
|
||||
#if ENABLE_RME
|
||||
if (security_state == NON_SECURE) {
|
||||
return CPU_CONTEXT_NS;
|
||||
} else {
|
||||
assert(security_state == REALM);
|
||||
return CPU_CONTEXT_REALM;
|
||||
}
|
||||
#else
|
||||
assert(security_state == NON_SECURE);
|
||||
return CPU_CONTEXT_NS;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
* APIs for initialising and accessing per-cpu data
|
||||
*************************************************************************/
|
||||
|
||||
void init_cpu_data_ptr(void);
|
||||
void init_cpu_ops(void);
|
||||
|
||||
#define get_cpu_data(_m) _cpu_data()->_m
|
||||
#define set_cpu_data(_m, _v) _cpu_data()->_m = (_v)
|
||||
#define get_cpu_data_by_index(_ix, _m) _cpu_data_by_index(_ix)->_m
|
||||
#define set_cpu_data_by_index(_ix, _m, _v) _cpu_data_by_index(_ix)->_m = (_v)
|
||||
/* ((cpu_data_t *)0)->_m is a dummy to get the sizeof the struct member _m */
|
||||
#define flush_cpu_data(_m) flush_dcache_range((uintptr_t) \
|
||||
&(_cpu_data()->_m), \
|
||||
sizeof(((cpu_data_t *)0)->_m))
|
||||
#define inv_cpu_data(_m) inv_dcache_range((uintptr_t) \
|
||||
&(_cpu_data()->_m), \
|
||||
sizeof(((cpu_data_t *)0)->_m))
|
||||
#define flush_cpu_data_by_index(_ix, _m) \
|
||||
flush_dcache_range((uintptr_t) \
|
||||
&(_cpu_data_by_index(_ix)->_m), \
|
||||
sizeof(((cpu_data_t *)0)->_m))
|
||||
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
#endif /* CPU_DATA_H */
|
||||
@@ -0,0 +1,106 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PUBSUB_H
|
||||
#define PUBSUB_H
|
||||
|
||||
#ifdef __LINKER__
|
||||
|
||||
/* For the linker ... */
|
||||
#define __pubsub_start_sym(event) __pubsub_##event##_start
|
||||
#define __pubsub_end_sym(event) __pubsub_##event##_end
|
||||
#define __pubsub_section(event) __pubsub_##event
|
||||
|
||||
/*
|
||||
* REGISTER_PUBSUB_EVENT has a different definition between linker and compiler
|
||||
* contexts. In linker context, this collects pubsub sections for each event,
|
||||
* placing guard symbols around each.
|
||||
*/
|
||||
#if defined(USE_ARM_LINK)
|
||||
#define REGISTER_PUBSUB_EVENT(event) \
|
||||
__pubsub_start_sym(event) +0 FIXED \
|
||||
{ \
|
||||
*(__pubsub_section(event)) \
|
||||
} \
|
||||
__pubsub_end_sym(event) +0 FIXED EMPTY 0 \
|
||||
{ \
|
||||
/* placeholder */ \
|
||||
}
|
||||
#else
|
||||
#define REGISTER_PUBSUB_EVENT(event) \
|
||||
__pubsub_start_sym(event) = .; \
|
||||
KEEP(*(__pubsub_section(event))); \
|
||||
__pubsub_end_sym(event) = .
|
||||
#endif
|
||||
|
||||
#else /* __LINKER__ */
|
||||
|
||||
/* For the compiler ... */
|
||||
|
||||
#include <assert.h>
|
||||
#include <cdefs.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#include <arch_helpers.h>
|
||||
|
||||
#if defined(USE_ARM_LINK)
|
||||
#define __pubsub_start_sym(event) Load$$__pubsub_##event##_start$$Base
|
||||
#define __pubsub_end_sym(event) Load$$__pubsub_##event##_end$$Base
|
||||
#else
|
||||
#define __pubsub_start_sym(event) __pubsub_##event##_start
|
||||
#define __pubsub_end_sym(event) __pubsub_##event##_end
|
||||
#endif
|
||||
|
||||
#define __pubsub_section(event) __section("__pubsub_" #event)
|
||||
|
||||
/*
|
||||
* In compiler context, REGISTER_PUBSUB_EVENT declares the per-event symbols
|
||||
* exported by the linker required for the other pubsub macros to work.
|
||||
*/
|
||||
#define REGISTER_PUBSUB_EVENT(event) \
|
||||
extern pubsub_cb_t __pubsub_start_sym(event)[]; \
|
||||
extern pubsub_cb_t __pubsub_end_sym(event)[]
|
||||
|
||||
/*
|
||||
* Have the function func called back when the specified event happens. This
|
||||
* macro places the function address into the pubsub section, which is picked up
|
||||
* and invoked by the invoke_pubsubs() function via the PUBLISH_EVENT* macros.
|
||||
*
|
||||
* The extern declaration is there to satisfy MISRA C-2012 rule 8.4.
|
||||
*/
|
||||
#define SUBSCRIBE_TO_EVENT(event, func) \
|
||||
extern pubsub_cb_t __cb_func_##func##event __pubsub_section(event); \
|
||||
pubsub_cb_t __cb_func_##func##event __pubsub_section(event) = (func)
|
||||
|
||||
/*
|
||||
* Iterate over subscribed handlers for a defined event. 'event' is the name of
|
||||
* the event, and 'subscriber' a local variable of type 'pubsub_cb_t *'.
|
||||
*/
|
||||
#define for_each_subscriber(event, subscriber) \
|
||||
for (subscriber = __pubsub_start_sym(event); \
|
||||
subscriber < __pubsub_end_sym(event); \
|
||||
subscriber++)
|
||||
|
||||
/*
|
||||
* Publish a defined event supplying an argument. All subscribed handlers are
|
||||
* invoked, but the return value of handlers are ignored for now.
|
||||
*/
|
||||
#define PUBLISH_EVENT_ARG(event, arg) \
|
||||
do { \
|
||||
pubsub_cb_t *subscriber; \
|
||||
for_each_subscriber(event, subscriber) { \
|
||||
(*subscriber)(arg); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
/* Publish a defined event with NULL argument */
|
||||
#define PUBLISH_EVENT(event) PUBLISH_EVENT_ARG(event, NULL)
|
||||
|
||||
/* Subscriber callback type */
|
||||
typedef void* (*pubsub_cb_t)(const void *arg);
|
||||
|
||||
#endif /* __LINKER__ */
|
||||
#endif /* PUBSUB_H */
|
||||
+43
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <lib/el3_runtime/pubsub.h>
|
||||
|
||||
/*
|
||||
* This file defines a list of pubsub events, declared using
|
||||
* REGISTER_PUBSUB_EVENT() macro.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Event published after a CPU has been powered up and finished its
|
||||
* initialization.
|
||||
*/
|
||||
REGISTER_PUBSUB_EVENT(psci_cpu_on_finish);
|
||||
|
||||
/*
|
||||
* These events are published before/after a CPU has been powered down/up
|
||||
* via the PSCI CPU SUSPEND API.
|
||||
*/
|
||||
REGISTER_PUBSUB_EVENT(psci_suspend_pwrdown_start);
|
||||
REGISTER_PUBSUB_EVENT(psci_suspend_pwrdown_finish);
|
||||
|
||||
#ifdef __aarch64__
|
||||
/*
|
||||
* These events are published by the AArch64 context management framework
|
||||
* after the secure context is restored/saved via
|
||||
* cm_el1_sysregs_context_{restore,save}() API.
|
||||
*/
|
||||
REGISTER_PUBSUB_EVENT(cm_entering_secure_world);
|
||||
REGISTER_PUBSUB_EVENT(cm_exited_secure_world);
|
||||
|
||||
/*
|
||||
* These events are published by the AArch64 context management framework
|
||||
* after the normal context is restored/saved via
|
||||
* cm_el1_sysregs_context_{restore,save}() API.
|
||||
*/
|
||||
REGISTER_PUBSUB_EVENT(cm_entering_normal_world);
|
||||
REGISTER_PUBSUB_EVENT(cm_exited_normal_world);
|
||||
#endif /* __aarch64__ */
|
||||
@@ -0,0 +1,47 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef AMU_H
|
||||
#define AMU_H
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <context.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#if __aarch64__
|
||||
void amu_enable(bool el2_unused, cpu_context_t *ctx);
|
||||
#else
|
||||
void amu_enable(bool el2_unused);
|
||||
#endif
|
||||
|
||||
#if ENABLE_AMU_AUXILIARY_COUNTERS
|
||||
/*
|
||||
* AMU data for a single core.
|
||||
*/
|
||||
struct amu_core {
|
||||
uint16_t enable; /* Mask of auxiliary counters to enable */
|
||||
};
|
||||
|
||||
/*
|
||||
* Topological platform data specific to the AMU.
|
||||
*/
|
||||
struct amu_topology {
|
||||
struct amu_core cores[PLATFORM_CORE_COUNT]; /* Per-core data */
|
||||
};
|
||||
|
||||
#if !ENABLE_AMU_FCONF
|
||||
/*
|
||||
* Retrieve the platform's AMU topology. A `NULL` return value is treated as a
|
||||
* non-fatal error, in which case no auxiliary counters will be enabled.
|
||||
*/
|
||||
const struct amu_topology *plat_amu_topology(void);
|
||||
#endif /* ENABLE_AMU_FCONF */
|
||||
#endif /* ENABLE_AMU_AUXILIARY_COUNTERS */
|
||||
|
||||
#endif /* AMU_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
/*
|
||||
* Copyright (c) 2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef BRBE_H
|
||||
#define BRBE_H
|
||||
|
||||
void brbe_enable(void);
|
||||
|
||||
#endif /* BRBE_H */
|
||||
@@ -0,0 +1,14 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MPAM_H
|
||||
#define MPAM_H
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
void mpam_enable(bool el2_unused);
|
||||
|
||||
#endif /* MPAM_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PAUTH_H
|
||||
#define PAUTH_H
|
||||
|
||||
/*******************************************************************************
|
||||
* ARMv8.3-PAuth support functions
|
||||
******************************************************************************/
|
||||
|
||||
/* Disable ARMv8.3 pointer authentication in EL1/EL3 */
|
||||
void pauth_disable_el1(void);
|
||||
void pauth_disable_el3(void);
|
||||
|
||||
#endif /* PAUTH_H */
|
||||
@@ -0,0 +1,203 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef RAS_H
|
||||
#define RAS_H
|
||||
|
||||
#define ERR_HANDLER_VERSION 1U
|
||||
|
||||
/* Error record access mechanism */
|
||||
#define ERR_ACCESS_SYSREG 0
|
||||
#define ERR_ACCESS_MEMMAP 1
|
||||
|
||||
/*
|
||||
* Register all error records on the platform.
|
||||
*
|
||||
* This macro must be used in the same file as the array of error record info
|
||||
* are declared. Only then would ARRAY_SIZE() yield a meaningful value.
|
||||
*/
|
||||
#define REGISTER_ERR_RECORD_INFO(_records) \
|
||||
const struct err_record_mapping err_record_mappings = { \
|
||||
.err_records = (_records), \
|
||||
.num_err_records = ARRAY_SIZE(_records), \
|
||||
}
|
||||
|
||||
/* Error record info iterator */
|
||||
#define for_each_err_record_info(_i, _info) \
|
||||
for ((_i) = 0, (_info) = err_record_mappings.err_records; \
|
||||
(_i) < err_record_mappings.num_err_records; \
|
||||
(_i)++, (_info)++)
|
||||
|
||||
#define ERR_RECORD_COMMON_(_probe, _handler, _aux) \
|
||||
.probe = _probe, \
|
||||
.handler = _handler, \
|
||||
.aux_data = _aux,
|
||||
|
||||
#define ERR_RECORD_SYSREG_V1(_idx_start, _num_idx, _probe, _handler, _aux) \
|
||||
{ \
|
||||
.version = 1, \
|
||||
.sysreg.idx_start = _idx_start, \
|
||||
.sysreg.num_idx = _num_idx, \
|
||||
.access = ERR_ACCESS_SYSREG, \
|
||||
ERR_RECORD_COMMON_(_probe, _handler, _aux) \
|
||||
}
|
||||
|
||||
#define ERR_RECORD_MEMMAP_V1(_base_addr, _size_num_k, _probe, _handler, _aux) \
|
||||
{ \
|
||||
.version = 1, \
|
||||
.memmap.base_addr = _base_addr, \
|
||||
.memmap.size_num_k = _size_num_k, \
|
||||
.access = ERR_ACCESS_MEMMAP, \
|
||||
ERR_RECORD_COMMON_(_probe, _handler, _aux) \
|
||||
}
|
||||
|
||||
/*
|
||||
* Macro to be used to name and declare an array of RAS interrupts along with
|
||||
* their handlers.
|
||||
*
|
||||
* This macro must be used in the same file as the array of interrupts are
|
||||
* declared. Only then would ARRAY_SIZE() yield a meaningful value. Also, the
|
||||
* array is expected to be sorted in the increasing order of interrupt number.
|
||||
*/
|
||||
#define REGISTER_RAS_INTERRUPTS(_array) \
|
||||
const struct ras_interrupt_mapping ras_interrupt_mappings = { \
|
||||
.intrs = (_array), \
|
||||
.num_intrs = ARRAY_SIZE(_array), \
|
||||
}
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <lib/extensions/ras_arch.h>
|
||||
|
||||
struct err_record_info;
|
||||
|
||||
struct ras_interrupt {
|
||||
/* Interrupt number, and the associated error record info */
|
||||
unsigned int intr_number;
|
||||
struct err_record_info *err_record;
|
||||
void *cookie;
|
||||
};
|
||||
|
||||
/* Function to probe a error record group for error */
|
||||
typedef int (*err_record_probe_t)(const struct err_record_info *info,
|
||||
int *probe_data);
|
||||
|
||||
/* Data passed to error record group handler */
|
||||
struct err_handler_data {
|
||||
/* Info passed on from top-level exception handler */
|
||||
uint64_t flags;
|
||||
void *cookie;
|
||||
void *handle;
|
||||
|
||||
/* Data structure version */
|
||||
unsigned int version;
|
||||
|
||||
/* Reason for EA: one the ERROR_* constants */
|
||||
unsigned int ea_reason;
|
||||
|
||||
/*
|
||||
* For EAs received at vector, the value read from ESR; for an EA
|
||||
* synchronized by ESB, the value of DISR.
|
||||
*/
|
||||
uint32_t syndrome;
|
||||
|
||||
/* For errors signalled via interrupt, the raw interrupt ID; otherwise, 0. */
|
||||
unsigned int interrupt;
|
||||
};
|
||||
|
||||
/* Function to handle error from an error record group */
|
||||
typedef int (*err_record_handler_t)(const struct err_record_info *info,
|
||||
int probe_data, const struct err_handler_data *const data);
|
||||
|
||||
/* Error record information */
|
||||
struct err_record_info {
|
||||
/* Function to probe error record group for errors */
|
||||
err_record_probe_t probe;
|
||||
|
||||
/* Function to handle error record group errors */
|
||||
err_record_handler_t handler;
|
||||
|
||||
/* Opaque group-specific data */
|
||||
void *aux_data;
|
||||
|
||||
/* Additional information for Standard Error Records */
|
||||
union {
|
||||
struct {
|
||||
/*
|
||||
* For a group accessed via memory-mapped register,
|
||||
* base address of the page hosting error records, and
|
||||
* the size of the record group.
|
||||
*/
|
||||
uintptr_t base_addr;
|
||||
|
||||
/* Size of group in number of KBs */
|
||||
unsigned int size_num_k;
|
||||
} memmap;
|
||||
|
||||
struct {
|
||||
/*
|
||||
* For error records accessed via system register, index of
|
||||
* the error record.
|
||||
*/
|
||||
unsigned int idx_start;
|
||||
unsigned int num_idx;
|
||||
} sysreg;
|
||||
};
|
||||
|
||||
/* Data structure version */
|
||||
unsigned int version;
|
||||
|
||||
/* Error record access mechanism */
|
||||
unsigned int access:1;
|
||||
};
|
||||
|
||||
struct err_record_mapping {
|
||||
struct err_record_info *err_records;
|
||||
size_t num_err_records;
|
||||
};
|
||||
|
||||
struct ras_interrupt_mapping {
|
||||
struct ras_interrupt *intrs;
|
||||
size_t num_intrs;
|
||||
};
|
||||
|
||||
extern const struct err_record_mapping err_record_mappings;
|
||||
extern const struct ras_interrupt_mapping ras_interrupt_mappings;
|
||||
|
||||
|
||||
/*
|
||||
* Helper functions to probe memory-mapped and system registers implemented in
|
||||
* Standard Error Record format
|
||||
*/
|
||||
static inline int ras_err_ser_probe_memmap(const struct err_record_info *info,
|
||||
int *probe_data)
|
||||
{
|
||||
assert(info->version == ERR_HANDLER_VERSION);
|
||||
|
||||
return ser_probe_memmap(info->memmap.base_addr, info->memmap.size_num_k,
|
||||
probe_data);
|
||||
}
|
||||
|
||||
static inline int ras_err_ser_probe_sysreg(const struct err_record_info *info,
|
||||
int *probe_data)
|
||||
{
|
||||
assert(info->version == ERR_HANDLER_VERSION);
|
||||
|
||||
return ser_probe_sysreg(info->sysreg.idx_start, info->sysreg.num_idx,
|
||||
probe_data);
|
||||
}
|
||||
|
||||
const char *ras_serr_to_str(unsigned int serr);
|
||||
int ras_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
|
||||
void *handle, uint64_t flags);
|
||||
void ras_init(void);
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* RAS_H */
|
||||
@@ -0,0 +1,265 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef RAS_ARCH_H
|
||||
#define RAS_ARCH_H
|
||||
|
||||
/*
|
||||
* Size of nodes implementing Standard Error Records - currently only 4k is
|
||||
* supported.
|
||||
*/
|
||||
#define STD_ERR_NODE_SIZE_NUM_K 4U
|
||||
|
||||
/*
|
||||
* Individual register offsets within an error record in Standard Error Record
|
||||
* format when error records are accessed through memory-mapped registers.
|
||||
*/
|
||||
#define ERR_FR(n) (0x0ULL + (64ULL * (n)))
|
||||
#define ERR_CTLR(n) (0x8ULL + (64ULL * (n)))
|
||||
#define ERR_STATUS(n) (0x10ULL + (64ULL * (n)))
|
||||
#define ERR_ADDR(n) (0x18ULL + (64ULL * (n)))
|
||||
#define ERR_MISC0(n) (0x20ULL + (64ULL * (n)))
|
||||
#define ERR_MISC1(n) (0x28ULL + (64ULL * (n)))
|
||||
|
||||
/* Group Status Register (ERR_STATUS) offset */
|
||||
#define ERR_GSR(base, size_num_k, n) \
|
||||
((base) + (0x380ULL * (size_num_k)) + (8ULL * (n)))
|
||||
|
||||
/* Management register offsets */
|
||||
#define ERR_DEVID(base, size_num_k) \
|
||||
((base) + ((0x400ULL * (size_num_k)) - 0x100ULL) + 0xc8ULL)
|
||||
|
||||
#define ERR_DEVID_MASK 0xffffUL
|
||||
|
||||
/* Standard Error Record status register fields */
|
||||
#define ERR_STATUS_AV_SHIFT 31
|
||||
#define ERR_STATUS_AV_MASK U(0x1)
|
||||
|
||||
#define ERR_STATUS_V_SHIFT 30
|
||||
#define ERR_STATUS_V_MASK U(0x1)
|
||||
|
||||
#define ERR_STATUS_UE_SHIFT 29
|
||||
#define ERR_STATUS_UE_MASK U(0x1)
|
||||
|
||||
#define ERR_STATUS_ER_SHIFT 28
|
||||
#define ERR_STATUS_ER_MASK U(0x1)
|
||||
|
||||
#define ERR_STATUS_OF_SHIFT 27
|
||||
#define ERR_STATUS_OF_MASK U(0x1)
|
||||
|
||||
#define ERR_STATUS_MV_SHIFT 26
|
||||
#define ERR_STATUS_MV_MASK U(0x1)
|
||||
|
||||
#define ERR_STATUS_CE_SHIFT 24
|
||||
#define ERR_STATUS_CE_MASK U(0x3)
|
||||
|
||||
#define ERR_STATUS_DE_SHIFT 23
|
||||
#define ERR_STATUS_DE_MASK U(0x1)
|
||||
|
||||
#define ERR_STATUS_PN_SHIFT 22
|
||||
#define ERR_STATUS_PN_MASK U(0x1)
|
||||
|
||||
#define ERR_STATUS_UET_SHIFT 20
|
||||
#define ERR_STATUS_UET_MASK U(0x3)
|
||||
|
||||
#define ERR_STATUS_IERR_SHIFT 8
|
||||
#define ERR_STATUS_IERR_MASK U(0xff)
|
||||
|
||||
#define ERR_STATUS_SERR_SHIFT 0
|
||||
#define ERR_STATUS_SERR_MASK U(0xff)
|
||||
|
||||
#define ERR_STATUS_GET_FIELD(_status, _field) \
|
||||
(((_status) >> ERR_STATUS_ ##_field ##_SHIFT) & ERR_STATUS_ ##_field ##_MASK)
|
||||
|
||||
#define ERR_STATUS_CLR_FIELD(_status, _field) \
|
||||
(_status) &= ~(ERR_STATUS_ ##_field ##_MASK << ERR_STATUS_ ##_field ##_SHIFT)
|
||||
|
||||
#define ERR_STATUS_SET_FIELD(_status, _field, _value) \
|
||||
(_status) |= (((_value) & ERR_STATUS_ ##_field ##_MASK) << ERR_STATUS_ ##_field ##_SHIFT)
|
||||
|
||||
#define ERR_STATUS_WRITE_FIELD(_status, _field, _value) do { \
|
||||
ERR_STATUS_CLR_FIELD(_status, _field, _value); \
|
||||
ERR_STATUS_SET_FIELD(_status, _field, _value); \
|
||||
} while (0)
|
||||
|
||||
|
||||
/* Standard Error Record control register fields */
|
||||
#define ERR_CTLR_WDUI_SHIFT 11
|
||||
#define ERR_CTLR_WDUI_MASK 0x1
|
||||
|
||||
#define ERR_CTLR_RDUI_SHIFT 10
|
||||
#define ERR_CTLR_RDUI_MASK 0x1
|
||||
#define ERR_CTLR_DUI_SHIFT ERR_CTLR_RDUI_SHIFT
|
||||
#define ERR_CTLR_DUI_MASK ERR_CTLR_RDUI_MASK
|
||||
|
||||
#define ERR_CTLR_WCFI_SHIFT 9
|
||||
#define ERR_CTLR_WCFI_MASK 0x1
|
||||
|
||||
#define ERR_CTLR_RCFI_SHIFT 8
|
||||
#define ERR_CTLR_RCFI_MASK 0x1
|
||||
#define ERR_CTLR_CFI_SHIFT ERR_CTLR_RCFI_SHIFT
|
||||
#define ERR_CTLR_CFI_MASK ERR_CTLR_RCFI_MASK
|
||||
|
||||
#define ERR_CTLR_WUE_SHIFT 7
|
||||
#define ERR_CTLR_WUE_MASK 0x1
|
||||
|
||||
#define ERR_CTLR_WFI_SHIFT 6
|
||||
#define ERR_CTLR_WFI_MASK 0x1
|
||||
|
||||
#define ERR_CTLR_WUI_SHIFT 5
|
||||
#define ERR_CTLR_WUI_MASK 0x1
|
||||
|
||||
#define ERR_CTLR_RUE_SHIFT 4
|
||||
#define ERR_CTLR_RUE_MASK 0x1
|
||||
#define ERR_CTLR_UE_SHIFT ERR_CTLR_RUE_SHIFT
|
||||
#define ERR_CTLR_UE_MASK ERR_CTLR_RUE_MASK
|
||||
|
||||
#define ERR_CTLR_RFI_SHIFT 3
|
||||
#define ERR_CTLR_RFI_MASK 0x1
|
||||
#define ERR_CTLR_FI_SHIFT ERR_CTLR_RFI_SHIFT
|
||||
#define ERR_CTLR_FI_MASK ERR_CTLR_RFI_MASK
|
||||
|
||||
#define ERR_CTLR_RUI_SHIFT 2
|
||||
#define ERR_CTLR_RUI_MASK 0x1
|
||||
#define ERR_CTLR_UI_SHIFT ERR_CTLR_RUI_SHIFT
|
||||
#define ERR_CTLR_UI_MASK ERR_CTLR_RUI_MASK
|
||||
|
||||
#define ERR_CTLR_ED_SHIFT 0
|
||||
#define ERR_CTLR_ED_MASK 0x1
|
||||
|
||||
#define ERR_CTLR_CLR_FIELD(_ctlr, _field) \
|
||||
(_ctlr) &= ~(ERR_CTLR_ ##_field _MASK << ERR_CTLR_ ##_field ##_SHIFT)
|
||||
|
||||
#define ERR_CTLR_SET_FIELD(_ctlr, _field, _value) \
|
||||
(_ctlr) |= (((_value) & ERR_CTLR_ ##_field ##_MASK) << ERR_CTLR_ ##_field ##_SHIFT)
|
||||
|
||||
#define ERR_CTLR_ENABLE_FIELD(_ctlr, _field) \
|
||||
ERR_CTLR_SET_FIELD(_ctlr, _field, ERR_CTLR_ ##_field ##_MASK)
|
||||
|
||||
/* Uncorrected error types for Asynchronous exceptions */
|
||||
#define ERROR_STATUS_UET_UC 0x0 /* Uncontainable */
|
||||
#define ERROR_STATUS_UET_UEU 0x1 /* Unrecoverable */
|
||||
#define ERROR_STATUS_UET_UEO 0x2 /* Restable */
|
||||
#define ERROR_STATUS_UET_UER 0x3 /* Recoverable */
|
||||
|
||||
/* Error types for Synchronous exceptions */
|
||||
#define ERROR_STATUS_SET_UER 0x0 /* Recoverable */
|
||||
#define ERROR_STATUS_SET_UEO 0x1 /* Restable */
|
||||
#define ERROR_STATUS_SET_UC 0x2 /* Uncontainable */
|
||||
#define ERROR_STATUS_SET_CE 0x3 /* Corrected */
|
||||
|
||||
/* Number of architecturally-defined primary error codes */
|
||||
#define ERROR_STATUS_NUM_SERR U(22)
|
||||
|
||||
/* Implementation Defined Syndrome bit in ESR */
|
||||
#define SERROR_IDS_BIT U(24)
|
||||
|
||||
/*
|
||||
* Asynchronous Error Type in exception syndrome. The field has same values in
|
||||
* both DISR_EL1 and ESR_EL3 for SError.
|
||||
*/
|
||||
#define EABORT_AET_SHIFT U(10)
|
||||
#define EABORT_AET_WIDTH U(3)
|
||||
#define EABORT_AET_MASK U(0x7)
|
||||
|
||||
/* DFSC field in Asynchronous exception syndrome */
|
||||
#define EABORT_DFSC_SHIFT U(0)
|
||||
#define EABORT_DFSC_WIDTH U(6)
|
||||
#define EABORT_DFSC_MASK U(0x3f)
|
||||
|
||||
/* Synchronous Error Type in exception syndrome. */
|
||||
#define EABORT_SET_SHIFT U(11)
|
||||
#define EABORT_SET_WIDTH U(2)
|
||||
#define EABORT_SET_MASK U(0x3)
|
||||
|
||||
/* DFSC code for SErrors */
|
||||
#define DFSC_SERROR 0x11
|
||||
|
||||
/* I/DFSC code for synchronous external abort */
|
||||
#define SYNC_EA_FSC 0x10
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <arch.h>
|
||||
#include <arch_helpers.h>
|
||||
#include <assert.h>
|
||||
#include <context.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Standard Error Record accessors for memory-mapped registers.
|
||||
*/
|
||||
|
||||
static inline uint64_t ser_get_feature(uintptr_t base, unsigned int idx)
|
||||
{
|
||||
return mmio_read_64(base + ERR_FR(idx));
|
||||
}
|
||||
|
||||
static inline uint64_t ser_get_control(uintptr_t base, unsigned int idx)
|
||||
{
|
||||
return mmio_read_64(base + ERR_CTLR(idx));
|
||||
}
|
||||
|
||||
static inline uint64_t ser_get_status(uintptr_t base, unsigned int idx)
|
||||
{
|
||||
return mmio_read_64(base + ERR_STATUS(idx));
|
||||
}
|
||||
|
||||
/*
|
||||
* Error handling agent would write to the status register to clear an
|
||||
* identified/handled error. Most fields in the status register are
|
||||
* conditional write-one-to-clear.
|
||||
*
|
||||
* Typically, to clear the status, it suffices to write back the same value
|
||||
* previously read. However, if there were new, higher-priority errors recorded
|
||||
* on the node since status was last read, writing read value won't clear the
|
||||
* status. Therefore, an error handling agent must wait on and verify the status
|
||||
* has indeed been cleared.
|
||||
*/
|
||||
static inline void ser_set_status(uintptr_t base, unsigned int idx,
|
||||
uint64_t status)
|
||||
{
|
||||
mmio_write_64(base + ERR_STATUS(idx), status);
|
||||
}
|
||||
|
||||
static inline uint64_t ser_get_addr(uintptr_t base, unsigned int idx)
|
||||
{
|
||||
return mmio_read_64(base + ERR_ADDR(idx));
|
||||
}
|
||||
|
||||
static inline uint64_t ser_get_misc0(uintptr_t base, unsigned int idx)
|
||||
{
|
||||
return mmio_read_64(base + ERR_MISC0(idx));
|
||||
}
|
||||
|
||||
static inline uint64_t ser_get_misc1(uintptr_t base, unsigned int idx)
|
||||
{
|
||||
return mmio_read_64(base + ERR_MISC1(idx));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Standard Error Record helpers for System registers.
|
||||
*/
|
||||
static inline void ser_sys_select_record(unsigned int idx)
|
||||
{
|
||||
unsigned int max_idx __unused =
|
||||
(unsigned int) read_erridr_el1() & ERRIDR_MASK;
|
||||
|
||||
assert(idx < max_idx);
|
||||
|
||||
write_errselr_el1(idx);
|
||||
isb();
|
||||
}
|
||||
|
||||
/* Library functions to probe Standard Error Record */
|
||||
int ser_probe_memmap(uintptr_t base, unsigned int size_num_k, int *probe_data);
|
||||
int ser_probe_sysreg(unsigned int idx_start, unsigned int num_idx, int *probe_data);
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* RAS_ARCH_H */
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SME_H
|
||||
#define SME_H
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <context.h>
|
||||
|
||||
/*
|
||||
* Maximum value of LEN field in SMCR_ELx. This is different than the maximum
|
||||
* supported value which is platform dependent. In the first version of SME the
|
||||
* LEN field is limited to 4 bits but will be expanded in future iterations.
|
||||
* To support different versions, the code that discovers the supported vector
|
||||
* lengths will write the max value into SMCR_ELx then read it back to see how
|
||||
* many bits are implemented.
|
||||
*/
|
||||
#define SME_SMCR_LEN_MAX U(0x1FF)
|
||||
|
||||
void sme_enable(cpu_context_t *context);
|
||||
void sme_disable(cpu_context_t *context);
|
||||
|
||||
#endif /* SME_H */
|
||||
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SPE_H
|
||||
#define SPE_H
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
bool spe_supported(void);
|
||||
void spe_enable(bool el2_unused);
|
||||
void spe_disable(void);
|
||||
|
||||
#endif /* SPE_H */
|
||||
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SVE_H
|
||||
#define SVE_H
|
||||
|
||||
#include <context.h>
|
||||
|
||||
void sve_enable(cpu_context_t *context);
|
||||
void sve_disable(cpu_context_t *context);
|
||||
|
||||
#endif /* SVE_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SYS_REG_TRACE_H
|
||||
#define SYS_REG_TRACE_H
|
||||
|
||||
#include <context.h>
|
||||
|
||||
#if __aarch64__
|
||||
void sys_reg_trace_enable(cpu_context_t *context);
|
||||
#else
|
||||
void sys_reg_trace_enable(void);
|
||||
#endif /* __aarch64__ */
|
||||
|
||||
#endif /* SYS_REG_TRACE_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
/*
|
||||
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef TRBE_H
|
||||
#define TRBE_H
|
||||
|
||||
void trbe_enable(void);
|
||||
|
||||
#endif /* TRBE_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
/*
|
||||
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef TRF_H
|
||||
#define TRF_H
|
||||
|
||||
void trf_enable(void);
|
||||
|
||||
#endif /* TRF_H */
|
||||
@@ -0,0 +1,70 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef FCONF_H
|
||||
#define FCONF_H
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* Public API */
|
||||
#define FCONF_GET_PROPERTY(a, b, c) a##__##b##_getter(c)
|
||||
|
||||
/*
|
||||
* This macro takes three arguments:
|
||||
* config: Configuration identifier
|
||||
* name: property namespace
|
||||
* callback: populate() function
|
||||
*/
|
||||
#define FCONF_REGISTER_POPULATOR(config, name, callback) \
|
||||
__attribute__((used, section(".fconf_populator"))) \
|
||||
const struct fconf_populator (name##__populator) = { \
|
||||
.config_type = (#config), \
|
||||
.info = (#name), \
|
||||
.populate = (callback) \
|
||||
};
|
||||
|
||||
/*
|
||||
* Populator callback
|
||||
*
|
||||
* This structure are used by the fconf_populate function and should only be
|
||||
* defined by the FCONF_REGISTER_POPULATOR macro.
|
||||
*/
|
||||
struct fconf_populator {
|
||||
/* Description of the data loaded by the callback */
|
||||
const char *config_type;
|
||||
const char *info;
|
||||
|
||||
/* Callback used by fconf_populate function with a provided config dtb.
|
||||
* Return 0 on success, err_code < 0 otherwise.
|
||||
*/
|
||||
int (*populate)(uintptr_t config);
|
||||
};
|
||||
|
||||
/* This function supports to load tb_fw_config and fw_config dtb */
|
||||
int fconf_load_config(unsigned int image_id);
|
||||
|
||||
/* Top level populate function
|
||||
*
|
||||
* This function takes a configuration dtb and calls all the registered
|
||||
* populator callback with it.
|
||||
*
|
||||
* Panic on error.
|
||||
*/
|
||||
void fconf_populate(const char *config_type, uintptr_t config);
|
||||
|
||||
/* FCONF specific getter */
|
||||
#define fconf__dtb_getter(prop) fconf_dtb_info.prop
|
||||
|
||||
/* Structure used to locally keep a reference to the config dtb. */
|
||||
struct fconf_dtb_info_t {
|
||||
uintptr_t base_addr;
|
||||
size_t size;
|
||||
};
|
||||
|
||||
extern struct fconf_dtb_info_t fconf_dtb_info;
|
||||
|
||||
#endif /* FCONF_H */
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef FCONF_AMU_GETTER_H
|
||||
#define FCONF_AMU_GETTER_H
|
||||
|
||||
#include <lib/extensions/amu.h>
|
||||
|
||||
#define amu__config_getter(id) fconf_amu_config.id
|
||||
|
||||
struct fconf_amu_config {
|
||||
const struct amu_topology *topology;
|
||||
};
|
||||
|
||||
extern struct fconf_amu_config fconf_amu_config;
|
||||
|
||||
#endif /* FCONF_AMU_GETTER_H */
|
||||
+39
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef FCONF_DYN_CFG_GETTER_H
|
||||
#define FCONF_DYN_CFG_GETTER_H
|
||||
|
||||
#include <lib/fconf/fconf.h>
|
||||
|
||||
#define FCONF_INVALID_IDX 0xFFFFFFFFU
|
||||
|
||||
/* Dynamic configuration related getter */
|
||||
#define dyn_cfg__dtb_getter(id) dyn_cfg_dtb_info_getter(id)
|
||||
|
||||
struct dyn_cfg_dtb_info_t {
|
||||
uintptr_t config_addr;
|
||||
uint32_t config_max_size;
|
||||
unsigned int config_id;
|
||||
/*
|
||||
* Load address in non-secure memory. Only needed by those
|
||||
* configuration files which require being loaded in secure
|
||||
* memory (at config_addr) as well as in non-secure memory
|
||||
* - e.g. HW_CONFIG
|
||||
*/
|
||||
uintptr_t ns_config_addr;
|
||||
};
|
||||
|
||||
unsigned int dyn_cfg_dtb_info_get_index(unsigned int config_id);
|
||||
struct dyn_cfg_dtb_info_t *dyn_cfg_dtb_info_getter(unsigned int config_id);
|
||||
int fconf_populate_dtb_registry(uintptr_t config);
|
||||
|
||||
/* Set config information in global DTB array */
|
||||
void set_config_info(uintptr_t config_addr, uintptr_t ns_config_addr,
|
||||
uint32_t config_max_size,
|
||||
unsigned int config_id);
|
||||
|
||||
#endif /* FCONF_DYN_CFG_GETTER_H */
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef FCONF_MPMM_GETTER_H
|
||||
#define FCONF_MPMM_GETTER_H
|
||||
|
||||
#include <lib/mpmm/mpmm.h>
|
||||
|
||||
#define mpmm__config_getter(id) fconf_mpmm_config.id
|
||||
|
||||
struct fconf_mpmm_config {
|
||||
const struct mpmm_topology *topology;
|
||||
};
|
||||
|
||||
extern struct fconf_mpmm_config fconf_mpmm_config;
|
||||
|
||||
#endif /* FCONF_MPMM_GETTER_H */
|
||||
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef FCONF_TBBR_GETTER_H
|
||||
#define FCONF_TBBR_GETTER_H
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <lib/fconf/fconf.h>
|
||||
|
||||
/* TBBR related getter */
|
||||
#define tbbr__cot_getter(id) __extension__ ({ \
|
||||
assert((id) < cot_desc_size); \
|
||||
cot_desc_ptr[id]; \
|
||||
})
|
||||
|
||||
#define tbbr__dyn_config_getter(id) tbbr_dyn_config.id
|
||||
|
||||
struct tbbr_dyn_config_t {
|
||||
uint32_t disable_auth;
|
||||
void *mbedtls_heap_addr;
|
||||
size_t mbedtls_heap_size;
|
||||
};
|
||||
|
||||
extern struct tbbr_dyn_config_t tbbr_dyn_config;
|
||||
|
||||
int fconf_populate_tbbr_dyn_config(uintptr_t config);
|
||||
|
||||
#endif /* FCONF_TBBR_GETTER_H */
|
||||
@@ -0,0 +1,280 @@
|
||||
/*
|
||||
* Copyright (c) 2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef GPT_RME_H
|
||||
#define GPT_RME_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <arch.h>
|
||||
|
||||
/******************************************************************************/
|
||||
/* GPT helper macros and definitions */
|
||||
/******************************************************************************/
|
||||
|
||||
/*
|
||||
* Structure for specifying a mapping range and it's properties. This should not
|
||||
* be manually initialized, using the MAP_GPT_REGION_x macros is recommended as
|
||||
* to avoid potential incompatibilities in the future.
|
||||
*/
|
||||
typedef struct pas_region {
|
||||
uintptr_t base_pa; /* Base address for PAS. */
|
||||
size_t size; /* Size of the PAS. */
|
||||
unsigned int attrs; /* PAS GPI and entry type. */
|
||||
} pas_region_t;
|
||||
|
||||
/* GPT GPI definitions */
|
||||
#define GPT_GPI_NO_ACCESS U(0x0)
|
||||
#define GPT_GPI_SECURE U(0x8)
|
||||
#define GPT_GPI_NS U(0x9)
|
||||
#define GPT_GPI_ROOT U(0xA)
|
||||
#define GPT_GPI_REALM U(0xB)
|
||||
#define GPT_GPI_ANY U(0xF)
|
||||
#define GPT_GPI_VAL_MASK UL(0xF)
|
||||
|
||||
#define GPT_NSE_SECURE U(0b00)
|
||||
#define GPT_NSE_ROOT U(0b01)
|
||||
#define GPT_NSE_NS U(0b10)
|
||||
#define GPT_NSE_REALM U(0b11)
|
||||
|
||||
#define GPT_NSE_SHIFT U(62)
|
||||
|
||||
/* PAS attribute GPI definitions. */
|
||||
#define GPT_PAS_ATTR_GPI_SHIFT U(0)
|
||||
#define GPT_PAS_ATTR_GPI_MASK U(0xF)
|
||||
#define GPT_PAS_ATTR_GPI(_attrs) (((_attrs) \
|
||||
>> GPT_PAS_ATTR_GPI_SHIFT) \
|
||||
& GPT_PAS_ATTR_GPI_MASK)
|
||||
|
||||
/* PAS attribute mapping type definitions */
|
||||
#define GPT_PAS_ATTR_MAP_TYPE_BLOCK U(0x0)
|
||||
#define GPT_PAS_ATTR_MAP_TYPE_GRANULE U(0x1)
|
||||
#define GPT_PAS_ATTR_MAP_TYPE_SHIFT U(4)
|
||||
#define GPT_PAS_ATTR_MAP_TYPE_MASK U(0x1)
|
||||
#define GPT_PAS_ATTR_MAP_TYPE(_attrs) (((_attrs) \
|
||||
>> GPT_PAS_ATTR_MAP_TYPE_SHIFT) \
|
||||
& GPT_PAS_ATTR_MAP_TYPE_MASK)
|
||||
|
||||
/*
|
||||
* Macro to initialize the attributes field in the pas_region_t structure.
|
||||
* [31:5] Reserved
|
||||
* [4] Mapping type (GPT_PAS_ATTR_MAP_TYPE_x definitions)
|
||||
* [3:0] PAS GPI type (GPT_GPI_x definitions)
|
||||
*/
|
||||
#define GPT_PAS_ATTR(_type, _gpi) \
|
||||
((((_type) & GPT_PAS_ATTR_MAP_TYPE_MASK) \
|
||||
<< GPT_PAS_ATTR_MAP_TYPE_SHIFT) | \
|
||||
(((_gpi) & GPT_PAS_ATTR_GPI_MASK) \
|
||||
<< GPT_PAS_ATTR_GPI_SHIFT))
|
||||
|
||||
/*
|
||||
* Macro to create a GPT entry for this PAS range as a block descriptor. If this
|
||||
* region does not fit the requirements for a block descriptor then GPT
|
||||
* initialization will fail.
|
||||
*/
|
||||
#define GPT_MAP_REGION_BLOCK(_pa, _sz, _gpi) \
|
||||
{ \
|
||||
.base_pa = (_pa), \
|
||||
.size = (_sz), \
|
||||
.attrs = GPT_PAS_ATTR(GPT_PAS_ATTR_MAP_TYPE_BLOCK, (_gpi)), \
|
||||
}
|
||||
|
||||
/*
|
||||
* Macro to create a GPT entry for this PAS range as a table descriptor. If this
|
||||
* region does not fit the requirements for a table descriptor then GPT
|
||||
* initialization will fail.
|
||||
*/
|
||||
#define GPT_MAP_REGION_GRANULE(_pa, _sz, _gpi) \
|
||||
{ \
|
||||
.base_pa = (_pa), \
|
||||
.size = (_sz), \
|
||||
.attrs = GPT_PAS_ATTR(GPT_PAS_ATTR_MAP_TYPE_GRANULE, (_gpi)), \
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/* GPT register field definitions */
|
||||
/******************************************************************************/
|
||||
|
||||
/*
|
||||
* Least significant address bits protected by each entry in level 0 GPT. This
|
||||
* field is read-only.
|
||||
*/
|
||||
#define GPCCR_L0GPTSZ_SHIFT U(20)
|
||||
#define GPCCR_L0GPTSZ_MASK U(0xF)
|
||||
|
||||
typedef enum {
|
||||
GPCCR_L0GPTSZ_30BITS = U(0x0),
|
||||
GPCCR_L0GPTSZ_34BITS = U(0x4),
|
||||
GPCCR_L0GPTSZ_36BITS = U(0x6),
|
||||
GPCCR_L0GPTSZ_39BITS = U(0x9)
|
||||
} gpccr_l0gptsz_e;
|
||||
|
||||
/* Granule protection check priority bit definitions */
|
||||
#define GPCCR_GPCP_SHIFT U(17)
|
||||
#define GPCCR_GPCP_BIT (ULL(1) << GPCCR_EL3_GPCP_SHIFT)
|
||||
|
||||
/* Granule protection check bit definitions */
|
||||
#define GPCCR_GPC_SHIFT U(16)
|
||||
#define GPCCR_GPC_BIT (ULL(1) << GPCCR_GPC_SHIFT)
|
||||
|
||||
/* Physical granule size bit definitions */
|
||||
#define GPCCR_PGS_SHIFT U(14)
|
||||
#define GPCCR_PGS_MASK U(0x3)
|
||||
#define SET_GPCCR_PGS(x) (((x) & GPCCR_PGS_MASK) << GPCCR_PGS_SHIFT)
|
||||
|
||||
typedef enum {
|
||||
GPCCR_PGS_4K = U(0x0),
|
||||
GPCCR_PGS_64K = U(0x1),
|
||||
GPCCR_PGS_16K = U(0x2)
|
||||
} gpccr_pgs_e;
|
||||
|
||||
/* GPT fetch shareability attribute bit definitions */
|
||||
#define GPCCR_SH_SHIFT U(12)
|
||||
#define GPCCR_SH_MASK U(0x3)
|
||||
#define SET_GPCCR_SH(x) (((x) & GPCCR_SH_MASK) << GPCCR_SH_SHIFT)
|
||||
|
||||
typedef enum {
|
||||
GPCCR_SH_NS = U(0x0),
|
||||
GPCCR_SH_OS = U(0x2),
|
||||
GPCCR_SH_IS = U(0x3)
|
||||
} gpccr_sh_e;
|
||||
|
||||
/* GPT fetch outer cacheability attribute bit definitions */
|
||||
#define GPCCR_ORGN_SHIFT U(10)
|
||||
#define GPCCR_ORGN_MASK U(0x3)
|
||||
#define SET_GPCCR_ORGN(x) (((x) & GPCCR_ORGN_MASK) << GPCCR_ORGN_SHIFT)
|
||||
|
||||
typedef enum {
|
||||
GPCCR_ORGN_NC = U(0x0),
|
||||
GPCCR_ORGN_WB_RA_WA = U(0x1),
|
||||
GPCCR_ORGN_WT_RA_NWA = U(0x2),
|
||||
GPCCR_ORGN_WB_RA_NWA = U(0x3)
|
||||
} gpccr_orgn_e;
|
||||
|
||||
/* GPT fetch inner cacheability attribute bit definitions */
|
||||
#define GPCCR_IRGN_SHIFT U(8)
|
||||
#define GPCCR_IRGN_MASK U(0x3)
|
||||
#define SET_GPCCR_IRGN(x) (((x) & GPCCR_IRGN_MASK) << GPCCR_IRGN_SHIFT)
|
||||
|
||||
typedef enum {
|
||||
GPCCR_IRGN_NC = U(0x0),
|
||||
GPCCR_IRGN_WB_RA_WA = U(0x1),
|
||||
GPCCR_IRGN_WT_RA_NWA = U(0x2),
|
||||
GPCCR_IRGN_WB_RA_NWA = U(0x3)
|
||||
} gpccr_irgn_e;
|
||||
|
||||
/* Protected physical address size bit definitions */
|
||||
#define GPCCR_PPS_SHIFT U(0)
|
||||
#define GPCCR_PPS_MASK U(0x7)
|
||||
#define SET_GPCCR_PPS(x) (((x) & GPCCR_PPS_MASK) << GPCCR_PPS_SHIFT)
|
||||
|
||||
typedef enum {
|
||||
GPCCR_PPS_4GB = U(0x0),
|
||||
GPCCR_PPS_64GB = U(0x1),
|
||||
GPCCR_PPS_1TB = U(0x2),
|
||||
GPCCR_PPS_4TB = U(0x3),
|
||||
GPCCR_PPS_16TB = U(0x4),
|
||||
GPCCR_PPS_256TB = U(0x5),
|
||||
GPCCR_PPS_4PB = U(0x6)
|
||||
} gpccr_pps_e;
|
||||
|
||||
/* Base Address for the GPT bit definitions */
|
||||
#define GPTBR_BADDR_SHIFT U(0)
|
||||
#define GPTBR_BADDR_VAL_SHIFT U(12)
|
||||
#define GPTBR_BADDR_MASK ULL(0xffffffffff)
|
||||
|
||||
/******************************************************************************/
|
||||
/* GPT public APIs */
|
||||
/******************************************************************************/
|
||||
|
||||
/*
|
||||
* Public API that initializes the entire protected space to GPT_GPI_ANY using
|
||||
* the L0 tables (block descriptors). Ideally, this function is invoked prior
|
||||
* to DDR discovery and initialization. The MMU must be initialized before
|
||||
* calling this function.
|
||||
*
|
||||
* Parameters
|
||||
* pps PPS value to use for table generation
|
||||
* l0_mem_base Base address of L0 tables in memory.
|
||||
* l0_mem_size Total size of memory available for L0 tables.
|
||||
*
|
||||
* Return
|
||||
* Negative Linux error code in the event of a failure, 0 for success.
|
||||
*/
|
||||
int gpt_init_l0_tables(gpccr_pps_e pps,
|
||||
uintptr_t l0_mem_base,
|
||||
size_t l0_mem_size);
|
||||
|
||||
/*
|
||||
* Public API that carves out PAS regions from the L0 tables and builds any L1
|
||||
* tables that are needed. This function ideally is run after DDR discovery and
|
||||
* initialization. The L0 tables must have already been initialized to GPI_ANY
|
||||
* when this function is called.
|
||||
*
|
||||
* Parameters
|
||||
* pgs PGS value to use for table generation.
|
||||
* l1_mem_base Base address of memory used for L1 tables.
|
||||
* l1_mem_size Total size of memory available for L1 tables.
|
||||
* *pas_regions Pointer to PAS regions structure array.
|
||||
* pas_count Total number of PAS regions.
|
||||
*
|
||||
* Return
|
||||
* Negative Linux error code in the event of a failure, 0 for success.
|
||||
*/
|
||||
int gpt_init_pas_l1_tables(gpccr_pgs_e pgs,
|
||||
uintptr_t l1_mem_base,
|
||||
size_t l1_mem_size,
|
||||
pas_region_t *pas_regions,
|
||||
unsigned int pas_count);
|
||||
|
||||
/*
|
||||
* Public API to initialize the runtime gpt_config structure based on the values
|
||||
* present in the GPTBR_EL3 and GPCCR_EL3 registers. GPT initialization
|
||||
* typically happens in a bootloader stage prior to setting up the EL3 runtime
|
||||
* environment for the granule transition service so this function detects the
|
||||
* initialization from a previous stage. Granule protection checks must be
|
||||
* enabled already or this function will return an error.
|
||||
*
|
||||
* Return
|
||||
* Negative Linux error code in the event of a failure, 0 for success.
|
||||
*/
|
||||
int gpt_runtime_init(void);
|
||||
|
||||
/*
|
||||
* Public API to enable granule protection checks once the tables have all been
|
||||
* initialized. This function is called at first initialization and then again
|
||||
* later during warm boots of CPU cores.
|
||||
*
|
||||
* Return
|
||||
* Negative Linux error code in the event of a failure, 0 for success.
|
||||
*/
|
||||
int gpt_enable(void);
|
||||
|
||||
/*
|
||||
* Public API to disable granule protection checks.
|
||||
*/
|
||||
void gpt_disable(void);
|
||||
|
||||
/*
|
||||
* This function is the core of the granule transition service. When a granule
|
||||
* transition request occurs it is routed to this function where the request is
|
||||
* validated then fulfilled if possible.
|
||||
*
|
||||
* TODO: implement support for transitioning multiple granules at once.
|
||||
*
|
||||
* Parameters
|
||||
* base: Base address of the region to transition, must be aligned to granule
|
||||
* size.
|
||||
* size: Size of region to transition, must be aligned to granule size.
|
||||
* src_sec_state: Security state of the originating SMC invoking the API.
|
||||
*
|
||||
* Return
|
||||
* Negative Linux error code in the event of a failure, 0 for success.
|
||||
*/
|
||||
int gpt_delegate_pas(uint64_t base, size_t size, unsigned int src_sec_state);
|
||||
int gpt_undelegate_pas(uint64_t base, size_t size, unsigned int src_sec_state);
|
||||
|
||||
#endif /* GPT_RME_H */
|
||||
@@ -0,0 +1,146 @@
|
||||
/*-
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Copyright (c) 2001 David E. O'Brien
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* @(#)endian.h 8.1 (Berkeley) 6/10/93
|
||||
* $NetBSD: endian.h,v 1.7 1999/08/21 05:53:51 simonb Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
/*
|
||||
* Portions copyright (c) 2018, ARM Limited and Contributors.
|
||||
* All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef ENDIAN__H
|
||||
#define ENDIAN__H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Definitions for byte order, according to byte significance from low
|
||||
* address to high.
|
||||
*/
|
||||
#define _LITTLE_ENDIAN 1234 /* LSB first: i386, vax */
|
||||
#define _BIG_ENDIAN 4321 /* MSB first: 68000, ibm, net */
|
||||
#define _PDP_ENDIAN 3412 /* LSB first in word, MSW first in long */
|
||||
|
||||
#ifdef __ARMEB__
|
||||
#define _BYTE_ORDER _BIG_ENDIAN
|
||||
#else
|
||||
#define _BYTE_ORDER _LITTLE_ENDIAN
|
||||
#endif /* __ARMEB__ */
|
||||
|
||||
#if __BSD_VISIBLE
|
||||
#define LITTLE_ENDIAN _LITTLE_ENDIAN
|
||||
#define BIG_ENDIAN _BIG_ENDIAN
|
||||
#define PDP_ENDIAN _PDP_ENDIAN
|
||||
#define BYTE_ORDER _BYTE_ORDER
|
||||
#endif
|
||||
|
||||
#ifdef __ARMEB__
|
||||
#define _QUAD_HIGHWORD 0
|
||||
#define _QUAD_LOWWORD 1
|
||||
#define __ntohl(x) ((uint32_t)(x))
|
||||
#define __ntohs(x) ((uint16_t)(x))
|
||||
#define __htonl(x) ((uint32_t)(x))
|
||||
#define __htons(x) ((uint16_t)(x))
|
||||
#else
|
||||
#define _QUAD_HIGHWORD 1
|
||||
#define _QUAD_LOWWORD 0
|
||||
#define __ntohl(x) (__bswap32(x))
|
||||
#define __ntohs(x) (__bswap16(x))
|
||||
#define __htonl(x) (__bswap32(x))
|
||||
#define __htons(x) (__bswap16(x))
|
||||
#endif /* __ARMEB__ */
|
||||
|
||||
static __inline uint64_t
|
||||
__bswap64(uint64_t _x)
|
||||
{
|
||||
|
||||
return ((_x >> 56) | ((_x >> 40) & 0xff00) | ((_x >> 24) & 0xff0000) |
|
||||
((_x >> 8) & 0xff000000) | ((_x << 8) & ((uint64_t)0xff << 32)) |
|
||||
((_x << 24) & ((uint64_t)0xff << 40)) |
|
||||
((_x << 40) & ((uint64_t)0xff << 48)) | ((_x << 56)));
|
||||
}
|
||||
|
||||
static __inline uint32_t
|
||||
__bswap32_var(uint32_t v)
|
||||
{
|
||||
uint32_t t1;
|
||||
|
||||
__asm __volatile("eor %1, %0, %0, ror #16\n"
|
||||
"bic %1, %1, #0x00ff0000\n"
|
||||
"mov %0, %0, ror #8\n"
|
||||
"eor %0, %0, %1, lsr #8\n"
|
||||
: "+r" (v), "=r" (t1));
|
||||
|
||||
return (v);
|
||||
}
|
||||
|
||||
static __inline uint16_t
|
||||
__bswap16_var(uint16_t v)
|
||||
{
|
||||
uint32_t ret = v & 0xffff;
|
||||
|
||||
__asm __volatile(
|
||||
"mov %0, %0, ror #8\n"
|
||||
"orr %0, %0, %0, lsr #16\n"
|
||||
"bic %0, %0, %0, lsl #16"
|
||||
: "+r" (ret));
|
||||
|
||||
return ((uint16_t)ret);
|
||||
}
|
||||
|
||||
#ifdef __OPTIMIZE__
|
||||
|
||||
#define __bswap32_constant(x) \
|
||||
((((x) & 0xff000000U) >> 24) | \
|
||||
(((x) & 0x00ff0000U) >> 8) | \
|
||||
(((x) & 0x0000ff00U) << 8) | \
|
||||
(((x) & 0x000000ffU) << 24))
|
||||
|
||||
#define __bswap16_constant(x) \
|
||||
((((x) & 0xff00) >> 8) | \
|
||||
(((x) & 0x00ff) << 8))
|
||||
|
||||
#define __bswap16(x) \
|
||||
((uint16_t)(__builtin_constant_p(x) ? \
|
||||
__bswap16_constant(x) : \
|
||||
__bswap16_var(x)))
|
||||
|
||||
#define __bswap32(x) \
|
||||
((uint32_t)(__builtin_constant_p(x) ? \
|
||||
__bswap32_constant(x) : \
|
||||
__bswap32_var(x)))
|
||||
|
||||
#else
|
||||
#define __bswap16(x) __bswap16_var(x)
|
||||
#define __bswap32(x) __bswap32_var(x)
|
||||
|
||||
#endif /* __OPTIMIZE__ */
|
||||
#endif /* ENDIAN__H */
|
||||
@@ -0,0 +1,100 @@
|
||||
/*-
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Copyright (c) 1989 Regents of the University of California.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* from: @(#)float.h 7.1 (Berkeley) 5/8/90
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _MACHINE_FLOAT_H_
|
||||
#define _MACHINE_FLOAT_H_ 1
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
|
||||
__BEGIN_DECLS
|
||||
extern int __flt_rounds(void);
|
||||
__END_DECLS
|
||||
|
||||
#define FLT_RADIX 2 /* b */
|
||||
#ifndef _ARM_HARD_FLOAT
|
||||
#define FLT_ROUNDS __flt_rounds()
|
||||
#else
|
||||
#define FLT_ROUNDS (-1)
|
||||
#endif
|
||||
#if __ISO_C_VISIBLE >= 1999
|
||||
#define FLT_EVAL_METHOD 0
|
||||
#define DECIMAL_DIG 17 /* max precision in decimal digits */
|
||||
#endif
|
||||
|
||||
#define FLT_MANT_DIG 24 /* p */
|
||||
#define FLT_EPSILON 1.19209290E-07F /* b**(1-p) */
|
||||
#define FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */
|
||||
#define FLT_MIN_EXP (-125) /* emin */
|
||||
#define FLT_MIN 1.17549435E-38F /* b**(emin-1) */
|
||||
#define FLT_MIN_10_EXP (-37) /* ceil(log10(b**(emin-1))) */
|
||||
#define FLT_MAX_EXP 128 /* emax */
|
||||
#define FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */
|
||||
#define FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */
|
||||
#if __ISO_C_VISIBLE >= 2011
|
||||
#define FLT_TRUE_MIN 1.40129846E-45F /* b**(emin-p) */
|
||||
#define FLT_DECIMAL_DIG 9 /* ceil(1+p*log10(b)) */
|
||||
#define FLT_HAS_SUBNORM 1
|
||||
#endif /* __ISO_C_VISIBLE >= 2011 */
|
||||
|
||||
#define DBL_MANT_DIG 53
|
||||
#define DBL_EPSILON 2.2204460492503131E-16
|
||||
#define DBL_DIG 15
|
||||
#define DBL_MIN_EXP (-1021)
|
||||
#define DBL_MIN 2.2250738585072014E-308
|
||||
#define DBL_MIN_10_EXP (-307)
|
||||
#define DBL_MAX_EXP 1024
|
||||
#define DBL_MAX 1.7976931348623157E+308
|
||||
#define DBL_MAX_10_EXP 308
|
||||
#if __ISO_C_VISIBLE >= 2011
|
||||
#define DBL_TRUE_MIN 4.9406564584124654E-324
|
||||
#define DBL_DECIMAL_DIG 17
|
||||
#define DBL_HAS_SUBNORM 1
|
||||
#endif /* __ISO_C_VISIBLE >= 2011 */
|
||||
|
||||
#define LDBL_MANT_DIG DBL_MANT_DIG
|
||||
#define LDBL_EPSILON ((long double)DBL_EPSILON)
|
||||
#define LDBL_DIG DBL_DIG
|
||||
#define LDBL_MIN_EXP DBL_MIN_EXP
|
||||
#define LDBL_MIN ((long double)DBL_MIN)
|
||||
#define LDBL_MIN_10_EXP DBL_MIN_10_EXP
|
||||
#define LDBL_MAX_EXP DBL_MAX_EXP
|
||||
#define LDBL_MAX ((long double)DBL_MAX)
|
||||
#define LDBL_MAX_10_EXP DBL_MAX_10_EXP
|
||||
#if __ISO_C_VISIBLE >= 2011
|
||||
#define LDBL_TRUE_MIN ((long double)DBL_TRUE_MIN)
|
||||
#define LDBL_DECIMAL_DIG DBL_DECIMAL_DIG
|
||||
#define LDBL_HAS_SUBNORM DBL_HAS_SUBNORM
|
||||
#endif /* __ISO_C_VISIBLE >= 2011 */
|
||||
|
||||
#endif /* _MACHINE_FLOAT_H_ */
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright 2020 Broadcom
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/*
|
||||
* Portions copyright (c) 2020, ARM Limited and Contributors.
|
||||
* All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef INTTYPES__H
|
||||
#define INTTYPES__H
|
||||
|
||||
#define PRId64 "lld" /* int64_t */
|
||||
#define PRIi64 "lli" /* int64_t */
|
||||
#define PRIo64 "llo" /* int64_t */
|
||||
#define PRIu64 "llu" /* uint64_t */
|
||||
#define PRIx64 "llx" /* uint64_t */
|
||||
#define PRIX64 "llX" /* uint64_t */
|
||||
|
||||
#define PRIdPTR "d" /* intptr_t */
|
||||
#define PRIiPTR "i" /* intptr_t */
|
||||
#define PRIoPTR "o" /* intptr_t */
|
||||
#define PRIuPTR "u" /* uintptr_t */
|
||||
#define PRIxPTR "x" /* uintptr_t */
|
||||
#define PRIXPTR "X" /* uintptr_t */
|
||||
|
||||
#endif /* INTTYPES__H */
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define SCHAR_MAX 0x7F
|
||||
#define SCHAR_MIN (-SCHAR_MAX - 1)
|
||||
#define CHAR_MAX 0x7F
|
||||
#define CHAR_MIN (-CHAR_MAX - 1)
|
||||
#define UCHAR_MAX 0xFFU
|
||||
#define SHRT_MAX 0x7FFF
|
||||
#define SHRT_MIN (-SHRT_MAX - 1)
|
||||
#define USHRT_MAX 0xFFFFU
|
||||
#define INT_MAX 0x7FFFFFFF
|
||||
#define INT_MIN (-INT_MAX - 1)
|
||||
#define UINT_MAX 0xFFFFFFFFU
|
||||
#define LONG_MAX 0x7FFFFFFFL
|
||||
#define LONG_MIN (-LONG_MAX - 1L)
|
||||
#define ULONG_MAX 0xFFFFFFFFUL
|
||||
#define LLONG_MAX 0x7FFFFFFFFFFFFFFFLL
|
||||
#define LLONG_MIN (-LLONG_MAX - 1LL)
|
||||
#define ULLONG_MAX 0xFFFFFFFFFFFFFFFFULL
|
||||
|
||||
#define __LONG_BIT 32
|
||||
#define __WORD_BIT 32
|
||||
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef STDDEF__H
|
||||
#define STDDEF__H
|
||||
|
||||
#ifndef SIZET_
|
||||
typedef unsigned int size_t;
|
||||
#define SIZET_
|
||||
#endif
|
||||
|
||||
#endif /* STDDEF__H */
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright 2020 Broadcom
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/*
|
||||
* Portions copyright (c) 2020, ARM Limited and Contributors.
|
||||
* All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef STDINT__H
|
||||
#define STDINT__H
|
||||
|
||||
#define INT64_MAX LLONG_MAX
|
||||
#define INT64_MIN LLONG_MIN
|
||||
#define UINT64_MAX ULLONG_MAX
|
||||
|
||||
#define INT64_C(x) x ## LL
|
||||
#define UINT64_C(x) x ## ULL
|
||||
|
||||
typedef long long int64_t;
|
||||
typedef unsigned long long uint64_t;
|
||||
typedef long long int64_least_t;
|
||||
typedef unsigned long long uint64_least_t;
|
||||
typedef long long int64_fast_t;
|
||||
typedef unsigned long long uint64_fast_t;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef STDIO__H
|
||||
#define STDIO__H
|
||||
|
||||
#ifndef SSIZET_
|
||||
typedef int ssize_t;
|
||||
#define SSIZET_
|
||||
#endif
|
||||
|
||||
#endif /* STDIO__H */
|
||||
@@ -0,0 +1,128 @@
|
||||
/*-
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Copyright (c) 2001 David E. O'Brien
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* @(#)endian.h 8.1 (Berkeley) 6/10/93
|
||||
* $NetBSD: endian.h,v 1.7 1999/08/21 05:53:51 simonb Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
/*
|
||||
* Portions copyright (c) 2018, ARM Limited and Contributors.
|
||||
* All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef ENDIAN__H
|
||||
#define ENDIAN__H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Definitions for byte order, according to byte significance from low
|
||||
* address to high.
|
||||
*/
|
||||
#define _LITTLE_ENDIAN 1234 /* LSB first: i386, vax */
|
||||
#define _BIG_ENDIAN 4321 /* MSB first: 68000, ibm, net */
|
||||
#define _PDP_ENDIAN 3412 /* LSB first in word, MSW first in long */
|
||||
|
||||
#define _BYTE_ORDER _LITTLE_ENDIAN
|
||||
|
||||
#if __BSD_VISIBLE
|
||||
#define LITTLE_ENDIAN _LITTLE_ENDIAN
|
||||
#define BIG_ENDIAN _BIG_ENDIAN
|
||||
#define PDP_ENDIAN _PDP_ENDIAN
|
||||
#define BYTE_ORDER _BYTE_ORDER
|
||||
#endif
|
||||
|
||||
#define _QUAD_HIGHWORD 1
|
||||
#define _QUAD_LOWWORD 0
|
||||
#define __ntohl(x) (__bswap32(x))
|
||||
#define __ntohs(x) (__bswap16(x))
|
||||
#define __htonl(x) (__bswap32(x))
|
||||
#define __htons(x) (__bswap16(x))
|
||||
|
||||
static __inline uint64_t
|
||||
__bswap64(uint64_t x)
|
||||
{
|
||||
uint64_t ret;
|
||||
|
||||
__asm __volatile("rev %0, %1\n"
|
||||
: "=&r" (ret), "+r" (x));
|
||||
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint32_t
|
||||
__bswap32_var(uint32_t v)
|
||||
{
|
||||
uint32_t ret;
|
||||
|
||||
__asm __volatile("rev32 %x0, %x1\n"
|
||||
: "=&r" (ret), "+r" (v));
|
||||
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint16_t
|
||||
__bswap16_var(uint16_t v)
|
||||
{
|
||||
uint32_t ret;
|
||||
|
||||
__asm __volatile("rev16 %w0, %w1\n"
|
||||
: "=&r" (ret), "+r" (v));
|
||||
|
||||
return ((uint16_t)ret);
|
||||
}
|
||||
|
||||
#ifdef __OPTIMIZE__
|
||||
|
||||
#define __bswap32_constant(x) \
|
||||
((((x) & 0xff000000U) >> 24) | \
|
||||
(((x) & 0x00ff0000U) >> 8) | \
|
||||
(((x) & 0x0000ff00U) << 8) | \
|
||||
(((x) & 0x000000ffU) << 24))
|
||||
|
||||
#define __bswap16_constant(x) \
|
||||
((((x) & 0xff00) >> 8) | \
|
||||
(((x) & 0x00ff) << 8))
|
||||
|
||||
#define __bswap16(x) \
|
||||
((uint16_t)(__builtin_constant_p(x) ? \
|
||||
__bswap16_constant((uint16_t)(x)) : \
|
||||
__bswap16_var(x)))
|
||||
|
||||
#define __bswap32(x) \
|
||||
((uint32_t)(__builtin_constant_p(x) ? \
|
||||
__bswap32_constant((uint32_t)(x)) : \
|
||||
__bswap32_var(x)))
|
||||
|
||||
#else
|
||||
#define __bswap16(x) __bswap16_var(x)
|
||||
#define __bswap32(x) __bswap32_var(x)
|
||||
|
||||
#endif /* __OPTIMIZE__ */
|
||||
#endif /* ENDIAN__H */
|
||||
@@ -0,0 +1,94 @@
|
||||
/*-
|
||||
* Copyright (c) 1989 Regents of the University of California.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* from: @(#)float.h 7.1 (Berkeley) 5/8/90
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _MACHINE_FLOAT_H_
|
||||
#define _MACHINE_FLOAT_H_
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
|
||||
__BEGIN_DECLS
|
||||
extern int __flt_rounds(void);
|
||||
__END_DECLS
|
||||
|
||||
#define FLT_RADIX 2 /* b */
|
||||
#define FLT_ROUNDS __flt_rounds()
|
||||
#if __ISO_C_VISIBLE >= 1999
|
||||
#define FLT_EVAL_METHOD 0
|
||||
#define DECIMAL_DIG 17 /* max precision in decimal digits */
|
||||
#endif
|
||||
|
||||
#define FLT_MANT_DIG 24 /* p */
|
||||
#define FLT_EPSILON 1.19209290E-07F /* b**(1-p) */
|
||||
#define FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */
|
||||
#define FLT_MIN_EXP (-125) /* emin */
|
||||
#define FLT_MIN 1.17549435E-38F /* b**(emin-1) */
|
||||
#define FLT_MIN_10_EXP (-37) /* ceil(log10(b**(emin-1))) */
|
||||
#define FLT_MAX_EXP 128 /* emax */
|
||||
#define FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */
|
||||
#define FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */
|
||||
#if __ISO_C_VISIBLE >= 2011
|
||||
#define FLT_TRUE_MIN 1.40129846E-45F /* b**(emin-p) */
|
||||
#define FLT_DECIMAL_DIG 9 /* ceil(1+p*log10(b)) */
|
||||
#define FLT_HAS_SUBNORM 1
|
||||
#endif /* __ISO_C_VISIBLE >= 2011 */
|
||||
|
||||
#define DBL_MANT_DIG 53
|
||||
#define DBL_EPSILON 2.2204460492503131E-16
|
||||
#define DBL_DIG 15
|
||||
#define DBL_MIN_EXP (-1021)
|
||||
#define DBL_MIN 2.2250738585072014E-308
|
||||
#define DBL_MIN_10_EXP (-307)
|
||||
#define DBL_MAX_EXP 1024
|
||||
#define DBL_MAX 1.7976931348623157E+308
|
||||
#define DBL_MAX_10_EXP 308
|
||||
#if __ISO_C_VISIBLE >= 2011
|
||||
#define DBL_TRUE_MIN 4.9406564584124654E-324
|
||||
#define DBL_DECIMAL_DIG 17
|
||||
#define DBL_HAS_SUBNORM 1
|
||||
#endif /* __ISO_C_VISIBLE >= 2011 */
|
||||
|
||||
#define LDBL_MANT_DIG 113
|
||||
#define LDBL_EPSILON 1.925929944387235853055977942584927319E-34L
|
||||
#define LDBL_DIG 33
|
||||
#define LDBL_MIN_EXP (-16381)
|
||||
#define LDBL_MIN 3.362103143112093506262677817321752603E-4932L
|
||||
#define LDBL_MIN_10_EXP (-4931)
|
||||
#define LDBL_MAX_EXP (+16384)
|
||||
#define LDBL_MAX 1.189731495357231765085759326628007016E+4932L
|
||||
#define LDBL_MAX_10_EXP (+4932)
|
||||
#if __ISO_C_VISIBLE >= 2011
|
||||
#define LDBL_TRUE_MIN 6.475175119438025110924438958227646552E-4966L
|
||||
#define LDBL_DECIMAL_DIG 36
|
||||
#define LDBL_HAS_SUBNORM 1
|
||||
#endif /* __ISO_C_VISIBLE >= 2011 */
|
||||
|
||||
#endif /* _MACHINE_FLOAT_H_ */
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright 2020 Broadcom
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/*
|
||||
* Portions copyright (c) 2020, ARM Limited and Contributors.
|
||||
* All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef INTTYPES__H
|
||||
#define INTTYPES__H
|
||||
|
||||
#define PRId64 "ld" /* int64_t */
|
||||
#define PRIi64 "li" /* int64_t */
|
||||
#define PRIo64 "lo" /* int64_t */
|
||||
#define PRIu64 "lu" /* uint64_t */
|
||||
#define PRIx64 "lx" /* uint64_t */
|
||||
#define PRIX64 "lX" /* uint64_t */
|
||||
|
||||
#define PRIdPTR "ld" /* intptr_t */
|
||||
#define PRIiPTR "li" /* intptr_t */
|
||||
#define PRIoPTR "lo" /* intptr_t */
|
||||
#define PRIuPTR "lu" /* uintptr_t */
|
||||
#define PRIxPTR "lx" /* uintptr_t */
|
||||
#define PRIXPTR "lX" /* uintptr_t */
|
||||
|
||||
#endif /* INTTYPES__H */
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define SCHAR_MAX 0x7F
|
||||
#define SCHAR_MIN (-SCHAR_MAX - 1)
|
||||
#define CHAR_MAX 0x7F
|
||||
#define CHAR_MIN (-CHAR_MAX - 1)
|
||||
#define UCHAR_MAX 0xFFU
|
||||
#define SHRT_MAX 0x7FFF
|
||||
#define SHRT_MIN (-SHRT_MAX - 1)
|
||||
#define USHRT_MAX 0xFFFFU
|
||||
#define INT_MAX 0x7FFFFFFF
|
||||
#define INT_MIN (-INT_MAX - 1)
|
||||
#define UINT_MAX 0xFFFFFFFFU
|
||||
#define LONG_MAX 0x7FFFFFFFFFFFFFFFL
|
||||
#define LONG_MIN (-LONG_MAX - 1L)
|
||||
#define ULONG_MAX 0xFFFFFFFFFFFFFFFFUL
|
||||
#define LLONG_MAX 0x7FFFFFFFFFFFFFFFLL
|
||||
#define LLONG_MIN (-LLONG_MAX - 1LL)
|
||||
#define ULLONG_MAX 0xFFFFFFFFFFFFFFFFULL
|
||||
|
||||
#define __LONG_BIT 64
|
||||
#define __WORD_BIT 32
|
||||
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SETJMP__H
|
||||
#define SETJMP__H
|
||||
|
||||
#define JMP_CTX_X19 0x0
|
||||
#define JMP_CTX_X21 0x10
|
||||
#define JMP_CTX_X23 0x20
|
||||
#define JMP_CTX_X25 0x30
|
||||
#define JMP_CTX_X27 0x40
|
||||
#define JMP_CTX_X29 0x50
|
||||
#define JMP_CTX_SP 0x60
|
||||
#define JMP_CTX_END 0x70 /* Aligned to 16 bytes */
|
||||
|
||||
#define JMP_SIZE (JMP_CTX_END >> 3)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <cdefs.h>
|
||||
|
||||
/* Jump buffer hosting x18 - x30 and sp_el0 registers */
|
||||
typedef uint64_t jmp_buf[JMP_SIZE] __aligned(16);
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* SETJMP__H */
|
||||
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef STDDEF__H
|
||||
#define STDDEF__H
|
||||
|
||||
#ifndef SIZET_
|
||||
typedef unsigned long size_t;
|
||||
#define SIZET_
|
||||
#endif
|
||||
|
||||
#endif /* STDDEF__H */
|
||||
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright 2020 Broadcom
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/*
|
||||
* Portions copyright (c) 2020, ARM Limited and Contributors.
|
||||
* All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef STDINT__H
|
||||
#define STDINT__H
|
||||
|
||||
#define INT64_MAX LONG_MAX
|
||||
#define INT64_MIN LONG_MIN
|
||||
#define UINT64_MAX ULONG_MAX
|
||||
|
||||
#define INT64_C(x) x ## L
|
||||
#define UINT64_C(x) x ## UL
|
||||
|
||||
typedef long int64_t;
|
||||
typedef unsigned long uint64_t;
|
||||
typedef long int64_least_t;
|
||||
typedef unsigned long uint64_least_t;
|
||||
typedef long int64_fast_t;
|
||||
typedef unsigned long uint64_fast_t;
|
||||
|
||||
typedef __int128 int128_t;
|
||||
typedef unsigned __int128 uint128_t;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef STDIO__H
|
||||
#define STDIO__H
|
||||
|
||||
#ifndef SSIZET_
|
||||
typedef long ssize_t;
|
||||
#define SSIZET_
|
||||
#endif
|
||||
|
||||
#endif /* STDIO__H */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user