GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,15 @@
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/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef AEM_GENERIC_H
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#define AEM_GENERIC_H
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#include <lib/utils_def.h>
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/* BASE AEM midr for revision 0 */
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#define BASE_AEM_MIDR U(0x410FD0F0)
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#endif /* AEM_GENERIC_H */
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@@ -0,0 +1,22 @@
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A12_H
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#define CORTEX_A12_H
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#include <lib/utils_def.h>
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/*******************************************************************************
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* Cortex-A12 midr with version/revision set to 0
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******************************************************************************/
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#define CORTEX_A12_MIDR U(0x410FC0D0)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A12_ACTLR_SMP_BIT (U(1) << 6)
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#endif /* CORTEX_A12_H */
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@@ -0,0 +1,30 @@
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A15_H
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#define CORTEX_A15_H
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#include <lib/utils_def.h>
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/*******************************************************************************
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* Auxiliary Control Register 2 specific definitions.
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******************************************************************************/
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#define CORTEX_A15_ACTLR2 p15, 1, c15, c0, 4
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#define CORTEX_A15_ACTLR2_INV_DCC_BIT (U(1) << 0)
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/*******************************************************************************
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* Cortex-A15 midr with version/revision set to 0
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******************************************************************************/
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#define CORTEX_A15_MIDR U(0x410FC0F0)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A15_ACTLR_INV_BTB_BIT (U(1) << 0)
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#define CORTEX_A15_ACTLR_SMP_BIT (U(1) << 6)
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#endif /* CORTEX_A15_H */
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@@ -0,0 +1,27 @@
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A17_H
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#define CORTEX_A17_H
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#include <lib/utils_def.h>
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/*******************************************************************************
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* Cortex-A17 midr with version/revision set to 0
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******************************************************************************/
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#define CORTEX_A17_MIDR U(0x410FC0E0)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A17_ACTLR_SMP_BIT (U(1) << 6)
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/*******************************************************************************
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* Implementation defined register specific definitions.
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******************************************************************************/
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#define CORTEX_A17_IMP_DEF_REG1 p15, 0, c15, c0, 1
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#endif /* CORTEX_A17_H */
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@@ -0,0 +1,22 @@
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/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A32_H
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#define CORTEX_A32_H
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#include <lib/utils_def.h>
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/* Cortex-A32 Main ID register for revision 0 */
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#define CORTEX_A32_MIDR U(0x410FD010)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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* CPUECTLR_EL1 is an implementation-specific register.
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******************************************************************************/
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#define CORTEX_A32_CPUECTLR_EL1 p15, 1, c15
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#define CORTEX_A32_CPUECTLR_SMPEN_BIT (ULL(1) << 6)
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#endif /* CORTEX_A32_H */
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@@ -0,0 +1,22 @@
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A5_H
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#define CORTEX_A5_H
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#include <lib/utils_def.h>
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/*******************************************************************************
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* Cortex-A8 midr with version/revision set to 0
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******************************************************************************/
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#define CORTEX_A5_MIDR U(0x410FC050)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A5_ACTLR_SMP_BIT (U(1) << 6)
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#endif /* CORTEX_A5_H */
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@@ -0,0 +1,73 @@
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/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A53_H
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#define CORTEX_A53_H
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#include <lib/utils_def.h>
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/* Cortex-A53 midr for revision 0 */
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#define CORTEX_A53_MIDR U(0x410FD030)
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/* Retention timer tick definitions */
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#define RETENTION_ENTRY_TICKS_2 U(0x1)
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#define RETENTION_ENTRY_TICKS_8 U(0x2)
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#define RETENTION_ENTRY_TICKS_32 U(0x3)
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#define RETENTION_ENTRY_TICKS_64 U(0x4)
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#define RETENTION_ENTRY_TICKS_128 U(0x5)
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#define RETENTION_ENTRY_TICKS_256 U(0x6)
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#define RETENTION_ENTRY_TICKS_512 U(0x7)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_ECTLR p15, 1, c15
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#define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6)
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#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0)
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#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
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#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3)
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#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
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/*******************************************************************************
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* CPU Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_MERRSR p15, 2, c15
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_CPUACTLR p15, 0, c15
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#define CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT U(44)
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#define CORTEX_A53_CPUACTLR_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT)
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#define CORTEX_A53_CPUACTLR_DTAH_SHIFT U(24)
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#define CORTEX_A53_CPUACTLR_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_DTAH_SHIFT)
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/*******************************************************************************
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* L2 Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_L2ACTLR p15, 1, c15, c0, 0
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#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14)
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#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3)
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/*******************************************************************************
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* L2 Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_L2ECTLR p15, 1, c9, c0, 3
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#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0)
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#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT)
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/*******************************************************************************
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* L2 Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_L2MERRSR p15, 3, c15
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#endif /* CORTEX_A53_H */
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@@ -0,0 +1,84 @@
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A57_H
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#define CORTEX_A57_H
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#include <lib/utils_def.h>
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/* Cortex-A57 midr for revision 0 */
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#define CORTEX_A57_MIDR U(0x410FD070)
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/* Retention timer tick definitions */
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#define RETENTION_ENTRY_TICKS_2 U(0x1)
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#define RETENTION_ENTRY_TICKS_8 U(0x2)
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#define RETENTION_ENTRY_TICKS_32 U(0x3)
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#define RETENTION_ENTRY_TICKS_64 U(0x4)
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#define RETENTION_ENTRY_TICKS_128 U(0x5)
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#define RETENTION_ENTRY_TICKS_256 U(0x6)
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#define RETENTION_ENTRY_TICKS_512 U(0x7)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_ECTLR p15, 1, c15
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#define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)
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#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
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#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
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#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
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#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0)
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#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
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/*******************************************************************************
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* CPU Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_CPUMERRSR p15, 2, c15
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_CPUACTLR p15, 0, c15
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#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59)
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#define CORTEX_A57_CPUACTLR_DIS_DMB_NULLIFICATION (ULL(1) << 58)
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#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55)
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#define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
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#define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52)
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#define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
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#define CORTEX_A57_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
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#define CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38)
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#define CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32)
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#define CORTEX_A57_CPUACTLR_DIS_STREAMING (ULL(3) << 27)
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#define CORTEX_A57_CPUACTLR_DIS_L1_STREAMING (ULL(3) << 25)
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#define CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
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/*******************************************************************************
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* L2 Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2
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#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
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#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
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#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
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#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
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/*******************************************************************************
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* L2 Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3
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#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0)
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#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
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/*******************************************************************************
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* L2 Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_L2MERRSR p15, 3, c15
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#endif /* CORTEX_A57_H */
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@@ -0,0 +1,22 @@
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A7_H
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#define CORTEX_A7_H
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#include <lib/utils_def.h>
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/*******************************************************************************
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* Cortex-A7 midr with version/revision set to 0
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******************************************************************************/
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#define CORTEX_A7_MIDR U(0x410FC070)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A7_ACTLR_SMP_BIT (U(1) << 6)
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#endif /* CORTEX_A7_H */
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@@ -0,0 +1,58 @@
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/*
|
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
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* SPDX-License-Identifier: BSD-3-Clause
|
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*/
|
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|
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#ifndef CORTEX_A72_H
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#define CORTEX_A72_H
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#include <lib/utils_def.h>
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/* Cortex-A72 midr for revision 0 */
|
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#define CORTEX_A72_MIDR U(0x410FD080)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A72_ECTLR p15, 1, c15
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#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
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#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
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#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
|
||||
#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
|
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|
||||
/*******************************************************************************
|
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* CPU Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_MERRSR p15, 2, c15
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||||
/*******************************************************************************
|
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* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
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||||
#define CORTEX_A72_CPUACTLR p15, 0, c15
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#define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
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#define CORTEX_A72_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55)
|
||||
#define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
|
||||
#define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
|
||||
#define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2
|
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||||
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
|
||||
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
|
||||
|
||||
#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
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||||
#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1)
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||||
#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_L2MERRSR p15, 3, c15
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||||
|
||||
#endif /* CORTEX_A72_H */
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@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A9_H
|
||||
#define CORTEX_A9_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Cortex-A9 midr with version/revision set to 0
|
||||
******************************************************************************/
|
||||
#define CORTEX_A9_MIDR U(0x410FC090)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A9_ACTLR_SMP_BIT (U(1) << 6)
|
||||
#define CORTEX_A9_ACTLR_FLZW_BIT (U(1) << 3)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control Register
|
||||
******************************************************************************/
|
||||
#define PCR p15, 0, c15, c0, 0
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <arch_helpers.h>
|
||||
DEFINE_COPROCR_RW_FUNCS(pcr, PCR)
|
||||
#endif
|
||||
|
||||
#endif /* CORTEX_A9_H */
|
||||
@@ -0,0 +1,230 @@
|
||||
/*
|
||||
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef CPU_MACROS_S
|
||||
#define CPU_MACROS_S
|
||||
|
||||
#include <arch.h>
|
||||
#include <lib/cpus/errata_report.h>
|
||||
|
||||
#if defined(IMAGE_BL1) || defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3)
|
||||
#define IMAGE_AT_EL3
|
||||
#endif
|
||||
|
||||
#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
|
||||
(MIDR_PN_MASK << MIDR_PN_SHIFT)
|
||||
|
||||
/* The number of CPU operations allowed */
|
||||
#define CPU_MAX_PWR_DWN_OPS 2
|
||||
|
||||
/* Special constant to specify that CPU has no reset function */
|
||||
#define CPU_NO_RESET_FUNC 0
|
||||
|
||||
/* Word size for 32-bit CPUs */
|
||||
#define CPU_WORD_SIZE 4
|
||||
|
||||
/*
|
||||
* Whether errata status needs reporting. Errata status is printed in debug
|
||||
* builds for both BL1 and BL32 images.
|
||||
*/
|
||||
#if (defined(IMAGE_BL1) || defined(IMAGE_BL32)) && DEBUG
|
||||
# define REPORT_ERRATA 1
|
||||
#else
|
||||
# define REPORT_ERRATA 0
|
||||
#endif
|
||||
|
||||
|
||||
.equ CPU_MIDR_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS
|
||||
.equ CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_ERRATA_LOCK_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_ERRATA_PRINTED_SIZE, CPU_WORD_SIZE
|
||||
|
||||
#ifndef IMAGE_AT_EL3
|
||||
.equ CPU_RESET_FUNC_SIZE, 0
|
||||
#endif
|
||||
|
||||
/* The power down core and cluster is needed only in BL32 */
|
||||
#ifndef IMAGE_BL32
|
||||
.equ CPU_PWR_DWN_OPS_SIZE, 0
|
||||
#endif
|
||||
|
||||
/* Fields required to print errata status */
|
||||
#if !REPORT_ERRATA
|
||||
.equ CPU_ERRATA_FUNC_SIZE, 0
|
||||
#endif
|
||||
|
||||
/* Only BL32 requires mutual exclusion and printed flag. */
|
||||
#if !(REPORT_ERRATA && defined(IMAGE_BL32))
|
||||
.equ CPU_ERRATA_LOCK_SIZE, 0
|
||||
.equ CPU_ERRATA_PRINTED_SIZE, 0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Define the offsets to the fields in cpu_ops structure.
|
||||
* Every offset is defined based on the offset and size of the previous
|
||||
* field.
|
||||
*/
|
||||
.equ CPU_MIDR, 0
|
||||
.equ CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE
|
||||
.equ CPU_PWR_DWN_OPS, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
|
||||
.equ CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE
|
||||
.equ CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE
|
||||
.equ CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE
|
||||
.equ CPU_OPS_SIZE, CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE
|
||||
|
||||
/*
|
||||
* Write given expressions as words
|
||||
*
|
||||
* _count:
|
||||
* Write at least _count words. If the given number of expressions
|
||||
* is less than _count, repeat the last expression to fill _count
|
||||
* words in total
|
||||
* _rest:
|
||||
* Optional list of expressions. _this is for parameter extraction
|
||||
* only, and has no significance to the caller
|
||||
*
|
||||
* Invoked as:
|
||||
* fill_constants 2, foo, bar, blah, ...
|
||||
*/
|
||||
.macro fill_constants _count:req, _this, _rest:vararg
|
||||
.ifgt \_count
|
||||
/* Write the current expression */
|
||||
.ifb \_this
|
||||
.error "Nothing to fill"
|
||||
.endif
|
||||
.word \_this
|
||||
|
||||
/* Invoke recursively for remaining expressions */
|
||||
.ifnb \_rest
|
||||
fill_constants \_count-1, \_rest
|
||||
.else
|
||||
fill_constants \_count-1, \_this
|
||||
.endif
|
||||
.endif
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Declare CPU operations
|
||||
*
|
||||
* _name:
|
||||
* Name of the CPU for which operations are being specified
|
||||
* _midr:
|
||||
* Numeric value expected to read from CPU's MIDR
|
||||
* _resetfunc:
|
||||
* Reset function for the CPU. If there's no CPU reset function,
|
||||
* specify CPU_NO_RESET_FUNC
|
||||
* _power_down_ops:
|
||||
* Comma-separated list of functions to perform power-down
|
||||
* operatios on the CPU. At least one, and up to
|
||||
* CPU_MAX_PWR_DWN_OPS number of functions may be specified.
|
||||
* Starting at power level 0, these functions shall handle power
|
||||
* down at subsequent power levels. If there aren't exactly
|
||||
* CPU_MAX_PWR_DWN_OPS functions, the last specified one will be
|
||||
* used to handle power down at subsequent levels
|
||||
*/
|
||||
.macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
|
||||
_power_down_ops:vararg
|
||||
.section cpu_ops, "a"
|
||||
.align 2
|
||||
.type cpu_ops_\_name, %object
|
||||
.word \_midr
|
||||
#if defined(IMAGE_AT_EL3)
|
||||
.word \_resetfunc
|
||||
#endif
|
||||
#ifdef IMAGE_BL32
|
||||
/* Insert list of functions */
|
||||
fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops
|
||||
#endif
|
||||
|
||||
#if REPORT_ERRATA
|
||||
.ifndef \_name\()_cpu_str
|
||||
/*
|
||||
* Place errata reported flag, and the spinlock to arbitrate access to
|
||||
* it in the data section.
|
||||
*/
|
||||
.pushsection .data
|
||||
define_asm_spinlock \_name\()_errata_lock
|
||||
\_name\()_errata_reported:
|
||||
.word 0
|
||||
.popsection
|
||||
|
||||
/* Place CPU string in rodata */
|
||||
.pushsection .rodata
|
||||
\_name\()_cpu_str:
|
||||
.asciz "\_name"
|
||||
.popsection
|
||||
.endif
|
||||
|
||||
/*
|
||||
* Mandatory errata status printing function for CPUs of
|
||||
* this class.
|
||||
*/
|
||||
.word \_name\()_errata_report
|
||||
|
||||
#ifdef IMAGE_BL32
|
||||
/* Pointers to errata lock and reported flag */
|
||||
.word \_name\()_errata_lock
|
||||
.word \_name\()_errata_reported
|
||||
#endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
#if REPORT_ERRATA
|
||||
/*
|
||||
* Print status of a CPU errata
|
||||
*
|
||||
* _chosen:
|
||||
* Identifier indicating whether or not a CPU errata has been
|
||||
* compiled in.
|
||||
* _cpu:
|
||||
* Name of the CPU
|
||||
* _id:
|
||||
* Errata identifier
|
||||
* _rev_var:
|
||||
* Register containing the combined value CPU revision and variant
|
||||
* - typically the return value of cpu_get_rev_var
|
||||
*/
|
||||
.macro report_errata _chosen, _cpu, _id, _rev_var=r4
|
||||
/* Stash a string with errata ID */
|
||||
.pushsection .rodata
|
||||
\_cpu\()_errata_\_id\()_str:
|
||||
.asciz "\_id"
|
||||
.popsection
|
||||
|
||||
/* Check whether errata applies */
|
||||
mov r0, \_rev_var
|
||||
bl check_errata_\_id
|
||||
|
||||
.ifeq \_chosen
|
||||
/*
|
||||
* Errata workaround has not been compiled in. If the errata would have
|
||||
* applied had it been compiled in, print its status as missing.
|
||||
*/
|
||||
cmp r0, #0
|
||||
movne r0, #ERRATA_MISSING
|
||||
.endif
|
||||
ldr r1, =\_cpu\()_cpu_str
|
||||
ldr r2, =\_cpu\()_errata_\_id\()_str
|
||||
bl errata_print_msg
|
||||
.endm
|
||||
#endif
|
||||
/*
|
||||
* Helper macro that reads the part number of the current CPU and jumps
|
||||
* to the given label if it matches the CPU MIDR provided.
|
||||
*
|
||||
* Clobbers: r0-r1
|
||||
*/
|
||||
.macro jump_if_cpu_midr _cpu_midr, _label
|
||||
ldcopr r0, MIDR
|
||||
ubfx r0, r0, #MIDR_PN_SHIFT, #12
|
||||
ldr r1, =((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
|
||||
cmp r0, r1
|
||||
beq \_label
|
||||
.endm
|
||||
|
||||
#endif /* CPU_MACROS_S */
|
||||
Reference in New Issue
Block a user