GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,15 @@
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/*
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* Copyright (c) 2022, Fujitsu Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef A64FX_H
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#define A64FX_H
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#include <lib/utils_def.h>
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/* A64FX midr for revision 0 */
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#define A64FX_MIDR U(0x461f0010)
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#endif /* A64FX_H */
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@@ -0,0 +1,18 @@
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/*
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* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef AEM_GENERIC_H
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#define AEM_GENERIC_H
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#include <lib/utils_def.h>
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/* BASE AEM midr for revision 0 */
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#define BASE_AEM_MIDR U(0x410FD0F0)
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/* Foundation AEM midr for revision 0 */
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#define FOUNDATION_AEM_MIDR U(0x410FD000)
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#endif /* AEM_GENERIC_H */
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@@ -0,0 +1,29 @@
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/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A35_H
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#define CORTEX_A35_H
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#include <lib/utils_def.h>
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/* Cortex-A35 Main ID register for revision 0 */
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#define CORTEX_A35_MIDR U(0x410FD040)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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* CPUECTLR_EL1 is an implementation-specific register.
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******************************************************************************/
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#define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1
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#define CORTEX_A35_CPUECTLR_SMPEN_BIT (ULL(1) << 6)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A35_CPUACTLR_EL1 S3_1_C15_C2_0
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#define CORTEX_A35_CPUACTLR_EL1_ENDCCASCI (ULL(1) << 44)
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#endif /* CORTEX_A35_H */
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@@ -0,0 +1,41 @@
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/*
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* Copyright (c) 2022, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A510_H
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#define CORTEX_A510_H
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#define CORTEX_A510_MIDR U(0x410FD460)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19)
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#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1)
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#define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23)
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#define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46)
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#define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2)
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#define CORTEX_A510_CPUECTLR_EL1_ATOM U(38)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* Complex auxiliary control register specific definitions
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******************************************************************************/
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#define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3
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/*******************************************************************************
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* Auxiliary control register specific definitions
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******************************************************************************/
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#define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0
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#define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17)
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#define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38)
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#endif /* CORTEX_A510_H */
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@@ -0,0 +1,85 @@
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/*
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* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A53_H
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#define CORTEX_A53_H
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#include <lib/utils_def.h>
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/* Cortex-A53 midr for revision 0 */
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#define CORTEX_A53_MIDR U(0x410FD030)
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/* Retention timer tick definitions */
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#define RETENTION_ENTRY_TICKS_2 U(0x1)
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#define RETENTION_ENTRY_TICKS_8 U(0x2)
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#define RETENTION_ENTRY_TICKS_32 U(0x3)
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#define RETENTION_ENTRY_TICKS_64 U(0x4)
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#define RETENTION_ENTRY_TICKS_128 U(0x5)
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#define RETENTION_ENTRY_TICKS_256 U(0x6)
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#define RETENTION_ENTRY_TICKS_512 U(0x7)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1
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#define CORTEX_A53_ECTLR_SMP_BIT (ULL(1) << 6)
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#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0)
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#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
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#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3)
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#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
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/*******************************************************************************
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* CPU Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_MERRSR_EL1 S3_1_C15_C2_2
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_CPUACTLR_EL1 S3_1_C15_C2_0
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#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT U(44)
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#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT)
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#define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT U(27)
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#define CORTEX_A53_CPUACTLR_EL1_RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT)
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#define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT U(25)
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#define CORTEX_A53_CPUACTLR_EL1_L1RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT)
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#define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT U(24)
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#define CORTEX_A53_CPUACTLR_EL1_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT)
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#define CORTEX_A53_CPUACTLR_EL1_L1PCTL_SHIFT U(13)
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#define CORTEX_A53_CPUACTLR_EL1_L1PCTL (ULL(7) << CORTEX_A53_CPUACTLR_EL1_L1PCTL_SHIFT)
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/*******************************************************************************
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* L2 Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0
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#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14)
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#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3)
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/*******************************************************************************
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* L2 Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3
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#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0)
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#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT)
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/*******************************************************************************
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* L2 Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3
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/*******************************************************************************
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* Helper function to access a53_cpuectlr_el1 register on Cortex-A53 CPUs
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******************************************************************************/
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#ifndef __ASSEMBLER__
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DEFINE_RENAME_SYSREG_RW_FUNCS(a53_cpuectlr_el1, CORTEX_A53_ECTLR_EL1)
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#endif /* __ASSEMBLER__ */
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#endif /* CORTEX_A53_H */
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@@ -0,0 +1,48 @@
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A55_H
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#define CORTEX_A55_H
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#include <lib/utils_def.h>
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/* Cortex-A55 MIDR for revision 0 */
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#define CORTEX_A55_MIDR U(0x410fd050)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A55_CPUECTLR_EL1_L1WSCTL (ULL(3) << 25)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A55_CPUACTLR_EL1 S3_0_C15_C1_0
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#define CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING (ULL(1) << 24)
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#define CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE (ULL(1) << 31)
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#define CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS (ULL(1) << 49)
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/*******************************************************************************
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* CPU Identification register specific definitions.
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******************************************************************************/
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#define CORTEX_A55_CLIDR_EL1 S3_1_C0_C0_1
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#define CORTEX_A55_CLIDR_EL1_CTYPE3 (ULL(7) << 6)
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/* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */
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#define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1)
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/* Instruction patching registers */
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#define CPUPSELR_EL3 S3_6_C15_C8_0
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#define CPUPCR_EL3 S3_6_C15_C8_1
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#define CPUPOR_EL3 S3_6_C15_C8_2
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#define CPUPMR_EL3 S3_6_C15_C8_3
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#endif /* CORTEX_A55_H */
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@@ -0,0 +1,88 @@
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/*
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* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A57_H
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#define CORTEX_A57_H
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#include <lib/utils_def.h>
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/* Cortex-A57 midr for revision 0 */
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#define CORTEX_A57_MIDR U(0x410FD070)
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/* Retention timer tick definitions */
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#define RETENTION_ENTRY_TICKS_2 U(0x1)
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#define RETENTION_ENTRY_TICKS_8 U(0x2)
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#define RETENTION_ENTRY_TICKS_32 U(0x3)
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#define RETENTION_ENTRY_TICKS_64 U(0x4)
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#define RETENTION_ENTRY_TICKS_128 U(0x5)
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#define RETENTION_ENTRY_TICKS_256 U(0x6)
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#define RETENTION_ENTRY_TICKS_512 U(0x7)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1
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#define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)
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#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
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#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
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#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
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#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0)
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#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
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/*******************************************************************************
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* CPU Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_MERRSR_EL1 S3_1_C15_C2_2
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0
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#define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION (ULL(1) << 58)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55)
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#define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52)
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#define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
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#define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
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#define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27)
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#define CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD (ULL(1) << 24)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
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/*******************************************************************************
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* L2 Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2
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#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
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#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
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#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
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#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
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#define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21)
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/*******************************************************************************
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* L2 Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_L2ECTLR_EL1 S3_1_C11_C0_3
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#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0)
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#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
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/*******************************************************************************
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* L2 Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
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||||
#define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3
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#endif /* CORTEX_A57_H */
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@@ -0,0 +1,31 @@
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/*
|
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* Copyright (c) 2019, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A65_H
|
||||
#define CORTEX_A65_H
|
||||
|
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#include <lib/utils_def.h>
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||||
|
||||
#define CORTEX_A65_MIDR U(0x410FD060)
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||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
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||||
#define CORTEX_A65_ECTLR_EL1 S3_0_C15_C1_4
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||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions
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||||
******************************************************************************/
|
||||
#define CORTEX_A65_CPUACTLR_EL1 S3_0_C15_C1_0
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|
||||
/*******************************************************************************
|
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* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
|
||||
#define CORTEX_A65_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
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|
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#endif /* CORTEX_A65_H */
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||||
+31
@@ -0,0 +1,31 @@
|
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/*
|
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* Copyright (c) 2019, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A65AE_H
|
||||
#define CORTEX_A65AE_H
|
||||
|
||||
#include <lib/utils_def.h>
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||||
|
||||
#define CORTEX_A65AE_MIDR U(0x410FD430)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A65AE_ECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A65AE_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
|
||||
#define CORTEX_A65AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
|
||||
|
||||
#endif /* CORTEX_A65AE_H */
|
||||
@@ -0,0 +1,65 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A710_H
|
||||
#define CORTEX_A710_H
|
||||
|
||||
#define CORTEX_A710_MIDR U(0x410FD470)
|
||||
|
||||
/* Cortex-A710 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_A710_BHB_LOOP_COUNT U(32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
#define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
#define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
|
||||
#define CORTEX_A710_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register 2 specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A710_CPUACTLR2_EL1 S3_0_C15_C1_1
|
||||
#define CORTEX_A710_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
|
||||
#define CORTEX_A710_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register 5 specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0
|
||||
#define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
|
||||
#define CORTEX_A710_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
|
||||
#define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A710_CPUECTLR2_EL1 S3_0_C15_C1_5
|
||||
#define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
|
||||
#define CPUECTLR2_EL1_PF_MODE_LSB U(11)
|
||||
#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Selected Instruction Private register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A710_CPUPSELR_EL3 S3_6_C15_C8_0
|
||||
#define CORTEX_A710_CPUPCR_EL3 S3_6_C15_C8_1
|
||||
#define CORTEX_A710_CPUPOR_EL3 S3_6_C15_C8_2
|
||||
#define CORTEX_A710_CPUPMR_EL3 S3_6_C15_C8_3
|
||||
|
||||
#endif /* CORTEX_A710_H */
|
||||
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A72_H
|
||||
#define CORTEX_A72_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A72 midr for revision 0 */
|
||||
#define CORTEX_A72_MIDR U(0x410FD080)
|
||||
|
||||
/* Cortex-A72 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_A72_BHB_LOOP_COUNT U(8)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1
|
||||
|
||||
#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
|
||||
#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
|
||||
#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
|
||||
#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_CPUACTLR_EL1 S3_1_C15_C2_0
|
||||
|
||||
#define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
|
||||
#define CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55)
|
||||
#define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
|
||||
#define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
|
||||
#define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0
|
||||
|
||||
#define CORTEX_A72_L2ACTLR_FORCE_TAG_BANK_CLK_ACTIVE (ULL(1) << 28)
|
||||
#define CORTEX_A72_L2ACTLR_FORCE_L2_LOGIC_CLK_ACTIVE (ULL(1) << 27)
|
||||
#define CORTEX_A72_L2ACTLR_FORCE_L2_GIC_TIMER_RCG_CLK_ACTIVE (ULL(1) << 26)
|
||||
#define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN (ULL(1) << 14)
|
||||
#define CORTEX_A72_L2ACTLR_DISABLE_DSB_WITH_NO_DVM_SYNC (ULL(1) << 11)
|
||||
#define CORTEX_A72_L2ACTLR_DISABLE_DVM_CMO_BROADCAST (ULL(1) << 8)
|
||||
#define CORTEX_A72_L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT (ULL(1) << 7)
|
||||
#define CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI (ULL(1) << 6)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
|
||||
|
||||
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
|
||||
#define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT U(5)
|
||||
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
|
||||
#define CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT U(9)
|
||||
|
||||
#define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK U(0x7)
|
||||
#define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK U(0x7)
|
||||
#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
|
||||
#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1)
|
||||
#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3
|
||||
|
||||
#endif /* CORTEX_A72_H */
|
||||
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A73_H
|
||||
#define CORTEX_A73_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A73 midr for revision 0 */
|
||||
#define CORTEX_A73_MIDR U(0x410FD090)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A73_CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */
|
||||
|
||||
#define CORTEX_A73_CPUECTLR_SMP_BIT (ULL(1) << 6)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A73_L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU implementation defined register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A73_IMP_DEF_REG1 S3_0_C15_C0_0
|
||||
|
||||
#define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (ULL(1) << 3)
|
||||
|
||||
#define CORTEX_A73_DIAGNOSTIC_REGISTER S3_0_C15_C0_1
|
||||
|
||||
#define CORTEX_A73_IMP_DEF_REG2 S3_0_C15_C0_2
|
||||
|
||||
/*******************************************************************************
|
||||
* Helper function to access a73_cpuectlr_el1 register on Cortex-A73 CPUs
|
||||
******************************************************************************/
|
||||
#ifndef __ASSEMBLER__
|
||||
DEFINE_RENAME_SYSREG_RW_FUNCS(a73_cpuectlr_el1, CORTEX_A73_CPUECTLR_EL1)
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* CORTEX_A73_H */
|
||||
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A75_H
|
||||
#define CORTEX_A75_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A75 MIDR */
|
||||
#define CORTEX_A75_MIDR U(0x410fd0a0)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A75_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_A75_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A75_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
|
||||
#define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 35)
|
||||
|
||||
/* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */
|
||||
#define CORTEX_A75_CORE_PWRDN_EN_MASK U(0x1)
|
||||
|
||||
#define CORTEX_A75_ACTLR_AMEN_BIT (ULL(1) << 4)
|
||||
|
||||
/*
|
||||
* The Cortex-A75 core implements five counters, 0-4. Events 0, 1, 2, are
|
||||
* fixed and are enabled (Group 0). Events 3 and 4 (Group 1) are
|
||||
* programmable by programming the appropriate Event count bits in
|
||||
* CPUAMEVTYPER<n> register and are disabled by default. Platforms may
|
||||
* enable this with suitable programming.
|
||||
*/
|
||||
#define CORTEX_A75_AMU_NR_COUNTERS U(5)
|
||||
#define CORTEX_A75_AMU_GROUP0_MASK U(0x7)
|
||||
#define CORTEX_A75_AMU_GROUP1_MASK (U(0) << 3)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <stdint.h>
|
||||
|
||||
uint64_t cortex_a75_amu_cnt_read(int idx);
|
||||
void cortex_a75_amu_cnt_write(int idx, uint64_t val);
|
||||
unsigned int cortex_a75_amu_read_cpuamcntenset_el0(void);
|
||||
unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void);
|
||||
void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask);
|
||||
void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask);
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* CORTEX_A75_H */
|
||||
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A76_H
|
||||
#define CORTEX_A76_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A76 MIDR for revision 0 */
|
||||
#define CORTEX_A76_MIDR U(0x410fd0b0)
|
||||
|
||||
/* Cortex-A76 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_A76_BHB_LOOP_COUNT U(24)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24)
|
||||
#define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A76_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
|
||||
#define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6)
|
||||
|
||||
#define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
|
||||
|
||||
#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1
|
||||
|
||||
#define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
|
||||
|
||||
#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16)
|
||||
|
||||
#define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2
|
||||
|
||||
#define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10)
|
||||
|
||||
|
||||
/* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */
|
||||
#define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1)
|
||||
|
||||
#endif /* CORTEX_A76_H */
|
||||
+28
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A76AE_H
|
||||
#define CORTEX_A76AE_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A76AE MIDR for revision 0 */
|
||||
#define CORTEX_A76AE_MIDR U(0x410FD0E0)
|
||||
|
||||
/* Cortex-A76 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_A76AE_BHB_LOOP_COUNT U(24)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A76AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
|
||||
/* Definitions of register field mask in CORTEX_A76AE_CPUPWRCTLR_EL1 */
|
||||
#define CORTEX_A76AE_CORE_PWRDN_EN_MASK U(0x1)
|
||||
|
||||
#define CORTEX_A76AE_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
#endif /* CORTEX_A76AE_H */
|
||||
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A77_H
|
||||
#define CORTEX_A77_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Cortex-A77 MIDR */
|
||||
#define CORTEX_A77_MIDR U(0x410FD0D0)
|
||||
|
||||
/* Cortex-A77 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_A77_BHB_LOOP_COUNT U(24)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
#define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
|
||||
#define CORTEX_A77_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A77_ACTLR2_EL1 S3_0_C15_C1_1
|
||||
#define CORTEX_A77_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
|
||||
#define CORTEX_A77_ACTLR2_EL1_BIT_0 ULL(1)
|
||||
|
||||
#define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0
|
||||
#define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1
|
||||
#define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2
|
||||
#define CORTEX_A77_CPUPMR_EL3 S3_6_C15_C8_3
|
||||
#define CORTEX_A77_CPUPOR2_EL3 S3_6_C15_C8_4
|
||||
#define CORTEX_A77_CPUPMR2_EL3 S3_6_C15_C8_5
|
||||
|
||||
#endif /* CORTEX_A77_H */
|
||||
@@ -0,0 +1,58 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2023, ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A78_H
|
||||
#define CORTEX_A78_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#define CORTEX_A78_MIDR U(0x410FD410)
|
||||
|
||||
/* Cortex-A78 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_A78_BHB_LOOP_COUNT U(32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
#define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
|
||||
#define CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)
|
||||
#define CPUECTLR_EL1_PF_MODE_LSB U(6)
|
||||
#define CPUECTLR_EL1_PF_MODE_WIDTH U(2)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
|
||||
|
||||
#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
|
||||
#define CORTEX_A78_ACTLR2_EL1_BIT_0 (ULL(1) << 0)
|
||||
#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
|
||||
#define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
|
||||
#define CORTEX_A78_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
|
||||
|
||||
#define CORTEX_A78_ACTLR3_EL1 S3_0_C15_C1_2
|
||||
|
||||
#define CORTEX_A78_ACTLR5_EL1 S3_0_C15_C9_0
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Activity Monitor Unit register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
|
||||
#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
|
||||
#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
|
||||
#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
|
||||
|
||||
#define CORTEX_A78_AMU_GROUP0_MASK U(0xF)
|
||||
#define CORTEX_A78_AMU_GROUP1_MASK U(0x7)
|
||||
|
||||
#endif /* CORTEX_A78_H */
|
||||
+31
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2022, ARM Limited. All rights reserved.
|
||||
* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A78_AE_H
|
||||
#define CORTEX_A78_AE_H
|
||||
|
||||
#include <cortex_a78.h>
|
||||
|
||||
#define CORTEX_A78_AE_MIDR U(0x410FD420)
|
||||
|
||||
/* Cortex-A78AE loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_A78_AE_BHB_LOOP_COUNT U(32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A78_AE_CPUECTLR_EL1 CORTEX_A78_CPUECTLR_EL1
|
||||
#define CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 CORTEX_A78_CPUECTLR_EL1_BIT_8
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register 2 specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A78_AE_ACTLR2_EL1 CORTEX_A78_ACTLR2_EL1
|
||||
#define CORTEX_A78_AE_ACTLR2_EL1_BIT_0 CORTEX_A78_ACTLR2_EL1_BIT_0
|
||||
#define CORTEX_A78_AE_ACTLR2_EL1_BIT_40 CORTEX_A78_ACTLR2_EL1_BIT_40
|
||||
|
||||
#endif /* CORTEX_A78_AE_H */
|
||||
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_A78C_H
|
||||
#define CORTEX_A78C_H
|
||||
|
||||
|
||||
#define CORTEX_A78C_MIDR U(0x410FD4B1)
|
||||
|
||||
/* Cortex-A76 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_A78C_BHB_LOOP_COUNT U(32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register 2 specific definitions.
|
||||
* ****************************************************************************/
|
||||
#define CORTEX_A78C_CPUACTLR2_EL1 S3_0_C15_C1_1
|
||||
#define CORTEX_A78C_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
|
||||
#define CORTEX_A78C_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
#define CORTEX_A78C_CPUECTLR_EL1_BIT_6 (ULL(1) << 6)
|
||||
#define CORTEX_A78C_CPUECTLR_EL1_BIT_7 (ULL(1) << 7)
|
||||
#define CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN (ULL(1) << 53)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A78C_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register 3 specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A78C_ACTLR3_EL1 S3_0_C15_C1_2
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Implementation Specific Selected Instruction registers
|
||||
******************************************************************************/
|
||||
#define CORTEX_A78C_IMP_CPUPSELR_EL3 S3_6_C15_C8_0
|
||||
#define CORTEX_A78C_IMP_CPUPCR_EL3 S3_6_C15_C8_1
|
||||
#define CORTEX_A78C_IMP_CPUPOR_EL3 S3_6_C15_C8_2
|
||||
#define CORTEX_A78C_IMP_CPUPMR_EL3 S3_6_C15_C8_3
|
||||
|
||||
#endif /* CORTEX_A78C_H */
|
||||
+23
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_HAYES_H
|
||||
#define CORTEX_HAYES_H
|
||||
|
||||
#define CORTEX_HAYES_MIDR U(0x410FD800)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_HAYES_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_HAYES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_HAYES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
#endif /* CORTEX_HAYES_H */
|
||||
+26
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_HUNTER_H
|
||||
#define CORTEX_HUNTER_H
|
||||
|
||||
#define CORTEX_HUNTER_MIDR U(0x410FD810)
|
||||
|
||||
/* Cortex Hunter loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_HUNTER_BHB_LOOP_COUNT U(132)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_HUNTER_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_HUNTER_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_HUNTER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
#endif /* CORTEX_HUNTER_H */
|
||||
+26
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (c) 2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_HUNTER_ELP_ARM_H
|
||||
#define CORTEX_HUNTER_ELP_ARM_H
|
||||
|
||||
#define CORTEX_HUNTER_ELP_ARM_MIDR U(0x410FD821)
|
||||
|
||||
/* Cortex Hunter ELP loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_HUNTER_ELP_ARM_BHB_LOOP_COUNT U(132)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_HUNTER_ELP_ARM_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
#endif /* CORTEX_HUNTER_ELP_ARM_H */
|
||||
+26
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_MAKALU_H
|
||||
#define CORTEX_MAKALU_H
|
||||
|
||||
#define CORTEX_MAKALU_MIDR U(0x410FD4D0)
|
||||
|
||||
/* Cortex Makalu loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_MAKALU_BHB_LOOP_COUNT U(38)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_MAKALU_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_MAKALU_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
#endif /* CORTEX_MAKALU_H */
|
||||
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Copyright (c) 2022, Google LLC. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_X1_H
|
||||
#define CORTEX_X1_H
|
||||
|
||||
/* Cortex-X1 MIDR for r1p0 */
|
||||
#define CORTEX_X1_MIDR U(0x411fd440)
|
||||
|
||||
/* Cortex-X1 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_X1_BHB_LOOP_COUNT U(32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_X1_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_X1_ACTLR2_EL1 S3_0_C15_C1_1
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_X1_CORE_PWRDN_EN_MASK U(0x1)
|
||||
|
||||
#endif /* CORTEX_X1_H */
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_X2_H
|
||||
#define CORTEX_X2_H
|
||||
|
||||
#define CORTEX_X2_MIDR U(0x410FD480)
|
||||
|
||||
/* Cortex-X2 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_X2_BHB_LOOP_COUNT U(32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
#define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register 2 specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X2_CPUECTLR2_EL1 S3_0_C15_C1_5
|
||||
|
||||
#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT U(11)
|
||||
#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
|
||||
#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control Register definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X2_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
#define CORTEX_X2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control Register 2 definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X2_CPUACTLR2_EL1 S3_0_C15_C1_1
|
||||
#define CORTEX_X2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control Register 5 definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0
|
||||
#define CORTEX_X2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Implementation Specific Selected Instruction registers
|
||||
******************************************************************************/
|
||||
#define CORTEX_X2_IMP_CPUPSELR_EL3 S3_6_C15_C8_0
|
||||
#define CORTEX_X2_IMP_CPUPCR_EL3 S3_6_C15_C8_1
|
||||
#define CORTEX_X2_IMP_CPUPOR_EL3 S3_6_C15_C8_2
|
||||
#define CORTEX_X2_IMP_CPUPMR_EL3 S3_6_C15_C8_3
|
||||
|
||||
#endif /* CORTEX_X2_H */
|
||||
@@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CORTEX_X3_H
|
||||
#define CORTEX_X3_H
|
||||
|
||||
#define CORTEX_X3_MIDR U(0x410FD4E0)
|
||||
|
||||
/* Cortex-X3 loop count for CVE-2022-23960 mitigation */
|
||||
#define CORTEX_X3_BHB_LOOP_COUNT U(132)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X3_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
#define CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT U(4)
|
||||
#define CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT U(7)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register 2 specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1
|
||||
#define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
|
||||
|
||||
#endif /* CORTEX_X3_H */
|
||||
@@ -0,0 +1,314 @@
|
||||
/*
|
||||
* Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef CPU_MACROS_S
|
||||
#define CPU_MACROS_S
|
||||
|
||||
#include <arch.h>
|
||||
#include <assert_macros.S>
|
||||
#include <lib/cpus/errata_report.h>
|
||||
|
||||
#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
|
||||
(MIDR_PN_MASK << MIDR_PN_SHIFT)
|
||||
|
||||
/* The number of CPU operations allowed */
|
||||
#define CPU_MAX_PWR_DWN_OPS 2
|
||||
|
||||
/* Special constant to specify that CPU has no reset function */
|
||||
#define CPU_NO_RESET_FUNC 0
|
||||
|
||||
#define CPU_NO_EXTRA1_FUNC 0
|
||||
#define CPU_NO_EXTRA2_FUNC 0
|
||||
#define CPU_NO_EXTRA3_FUNC 0
|
||||
|
||||
/* Word size for 64-bit CPUs */
|
||||
#define CPU_WORD_SIZE 8
|
||||
|
||||
/*
|
||||
* Whether errata status needs reporting. Errata status is printed in debug
|
||||
* builds for both BL1 and BL31 images.
|
||||
*/
|
||||
#if (defined(IMAGE_BL1) || defined(IMAGE_BL31)) && DEBUG
|
||||
# define REPORT_ERRATA 1
|
||||
#else
|
||||
# define REPORT_ERRATA 0
|
||||
#endif
|
||||
|
||||
|
||||
.equ CPU_MIDR_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_EXTRA1_FUNC_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_EXTRA2_FUNC_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_EXTRA3_FUNC_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_E_HANDLER_FUNC_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS
|
||||
.equ CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_ERRATA_LOCK_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_ERRATA_PRINTED_SIZE, CPU_WORD_SIZE
|
||||
.equ CPU_REG_DUMP_SIZE, CPU_WORD_SIZE
|
||||
|
||||
#ifndef IMAGE_AT_EL3
|
||||
.equ CPU_RESET_FUNC_SIZE, 0
|
||||
#endif
|
||||
|
||||
/* The power down core and cluster is needed only in BL31 */
|
||||
#ifndef IMAGE_BL31
|
||||
.equ CPU_PWR_DWN_OPS_SIZE, 0
|
||||
#endif
|
||||
|
||||
/* Fields required to print errata status. */
|
||||
#if !REPORT_ERRATA
|
||||
.equ CPU_ERRATA_FUNC_SIZE, 0
|
||||
#endif
|
||||
|
||||
/* Only BL31 requieres mutual exclusion and printed flag. */
|
||||
#if !(REPORT_ERRATA && defined(IMAGE_BL31))
|
||||
.equ CPU_ERRATA_LOCK_SIZE, 0
|
||||
.equ CPU_ERRATA_PRINTED_SIZE, 0
|
||||
#endif
|
||||
|
||||
#if !defined(IMAGE_BL31) || !CRASH_REPORTING
|
||||
.equ CPU_REG_DUMP_SIZE, 0
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Define the offsets to the fields in cpu_ops structure.
|
||||
* Every offset is defined based in the offset and size of the previous
|
||||
* field.
|
||||
*/
|
||||
.equ CPU_MIDR, 0
|
||||
.equ CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE
|
||||
.equ CPU_EXTRA1_FUNC, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
|
||||
.equ CPU_EXTRA2_FUNC, CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE
|
||||
.equ CPU_EXTRA3_FUNC, CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE
|
||||
.equ CPU_E_HANDLER_FUNC, CPU_EXTRA3_FUNC + CPU_EXTRA3_FUNC_SIZE
|
||||
.equ CPU_PWR_DWN_OPS, CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE
|
||||
.equ CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE
|
||||
.equ CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE
|
||||
.equ CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE
|
||||
.equ CPU_REG_DUMP, CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE
|
||||
.equ CPU_OPS_SIZE, CPU_REG_DUMP + CPU_REG_DUMP_SIZE
|
||||
|
||||
/*
|
||||
* Write given expressions as quad words
|
||||
*
|
||||
* _count:
|
||||
* Write at least _count quad words. If the given number of
|
||||
* expressions is less than _count, repeat the last expression to
|
||||
* fill _count quad words in total
|
||||
* _rest:
|
||||
* Optional list of expressions. _this is for parameter extraction
|
||||
* only, and has no significance to the caller
|
||||
*
|
||||
* Invoked as:
|
||||
* fill_constants 2, foo, bar, blah, ...
|
||||
*/
|
||||
.macro fill_constants _count:req, _this, _rest:vararg
|
||||
.ifgt \_count
|
||||
/* Write the current expression */
|
||||
.ifb \_this
|
||||
.error "Nothing to fill"
|
||||
.endif
|
||||
.quad \_this
|
||||
|
||||
/* Invoke recursively for remaining expressions */
|
||||
.ifnb \_rest
|
||||
fill_constants \_count-1, \_rest
|
||||
.else
|
||||
fill_constants \_count-1, \_this
|
||||
.endif
|
||||
.endif
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Declare CPU operations
|
||||
*
|
||||
* _name:
|
||||
* Name of the CPU for which operations are being specified
|
||||
* _midr:
|
||||
* Numeric value expected to read from CPU's MIDR
|
||||
* _resetfunc:
|
||||
* Reset function for the CPU. If there's no CPU reset function,
|
||||
* specify CPU_NO_RESET_FUNC
|
||||
* _extra1:
|
||||
* This is a placeholder for future per CPU operations. Currently,
|
||||
* some CPUs use this entry to set a test function to determine if
|
||||
* the workaround for CVE-2017-5715 needs to be applied or not.
|
||||
* _extra2:
|
||||
* This is a placeholder for future per CPU operations. Currently
|
||||
* some CPUs use this entry to set a function to disable the
|
||||
* workaround for CVE-2018-3639.
|
||||
* _extra3:
|
||||
* This is a placeholder for future per CPU operations. Currently,
|
||||
* some CPUs use this entry to set a test function to determine if
|
||||
* the workaround for CVE-2022-23960 needs to be applied or not.
|
||||
* _e_handler:
|
||||
* This is a placeholder for future per CPU exception handlers.
|
||||
* _power_down_ops:
|
||||
* Comma-separated list of functions to perform power-down
|
||||
* operatios on the CPU. At least one, and up to
|
||||
* CPU_MAX_PWR_DWN_OPS number of functions may be specified.
|
||||
* Starting at power level 0, these functions shall handle power
|
||||
* down at subsequent power levels. If there aren't exactly
|
||||
* CPU_MAX_PWR_DWN_OPS functions, the last specified one will be
|
||||
* used to handle power down at subsequent levels
|
||||
*/
|
||||
.macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \
|
||||
_extra1:req, _extra2:req, _extra3:req, _e_handler:req, _power_down_ops:vararg
|
||||
.section cpu_ops, "a"
|
||||
.align 3
|
||||
.type cpu_ops_\_name, %object
|
||||
.quad \_midr
|
||||
#if defined(IMAGE_AT_EL3)
|
||||
.quad \_resetfunc
|
||||
#endif
|
||||
.quad \_extra1
|
||||
.quad \_extra2
|
||||
.quad \_extra3
|
||||
.quad \_e_handler
|
||||
#ifdef IMAGE_BL31
|
||||
/* Insert list of functions */
|
||||
fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops
|
||||
#endif
|
||||
|
||||
#if REPORT_ERRATA
|
||||
.ifndef \_name\()_cpu_str
|
||||
/*
|
||||
* Place errata reported flag, and the spinlock to arbitrate access to
|
||||
* it in the data section.
|
||||
*/
|
||||
.pushsection .data
|
||||
define_asm_spinlock \_name\()_errata_lock
|
||||
\_name\()_errata_reported:
|
||||
.word 0
|
||||
.popsection
|
||||
|
||||
/* Place CPU string in rodata */
|
||||
.pushsection .rodata
|
||||
\_name\()_cpu_str:
|
||||
.asciz "\_name"
|
||||
.popsection
|
||||
.endif
|
||||
|
||||
/*
|
||||
* Mandatory errata status printing function for CPUs of
|
||||
* this class.
|
||||
*/
|
||||
.quad \_name\()_errata_report
|
||||
|
||||
#ifdef IMAGE_BL31
|
||||
/* Pointers to errata lock and reported flag */
|
||||
.quad \_name\()_errata_lock
|
||||
.quad \_name\()_errata_reported
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(IMAGE_BL31) && CRASH_REPORTING
|
||||
.quad \_name\()_cpu_reg_dump
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
|
||||
_power_down_ops:vararg
|
||||
declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, 0, 0, \
|
||||
\_power_down_ops
|
||||
.endm
|
||||
|
||||
.macro declare_cpu_ops_eh _name:req, _midr:req, _resetfunc:req, \
|
||||
_e_handler:req, _power_down_ops:vararg
|
||||
declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
|
||||
0, 0, 0, \_e_handler, \_power_down_ops
|
||||
.endm
|
||||
|
||||
.macro declare_cpu_ops_wa _name:req, _midr:req, \
|
||||
_resetfunc:req, _extra1:req, _extra2:req, \
|
||||
_extra3:req, _power_down_ops:vararg
|
||||
declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
|
||||
\_extra1, \_extra2, \_extra3, 0, \_power_down_ops
|
||||
.endm
|
||||
|
||||
#if REPORT_ERRATA
|
||||
/*
|
||||
* Print status of a CPU errata
|
||||
*
|
||||
* _chosen:
|
||||
* Identifier indicating whether or not a CPU errata has been
|
||||
* compiled in.
|
||||
* _cpu:
|
||||
* Name of the CPU
|
||||
* _id:
|
||||
* Errata identifier
|
||||
* _rev_var:
|
||||
* Register containing the combined value CPU revision and variant
|
||||
* - typically the return value of cpu_get_rev_var
|
||||
*/
|
||||
.macro report_errata _chosen, _cpu, _id, _rev_var=x8
|
||||
/* Stash a string with errata ID */
|
||||
.pushsection .rodata
|
||||
\_cpu\()_errata_\_id\()_str:
|
||||
.asciz "\_id"
|
||||
.popsection
|
||||
|
||||
/* Check whether errata applies */
|
||||
mov x0, \_rev_var
|
||||
/* Shall clobber: x0-x7 */
|
||||
bl check_errata_\_id
|
||||
|
||||
.ifeq \_chosen
|
||||
/*
|
||||
* Errata workaround has not been compiled in. If the errata would have
|
||||
* applied had it been compiled in, print its status as missing.
|
||||
*/
|
||||
cbz x0, 900f
|
||||
mov x0, #ERRATA_MISSING
|
||||
.endif
|
||||
900:
|
||||
adr x1, \_cpu\()_cpu_str
|
||||
adr x2, \_cpu\()_errata_\_id\()_str
|
||||
bl errata_print_msg
|
||||
.endm
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This macro is used on some CPUs to detect if they are vulnerable
|
||||
* to CVE-2017-5715.
|
||||
*/
|
||||
.macro cpu_check_csv2 _reg _label
|
||||
mrs \_reg, id_aa64pfr0_el1
|
||||
ubfx \_reg, \_reg, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH
|
||||
/*
|
||||
* If the field equals 1, branch targets trained in one context cannot
|
||||
* affect speculative execution in a different context.
|
||||
*
|
||||
* If the field equals 2, it means that the system is also aware of
|
||||
* SCXTNUM_ELx register contexts. We aren't using them in the TF, so we
|
||||
* expect users of the registers to do the right thing.
|
||||
*
|
||||
* Only apply mitigations if the value of this field is 0.
|
||||
*/
|
||||
#if ENABLE_ASSERTIONS
|
||||
cmp \_reg, #3 /* Only values 0 to 2 are expected */
|
||||
ASM_ASSERT(lo)
|
||||
#endif
|
||||
|
||||
cmp \_reg, #0
|
||||
bne \_label
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Helper macro that reads the part number of the current
|
||||
* CPU and jumps to the given label if it matches the CPU
|
||||
* MIDR provided.
|
||||
*
|
||||
* Clobbers x0.
|
||||
*/
|
||||
.macro jump_if_cpu_midr _cpu_midr, _label
|
||||
mrs x0, midr_el1
|
||||
ubfx x0, x0, MIDR_PN_SHIFT, #12
|
||||
cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
|
||||
b.eq \_label
|
||||
.endm
|
||||
|
||||
#endif /* CPU_MACROS_S */
|
||||
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef CPUAMU_H
|
||||
#define CPUAMU_H
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Activity Monitor Unit register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CPUAMCNTENCLR_EL0 S3_3_C15_C9_7
|
||||
#define CPUAMCNTENSET_EL0 S3_3_C15_C9_6
|
||||
#define CPUAMCFGR_EL0 S3_3_C15_C10_6
|
||||
#define CPUAMUSERENR_EL0 S3_3_C15_C10_7
|
||||
|
||||
/* Activity Monitor Event Counter Registers */
|
||||
#define CPUAMEVCNTR0_EL0 S3_3_C15_C9_0
|
||||
#define CPUAMEVCNTR1_EL0 S3_3_C15_C9_1
|
||||
#define CPUAMEVCNTR2_EL0 S3_3_C15_C9_2
|
||||
#define CPUAMEVCNTR3_EL0 S3_3_C15_C9_3
|
||||
#define CPUAMEVCNTR4_EL0 S3_3_C15_C9_4
|
||||
|
||||
/* Activity Monitor Event Type Registers */
|
||||
#define CPUAMEVTYPER0_EL0 S3_3_C15_C10_0
|
||||
#define CPUAMEVTYPER1_EL0 S3_3_C15_C10_1
|
||||
#define CPUAMEVTYPER2_EL0 S3_3_C15_C10_2
|
||||
#define CPUAMEVTYPER3_EL0 S3_3_C15_C10_3
|
||||
#define CPUAMEVTYPER4_EL0 S3_3_C15_C10_4
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <stdint.h>
|
||||
|
||||
uint64_t cpuamu_cnt_read(unsigned int idx);
|
||||
void cpuamu_cnt_write(unsigned int idx, uint64_t val);
|
||||
unsigned int cpuamu_read_cpuamcntenset_el0(void);
|
||||
unsigned int cpuamu_read_cpuamcntenclr_el0(void);
|
||||
void cpuamu_write_cpuamcntenset_el0(unsigned int mask);
|
||||
void cpuamu_write_cpuamcntenclr_el0(unsigned int mask);
|
||||
|
||||
int midr_match(unsigned int cpu_midr);
|
||||
void cpuamu_context_save(unsigned int nr_counters);
|
||||
void cpuamu_context_restore(unsigned int nr_counters);
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* CPUAMU_H */
|
||||
@@ -0,0 +1,54 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef DENVER_H
|
||||
#define DENVER_H
|
||||
|
||||
/* MIDR values for Denver */
|
||||
#define DENVER_MIDR_PN0 U(0x4E0F0000)
|
||||
#define DENVER_MIDR_PN1 U(0x4E0F0010)
|
||||
#define DENVER_MIDR_PN2 U(0x4E0F0020)
|
||||
#define DENVER_MIDR_PN3 U(0x4E0F0030)
|
||||
#define DENVER_MIDR_PN4 U(0x4E0F0040)
|
||||
#define DENVER_MIDR_PN5 U(0x4E0F0050)
|
||||
#define DENVER_MIDR_PN6 U(0x4E0F0060)
|
||||
#define DENVER_MIDR_PN7 U(0x4E0F0070)
|
||||
#define DENVER_MIDR_PN8 U(0x4E0F0080)
|
||||
#define DENVER_MIDR_PN9 U(0x4E0F0090)
|
||||
|
||||
/* Implementer code in the MIDR register */
|
||||
#define DENVER_IMPL U(0x4E)
|
||||
|
||||
/* CPU state ids - implementation defined */
|
||||
#define DENVER_CPU_STATE_POWER_DOWN U(0x3)
|
||||
|
||||
/* Speculative store buffering */
|
||||
#define DENVER_CPU_DIS_SSB_EL3 (U(1) << 11)
|
||||
#define DENVER_PN4_CPU_DIS_SSB_EL3 (U(1) << 18)
|
||||
|
||||
/* Speculative memory disambiguation */
|
||||
#define DENVER_CPU_DIS_MD_EL3 (U(1) << 9)
|
||||
#define DENVER_PN4_CPU_DIS_MD_EL3 (U(1) << 17)
|
||||
|
||||
/* Core power management states */
|
||||
#define DENVER_CPU_PMSTATE_C1 U(0x1)
|
||||
#define DENVER_CPU_PMSTATE_C6 U(0x6)
|
||||
#define DENVER_CPU_PMSTATE_C7 U(0x7)
|
||||
#define DENVER_CPU_PMSTATE_MASK U(0xF)
|
||||
|
||||
/* ACTRL_ELx bits to enable dual execution*/
|
||||
#define DENVER_CPU_ENABLE_DUAL_EXEC_EL2 (ULL(1) << 9)
|
||||
#define DENVER_CPU_ENABLE_DUAL_EXEC_EL3 (ULL(1) << 9)
|
||||
#define DENVER_CPU_ENABLE_DUAL_EXEC_EL1 (U(1) << 4)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
/* Disable Dynamic Code Optimisation */
|
||||
void denver_disable_dco(void);
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* DENVER_H */
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef DSU_DEF_H
|
||||
#define DSU_DEF_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/********************************************************************
|
||||
* DSU Cluster Configuration registers definitions
|
||||
********************************************************************/
|
||||
#define CLUSTERCFR_EL1 S3_0_C15_C3_0
|
||||
|
||||
#define CLUSTERCFR_ACP_SHIFT U(11)
|
||||
|
||||
/********************************************************************
|
||||
* DSU Cluster Main Revision ID registers definitions
|
||||
********************************************************************/
|
||||
#define CLUSTERIDR_EL1 S3_0_C15_C3_1
|
||||
|
||||
#define CLUSTERIDR_REV_SHIFT U(0)
|
||||
#define CLUSTERIDR_REV_BITS U(4)
|
||||
#define CLUSTERIDR_VAR_SHIFT U(4)
|
||||
#define CLUSTERIDR_VAR_BITS U(4)
|
||||
|
||||
/********************************************************************
|
||||
* DSU Cluster Auxiliary Control registers definitions
|
||||
********************************************************************/
|
||||
#define CLUSTERACTLR_EL1 S3_0_C15_C3_3
|
||||
|
||||
#define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15)
|
||||
#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15)
|
||||
|
||||
/********************************************************************
|
||||
* Masks applied for DSU errata workarounds
|
||||
********************************************************************/
|
||||
#define DSU_ERRATA_936184_MASK (U(0x3) << 15)
|
||||
|
||||
#endif /* DSU_DEF_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Arm Limited. All rights reserverd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef AARCH64_GENERIC_H
|
||||
#define AARCH64_GENERIC_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/*
|
||||
* 0x0 value on the MIDR implementer value is reserved for software use,
|
||||
* so use an MIDR value of 0 for a default CPU library.
|
||||
*/
|
||||
#define AARCH64_GENERIC_MIDR U(0)
|
||||
|
||||
#endif /* AARCH64_GENERIC_H */
|
||||
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef NEOVERSE_E1_H
|
||||
#define NEOVERSE_E1_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#define NEOVERSE_E1_MIDR U(0x410FD4A0)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_E1_ECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_E1_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions.
|
||||
******************************************************************************/
|
||||
|
||||
#define NEOVERSE_E1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
|
||||
|
||||
#endif /* NEOVERSE_E1_H */
|
||||
@@ -0,0 +1,70 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef NEOVERSE_N1_H
|
||||
#define NEOVERSE_N1_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* Neoverse N1 MIDR for revision 0 */
|
||||
#define NEOVERSE_N1_MIDR U(0x410fd0c0)
|
||||
|
||||
/* Neoverse N1 loop count for CVE-2022-23960 mitigation */
|
||||
#define NEOVERSE_N1_BHB_LOOP_COUNT U(24)
|
||||
|
||||
/* Exception Syndrome register EC code for IC Trap */
|
||||
#define NEOVERSE_N1_EC_IC_TRAP U(0x1f)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
|
||||
/* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */
|
||||
#define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1)
|
||||
|
||||
#define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4)
|
||||
|
||||
#define NEOVERSE_N1_AMU_NR_COUNTERS U(5)
|
||||
#define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
#define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24)
|
||||
#define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51)
|
||||
#define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
|
||||
#define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6)
|
||||
#define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
|
||||
|
||||
#define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1
|
||||
|
||||
#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
|
||||
#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
|
||||
#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11)
|
||||
#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15)
|
||||
#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16)
|
||||
#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)
|
||||
|
||||
#define NEOVERSE_N1_CPUACTLR3_EL1 S3_0_C15_C1_2
|
||||
|
||||
#define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10)
|
||||
|
||||
/* Instruction patching registers */
|
||||
#define CPUPSELR_EL3 S3_6_C15_C8_0
|
||||
#define CPUPCR_EL3 S3_6_C15_C8_1
|
||||
#define CPUPOR_EL3 S3_6_C15_C8_2
|
||||
#define CPUPMR_EL3 S3_6_C15_C8_3
|
||||
|
||||
#endif /* NEOVERSE_N1_H */
|
||||
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Copyright (c) 2020-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef NEOVERSE_N2_H
|
||||
#define NEOVERSE_N2_H
|
||||
|
||||
/* Neoverse N2 ID register for revision r0p0 */
|
||||
#define NEOVERSE_N2_MIDR U(0x410FD490)
|
||||
|
||||
/* Neoverse N2 loop count for CVE-2022-23960 mitigation */
|
||||
#define NEOVERSE_N2_BHB_LOOP_COUNT U(32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power control register
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
|
||||
#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
|
||||
#define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register 2 specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
|
||||
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
|
||||
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
|
||||
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
|
||||
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register 5 specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0
|
||||
#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
|
||||
#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
|
||||
#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5
|
||||
#define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
|
||||
#define CPUECTLR2_EL1_PF_MODE_LSB U(11)
|
||||
#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
|
||||
|
||||
#endif /* NEOVERSE_N2_H */
|
||||
+18
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef NEOVERSE_N_COMMON_H
|
||||
#define NEOVERSE_N_COMMON_H
|
||||
|
||||
/******************************************************************************
|
||||
* Neoverse Nx CPU Configuration register definitions
|
||||
*****************************************************************************/
|
||||
#define CPUCFR_EL1 S3_0_C15_C0_0
|
||||
|
||||
/* SCU bit of CPU Configuration Register, EL1 */
|
||||
#define SCU_SHIFT U(2)
|
||||
|
||||
#endif /* NEOVERSE_N_COMMON_H */
|
||||
+27
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (c) 2022, ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef NEOVERSE_POSEIDON_H
|
||||
#define NEOVERSE_POSEIDON_H
|
||||
|
||||
|
||||
#define NEOVERSE_POSEIDON_MIDR U(0x410FD830)
|
||||
|
||||
/* Neoverse Poseidon loop count for CVE-2022-23960 mitigation */
|
||||
#define NEOVERSE_POSEIDON_BHB_LOOP_COUNT U(132)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_POSEIDON_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
#endif /* NEOVERSE_POSEIDON_H */
|
||||
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2023, ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef NEOVERSE_V1_H
|
||||
#define NEOVERSE_V1_H
|
||||
|
||||
#define NEOVERSE_V1_MIDR U(0x410FD400)
|
||||
|
||||
/* Neoverse V1 loop count for CVE-2022-23960 mitigation */
|
||||
#define NEOVERSE_V1_BHB_LOOP_COUNT U(32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
#define NEOVERSE_V1_CPUPSELR_EL3 S3_6_C15_C8_0
|
||||
#define NEOVERSE_V1_CPUPOR_EL3 S3_6_C15_C8_2
|
||||
#define NEOVERSE_V1_CPUPMR_EL3 S3_6_C15_C8_3
|
||||
#define NEOVERSE_V1_CPUPCR_EL3 S3_6_C15_C8_1
|
||||
#define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
|
||||
#define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
|
||||
#define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)
|
||||
#define CPUECTLR_EL1_PF_MODE_LSB U(6)
|
||||
#define CPUECTLR_EL1_PF_MODE_WIDTH U(2)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1
|
||||
#define NEOVERSE_V1_ACTLR2_EL1_BIT_0 ULL(1)
|
||||
#define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
|
||||
#define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28)
|
||||
#define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
|
||||
|
||||
#define NEOVERSE_V1_ACTLR3_EL1 S3_0_C15_C1_2
|
||||
|
||||
#define NEOVERSE_V1_ACTLR5_EL1 S3_0_C15_C9_0
|
||||
|
||||
#endif /* NEOVERSE_V1_H */
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef NEOVERSE_V2_H
|
||||
#define NEOVERSE_V2_H
|
||||
|
||||
#define NEOVERSE_V2_MIDR U(0x410FD4F0)
|
||||
|
||||
/* Neoverse V2 loop count for CVE-2022-23960 mitigation */
|
||||
#define NEOVERSE_V2_BHB_LOOP_COUNT U(132)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
#endif /* NEOVERSE_V2_H */
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef QEMU_MAX_H
|
||||
#define QEMU_MAX_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/*
|
||||
* QEMU MAX midr for revision 0
|
||||
* 00 - Reserved for software use
|
||||
* 0 - Variant
|
||||
* F - Architectural features identified in ID_* registers
|
||||
* 051 - 'Q', in a 12-bit field.
|
||||
* 0 - Revision
|
||||
*/
|
||||
#define QEMU_MAX_MIDR U(0x000F0510)
|
||||
|
||||
#endif /* QEMU_MAX_H */
|
||||
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef RAINIER_H
|
||||
#define RAINIER_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* RAINIER MIDR for revision 0 */
|
||||
#define RAINIER_MIDR U(0x3f0f4120)
|
||||
|
||||
/* Exception Syndrome register EC code for IC Trap */
|
||||
#define RAINIER_EC_IC_TRAP U(0x1f)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define RAINIER_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
|
||||
/* Definitions of register field mask in RAINIER_CPUPWRCTLR_EL1 */
|
||||
#define RAINIER_CORE_PWRDN_EN_MASK U(0x1)
|
||||
|
||||
#define RAINIER_ACTLR_AMEN_BIT (U(1) << 4)
|
||||
|
||||
#define RAINIER_AMU_NR_COUNTERS U(5)
|
||||
#define RAINIER_AMU_GROUP0_MASK U(0x1f)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define RAINIER_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
|
||||
#define RAINIER_WS_THR_L2_MASK (ULL(3) << 24)
|
||||
#define RAINIER_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define RAINIER_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
|
||||
#define RAINIER_CPUACTLR_EL1_BIT_6 (ULL(1) << 6)
|
||||
#define RAINIER_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
|
||||
|
||||
#define RAINIER_CPUACTLR2_EL1 S3_0_C15_C1_1
|
||||
|
||||
#define RAINIER_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
|
||||
#define RAINIER_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
|
||||
#define RAINIER_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11)
|
||||
#define RAINIER_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15)
|
||||
#define RAINIER_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16)
|
||||
#define RAINIER_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)
|
||||
|
||||
#define RAINIER_CPUACTLR3_EL1 S3_0_C15_C1_2
|
||||
|
||||
#define RAINIER_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10)
|
||||
|
||||
/* Instruction patching registers */
|
||||
#define CPUPSELR_EL3 S3_6_C15_C8_0
|
||||
#define CPUPCR_EL3 S3_6_C15_C8_1
|
||||
#define CPUPOR_EL3 S3_6_C15_C8_2
|
||||
#define CPUPMR_EL3 S3_6_C15_C8_3
|
||||
|
||||
#endif /* RAINIER_H */
|
||||
Reference in New Issue
Block a user