GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BOARD_CSS_DEF_H
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#define BOARD_CSS_DEF_H
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#include <lib/utils_def.h>
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#include <plat/arm/board/common/v2m_def.h>
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#include <plat/arm/soc/common/soc_css_def.h>
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#include <plat/common/common_def.h>
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/*
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* Definitions common to all ARM CSS-based development platforms
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*/
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/* Platform ID address */
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#define BOARD_CSS_PLAT_ID_REG_ADDR 0x7ffe00e0
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/* Platform ID related accessors */
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#define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f
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#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0
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#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK 0xf00
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#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT 0x8
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#define BOARD_CSS_PLAT_TYPE_RTL 0x00
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#define BOARD_CSS_PLAT_TYPE_FPGA 0x01
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#define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02
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#define BOARD_CSS_PLAT_TYPE_FVP 0x03
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#ifndef __ASSEMBLER__
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#include <lib/mmio.h>
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#define BOARD_CSS_GET_PLAT_TYPE(addr) \
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((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
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>> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
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#endif /* __ASSEMBLER__ */
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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/* Reserve the last block of flash for PSCI MEM PROTECT flag */
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#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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#if ARM_GPT_SUPPORT
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/*
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* Offset of the FIP in the GPT image. BL1 component uses this option
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* as it does not load the partition table to get the FIP base
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* address. At sector 34 by default (i.e. after reserved sectors 0-33)
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* Offset = 34 * 512(sector size) = 17408 i.e. 0x4400
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*/
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#define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400
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#endif /* ARM_GPT_SUPPORT */
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#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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/* UART related constants */
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#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE
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#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ
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#define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE
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#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
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#define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE
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#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
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#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
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#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
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#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE
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#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
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#endif /* BOARD_CSS_DEF_H */
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/*
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef V2M_DEF_H
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#define V2M_DEF_H
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#include <lib/utils_def.h>
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/* Base address of all V2M */
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#ifdef PLAT_V2M_OFFSET
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#define V2M_OFFSET PLAT_V2M_OFFSET
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#else
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#define V2M_OFFSET UL(0)
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#endif
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/* V2M motherboard system registers & offsets */
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#define V2M_SYSREGS_BASE UL(0x1c010000)
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#define V2M_SYS_ID UL(0x0)
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#define V2M_SYS_SWITCH UL(0x4)
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#define V2M_SYS_LED UL(0x8)
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#define V2M_SYS_NVFLAGS UL(0x38)
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#define V2M_SYS_NVFLAGSSET UL(0x38)
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#define V2M_SYS_NVFLAGSCLR UL(0x3c)
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#define V2M_SYS_CFGDATA UL(0xa0)
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#define V2M_SYS_CFGCTRL UL(0xa4)
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#define V2M_SYS_CFGSTATUS UL(0xa8)
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#define V2M_CFGCTRL_START BIT_32(31)
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#define V2M_CFGCTRL_RW BIT_32(30)
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#define V2M_CFGCTRL_FUNC_SHIFT 20
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#define V2M_CFGCTRL_FUNC(fn) ((fn) << V2M_CFGCTRL_FUNC_SHIFT)
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#define V2M_FUNC_CLK_GEN U(0x01)
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#define V2M_FUNC_TEMP U(0x04)
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#define V2M_FUNC_DB_RESET U(0x05)
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#define V2M_FUNC_SCC_CFG U(0x06)
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#define V2M_FUNC_SHUTDOWN U(0x08)
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#define V2M_FUNC_REBOOT U(0x09)
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/* NVFLAGS in the V2M motherboard which is preserved after a watchdog reset */
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#define V2M_SYS_NVFLAGS_ADDR (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS)
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/*
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* V2M sysled bit definitions. The values written to this
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* register are defined in arch.h & runtime_svc.h. Only
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* used by the primary cpu to diagnose any cold boot issues.
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*
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* SYS_LED[0] - Security state (S=0/NS=1)
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* SYS_LED[2:1] - Exception Level (EL3-EL0)
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* SYS_LED[7:3] - Exception Class (Sync/Async & origin)
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*
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*/
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#define V2M_SYS_LED_SS_SHIFT 0x0
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#define V2M_SYS_LED_EL_SHIFT 0x1
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#define V2M_SYS_LED_EC_SHIFT 0x3
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#define V2M_SYS_LED_SS_MASK U(0x1)
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#define V2M_SYS_LED_EL_MASK U(0x3)
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#define V2M_SYS_LED_EC_MASK U(0x1f)
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/* V2M sysid register bits */
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#define V2M_SYS_ID_REV_SHIFT 28
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#define V2M_SYS_ID_HBI_SHIFT 16
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#define V2M_SYS_ID_BLD_SHIFT 12
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#define V2M_SYS_ID_ARCH_SHIFT 8
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#define V2M_SYS_ID_FPGA_SHIFT 0
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#define V2M_SYS_ID_REV_MASK U(0xf)
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#define V2M_SYS_ID_HBI_MASK U(0xfff)
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#define V2M_SYS_ID_BLD_MASK U(0xf)
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#define V2M_SYS_ID_ARCH_MASK U(0xf)
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#define V2M_SYS_ID_FPGA_MASK U(0xff)
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#define V2M_SYS_ID_BLD_LENGTH 4
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/* NOR Flash */
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#define V2M_FLASH0_BASE (V2M_OFFSET + UL(0x08000000))
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#define V2M_FLASH0_SIZE UL(0x04000000)
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#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */
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#define V2M_IOFPGA_BASE (V2M_OFFSET + UL(0x1c000000))
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#define V2M_IOFPGA_SIZE UL(0x03000000)
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/* PL011 UART related constants */
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#define V2M_IOFPGA_UART0_BASE (V2M_OFFSET + UL(0x1c090000))
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#define V2M_IOFPGA_UART1_BASE (V2M_OFFSET + UL(0x1c0a0000))
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#define V2M_IOFPGA_UART2_BASE (V2M_OFFSET + UL(0x1c0b0000))
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#define V2M_IOFPGA_UART3_BASE (V2M_OFFSET + UL(0x1c0c0000))
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#define V2M_IOFPGA_UART0_CLK_IN_HZ 24000000
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#define V2M_IOFPGA_UART1_CLK_IN_HZ 24000000
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#define V2M_IOFPGA_UART2_CLK_IN_HZ 24000000
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#define V2M_IOFPGA_UART3_CLK_IN_HZ 24000000
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/* SP804 timer related constants */
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#define V2M_SP804_TIMER0_BASE (V2M_OFFSET + UL(0x1C110000))
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#define V2M_SP804_TIMER1_BASE (V2M_OFFSET + UL(0x1C120000))
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/* SP810 controller */
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#define V2M_SP810_BASE (V2M_OFFSET + UL(0x1c020000))
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#define V2M_SP810_CTRL_TIM0_SEL BIT_32(15)
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#define V2M_SP810_CTRL_TIM1_SEL BIT_32(17)
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#define V2M_SP810_CTRL_TIM2_SEL BIT_32(19)
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#define V2M_SP810_CTRL_TIM3_SEL BIT_32(21)
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/*
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* The flash can be mapped either as read-only or read-write.
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*
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* If it is read-write then it should also be mapped as device memory because
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* NOR flash programming involves sending a fixed, ordered sequence of commands.
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*
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* If it is read-only then it should also be mapped as:
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* - Normal memory, because reading from NOR flash is transparent, it is like
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* reading from RAM.
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* - Non-executable by default. If some parts of the flash need to be executable
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* then platform code is responsible for re-mapping the appropriate portion
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* of it as executable.
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*/
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#define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\
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V2M_FLASH0_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
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V2M_FLASH0_SIZE, \
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MT_RO_DATA | MT_SECURE)
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#define V2M_MAP_IOFPGA MAP_REGION_FLAT(V2M_IOFPGA_BASE,\
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V2M_IOFPGA_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/* Region equivalent to V2M_MAP_IOFPGA suitable for mapping at EL0 */
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#define V2M_MAP_IOFPGA_EL0 MAP_REGION_FLAT( \
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V2M_IOFPGA_BASE, \
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V2M_IOFPGA_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
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#endif /* V2M_DEF_H */
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