GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef ARMADA_COMMON_H
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#define ARMADA_COMMON_H
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#include <stdint.h>
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#include <io_addr_dec.h>
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int marvell_get_io_dec_win_conf(struct dec_win_config **win, uint32_t *size);
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#endif /* ARMADA_COMMON_H */
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+74
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef BOARD_MARVELL_DEF_H
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#define BOARD_MARVELL_DEF_H
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/*
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* Required platform porting definitions common to all ARM
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* development platforms
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*/
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/* Size of cacheable stacks */
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#if IMAGE_BL1
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#if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE 0x1000
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#else
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# define PLATFORM_STACK_SIZE 0x440
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#endif
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#elif IMAGE_BL2
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# if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE 0x1000
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# else
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# define PLATFORM_STACK_SIZE 0x400
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# endif
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#elif IMAGE_BL31
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# define PLATFORM_STACK_SIZE 0x400
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#elif IMAGE_BL32
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# define PLATFORM_STACK_SIZE 0x440
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#endif
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/*
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* PLAT_MARVELL_MMAP_ENTRIES depends on the number of entries in the
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* plat_arm_mmap array defined for each BL stage.
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*/
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#if IMAGE_BLE
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# define PLAT_MARVELL_MMAP_ENTRIES 3
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#endif
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#if IMAGE_BL1
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# if TRUSTED_BOARD_BOOT
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# define PLAT_MARVELL_MMAP_ENTRIES 7
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# else
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# define PLAT_MARVELL_MMAP_ENTRIES 6
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# endif /* TRUSTED_BOARD_BOOT */
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#endif
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#if IMAGE_BL2
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# define PLAT_MARVELL_MMAP_ENTRIES 8
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#endif
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#if IMAGE_BL31
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#define PLAT_MARVELL_MMAP_ENTRIES 5
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#endif
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/*
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* Platform specific page table and MMU setup constants
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*/
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#if IMAGE_BL1
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#define MAX_XLAT_TABLES 4
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#elif IMAGE_BLE
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# define MAX_XLAT_TABLES 4
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#elif IMAGE_BL2
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# define MAX_XLAT_TABLES 4
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#elif IMAGE_BL31
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# define MAX_XLAT_TABLES 4
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#elif IMAGE_BL32
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# define MAX_XLAT_TABLES 4
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#endif
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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#endif /* BOARD_MARVELL_DEF_H */
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+188
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef MARVELL_DEF_H
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#define MARVELL_DEF_H
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#include <platform_def.h>
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#include <arch.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/common_def.h>
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/****************************************************************************
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* Definitions common to all MARVELL standard platforms
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****************************************************************************
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*/
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/* Special value used to verify platform parameters from BL2 to BL31 */
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#define MARVELL_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define PLAT_MARVELL_NORTHB_COUNT 1
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#define PLAT_MARVELL_CLUSTER_COUNT 1
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#define MARVELL_CACHE_WRITEBACK_SHIFT 6
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/*
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* Macros mapping the MPIDR Affinity levels to MARVELL Platform Power levels.
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* The power levels have a 1:1 mapping with the MPIDR affinity levels.
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*/
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#define MARVELL_PWR_LVL0 MPIDR_AFFLVL0
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#define MARVELL_PWR_LVL1 MPIDR_AFFLVL1
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#define MARVELL_PWR_LVL2 MPIDR_AFFLVL2
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/*
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* Macros for local power states in Marvell platforms encoded by State-ID field
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* within the power-state parameter.
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*/
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/* Local power state for power domains in Run state. */
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#define MARVELL_LOCAL_STATE_RUN 0
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/* Local power state for retention. Valid only for CPU power domains */
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#define MARVELL_LOCAL_STATE_RET 1
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/* Local power state for OFF/power-down.
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* Valid for CPU and cluster power domains
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*/
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#define MARVELL_LOCAL_STATE_OFF 2
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/* This leaves a gap between end of DRAM and start of ROM block */
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#define MARVELL_TRUSTED_DRAM_SIZE 0x80000 /* 512 KB */
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/* The first 4KB of Trusted SRAM are used as shared memory */
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#define MARVELL_SHARED_RAM_BASE PLAT_MARVELL_ATF_BASE
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#define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
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/* The remaining Trusted SRAM is used to load the BL images */
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#define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \
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MARVELL_SHARED_RAM_SIZE)
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#define MARVELL_BL_RAM_SIZE (MARVELL_TRUSTED_DRAM_SIZE - \
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MARVELL_SHARED_RAM_SIZE)
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#define MARVELL_DRAM_BASE ULL(0x0)
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#define MARVELL_DRAM_SIZE ULL(0x20000000)
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#define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \
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MARVELL_DRAM_SIZE - 1)
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#define MARVELL_IRQ_SEC_PHY_TIMER 29
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#define MARVELL_IRQ_SEC_SGI_0 8
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#define MARVELL_IRQ_SEC_SGI_1 9
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#define MARVELL_IRQ_SEC_SGI_2 10
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#define MARVELL_IRQ_SEC_SGI_3 11
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#define MARVELL_IRQ_SEC_SGI_4 12
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#define MARVELL_IRQ_SEC_SGI_5 13
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#define MARVELL_IRQ_SEC_SGI_6 14
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#define MARVELL_IRQ_SEC_SGI_7 15
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#define MARVELL_MAP_SHARED_RAM MAP_REGION_FLAT( \
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MARVELL_SHARED_RAM_BASE, \
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MARVELL_SHARED_RAM_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define MARVELL_MAP_DRAM MAP_REGION_FLAT( \
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MARVELL_DRAM_BASE, \
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MARVELL_DRAM_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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/*
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* The number of regions like RO(code), coherent and data required by
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* different BL stages which need to be mapped in the MMU.
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*/
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#if USE_COHERENT_MEM
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#define MARVELL_BL_REGIONS 3
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#else
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#define MARVELL_BL_REGIONS 2
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#endif
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#define MAX_MMAP_REGIONS (PLAT_MARVELL_MMAP_ENTRIES + \
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MARVELL_BL_REGIONS)
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#define MARVELL_CONSOLE_BAUDRATE 115200
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/****************************************************************************
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* Required platform porting definitions common to all MARVELL std. platforms
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****************************************************************************
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*/
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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/*
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* This macro defines the deepest retention state possible. A higher state
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* id will represent an invalid or a power down state.
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*/
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#define PLAT_MAX_RET_STATE MARVELL_LOCAL_STATE_RET
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/*
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* This macro defines the deepest power down states possible. Any state ID
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* higher than this is invalid.
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*/
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#define PLAT_MAX_OFF_STATE MARVELL_LOCAL_STATE_OFF
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#define PLATFORM_CORE_COUNT PLAT_MARVELL_CLUSTER_CORE_COUNT
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_GRANULE (1 << MARVELL_CACHE_WRITEBACK_SHIFT)
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/*****************************************************************************
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* BL1 specific defines.
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* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
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* addresses.
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*****************************************************************************
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*/
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#define BL1_RO_BASE PLAT_MARVELL_TRUSTED_ROM_BASE
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#define BL1_RO_LIMIT (PLAT_MARVELL_TRUSTED_ROM_BASE \
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+ PLAT_MARVELL_TRUSTED_ROM_SIZE)
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/*
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* Put BL1 RW at the top of the Trusted SRAM.
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*/
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#define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \
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MARVELL_BL_RAM_SIZE - \
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PLAT_MARVELL_MAX_BL1_RW_SIZE)
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#define BL1_RW_LIMIT (MARVELL_BL_RAM_BASE + MARVELL_BL_RAM_SIZE)
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/*****************************************************************************
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* BL2 specific defines.
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*****************************************************************************
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*/
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/*
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* Put BL2 just below BL31.
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*/
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#define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE)
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#define BL2_LIMIT BL31_BASE
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/*****************************************************************************
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* BL31 specific defines.
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*****************************************************************************
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*/
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/*
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* Put BL31 at the top of the Trusted SRAM.
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*/
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#define BL31_BASE (MARVELL_BL_RAM_BASE + \
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MARVELL_BL_RAM_SIZE - \
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PLAT_MARVEL_MAX_BL31_SIZE)
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#define BL31_PROGBITS_LIMIT BL1_RW_BASE
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#define BL31_LIMIT (MARVELL_BL_RAM_BASE + \
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MARVELL_BL_RAM_SIZE)
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/*****************************************************************************
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* BL32 specific defines.
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*****************************************************************************
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*/
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#define BL32_BASE PLAT_MARVELL_TRUSTED_RAM_BASE
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#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_RAM_SIZE)
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#ifdef SPD_none
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#undef BL32_BASE
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#endif /* SPD_none */
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#endif /* MARVELL_DEF_H */
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+105
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/*
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* Copyright (C) 2016 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef PLAT_MARVELL_H
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#define PLAT_MARVELL_H
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#include <stdint.h>
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#include <common/bl_common.h>
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#include <lib/cassert.h>
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#include <lib/el3_runtime/cpu_data.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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/*
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* Extern declarations common to Marvell standard platforms
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*/
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extern const mmap_region_t plat_marvell_mmap[];
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#define MARVELL_CASSERT_MMAP \
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CASSERT((ARRAY_SIZE(plat_marvell_mmap) + MARVELL_BL_REGIONS) \
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<= MAX_MMAP_REGIONS, \
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assert_max_mmap_regions)
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/*
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* Utility functions common to Marvell standard platforms
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*/
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void marvell_setup_page_tables(uintptr_t total_base,
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size_t total_size,
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uintptr_t code_start,
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uintptr_t code_limit,
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uintptr_t rodata_start,
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uintptr_t rodata_limit
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#if USE_COHERENT_MEM
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, uintptr_t coh_start,
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uintptr_t coh_limit
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#endif
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);
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/* Console utility functions */
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void marvell_console_boot_init(void);
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void marvell_console_boot_end(void);
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void marvell_console_runtime_init(void);
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void marvell_console_runtime_end(void);
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/* IO storage utility functions */
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void marvell_io_setup(void);
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/* Systimer utility function */
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void marvell_configure_sys_timer(void);
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/* Topology utility function */
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int marvell_check_mpidr(u_register_t mpidr);
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/* BL1 utility functions */
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void marvell_bl1_early_platform_setup(void);
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void marvell_bl1_platform_setup(void);
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void marvell_bl1_plat_arch_setup(void);
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/* BL2 utility functions */
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void marvell_bl2_early_platform_setup(meminfo_t *mem_layout);
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void marvell_bl2_platform_setup(void);
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void marvell_bl2_plat_arch_setup(void);
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uint32_t marvell_get_spsr_for_bl32_entry(void);
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uint32_t marvell_get_spsr_for_bl33_entry(void);
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/* BL31 utility functions */
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void marvell_bl31_early_platform_setup(void *from_bl2,
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uintptr_t soc_fw_config,
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uintptr_t hw_config,
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void *plat_params_from_bl2);
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void marvell_bl31_platform_setup(void);
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void marvell_bl31_plat_runtime_setup(void);
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void marvell_bl31_plat_arch_setup(void);
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/* FIP TOC validity check */
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int marvell_io_is_toc_valid(void);
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/*
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* PSCI functionality
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*/
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void marvell_psci_arch_init(int idx);
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void plat_marvell_system_reset(void);
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/*
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* Optional functions required in Marvell standard platforms
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*/
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void plat_marvell_io_setup(void);
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int plat_marvell_get_alt_image_source(
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unsigned int image_id,
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uintptr_t *dev_handle,
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uintptr_t *image_spec);
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unsigned int plat_marvell_calc_core_pos(u_register_t mpidr);
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void plat_marvell_interconnect_init(void);
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void plat_marvell_interconnect_enter_coherency(void);
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const mmap_region_t *plat_marvell_get_mmap(void);
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uint32_t get_ref_clk(void);
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#endif /* PLAT_MARVELL_H */
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+129
@@ -0,0 +1,129 @@
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/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef ARMADA_COMMON_H
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#define ARMADA_COMMON_H
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#include <drivers/marvell/amb_adec.h>
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#include <drivers/marvell/ccu.h>
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#include <drivers/marvell/io_win.h>
|
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#include <drivers/marvell/iob.h>
|
||||
|
||||
/*
|
||||
* This struct supports skip image request
|
||||
* detection_method: the method used to detect the request "signal".
|
||||
* info:
|
||||
* GPIO:
|
||||
* detection_method: HIGH (pressed button), LOW (unpressed button),
|
||||
* num (button mpp number).
|
||||
* i2c:
|
||||
* i2c_addr: the address of the i2c chosen.
|
||||
* i2d_reg: the i2c register chosen.
|
||||
* test:
|
||||
* choose the DIE you picked the button in (AP or CP).
|
||||
* in case of CP(cp_index = 0 if CP0, cp_index = 1 if CP1)
|
||||
*/
|
||||
struct skip_image {
|
||||
enum {
|
||||
GPIO,
|
||||
I2C,
|
||||
USER_DEFINED
|
||||
} detection_method;
|
||||
|
||||
struct {
|
||||
struct {
|
||||
int num;
|
||||
enum {
|
||||
HIGH,
|
||||
LOW
|
||||
} button_state;
|
||||
|
||||
} gpio;
|
||||
|
||||
struct {
|
||||
int i2c_addr;
|
||||
int i2c_reg;
|
||||
} i2c;
|
||||
|
||||
struct {
|
||||
enum {
|
||||
CP,
|
||||
AP
|
||||
} cp_ap;
|
||||
int cp_index;
|
||||
} test;
|
||||
} info;
|
||||
};
|
||||
|
||||
/*
|
||||
* This struct supports SoC power off method
|
||||
* type: the method used to power off the SoC
|
||||
* cfg:
|
||||
* PMIC_GPIO:
|
||||
* pin_count: current GPIO pin number used for toggling the signal for
|
||||
* notifying external PMIC
|
||||
* info: holds the GPIOs information, CP GPIO should be used and
|
||||
* all GPIOs should be within same GPIO config. register
|
||||
* step_count: current step number to toggle the GPIO for PMIC
|
||||
* seq: GPIO toggling values in sequence, each bit represents a GPIO.
|
||||
* For example, bit0 represents first GPIO used for toggling
|
||||
* the GPIO the last step is used to trigger the power off
|
||||
* signal
|
||||
* delay_ms: transition interval for the GPIO setting to take effect
|
||||
* in unit of ms
|
||||
*/
|
||||
/* Max GPIO number used to notify PMIC to power off the SoC */
|
||||
#define PMIC_GPIO_MAX_NUMBER 8
|
||||
/* Max GPIO toggling steps in sequence to power off the SoC */
|
||||
#define PMIC_GPIO_MAX_TOGGLE_STEP 8
|
||||
|
||||
enum gpio_output_state {
|
||||
GPIO_LOW = 0,
|
||||
GPIO_HIGH
|
||||
};
|
||||
|
||||
typedef struct gpio_info {
|
||||
int cp_index;
|
||||
int gpio_index;
|
||||
} gpio_info_t;
|
||||
|
||||
struct power_off_method {
|
||||
enum {
|
||||
PMIC_GPIO,
|
||||
} type;
|
||||
|
||||
struct {
|
||||
struct {
|
||||
int pin_count;
|
||||
struct gpio_info info[PMIC_GPIO_MAX_NUMBER];
|
||||
int step_count;
|
||||
uint32_t seq[PMIC_GPIO_MAX_TOGGLE_STEP];
|
||||
int delay_ms;
|
||||
} gpio;
|
||||
} cfg;
|
||||
};
|
||||
|
||||
int marvell_gpio_config(void);
|
||||
uint32_t marvell_get_io_win_gcr_target(int ap_idx);
|
||||
uint32_t marvell_get_ccu_gcr_target(int ap_idx);
|
||||
|
||||
|
||||
/*
|
||||
* The functions below are defined as Weak and may be overridden
|
||||
* in specific Marvell standard platform
|
||||
*/
|
||||
int marvell_get_amb_memory_map(struct addr_map_win **win,
|
||||
uint32_t *size, uintptr_t base);
|
||||
int marvell_get_io_win_memory_map(int ap_idx, struct addr_map_win **win,
|
||||
uint32_t *size);
|
||||
int marvell_get_iob_memory_map(struct addr_map_win **win,
|
||||
uint32_t *size, uintptr_t base);
|
||||
int marvell_get_ccu_memory_map(int ap_idx, struct addr_map_win **win,
|
||||
uint32_t *size);
|
||||
int system_power_off(void);
|
||||
|
||||
#endif /* ARMADA_COMMON_H */
|
||||
+74
@@ -0,0 +1,74 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef BOARD_MARVELL_DEF_H
|
||||
#define BOARD_MARVELL_DEF_H
|
||||
|
||||
/*
|
||||
* Required platform porting definitions common to all ARM
|
||||
* development platforms
|
||||
*/
|
||||
|
||||
/* Size of cacheable stacks */
|
||||
#if IMAGE_BL1
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
# define PLATFORM_STACK_SIZE 0x1000
|
||||
#else
|
||||
# define PLATFORM_STACK_SIZE 0x440
|
||||
#endif
|
||||
#elif IMAGE_BL2
|
||||
# if TRUSTED_BOARD_BOOT
|
||||
# define PLATFORM_STACK_SIZE 0x1000
|
||||
# else
|
||||
# define PLATFORM_STACK_SIZE 0x400
|
||||
# endif
|
||||
#elif IMAGE_BL31
|
||||
# define PLATFORM_STACK_SIZE 0x400
|
||||
#elif IMAGE_BL32
|
||||
# define PLATFORM_STACK_SIZE 0x440
|
||||
#endif
|
||||
|
||||
/*
|
||||
* PLAT_MARVELL_MMAP_ENTRIES depends on the number of entries in the
|
||||
* plat_arm_mmap array defined for each BL stage.
|
||||
*/
|
||||
#if IMAGE_BLE
|
||||
# define PLAT_MARVELL_MMAP_ENTRIES 3
|
||||
#endif
|
||||
#if IMAGE_BL1
|
||||
# if TRUSTED_BOARD_BOOT
|
||||
# define PLAT_MARVELL_MMAP_ENTRIES 7
|
||||
# else
|
||||
# define PLAT_MARVELL_MMAP_ENTRIES 6
|
||||
# endif /* TRUSTED_BOARD_BOOT */
|
||||
#endif
|
||||
#if IMAGE_BL2
|
||||
# define PLAT_MARVELL_MMAP_ENTRIES 8
|
||||
#endif
|
||||
#if IMAGE_BL31
|
||||
#define PLAT_MARVELL_MMAP_ENTRIES 5
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Platform specific page table and MMU setup constants
|
||||
*/
|
||||
#if IMAGE_BL1
|
||||
#define MAX_XLAT_TABLES 4
|
||||
#elif IMAGE_BLE
|
||||
# define MAX_XLAT_TABLES 4
|
||||
#elif IMAGE_BL2
|
||||
# define MAX_XLAT_TABLES 4
|
||||
#elif IMAGE_BL31
|
||||
# define MAX_XLAT_TABLES 4
|
||||
#elif IMAGE_BL32
|
||||
# define MAX_XLAT_TABLES 4
|
||||
#endif
|
||||
|
||||
#define MAX_IO_DEVICES 3
|
||||
#define MAX_IO_HANDLES 4
|
||||
|
||||
#endif /* BOARD_MARVELL_DEF_H */
|
||||
+33
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (C) 2021 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef EFUSE_DEF_H
|
||||
#define EFUSE_DEF_H
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#define MVEBU_AP_EFUSE_SRV_CTRL_REG (MVEBU_AP_GEN_MGMT_BASE + 0x8)
|
||||
#define EFUSE_SRV_CTRL_LD_SELECT_OFFS 6
|
||||
#define EFUSE_SRV_CTRL_LD_SELECT_MASK (1 << EFUSE_SRV_CTRL_LD_SELECT_OFFS)
|
||||
|
||||
#define MVEBU_AP_LD_EFUSE_BASE (MVEBU_AP_GEN_MGMT_BASE + 0xF00)
|
||||
/* Bits [31:0] - 32 data bits total */
|
||||
#define MVEBU_AP_LDX_31_0_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE)
|
||||
/* Bits [62:32] - 31 data bits total 32nd bit is parity for bits [62:0]*/
|
||||
#define MVEBU_AP_LDX_62_32_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x4)
|
||||
/* Bits [94:63] - 32 data bits total */
|
||||
#define MVEBU_AP_LDX_94_63_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x8)
|
||||
/* Bits [125:95] - 31 data bits total, 32nd bit is parity for bits [125:63] */
|
||||
#define MVEBU_AP_LDX_125_95_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0xC)
|
||||
/* Bits [157:126] - 32 data bits total */
|
||||
#define MVEBU_AP_LDX_126_157_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x10)
|
||||
/* Bits [188:158] - 31 data bits total, 32nd bit is parity for bits [188:126] */
|
||||
#define MVEBU_AP_LDX_188_158_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x14)
|
||||
/* Bits [220:189] - 32 data bits total */
|
||||
#define MVEBU_AP_LDX_220_189_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x18)
|
||||
|
||||
#endif /* EFUSE_DEF_H */
|
||||
+222
@@ -0,0 +1,222 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef MARVELL_DEF_H
|
||||
#define MARVELL_DEF_H
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <arch.h>
|
||||
#include <common/tbbr/tbbr_img_def.h>
|
||||
#include <lib/xlat_tables/xlat_tables_v2.h>
|
||||
#include <plat/common/common_def.h>
|
||||
|
||||
/******************************************************************************
|
||||
* Definitions common to all MARVELL standard platforms
|
||||
*****************************************************************************/
|
||||
|
||||
/* Special value used to verify platform parameters from BL2 to BL31 */
|
||||
#define MARVELL_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
|
||||
|
||||
|
||||
#define MARVELL_CACHE_WRITEBACK_SHIFT 6
|
||||
|
||||
/*
|
||||
* Macros mapping the MPIDR Affinity levels to MARVELL Platform Power levels.
|
||||
* The power levels have a 1:1 mapping with the MPIDR affinity levels.
|
||||
*/
|
||||
#define MARVELL_PWR_LVL0 MPIDR_AFFLVL0
|
||||
#define MARVELL_PWR_LVL1 MPIDR_AFFLVL1
|
||||
#define MARVELL_PWR_LVL2 MPIDR_AFFLVL2
|
||||
|
||||
/*
|
||||
* Macros for local power states in Marvell platforms encoded by
|
||||
* State-ID field within the power-state parameter.
|
||||
*/
|
||||
/* Local power state for power domains in Run state. */
|
||||
#define MARVELL_LOCAL_STATE_RUN 0
|
||||
/* Local power state for retention. Valid only for CPU power domains */
|
||||
#define MARVELL_LOCAL_STATE_RET 1
|
||||
/*
|
||||
* Local power state for OFF/power-down. Valid for CPU
|
||||
* and cluster power domains
|
||||
*/
|
||||
#define MARVELL_LOCAL_STATE_OFF 2
|
||||
|
||||
/* This leaves a gap between end of DRAM and start of ROM block */
|
||||
#define MARVELL_TRUSTED_DRAM_SIZE 0x80000 /* 512 KB */
|
||||
|
||||
/* The first 4KB of Trusted SRAM are used as shared memory */
|
||||
#define MARVELL_SHARED_RAM_BASE PLAT_MARVELL_ATF_BASE
|
||||
#define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
|
||||
|
||||
/* The remaining Trusted SRAM is used to load the BL images */
|
||||
#define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \
|
||||
MARVELL_SHARED_RAM_SIZE)
|
||||
#define MARVELL_BL_RAM_SIZE (MARVELL_TRUSTED_DRAM_SIZE - \
|
||||
MARVELL_SHARED_RAM_SIZE)
|
||||
/* Non-shared DRAM */
|
||||
#define MARVELL_DRAM_BASE ULL(0x0)
|
||||
#define MARVELL_DRAM_SIZE ULL(0x80000000)
|
||||
#define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \
|
||||
MARVELL_DRAM_SIZE - 1)
|
||||
|
||||
#define MARVELL_IRQ_PIC0 28
|
||||
#define MARVELL_IRQ_SEC_PHY_TIMER 29
|
||||
|
||||
#define MARVELL_IRQ_SEC_SGI_0 8
|
||||
#define MARVELL_IRQ_SEC_SGI_1 9
|
||||
#define MARVELL_IRQ_SEC_SGI_2 10
|
||||
#define MARVELL_IRQ_SEC_SGI_3 11
|
||||
#define MARVELL_IRQ_SEC_SGI_4 12
|
||||
#define MARVELL_IRQ_SEC_SGI_5 13
|
||||
#define MARVELL_IRQ_SEC_SGI_6 14
|
||||
#define MARVELL_IRQ_SEC_SGI_7 15
|
||||
|
||||
#ifdef SPD_opteed
|
||||
/*
|
||||
* BL2 needs to map 4MB at the end of TZC_DRAM1 in order to
|
||||
* load/authenticate the trusted os extra image. The first 512KB of
|
||||
* TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading
|
||||
* for OPTEE is paged image which only include the paging part using
|
||||
* virtual memory but without "init" data. OPTEE will copy the "init" data
|
||||
* (from pager image) to the first 512KB of TZC_DRAM, and then copy the
|
||||
* extra image behind the "init" data.
|
||||
*/
|
||||
#define MARVELL_OPTEE_PAGEABLE_LOAD_BASE \
|
||||
(PLAT_MARVELL_TRUSTED_RAM_BASE + \
|
||||
PLAT_MARVELL_TRUSTED_RAM_SIZE - \
|
||||
MARVELL_OPTEE_PAGEABLE_LOAD_SIZE)
|
||||
#define MARVELL_OPTEE_PAGEABLE_LOAD_SIZE 0x400000
|
||||
#define MARVELL_OPTEE_PAGEABLE_LOAD_MEM \
|
||||
MAP_REGION_FLAT( \
|
||||
MARVELL_OPTEE_PAGEABLE_LOAD_BASE, \
|
||||
MARVELL_OPTEE_PAGEABLE_LOAD_SIZE, \
|
||||
MT_MEMORY | MT_RW | MT_SECURE)
|
||||
|
||||
/*
|
||||
* Map the memory for the OP-TEE core (also known as OP-TEE pager when paging
|
||||
* support is enabled).
|
||||
*/
|
||||
#define MARVELL_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \
|
||||
BL32_BASE, \
|
||||
BL32_LIMIT - BL32_BASE, \
|
||||
MT_MEMORY | MT_RW | MT_SECURE)
|
||||
#endif /* SPD_opteed */
|
||||
|
||||
#define MARVELL_MAP_SECURE_RAM MAP_REGION_FLAT( \
|
||||
MARVELL_SHARED_RAM_BASE, \
|
||||
MARVELL_SHARED_RAM_SIZE, \
|
||||
MT_MEMORY | MT_RW | MT_SECURE)
|
||||
|
||||
#define MARVELL_MAP_DRAM MAP_REGION_FLAT( \
|
||||
MARVELL_DRAM_BASE, \
|
||||
MARVELL_DRAM_SIZE, \
|
||||
MT_MEMORY | MT_RW | MT_NS)
|
||||
|
||||
/*
|
||||
* The number of regions like RO(code), coherent and data required by
|
||||
* different BL stages which need to be mapped in the MMU.
|
||||
*/
|
||||
#if USE_COHERENT_MEM
|
||||
#define MARVELL_BL_REGIONS 3
|
||||
#else
|
||||
#define MARVELL_BL_REGIONS 2
|
||||
#endif
|
||||
|
||||
#define MAX_MMAP_REGIONS (PLAT_MARVELL_MMAP_ENTRIES + \
|
||||
MARVELL_BL_REGIONS)
|
||||
|
||||
#define MARVELL_CONSOLE_BAUDRATE 115200
|
||||
|
||||
/******************************************************************************
|
||||
* Required platform porting definitions common to all MARVELL std. platforms
|
||||
*****************************************************************************/
|
||||
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
|
||||
/*
|
||||
* This macro defines the deepest retention state possible. A higher state
|
||||
* id will represent an invalid or a power down state.
|
||||
*/
|
||||
#define PLAT_MAX_RET_STATE MARVELL_LOCAL_STATE_RET
|
||||
|
||||
/*
|
||||
* This macro defines the deepest power down states possible. Any state ID
|
||||
* higher than this is invalid.
|
||||
*/
|
||||
#define PLAT_MAX_OFF_STATE MARVELL_LOCAL_STATE_OFF
|
||||
|
||||
|
||||
#define PLATFORM_CORE_COUNT PLAT_MARVELL_CORE_COUNT
|
||||
#define PLAT_NUM_PWR_DOMAINS (PLAT_MARVELL_CLUSTER_COUNT + \
|
||||
PLATFORM_CORE_COUNT)
|
||||
|
||||
/*
|
||||
* Some data must be aligned on the biggest cache line size in the platform.
|
||||
* This is known only to the platform as it might have a combination of
|
||||
* integrated and external caches.
|
||||
*/
|
||||
#define CACHE_WRITEBACK_GRANULE (1 << MARVELL_CACHE_WRITEBACK_SHIFT)
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* BL1 specific defines.
|
||||
* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
|
||||
* addresses.
|
||||
******************************************************************************/
|
||||
#define BL1_RO_BASE PLAT_MARVELL_TRUSTED_ROM_BASE
|
||||
#define BL1_RO_LIMIT (PLAT_MARVELL_TRUSTED_ROM_BASE \
|
||||
+ PLAT_MARVELL_TRUSTED_ROM_SIZE)
|
||||
/*
|
||||
* Put BL1 RW at the top of the Trusted SRAM.
|
||||
*/
|
||||
#define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \
|
||||
MARVELL_BL_RAM_SIZE - \
|
||||
PLAT_MARVELL_MAX_BL1_RW_SIZE)
|
||||
#define BL1_RW_LIMIT (MARVELL_BL_RAM_BASE + MARVELL_BL_RAM_SIZE)
|
||||
|
||||
/*******************************************************************************
|
||||
* BLE specific defines.
|
||||
******************************************************************************/
|
||||
#define BLE_BASE PLAT_MARVELL_SRAM_BASE
|
||||
#define BLE_LIMIT PLAT_MARVELL_SRAM_END
|
||||
|
||||
/*******************************************************************************
|
||||
* BL2 specific defines.
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Put BL2 just below BL31.
|
||||
*/
|
||||
#define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE)
|
||||
#define BL2_LIMIT BL31_BASE
|
||||
|
||||
/*******************************************************************************
|
||||
* BL31 specific defines.
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Put BL31 at the top of the Trusted SRAM.
|
||||
*/
|
||||
#define BL31_BASE (MARVELL_BL_RAM_BASE + \
|
||||
MARVELL_BL_RAM_SIZE - \
|
||||
PLAT_MARVEL_MAX_BL31_SIZE)
|
||||
#define BL31_PROGBITS_LIMIT BL1_RW_BASE
|
||||
#define BL31_LIMIT (MARVELL_BL_RAM_BASE + \
|
||||
MARVELL_BL_RAM_SIZE)
|
||||
|
||||
/*******************************************************************************
|
||||
* BL32 specific defines.
|
||||
******************************************************************************/
|
||||
#define BL32_BASE PLAT_MARVELL_TRUSTED_RAM_BASE
|
||||
#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_RAM_SIZE)
|
||||
|
||||
#ifdef SPD_none
|
||||
#undef BL32_BASE
|
||||
#endif /* SPD_none */
|
||||
|
||||
#endif /* MARVELL_DEF_H */
|
||||
+138
@@ -0,0 +1,138 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef PLAT_MARVELL_H
|
||||
#define PLAT_MARVELL_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <common/bl_common.h>
|
||||
#include <lib/cassert.h>
|
||||
#include <lib/el3_runtime/cpu_data.h>
|
||||
#include <lib/utils.h>
|
||||
#include <lib/xlat_tables/xlat_tables_v2.h>
|
||||
|
||||
/*
|
||||
* Extern declarations common to Marvell standard platforms
|
||||
*/
|
||||
extern const mmap_region_t plat_marvell_mmap[];
|
||||
|
||||
#define MARVELL_CASSERT_MMAP \
|
||||
CASSERT((ARRAY_SIZE(plat_marvell_mmap) + MARVELL_BL_REGIONS) \
|
||||
<= MAX_MMAP_REGIONS, \
|
||||
assert_max_mmap_regions)
|
||||
|
||||
struct marvell_bl31_params {
|
||||
param_header_t h;
|
||||
image_info_t *bl31_image_info;
|
||||
entry_point_info_t *bl32_ep_info;
|
||||
image_info_t *bl32_image_info;
|
||||
entry_point_info_t *bl33_ep_info;
|
||||
image_info_t *bl33_image_info;
|
||||
};
|
||||
|
||||
/*
|
||||
* Utility functions common to Marvell standard platforms
|
||||
*/
|
||||
void marvell_setup_page_tables(uintptr_t total_base,
|
||||
size_t total_size,
|
||||
uintptr_t code_start,
|
||||
uintptr_t code_limit,
|
||||
uintptr_t rodata_start,
|
||||
uintptr_t rodata_limit
|
||||
#if USE_COHERENT_MEM
|
||||
, uintptr_t coh_start,
|
||||
uintptr_t coh_limit
|
||||
#endif
|
||||
);
|
||||
|
||||
/* Console utility functions */
|
||||
void marvell_console_boot_init(void);
|
||||
void marvell_console_boot_end(void);
|
||||
void marvell_console_runtime_init(void);
|
||||
void marvell_console_runtime_end(void);
|
||||
|
||||
/* IO storage utility functions */
|
||||
void marvell_io_setup(void);
|
||||
|
||||
/* Systimer utility function */
|
||||
void marvell_configure_sys_timer(void);
|
||||
|
||||
/* Topology utility function */
|
||||
int marvell_check_mpidr(u_register_t mpidr);
|
||||
|
||||
/* BLE utility functions */
|
||||
int ble_plat_setup(int *skip);
|
||||
void plat_marvell_dram_update_topology(void);
|
||||
void ble_plat_pcie_ep_setup(void);
|
||||
struct pci_hw_cfg *plat_get_pcie_hw_data(void);
|
||||
|
||||
/* BL1 utility functions */
|
||||
void marvell_bl1_early_platform_setup(void);
|
||||
void marvell_bl1_platform_setup(void);
|
||||
void marvell_bl1_plat_arch_setup(void);
|
||||
|
||||
/* BL2 utility functions */
|
||||
void marvell_bl2_early_platform_setup(meminfo_t *mem_layout);
|
||||
void marvell_bl2_platform_setup(void);
|
||||
void marvell_bl2_plat_arch_setup(void);
|
||||
uint32_t marvell_get_spsr_for_bl32_entry(void);
|
||||
uint32_t marvell_get_spsr_for_bl33_entry(void);
|
||||
|
||||
/* BL31 utility functions */
|
||||
void marvell_bl31_early_platform_setup(void *from_bl2,
|
||||
uintptr_t soc_fw_config,
|
||||
uintptr_t hw_config,
|
||||
void *plat_params_from_bl2);
|
||||
void marvell_bl31_platform_setup(void);
|
||||
void marvell_bl31_plat_runtime_setup(void);
|
||||
void marvell_bl31_plat_arch_setup(void);
|
||||
|
||||
/* Power management config to power off the SoC */
|
||||
void *plat_marvell_get_pm_cfg(void);
|
||||
|
||||
/* Check if MSS AP CM3 firmware contains PM support */
|
||||
_Bool is_pm_fw_running(void);
|
||||
|
||||
/* Bootrom image recovery utility functions */
|
||||
void *plat_marvell_get_skip_image_data(void);
|
||||
|
||||
/* FIP TOC validity check */
|
||||
int marvell_io_is_toc_valid(void);
|
||||
|
||||
/*
|
||||
* PSCI functionality
|
||||
*/
|
||||
void marvell_psci_arch_init(int ap_idx);
|
||||
void plat_marvell_system_reset(void);
|
||||
|
||||
/*
|
||||
* Miscellaneous platform SMC routines
|
||||
*/
|
||||
#ifdef MVEBU_PMU_IRQ_WA
|
||||
void mvebu_pmu_interrupt_enable(void);
|
||||
void mvebu_pmu_interrupt_disable(void);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Optional functions required in Marvell standard platforms
|
||||
*/
|
||||
void plat_marvell_io_setup(void);
|
||||
int plat_marvell_get_alt_image_source(
|
||||
unsigned int image_id,
|
||||
uintptr_t *dev_handle,
|
||||
uintptr_t *image_spec);
|
||||
unsigned int plat_marvell_calc_core_pos(u_register_t mpidr);
|
||||
|
||||
const mmap_region_t *plat_marvell_get_mmap(void);
|
||||
void marvell_ble_prepare_exit(void);
|
||||
void marvell_exit_bootrom(uintptr_t base);
|
||||
|
||||
int plat_marvell_early_cpu_powerdown(void);
|
||||
int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info);
|
||||
|
||||
#endif /* PLAT_MARVELL_H */
|
||||
+99
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef PLAT_PM_TRACE_H
|
||||
#define PLAT_PM_TRACE_H
|
||||
|
||||
/*
|
||||
* PM Trace is for Debug purpose only!!!
|
||||
* It should not be enabled during System Run time
|
||||
*/
|
||||
#undef PM_TRACE_ENABLE
|
||||
|
||||
|
||||
/* trace entry time */
|
||||
struct pm_trace_entry {
|
||||
/* trace entry time stamp */
|
||||
unsigned int timestamp;
|
||||
|
||||
/* trace info
|
||||
* [16-31] - API Trace Id
|
||||
* [00-15] - API Step Id
|
||||
*/
|
||||
unsigned int trace_info;
|
||||
};
|
||||
|
||||
struct pm_trace_ctrl {
|
||||
/* trace pointer - points to next free entry in trace cyclic queue */
|
||||
unsigned int trace_pointer;
|
||||
|
||||
/* trace count - number of entries in the queue, clear upon read */
|
||||
unsigned int trace_count;
|
||||
};
|
||||
|
||||
/* trace size definition */
|
||||
#define AP_MSS_ATF_CORE_INFO_SIZE (256)
|
||||
#define AP_MSS_ATF_CORE_ENTRY_SIZE (8)
|
||||
#define AP_MSS_ATF_TRACE_SIZE_MASK (0xFF)
|
||||
|
||||
/* trace address definition */
|
||||
#define AP_MSS_TIMER_BASE (MVEBU_REGS_BASE_MASK + 0x580110)
|
||||
|
||||
#define AP_MSS_ATF_CORE_0_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x520140)
|
||||
#define AP_MSS_ATF_CORE_1_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x520150)
|
||||
#define AP_MSS_ATF_CORE_2_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x520160)
|
||||
#define AP_MSS_ATF_CORE_3_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x520170)
|
||||
#define AP_MSS_ATF_CORE_CTRL_BASE (AP_MSS_ATF_CORE_0_CTRL_BASE)
|
||||
|
||||
#define AP_MSS_ATF_CORE_0_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5201C0)
|
||||
#define AP_MSS_ATF_CORE_0_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5201C4)
|
||||
#define AP_MSS_ATF_CORE_1_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5209C0)
|
||||
#define AP_MSS_ATF_CORE_1_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5209C4)
|
||||
#define AP_MSS_ATF_CORE_2_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5211C0)
|
||||
#define AP_MSS_ATF_CORE_2_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5211C4)
|
||||
#define AP_MSS_ATF_CORE_3_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5219C0)
|
||||
#define AP_MSS_ATF_CORE_3_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5219C4)
|
||||
#define AP_MSS_ATF_CORE_INFO_BASE (AP_MSS_ATF_CORE_0_INFO_BASE)
|
||||
|
||||
/* trace info definition */
|
||||
#define TRACE_PWR_DOMAIN_OFF (0x10000)
|
||||
#define TRACE_PWR_DOMAIN_SUSPEND (0x20000)
|
||||
#define TRACE_PWR_DOMAIN_SUSPEND_FINISH (0x30000)
|
||||
#define TRACE_PWR_DOMAIN_ON (0x40000)
|
||||
#define TRACE_PWR_DOMAIN_ON_FINISH (0x50000)
|
||||
|
||||
#define TRACE_PWR_DOMAIN_ON_MASK (0xFF)
|
||||
|
||||
#ifdef PM_TRACE_ENABLE
|
||||
|
||||
/* trace API definition */
|
||||
void pm_core_0_trace(unsigned int trace);
|
||||
void pm_core_1_trace(unsigned int trace);
|
||||
void pm_core_2_trace(unsigned int trace);
|
||||
void pm_core_3_trace(unsigned int trace);
|
||||
|
||||
typedef void (*core_trace_func)(unsigned int);
|
||||
|
||||
extern core_trace_func funcTbl[PLATFORM_CORE_COUNT];
|
||||
|
||||
#define PM_TRACE(trace) funcTbl[plat_my_core_pos()](trace)
|
||||
|
||||
#else
|
||||
|
||||
#define PM_TRACE(trace)
|
||||
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* pm_trace_add
|
||||
*
|
||||
* DESCRIPTION: Add PM trace
|
||||
******************************************************************************
|
||||
*/
|
||||
void pm_trace_add(unsigned int trace, unsigned int core);
|
||||
|
||||
#endif /* PLAT_PM_TRACE_H */
|
||||
+39
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef CCI_MACROS_S
|
||||
#define CCI_MACROS_S
|
||||
|
||||
#include <drivers/arm/cci.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
.section .rodata.cci_reg_name, "aS"
|
||||
cci_iface_regs:
|
||||
.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
|
||||
|
||||
/* ------------------------------------------------
|
||||
* The below required platform porting macro prints
|
||||
* out relevant interconnect registers whenever an
|
||||
* unhandled exception is taken in BL31.
|
||||
* Clobbers: x0 - x9, sp
|
||||
* ------------------------------------------------
|
||||
*/
|
||||
.macro print_cci_regs
|
||||
adr x6, cci_iface_regs
|
||||
/* Store in x7 the base address of the first interface */
|
||||
mov_imm x7, (PLAT_MARVELL_CCI_BASE + SLAVE_IFACE_OFFSET( \
|
||||
PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX))
|
||||
ldr w8, [x7, #SNOOP_CTRL_REG]
|
||||
/* Store in x7 the base address of the second interface */
|
||||
mov_imm x7, (PLAT_MARVELL_CCI_BASE + SLAVE_IFACE_OFFSET( \
|
||||
PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX))
|
||||
ldr w9, [x7, #SNOOP_CTRL_REG]
|
||||
/* Store to the crash buf and print to console */
|
||||
bl str_in_crash_buf_print
|
||||
.endm
|
||||
|
||||
#endif /* CCI_MACROS_S */
|
||||
+134
@@ -0,0 +1,134 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef MARVELL_MACROS_S
|
||||
#define MARVELL_MACROS_S
|
||||
|
||||
#include <drivers/arm/cci.h>
|
||||
#include <drivers/arm/gic_common.h>
|
||||
#include <drivers/arm/gicv2.h>
|
||||
#include <drivers/arm/gicv3.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
/*
|
||||
* These Macros are required by ATF
|
||||
*/
|
||||
|
||||
.section .rodata.gic_reg_name, "aS"
|
||||
/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */
|
||||
gicc_regs:
|
||||
.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
|
||||
|
||||
#ifdef USE_CCI
|
||||
/* Applicable only to GICv3 with SRE enabled */
|
||||
icc_regs:
|
||||
.asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", ""
|
||||
#endif
|
||||
/* Registers common to both GICv2 and GICv3 */
|
||||
gicd_pend_reg:
|
||||
.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \
|
||||
" Offset:\t\t\tvalue\n"
|
||||
newline:
|
||||
.asciz "\n"
|
||||
spacer:
|
||||
.asciz ":\t\t0x"
|
||||
|
||||
/* ---------------------------------------------
|
||||
* The below utility macro prints out relevant GIC
|
||||
* registers whenever an unhandled exception is
|
||||
* taken in BL31 on ARM standard platforms.
|
||||
* Expects: GICD base in x16, GICC base in x17
|
||||
* Clobbers: x0 - x10, sp
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
.macro marvell_print_gic_regs
|
||||
/* Check for GICv3 system register access */
|
||||
mrs x7, id_aa64pfr0_el1
|
||||
ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
|
||||
cmp x7, #1
|
||||
b.ne print_gicv2
|
||||
|
||||
/* Check for SRE enable */
|
||||
mrs x8, ICC_SRE_EL3
|
||||
tst x8, #ICC_SRE_SRE_BIT
|
||||
b.eq print_gicv2
|
||||
|
||||
#ifdef USE_CCI
|
||||
/* Load the icc reg list to x6 */
|
||||
adr x6, icc_regs
|
||||
/* Load the icc regs to gp regs used by str_in_crash_buf_print */
|
||||
mrs x8, ICC_HPPIR0_EL1
|
||||
mrs x9, ICC_HPPIR1_EL1
|
||||
mrs x10, ICC_CTLR_EL3
|
||||
/* Store to the crash buf and print to console */
|
||||
bl str_in_crash_buf_print
|
||||
#endif
|
||||
b print_gic_common
|
||||
|
||||
print_gicv2:
|
||||
/* Load the gicc reg list to x6 */
|
||||
adr x6, gicc_regs
|
||||
/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
|
||||
ldr w8, [x17, #GICC_HPPIR]
|
||||
ldr w9, [x17, #GICC_AHPPIR]
|
||||
ldr w10, [x17, #GICC_CTLR]
|
||||
/* Store to the crash buf and print to console */
|
||||
bl str_in_crash_buf_print
|
||||
|
||||
print_gic_common:
|
||||
/* Print the GICD_ISPENDR regs */
|
||||
add x7, x16, #GICD_ISPENDR
|
||||
adr x4, gicd_pend_reg
|
||||
bl asm_print_str
|
||||
gicd_ispendr_loop:
|
||||
sub x4, x7, x16
|
||||
cmp x4, #0x280
|
||||
b.eq exit_print_gic_regs
|
||||
bl asm_print_hex
|
||||
|
||||
adr x4, spacer
|
||||
bl asm_print_str
|
||||
|
||||
ldr x4, [x7], #8
|
||||
bl asm_print_hex
|
||||
|
||||
adr x4, newline
|
||||
bl asm_print_str
|
||||
b gicd_ispendr_loop
|
||||
exit_print_gic_regs:
|
||||
.endm
|
||||
|
||||
|
||||
.section .rodata.cci_reg_name, "aS"
|
||||
cci_iface_regs:
|
||||
.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
|
||||
|
||||
/* ------------------------------------------------
|
||||
* The below required platform porting macro prints
|
||||
* out relevant interconnect registers whenever an
|
||||
* unhandled exception is taken in BL31.
|
||||
* Clobbers: x0 - x9, sp
|
||||
* ------------------------------------------------
|
||||
*/
|
||||
.macro print_cci_regs
|
||||
#ifdef USE_CCI
|
||||
adr x6, cci_iface_regs
|
||||
/* Store in x7 the base address of the first interface */
|
||||
mov_imm x7, (PLAT_MARVELL_CCI_BASE + SLAVE_IFACE_OFFSET( \
|
||||
PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX))
|
||||
ldr w8, [x7, #SNOOP_CTRL_REG]
|
||||
/* Store in x7 the base address of the second interface */
|
||||
mov_imm x7, (PLAT_MARVELL_CCI_BASE + SLAVE_IFACE_OFFSET( \
|
||||
PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX))
|
||||
ldr w9, [x7, #SNOOP_CTRL_REG]
|
||||
/* Store to the crash buf and print to console */
|
||||
bl str_in_crash_buf_print
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
||||
#endif /* MARVELL_MACROS_S */
|
||||
+34
@@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef MARVELL_PLAT_PRIV_H
|
||||
#define MARVELL_PLAT_PRIV_H
|
||||
|
||||
#include <lib/utils.h>
|
||||
|
||||
/*****************************************************************************
|
||||
* Function and variable prototypes
|
||||
*****************************************************************************
|
||||
*/
|
||||
void plat_delay_timer_init(void);
|
||||
|
||||
uint64_t mvebu_get_dram_size(uint64_t ap_base_addr);
|
||||
|
||||
/*
|
||||
* GIC operation, mandatory functions required in Marvell standard platforms
|
||||
*/
|
||||
void plat_marvell_gic_driver_init(void);
|
||||
void plat_marvell_gic_init(void);
|
||||
void plat_marvell_gic_cpuif_enable(void);
|
||||
void plat_marvell_gic_cpuif_disable(void);
|
||||
void plat_marvell_gic_pcpu_init(void);
|
||||
void plat_marvell_gic_irq_save(void);
|
||||
void plat_marvell_gic_irq_restore(void);
|
||||
void plat_marvell_gic_irq_pcpu_save(void);
|
||||
void plat_marvell_gic_irq_pcpu_restore(void);
|
||||
|
||||
#endif /* MARVELL_PLAT_PRIV_H */
|
||||
+26
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef MARVELL_PM_H
|
||||
#define MARVELL_PM_H
|
||||
|
||||
#define MVEBU_MAILBOX_MAGIC_NUM PLAT_MARVELL_MAILBOX_MAGIC_NUM
|
||||
#define MVEBU_MAILBOX_SUSPEND_STATE 0xb007de7c
|
||||
|
||||
/* Mailbox entry indexes */
|
||||
/* Magic number for validity check */
|
||||
#define MBOX_IDX_MAGIC 0
|
||||
/* Recovery from suspend entry point */
|
||||
#define MBOX_IDX_SEC_ADDR 1
|
||||
/* Suspend state magic number */
|
||||
#define MBOX_IDX_SUSPEND_MAGIC 2
|
||||
/* Recovery jump address for ROM bypass */
|
||||
#define MBOX_IDX_ROM_EXIT_ADDR 3
|
||||
/* BLE execution start counter value */
|
||||
#define MBOX_IDX_START_CNT 4
|
||||
|
||||
#endif /* MARVELL_PM_H */
|
||||
+39
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef MVEBU_H
|
||||
#define MVEBU_H
|
||||
|
||||
/* Use this functions only when printf is allowed */
|
||||
#define debug_enter() VERBOSE("----> Enter %s\n", __func__)
|
||||
#define debug_exit() VERBOSE("<---- Exit %s\n", __func__)
|
||||
|
||||
/* Macro for testing alignment. Positive if number is NOT aligned */
|
||||
#define IS_NOT_ALIGN(number, align) ((number) & ((align) - 1))
|
||||
|
||||
/* Macro for alignment up. For example, ALIGN_UP(0x0330, 0x20) = 0x0340 */
|
||||
#define ALIGN_UP(number, align) (((number) & ((align) - 1)) ? \
|
||||
(((number) + (align)) & ~((align)-1)) : (number))
|
||||
|
||||
/* Macro for testing whether a number is a power of 2. Positive if so */
|
||||
#define IS_POWER_OF_2(number) ((number) != 0 && \
|
||||
(((number) & ((number) - 1)) == 0))
|
||||
|
||||
/*
|
||||
* Macro for ronding up to next power of 2
|
||||
* it is done by count leading 0 (clz assembly opcode) and see msb set bit.
|
||||
* then you can shift it left and get number which power of 2
|
||||
* Note: this Macro is for 32 bit number
|
||||
*/
|
||||
#define ROUND_UP_TO_POW_OF_2(number) (1 << \
|
||||
(32 - __builtin_clz((number) - 1)))
|
||||
|
||||
#define _1MB_ (1024ULL * 1024ULL)
|
||||
#define _1GB_ (_1MB_ * 1024ULL)
|
||||
#define _2GB_ (2 * _1GB_)
|
||||
|
||||
#endif /* MVEBU_H */
|
||||
Reference in New Issue
Block a user